CN215071629U - Simple and easy DC line surge current suppression circuit - Google Patents
Simple and easy DC line surge current suppression circuit Download PDFInfo
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- CN215071629U CN215071629U CN202023343416.3U CN202023343416U CN215071629U CN 215071629 U CN215071629 U CN 215071629U CN 202023343416 U CN202023343416 U CN 202023343416U CN 215071629 U CN215071629 U CN 215071629U
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Abstract
The utility model relates to a simple and easy DC circuit surge current suppression circuit, including the direct current input end, direct current output and charging capacitor, charging capacitor's one end is connected at the direct current output end, other end ground connection, be equipped with protection circuit on the high potential route between direct current input end and the charging capacitor, protection circuit includes power supply, driving resistor, the transistor, power resistor and reset circuit, power supply passes through the grid that driving resistor connects the transistor, power resistor connects in parallel with the transistor, and charge for charging capacitor through power resistor, reset circuit one end is connected between the grid of driving resistor and transistor, direct current output is connected to the other end. The utility model discloses utilize simple resistance restriction or control power supply's supply current, the surge current that the voltage power failure that appears in the suppression circuit resumes to arouse effectively charges the capacitive load capacity of taking of improving circuit, the anti thunderbolt and the interference killing feature of improving circuit through power resistance.
Description
Technical Field
The utility model relates to a surge suppression circuit field, specific theory relates to a simple and easy DC circuit surge current suppression circuit.
Background
At the moment of power-on of the DC line, namely at the moment of switching/hot plugging, due to capacitive load, instantaneous large surge current and voltage spike exist, impact is caused to front and rear-stage equipment, and electromagnetic field interference is caused. In order to protect these electric devices and prevent the electric devices from being damaged by surge current, it is necessary to provide a protection circuit in the circuit to suppress the surge.
Although professional surge suppression circuits such as TPS2493PW series of TI company on the market can achieve the effect of surge suppression, the integrated circuit has high cost, limited using voltage range and poor lightning protection and anti-interference capabilities.
The above problems are worth solving.
Disclosure of Invention
In order to overcome the deficiencies of the prior art, the utility model provides a simple and easy DC line surge current suppression circuit.
The utility model discloses technical scheme as follows:
a simple DC line surge current suppression circuit comprises a direct current input end, a direct current output end and a charging capacitor, wherein one end of the charging capacitor is connected with the direct current output end, the other end of the charging capacitor is grounded, it is characterized in that a protection circuit is arranged on a high potential path between the direct current input end and the charging capacitor, the protection circuit comprises a power supply, a first driving resistor R1, a first transistor Q1, a second power resistor R2 and a reset circuit, the power supply is connected with the gate of the first transistor Q1 through the first driving resistor R1, the second power resistor R2 has one end connected to the drain of the first transistor Q1, the other end connected to the source of the first transistor Q1, one end of the reset circuit is connected between the first driving resistor R1 and the gate of the first transistor Q1, and the other end of the reset circuit is connected with the direct current output end.
According to above-mentioned scheme the utility model discloses, its characterized in that, power supply is voltage source or constant current source.
The utility model according to the above scheme is characterized in that the reset circuit comprises a photoelectric coupler, a second transistor Q2, a second capacitor C2, a third power resistor R3, a fourth driving resistor R4, a fifth driving resistor R5 and a pull-down resistor R6, the anode of the light emitting diode terminal of the photoelectric coupler is connected with a key switch through the fifth driving resistor R5, the cathode of the photoelectric coupler is grounded, the collector at the triode end of the photoelectric coupler is connected with the power supply, the emitters of the first and second transistors are simultaneously connected with the second capacitor C2 and the gate of the second transistor Q2 through the fourth driving resistor R4, the third power resistor R3 is connected in parallel with the second capacitor C2, the source of the second transistor Q2 is connected with the source of the first transistor Q1, the drain of the second transistor Q2 is connected to the gate of the first transistor Q1 through the pull-down resistor R6.
Furthermore, a power failure detection circuit is arranged between the direct current input end and the grounding end, and the third end of the power failure detection circuit is connected to the key switch.
According to the utility model discloses of above-mentioned scheme, its characterized in that, first transistor Q1 is MOS pipe or triode or IGBT, second transistor Q2 is MOS pipe or triode or IGBT.
According to the utility model discloses of above-mentioned scheme, its characterized in that, second power resistance R2 is wire winding resistance or metal film resistance or carbon film resistance or cement resistance or thermistor.
A simple DC line surge current suppression circuit comprises a first DC input end DC-IN, a second DC input end DC-IN, a DC output end DC-OUT and a charging capacitor, wherein one end of the charging capacitor is connected with the first DC input end DC-IN, the other end of the charging capacitor is grounded, a first protection circuit is arranged on a low potential path between the second DC input end DC-IN and the charging capacitor, the first protection circuit comprises a power supply, a first driving resistor R1, a first transistor Q1, a second power resistor R2 and a reset circuit, the power supply is connected with a grid electrode of the first transistor Q1 through the first driving resistor R1, one end of the second power resistor R2 is connected with a drain electrode of the first transistor Q1, the other end of the second power resistor R2 is connected with a source electrode of the first transistor Q1, one end of the reset circuit is connected between the first driving resistor R1 and the grid electrode of the first transistor Q1, the other end of the first direct current input end is connected with the second direct current input end DC-.
Further, a second protection circuit is arranged on a high potential path between the first direct current input end DC-IN and the charging capacitor, and the second protection circuit is the same as the first protection circuit.
According to the above scheme the utility model discloses, its beneficial effect lies in:
the utility model discloses utilize simple resistance restriction or control power supply's supply current for the transistor gets into linear region when starting, thereby the surge current that the voltage power failure that appears in the suppression circuit resumes to arouse effectively, and is further, charges the capacitive load ability of taking of improvement circuit through power resistance, improves the shock resistance of transistor, and improvement circuit's anti-thunderbolt and interference killing feature are compared in current professional surge suppression circuit, need not receive the integrated circuit restriction of transistor, and the circuit is simple, effective.
Drawings
FIG. 1 is a schematic circuit diagram according to a first embodiment;
FIG. 2 is a circuit diagram according to the first embodiment;
FIG. 3 is a start-up timing diagram according to the first embodiment;
fig. 4 is a schematic circuit diagram of the second embodiment.
Detailed Description
For better understanding of the objects, technical solutions and technical effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and embodiments. It is to be noted that the following examples are only for explaining the present invention and are not intended to limit the present invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present, and when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Example one
As shown IN fig. 1 and 2, a simple DC line inrush current suppression circuit includes a DC input terminal DC-IN, a DC output terminal DC-OUT, and a charging capacitor C1, wherein one end of the charging capacitor C1 is connected to the DC output terminal DC-OUT, the other end is grounded GND, and a protection circuit is disposed on a high potential path between the DC input terminal DC-IN and the charging capacitor C1.
The protection circuit comprises a power supply, a first driving resistor R1, a first transistor Q1, a second power resistor R2 and a reset circuit, wherein the power supply is connected with the grid electrode of the first transistor Q1 through the first driving resistor R1, one end of the second power resistor R2 is connected with the drain electrode of the first transistor Q1, the other end of the second power resistor R2 is connected with the source electrode of the first transistor Q1, the charging capacitor C1 is charged through the second power resistor R2, one end of the reset circuit is connected between the first driving resistor R1 and the first transistor Q1, and the other end of the reset circuit is connected with a direct current output end. Preferably, the power supply is a voltage source VCC or a constant current source.
The utility model discloses an utilize the drive current of first transistor Q1 of first drive resistance R1 control or power supply's input current to make first transistor Q1 get into and switch on the amplification area, reach the purpose of restraining surge current and voltage, the parallelly connected second power resistance R2 of first transistor Q1 supplements as the reposition of redundant personnel simultaneously, improves the shock resistance of first transistor Q1, can take bigger electric capacity load.
The utility model discloses reaction rate is fast, reaches the level of making a delicate matter, and the surge current that the voltage power failure that appears in the suppression circuit resumes to arouse effectively.
In this embodiment, the reset circuit includes a photocoupler, a second transistor Q2, a second capacitor C2, a third power resistor R3, a fourth driving resistor R4, a fifth driving resistor R5 and a pull-down resistor R6, the anode of the light emitting diode terminal OT1-B of the photocoupler is connected to the key switch KZ through the fifth driving resistor R5, and the cathode thereof is grounded; the collector of a triode terminal OT1-A of the photocoupler is connected with a power supply, the emitter of the triode terminal OT1-A is simultaneously connected with the grid of a second capacitor C2 and a second transistor Q2 through a fourth driving resistor R4, a third power resistor R3 is connected in parallel with a second capacitor C2, the source of the second transistor Q2 is connected with the source of a first transistor Q1, and the drain of the second transistor Q2 is connected between the grid of the first driving resistor R1 and the first transistor Q1 through a pull-down resistor R6.
The second power resistor R2 takes a value according to the size of the charging capacitor C1 and the required charging time; the second power resistor R2 is a wire-wound resistor, a metal film resistor, a carbon film resistor, a cement resistor or a thermistor.
IN this embodiment, a power down detection circuit is disposed between the DC input terminal DC-IN and the ground terminal GND, and a third terminal of the power down detection circuit is connected to the key switch KZ.
As shown IN fig. 3, the specific working process of this embodiment is that after the DC input terminal DC-IN is powered on, the charging capacitor C1 is charged through the second power resistor R2, and at the same time VCC is powered on, the first transistor Q1 is driven by the first driving resistor R1 to gradually enter the amplification region, and the charging capacitor C1 starts to be charged, and since the first transistor Q1 is IN the amplification region, the surge current can be limited. Because the driving resistor of the transistor Q1 is large, before the first transistor Q1 enters the amplification region, the second power resistor R2 charges the charging capacitor C1 first, so that the charging time is shortened, the voltage difference is reduced, the surge current passing through the first transistor Q1 is reduced, the power consumption of the first transistor Q1 is reduced, and the overall surge current is also reduced. After the first transistor Q1 is used each time, the driving voltage reaches the maximum, when the power failure detection circuit detects that the DC-IN input terminal DC-IN is powered down, the fifth driving resistor R5 drives the OT1 terminal of the photocoupler to conduct, the fourth driving resistor R4 drives the second transistor Q2, the first transistor Q1 is pulled down by the pull-down resistor R6 to drive, so that the first transistor Q1 is reset, and the last charging process is repeated after the DC-IN input terminal DC-IN is restored.
Preferably, the first transistor Q1 is a MOS transistor, a triode or an IGBT; the second transistor Q2 is a MOS transistor, a triode or an IGBT.
In addition to the design manner of the protection circuit in the above scheme, in other embodiments, the same protection circuit may also be disposed on the low-potential path between the dc input terminal and the charging capacitor C1, and the protection circuit has the same structure as the protection circuit on the high-potential path in this embodiment, and is not described herein again.
Example two
As shown IN fig. 4, a simple DC line surge current suppression circuit includes a first DC input terminal DC-IN, a second DC input terminal DC-, a DC output terminal DC-OUT and a charging capacitor C1, wherein one end of the charging capacitor C1 is connected to the first DC input terminal DC-IN, the other end is grounded, a first protection circuit is disposed IN a low potential path between the second DC input terminal DC-and the charging capacitor C1, the first protection circuit includes a power supply VCC, a first driving resistor R1, a first transistor Q1, a second power resistor R2 and a reset circuit, the power supply is connected to a gate of the first transistor Q1 through the first driving resistor R1, one end of the second power resistor R2 is connected to a drain of the first transistor Q1, the other end is connected to a source of the first transistor Q1, the charging capacitor C1 is provided through the second power resistor R2, one end of the reset circuit is connected between the first driving resistor R1 and the gate of the first transistor Q1, the other end is connected with a second direct current input end DC-.
IN this embodiment, except that the first protection circuit is disposed on the low potential path between the second DC input terminal DC-and the charging capacitor C1, and the second protection circuit is disposed on the high potential path between the first DC input terminal DC-IN and the charging capacitor C1, the second protection circuit has the same structure as the first protection circuit, and is not repeated herein.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (8)
1. A simple DC line surge current suppression circuit comprises a DC input end, a DC output end and a charging capacitor, wherein one end of the charging capacitor is connected with the DC output end, and the other end is grounded, and is characterized in that a protection circuit is arranged on a high-potential path between the DC input end and the charging capacitor,
the protection circuit includes power supply, first drive resistance R1, first transistor Q1, second power resistance R2 and reset circuit, power supply passes through first drive resistance R1 connects first transistor Q1's grid, second power resistance R2 one end is connected first transistor Q1's drain electrode, the other end is connected first transistor Q1's source electrode, reset circuit one end is connected first drive resistance R1 with between first transistor Q1's the grid, the other end is connected the direct current output.
2. A simple DC line inrush current suppression circuit as in claim 1, wherein the power supply is a voltage source or a constant current source.
3. The simple DC line surge current suppression circuit of claim 1, wherein the reset circuit comprises a photocoupler, a second transistor Q2, a second capacitor C2, a third power resistor R3, a fourth driving resistor R4, a fifth driving resistor R5 and a pull-down resistor R6,
the anode of the led of the photocoupler is connected to the key switch through the fifth driving resistor R5, the cathode thereof is grounded, the collector of the triode of the photocoupler is connected to the power supply, the emitter thereof is simultaneously connected to the second capacitor C2 and the gate of the second transistor Q2 through the fourth driving resistor R4, the third power resistor R3 is connected in parallel to the second capacitor C2, the source of the second transistor Q2 is connected to the source of the first transistor Q1, and the drain of the second transistor Q2 is connected to the gate of the first transistor Q1 through the pull-down resistor R6.
4. A simple DC line inrush current suppression circuit as in claim 3, wherein a power down detection circuit is disposed between the DC input terminal and the ground terminal, and a third terminal of the power down detection circuit is connected to the keyswitch.
5. A simple DC line inrush current suppression circuit as claimed in claim 3, wherein the first transistor Q1 is a MOS transistor or a transistor or an IGBT, and the second transistor Q2 is a MOS transistor or a transistor or an IGBT.
6. A simple DC circuit surge current suppression circuit according to claim 1, wherein the second power resistor R2 is a wire resistor, a metal film resistor, a carbon film resistor, a cement resistor, or a thermistor.
7. A simple DC line surge current suppression circuit comprises a first DC input end, a second DC input end, a DC output end and a charging capacitor, wherein one end of the charging capacitor is connected with the first DC input end, the other end of the charging capacitor is grounded, a first protection circuit is arranged on a low potential path between the second DC input end and the charging capacitor, the first protection circuit comprises a power supply, a first driving resistor R1, a first transistor Q1, a second power resistor R2 and a reset circuit,
the power supply is connected with the grid electrode of the first transistor Q1 through the first driving resistor R1, one end of the second power resistor R2 is connected with the drain electrode of the first transistor Q1, the other end of the second power resistor R2 is connected with the source electrode of the first transistor Q1, one end of the reset circuit is connected between the first driving resistor R1 and the grid electrode of the first transistor Q1, and the other end of the reset circuit is connected with the second direct current input end.
8. A simple DC line inrush current suppression circuit as in claim 7, wherein a second protection circuit is provided in the high potential path between the first DC input and the charging capacitor, and the second protection circuit is the same as the first protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023343416.3U CN215071629U (en) | 2020-12-31 | 2020-12-31 | Simple and easy DC line surge current suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023343416.3U CN215071629U (en) | 2020-12-31 | 2020-12-31 | Simple and easy DC line surge current suppression circuit |
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| Publication Number | Publication Date |
|---|---|
| CN215071629U true CN215071629U (en) | 2021-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202023343416.3U Active CN215071629U (en) | 2020-12-31 | 2020-12-31 | Simple and easy DC line surge current suppression circuit |
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| CN (1) | CN215071629U (en) |
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