WO2020051832A1 - Circuit de protection contre les décharges électrostatiques et puce de circuit intégré - Google Patents

Circuit de protection contre les décharges électrostatiques et puce de circuit intégré Download PDF

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Publication number
WO2020051832A1
WO2020051832A1 PCT/CN2018/105486 CN2018105486W WO2020051832A1 WO 2020051832 A1 WO2020051832 A1 WO 2020051832A1 CN 2018105486 W CN2018105486 W CN 2018105486W WO 2020051832 A1 WO2020051832 A1 WO 2020051832A1
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Prior art keywords
field effect
voltage
module
effect transistor
unit
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PCT/CN2018/105486
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English (en)
Chinese (zh)
Inventor
张�浩
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深圳市汇顶科技股份有限公司
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Priority to CN201880001540.8A priority Critical patent/CN109314388B/zh
Priority to PCT/CN2018/105486 priority patent/WO2020051832A1/fr
Publication of WO2020051832A1 publication Critical patent/WO2020051832A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/047—Free-wheeling circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Definitions

  • the present application relates to the field of electronic technology, and in particular, to an electrostatic discharge protection circuit and an integrated circuit chip.
  • Electrostatic discharge is a transient process in which a large amount of electric charge is poured into an integrated circuit from the outside to the inside of the integrated circuit when it is floating. In this process, it is easy to cause the failure of the integrated circuit chip.
  • FIG. 1 a typical electrostatic discharge protection circuit in the prior art is shown in FIG. 1 and includes a capacitor C1, a capacitor C3, a resistor R1, and field effect transistors M1, M2, M3, M4, M5, M6, and M7. , M8, and M9.
  • VDDH at the power supply pins is slowly powered on, GND is at 0 potential, M5, M6, M7, M8, and M9 provide the VDDH to GND voltage division, and VM is the intermediate potential obtained after VDDH voltage division (VM equals 0.5VDDH) ), VG_ND is low, M2 is on, M1 is off, there is no leakage from VDDH to GND, and the potential between VM and VDDH is not too high to break through M2.
  • VDDH During the VDDH electrostatic attack at the power pin, VDDH increases sharply, the power pin is at a high potential, the VM potential is pulled up under the coupling of C3, and the capacitor C1 is slowly charged through the resistor R1, and VG_ND is pulled to VM , M1 and M2 are turned on at the same time to achieve electrostatic discharge at VDDH.
  • VG_ND before the upper plate of C1 is charged to a high potential, VG_ND is always at the same high potential as VM, and static electricity is discharged from VDDH to GND through M1 and M2.
  • M1 is turned off, and the static discharge path is disconnected.
  • VM in the above circuit is coupled by C3 to a high level as close to VDDH as possible.
  • M1 and M2 it is necessary to make VM equal to VDDH, but under this condition, the size of M2 is larger, the required capacitance of capacitor C3 is larger, and the size of C3 is larger, so that the layout area of the entire circuit It is very large, and it is easy to cause waste of chip area.
  • the purpose of some embodiments of the present application is to provide an electrostatic discharge protection circuit and an integrated circuit chip, which aim to reduce the layout area of the electrostatic discharge circuit and obtain a stronger electrostatic discharge capability.
  • An embodiment of the present application provides an electrostatic discharge protection circuit, including a field effect tube triggering module, a voltage dividing module, and a bleeding module connected in parallel between a power pin and a ground pin; wherein the voltage dividing module includes a first A voltage dividing unit and a second voltage dividing unit, the first voltage dividing unit and the second voltage dividing unit are connected in series, and the connection point of the first voltage dividing unit and the second voltage dividing unit is used as an output terminal of the voltage dividing module;
  • the output of the FET trigger module is connected to the output of the voltage divider module
  • the output of the voltage divider module is connected to the input of the bleeder module
  • the FET trigger module is turned on when the power pin is subjected to electrostatic attack, the first voltage dividing unit is shorted, the voltage of the output terminal of the voltage dividing module is pulled up to a high level, the bleeder module is turned on and the power pin is discharged. Of static electricity.
  • An embodiment of the present application further provides an integrated circuit chip including the above-mentioned electrostatic discharge protection circuit.
  • the embodiment of the present application provides a field effect tube triggering module in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field effect tube triggering module is directly guided when the power pin is subjected to electrostatic attack.
  • the output terminal voltage of the voltage-dividing module is pulled up to a high level.
  • the bleeder module is turned on, and a point of static electricity at the power pin is discharged to the ground through the bleeder module.
  • the field-effect transistor trigger module is directly turned on, the voltage at the output end of the voltage-dividing module can be pulled up to be equal to the voltage at the power supply pin, without the need for coupling through capacitors. Capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the FET trigger module specifically includes: a detection unit and a FET; the detection unit is connected between the power pin and the ground pin, and the output end of the detection unit is connected to the gate of the FET; The source is connected to the power pin, and the drain is used as the output terminal of the FET trigger module. Among them, when the power pin is electrostatically attacked, the output of the detection unit is low.
  • This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application.
  • the detection unit is used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.
  • the detection unit specifically includes: a resistor and a capacitor; the resistor and the capacitor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the resistor and the capacitor serves as the output end of the detection unit.
  • the structure of the detection unit provided in this embodiment is relatively simple.
  • the field-effect tube triggering module specifically includes a third voltage-dividing unit, a fourth voltage-dividing unit, a detection unit, a driving unit, and a field-effect tube; a first end of the third voltage-dividing unit is connected to a power pin, and a second end Connected to the first end of the fourth voltage division unit; the second end of the fourth voltage division unit is connected to the ground pin; the detection unit and the drive unit are connected in parallel between the power pin and the ground pin; the third voltage division unit The second end of the MOSFET is connected to the first input of the drive unit; the output of the detection unit is connected to the second input of the drive unit; the gate of the FET is connected to the output of the drive unit, and the source is connected to the power pin The drain is used as the output terminal of the FET trigger module.
  • the second terminal of the third voltage dividing unit When the power pin is subjected to electrostatic attack, the second terminal of the third voltage dividing unit is low, and the output of the detection unit is high. The output is low.
  • This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application.
  • the detection unit and the driving unit are used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.
  • the detection unit specifically includes: a capacitor and a resistor; the capacitor and the resistor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the capacitor and the resistance is used as the output terminal of the detection unit.
  • the structure of the detection unit provided in this embodiment is relatively simple.
  • the driving unit specifically includes: a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor; the gate of the first field-effect transistor is connected to the output terminal of the detection unit, and the source and The ground pin is connected, the drain is connected to the source of the second FET; the gate of the second FET is connected to the second end of the third voltage division unit, and the drain is connected to the drain of the third FET ; The source of the third FET is connected to the power pin, the gate is connected to the source of the fourth FET; the gate of the fourth FET is connected to the second end of the third voltage-dividing unit, and the drain Connected to the output of the detection unit.
  • This embodiment provides a specific implementation form of the driving unit, which increases the flexibility of the embodiments of the present application.
  • the driving unit is composed of a plurality of field effect transistors, and the layout area of the driving unit is small.
  • FIG. 1 is a circuit diagram of an electrostatic discharge protection circuit in the prior art
  • FIG. 2 is a schematic diagram of an electrostatic discharge protection circuit in the first embodiment of the present application.
  • FIG. 3 is a schematic diagram of an electrostatic discharge protection circuit in a second embodiment of the present application.
  • the first embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 2, including a field effect tube trigger module, a voltage division module, and a bleeder module connected in parallel between a power pin VDDH and a ground pin GND. 103.
  • the voltage dividing module includes a first voltage dividing unit 1021 and a second voltage dividing unit 1022.
  • the first voltage dividing unit 1021 and the second voltage dividing unit 1022 are connected in series, and the first voltage dividing unit 1021 and the second voltage dividing unit 1022.
  • the connection point is used as the output of the voltage divider module.
  • the output terminal of the field effect tube triggering module is connected to the output terminal of the voltage dividing module, and the output terminal of the voltage dividing module is connected to the input terminal of the bleeder module 103.
  • the FET trigger module is turned on when the power pin VDDH is subjected to an electrostatic attack, the first voltage dividing unit 1021 is shorted, the output terminal voltage of the voltage dividing module is pulled up to a high level, and the bleeder module 103 is turned on and discharged. Discharge the static electricity at the pin VDDH.
  • the field-effect transistor triggering module includes a detection unit 1011 and a field-effect transistor M10.
  • the detection unit 1011 is connected between the power pin VDDH and the ground pin GND, and the output terminal of the detection unit 1011 is connected to the gate of the field effect transistor M10.
  • the source of the MOSFET M10 is connected to the power pin VDDH, and the drain is used as the output terminal of the MOSFET trigger module.
  • the detection unit 1011 includes a resistor R2 and a capacitor C2.
  • the resistor R2 and the capacitor C2 are connected in series between the power pin VDDH and the ground pin GND in order.
  • the connection terminal of the resistor R2 and the capacitor C2 is used as the output terminal of the detection unit, that is, RC2_OUT is used as the output terminal.
  • the first voltage dividing unit 1021 may include field effect transistors M7, M8, and M9.
  • the specific connection relationship may be as shown in FIG. 2:
  • the source of M9 is connected to VDDH.
  • the gate of M9 is connected to the drain and connected to the source of M8.
  • the gate of M8 is connected to the drain and connected to the source of M7.
  • the gate of M7 is connected to the drain, and is connected to the second voltage dividing unit 1022.
  • the second voltage dividing unit 1022 may include field effect transistors M5 and M6.
  • the specific connection relationship may be as shown in FIG. 2, that is, the gate of M7 is connected to the drain, and the gate and drain of M6 are connected, and the source of M6
  • the electrode is connected to the gate and drain of M5, and the source of M5 is connected to the ground pin GND.
  • the bleed module 103 includes a buffer unit, an inverter, a fifth field-effect transistor M1 and a sixth field-effect transistor M2.
  • the buffer unit and the inverter are connected in parallel between the output terminal of the voltage dividing module and the ground pin GND.
  • the output of the buffer unit is connected to the input of the inverter, the output of the inverter is connected to the gate of M1, the source of M1 is connected to the ground pin GND, and the drain is connected to the source of M2.
  • the drain of M2 is connected to the power pin VDDH, and the gate is used as the input terminal of the bleeder module 103.
  • the buffer unit is an RC oscillation circuit, which is composed of a resistor R1 and a capacitor C1.
  • One end of the resistor R1 is connected to the output end of the voltage dividing module, and the other end is connected to C1, and C1 is also connected to the ground pin GND.
  • the inverter consists of field-effect transistors M3 and M4. The specific connection is shown in Figure 2.
  • VDDH has not been attacked by static electricity
  • VDDH is slowly powered on.
  • M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND.
  • VM is the intermediate potential obtained after VDDH division. VM is equal to 0.5VDDH, and M2 is turned on.
  • RC1_OUT is high, RC1_OUT is VG_ND via the inverter, VG_ND is low, M1 is off, there is no static current, and the bleeder module 103 is not turned on.
  • RC2_OUT is high-level VDDH, M10 is in the off state, there is no quiescent current, and because the drain voltage of M10 is VM, there is no risk of overvoltage in M10.
  • VDDH is subject to electrostatic attack
  • VDDH voltage increases sharply, and R2 and C2 in the detection unit 1011 are too late to respond, so RC2_OUT is low relative to VDDH, M10 is turned on, the first voltage dividing unit 1021 is shorted, and VM is pulled up to VDDH, M2 Continuity.
  • R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on. Since M1 and M2 are both on, that is, the bleeder module 103 is on, the static electricity at VDDH is discharged to GND through M1 and M2.
  • a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack.
  • the output terminal voltage of the voltage dividing module is pulled up to a high level.
  • the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103.
  • the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, and no coupling is required through the capacitor. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the second embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 3.
  • the second embodiment is substantially the same as the first embodiment, and the main difference is that the implementation form of the field effect tube trigger module is different, which will be described in detail below:
  • the field-effect transistor triggering module specifically includes a third voltage-dividing unit 1012, a fourth voltage-dividing unit 1013, a detection unit 1011, a driving unit 1014, and a field-effect tube M10.
  • the first terminal of the third voltage dividing unit 1012 is connected to the power pin VDDH
  • the second terminal is connected to the first terminal of the fourth voltage dividing unit 1013
  • the second terminal of the fourth voltage dividing unit 1013 is connected to the ground pin GND.
  • the detection unit 1011 and the driving unit 1014 are both connected in parallel between the power pin VDDH and the ground pin GND.
  • the second terminal of the third voltage dividing unit 1012 is connected to the first input terminal of the driving unit 1014, the output terminal of the detecting unit 1011 is connected to the second input terminal of the driving unit 1014, and the gate of the field effect tube M10 is connected to the driving unit 1014.
  • the output terminal is connected, the source is connected to the power pin VDDH, and the drain is used as the output terminal of the FET trigger module.
  • the second terminal of the third voltage dividing unit 1012 is at a low level
  • the output terminal of the detection unit 1011 is at a high level
  • the output terminal of the driving unit 1013 is at a low level.
  • the detection unit 1011 includes a capacitor C3 and a resistor R3.
  • the capacitor C3 and the resistor R3 are connected in series between the power pin VDDH and the ground pin GND.
  • the connection terminal of the capacitor C3 and the resistor R3 serves as an output terminal of the detection unit 1011.
  • the third voltage-dividing unit 1012 includes field-effect transistors M17, M18, and M19.
  • the specific connection is shown in FIG. That is, the source of M19 is connected to VDDH.
  • the gate of M19 is connected to the drain and is connected to the source of M18.
  • the gate of M18 is connected to the drain and is connected to the source of M17.
  • the gate of M17 is connected to the drain, and is connected to the second voltage dividing unit 1013.
  • the second voltage dividing unit 1013 includes field effect tubes M15 and M16, and the specific connection is shown in FIG. 3. That is, the gate of M17 is connected to the gate and drain of M6, the source of M16 is connected to the gate and drain of M15, and the source of M15 is connected to the ground pin GND.
  • the driving unit 1014 includes a first field effect tube M11, a second field effect tube M12, a third field effect tube M13, and a fourth field effect tube M14.
  • the gate of M11 is connected to the output terminal of detection unit 1011, the source is connected to the ground pin, and the drain is connected to the source of M12.
  • the gate of M12 is connected to the second end of the third voltage dividing unit 1012, and the drain is connected to the drain of M13.
  • the source of M13 is connected to the power pin VDDH, and the gate is connected to the source of M14.
  • the gate of M14 is connected to the second terminal of the third voltage division unit 1012, and the drain is connected to the output terminal of the detection unit 1011.
  • VDDH has not been attacked by static electricity.
  • VDDH powers up slowly.
  • M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND.
  • VM is the intermediate potential obtained after VDDH division.
  • VM is equal to 0.5VDDH, VM is high, M2 is on, and RC2_OUT is low Level, M11 is off.
  • M15, M16, M17, M18, and M19 provide the voltage division from VDDH to GND
  • VX is the intermediate potential obtained after VDDH division.
  • VX is equal to 0.5VDDH, VX is high, and M14 and M12 are turned off.
  • the gate of M13 is low level, M13 is turned on, the gate voltage of M10 is pulled to a high potential VDDH by M13, M10 is in the off state, and no leakage will occur in M10 and M11. Since VM is equal to 0.5VDDH and VM is high level, RC1_OUT is high level, RC1_OUT is VG_ND via the inverter, VG_ND is low level, M1 is turned off, there is no static current, and the bleeder module 103 is not turned on.
  • VDDH is attacked by static electricity.
  • VDDH voltage increases sharply, RC2_OUT is high level, VX is equal to 0.5VDDH, VX is high level, M11, M12, M14 are turned on at the same time, so that the gate voltage of M10 is pulled to low level GND, and M10 is turned on, so that VM is pulled to VDDH and M2 is turned on.
  • R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on.
  • a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack.
  • the output terminal voltage of the voltage dividing module is pulled up to a high level.
  • the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103.
  • the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, without the need for coupling through the capacitor, so that the strong discharge of the electrostatic discharge circuit can be achieved. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the third embodiment of the present application relates to an integrated circuit chip, and the integrated circuit chip is provided with the electrostatic discharge protection circuit mentioned in the above embodiment.

Abstract

La présente invention se rapporte au domaine technique de l'électronique, et concerne un circuit de protection contre les décharges électrostatiques et une puce de circuit intégré. Le circuit de protection contre les décharges électrostatiques comprend : un module de déclenchement à transistor à effet de champ, un module diviseur de tension et un module de décharge (103) qui sont connectés en parallèle entre une broche d'alimentation électrique et une broche de masse ; le module diviseur de tension comprend une première unité de division de tension (1021) et une seconde unité de division de tension (1022) ; la première unité de division de tension et la seconde unité de division de tension sont connectées en série, et le point de connexion sert de borne de sortie du module diviseur de tension ; une borne de sortie du module de déclenchement à transistor à effet de champ est connectée à la borne de sortie du module diviseur de tension ; la borne de sortie du module diviseur de tension est connectée à une borne d'entrée du module de décharge ; lorsque la broche d'alimentation électrique subit une attaque électrostatique, le module de déclenchement à transistor à effet de champ est mis à l'état passant, la première unité de division de tension est court-circuitée, la tension à la borne de sortie du module diviseur de tension est amenée à un niveau élevé, et le module de décharge est mis sous tension et décharge l'électricité statique présente au niveau de la broche d'alimentation électrique. La présente invention peut réduire la surface d'implantation d'un circuit de décharge électrostatique et atteindre de plus fortes capacités de décharge électrostatique.
PCT/CN2018/105486 2018-09-13 2018-09-13 Circuit de protection contre les décharges électrostatiques et puce de circuit intégré WO2020051832A1 (fr)

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Application Number Priority Date Filing Date Title
CN201880001540.8A CN109314388B (zh) 2018-09-13 2018-09-13 静电泄放保护电路及集成电路芯片
PCT/CN2018/105486 WO2020051832A1 (fr) 2018-09-13 2018-09-13 Circuit de protection contre les décharges électrostatiques et puce de circuit intégré

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PCT/CN2018/105486 WO2020051832A1 (fr) 2018-09-13 2018-09-13 Circuit de protection contre les décharges électrostatiques et puce de circuit intégré

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110994574B (zh) * 2019-10-15 2022-02-18 珠海亿智电子科技有限公司 耐高压的电源钳位电路
CN112086946B (zh) * 2020-08-13 2024-03-19 珠海亿智电子科技有限公司 具有交流检测和直流检测的耐高压钳位电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070230073A1 (en) * 2006-04-04 2007-10-04 Ming-Dou Ker High-voltage tolerant power-rail esd clamp circuit
US7586721B2 (en) * 2007-07-10 2009-09-08 United Microelectronics Corp. ESD detection circuit
CN102315633A (zh) * 2010-07-06 2012-01-11 瑞昱半导体股份有限公司 静电防护电路
CN104979814A (zh) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 一种静电放电保护电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781388A (en) * 1996-09-03 1998-07-14 Motorola, Inc. Non-breakdown triggered electrostatic discharge protection circuit for an integrated circuit and method therefor
TWI264106B (en) * 2002-04-30 2006-10-11 Winbond Electronics Corp Static charge protection circuit of adopting gate-coupled MOSFET (metal-oxide-semiconductor field effect transistor)
CN101442869B (zh) * 2007-11-23 2011-08-24 上海华虹Nec电子有限公司 动态侦测静电保护电路
US9001479B2 (en) * 2012-02-07 2015-04-07 Mediatek Inc. ESD protection circuit
CN103001205A (zh) * 2012-11-02 2013-03-27 长沙景嘉微电子股份有限公司 一种应用于电源管脚的静电保护电路
US9112351B2 (en) * 2013-02-05 2015-08-18 Freescale Semiconductor Inc. Electrostatic discharge circuit
CN103248033B (zh) * 2013-05-09 2015-07-22 北京大学 瞬态和直流同步触发型电源钳位esd保护电路
CN104269399A (zh) * 2014-08-12 2015-01-07 无锡市晶源微电子有限公司 一种防静电保护电路
CN204180038U (zh) * 2014-11-20 2015-02-25 辽宁大学 用于集成电路的静电放电触发电路
CN106099887A (zh) * 2015-11-20 2016-11-09 厦门宇臻集成电路科技有限公司 一种耐高压rc触发式esd电路
CN105680433B (zh) * 2016-03-24 2018-01-26 北京大学 一种esd电源钳位保护电路
CN206480626U (zh) * 2017-01-22 2017-09-08 建荣集成电路科技(珠海)有限公司 一种静电放电保护电路、芯片及电子设备
WO2018214160A1 (fr) * 2017-05-26 2018-11-29 深圳市汇顶科技股份有限公司 Circuit de protection contre les décharges électrostatiques et procédé de protection contre les décharges électrostatiques
CN107946297A (zh) * 2017-11-16 2018-04-20 长江存储科技有限责任公司 静电放电保护电路、集成电路芯片及电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070230073A1 (en) * 2006-04-04 2007-10-04 Ming-Dou Ker High-voltage tolerant power-rail esd clamp circuit
US7586721B2 (en) * 2007-07-10 2009-09-08 United Microelectronics Corp. ESD detection circuit
CN102315633A (zh) * 2010-07-06 2012-01-11 瑞昱半导体股份有限公司 静电防护电路
CN104979814A (zh) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 一种静电放电保护电路

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