WO2020048081A1 - Goa 电路及液晶面板 - Google Patents

Goa 电路及液晶面板 Download PDF

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Publication number
WO2020048081A1
WO2020048081A1 PCT/CN2019/072522 CN2019072522W WO2020048081A1 WO 2020048081 A1 WO2020048081 A1 WO 2020048081A1 CN 2019072522 W CN2019072522 W CN 2019072522W WO 2020048081 A1 WO2020048081 A1 WO 2020048081A1
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Prior art keywords
signal
level
film transistor
thin film
source
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PCT/CN2019/072522
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English (en)
French (fr)
Inventor
陈帅
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the technical field of liquid crystal panels, and in particular, to a GOA circuit and a liquid crystal panel using the GOA circuit.
  • GOA Gate Drive On Array
  • Figure 1 shows a basic GOA circuit structural unit. These include a pull-up control unit 101, a pull-up unit 102, a signal download unit 103, a pull-down unit 104, a pull-down sustaining unit 105, and a bootstrap capacitor Cbt.
  • the pull-up control unit 101 mainly implements a Q (N) point to implement pre- Charging; the pull-up unit 102 is mainly used to increase the G (N) potential and control the opening of the gate; the signal transmission unit 103 is mainly used to control the opening and closing of the next-stage signal; the pull-down unit 104 is mainly used to pull Low Q (N) point and G (N) potential to VSS; the pull-down maintaining unit 105 mainly controls the Q (N) point and G (N) potential to be maintained at VSS; the bootstrap capacitor Cbt is mainly to increase And maintain the Q (N) point potential.
  • the electronic component in the pull-down sustaining unit 105 is actually an inverter, and its specific circuit structure is shown in FIG. 2.
  • LC is a high-level signal
  • VSS is a low-level signal.
  • a high-potential signal is input at the input terminal Input
  • a low-potential signal is output at the output terminal.
  • the output terminal outputs a high-potential signal. Therefore, taking the 2CK signal as an example, the unipolar GOA circuit structure is shown in FIG. 3, which includes a pull-up control unit 101, a pull-up unit 102, a signal transmission unit 103, a pull-down unit 104, a pull-down maintenance unit 105, and a bootstrap capacitor.
  • Cbt the unipolar GOA circuit structure
  • the liquid crystal panel using GOA technology includes two parts, which are divided into a display area and a GOA circuit area.
  • the requirements of the potential signals are different in these two different areas.
  • the requirements of the potential signals in the display area are that all gates output high potential signals in order to effectively release the charge stored in the pixel through the data line.
  • the GOA circuit area has a potential The signal requirement is that all GOA control signals are low-potential signals in order to ensure that the TFT device in the entire GOA circuit is in an off state to prevent charge residue.
  • the charge in the liquid crystal panel (including the pixel display area and the GOA circuit area) is not released when the power is turned on or off.
  • An object of the present invention is to provide a GOA circuit.
  • the GOA circuit changes a constant voltage low-level signal line into a first voltage source signal line and a second voltage source signal on the basis of the original circuit, and adds a first A thin film transistor, a second thin film transistor, and an external circuit control signal to achieve effective charge release of the liquid crystal panel when it is turned on or off, thereby improving the stability and reliability of the liquid crystal panel.
  • the present invention provides a GOA circuit suitable for a liquid crystal panel, wherein the GOA circuit includes a plurality of cascaded GOA units, and the n-th GOA unit includes: a clock signal source for providing a clock signal of this stage; A pull-up control module is used to receive the n-1 level scanning signal and is controlled by the n-1 level transmission signal to generate a scanning level signal of this level; a pull-up module is used to receive the scanning signal of this level The control of the scanning level signal outputs the clock signal of this stage to the output end of the scanning signal of the stage; the download module is used for receiving the clock signal of the stage and receives the scanning level signal of the stage Control generates an n-th stage transmission signal; a pull-down module is configured to output a first low level provided by a constant voltage low-level source to the scanning signal of the current stage according to the n + 1 stage scanning signal Output terminal; pull-down maintenance module for maintaining the low level of the scanning level signal of the present stage; a bootstrap capacitor for generating
  • the output terminal of the control module is pulled, the source of the second thin film transistor is electrically connected to the first voltage source signal of the constant voltage low level source, and the external circuit control signal is set when the liquid crystal panel is turned off
  • the external circuit control signal changes from low level to high level and turns to zero level after the first predetermined time; when the liquid crystal panel is turned on, the external circuit control signal changes from zero level Turn to high level and turn to a low level after the second predetermined time; the first predetermined time is 5 milliseconds.
  • the present invention also provides a GOA circuit suitable for a liquid crystal panel.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein the n-th GOA unit includes: a constant voltage low level source, the constant voltage is low
  • the level source includes a first voltage source signal and a second voltage source signal, and the first voltage source signal is set to change the first voltage source signal from a low level to a high level when the liquid crystal panel is turned off. And after a first predetermined time, it turns to zero level; when the liquid crystal panel is turned on, the first voltage source signal changes from zero level to high level, and after a second predetermined time, it turns to one.
  • a pull-down sustaining module includes a first thin film transistor and a second thin film transistor and an external circuit control signal; the first The gate of the thin film transistor is electrically connected to The gate of the second thin film transistor, the drain of the first thin film transistor are electrically connected to the output terminal of the scanning signal of this stage, and the source of the first thin film transistor is electrically connected to the constant A second voltage source signal of a low-level source; the drain of the second thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source of the second thin film transistor is electrically connected to the A first voltage source signal of a constant-voltage low-level source; wherein the external circuit control signal is set to switch from a low level to a high level when the liquid
  • the n-th GOA unit further includes: a clock signal source for providing a clock signal of this level; a pull-up control module for receiving the n-1 level scanning signal and receiving the The control of the n-1th stage transmission signal generates the scanning level signal of this stage; the pull-up module is used to be controlled by the scanning level signal of this stage to output the clock signal of this stage to the scanning of this stage A signal output end; a download module for receiving the clock signal of the current stage and controlled by the scan level signal of the current stage to generate an n-th stage transmission signal; a pull-down module for receiving an n + th stage signal Level 1 scanning signal, which outputs the first low level provided by the constant voltage low level source to the output terminal of the scanning signal of the current stage; pull-down maintaining module for maintaining the scanning level signal of the current low Level; bootstrap capacitor for generating the high level of the scanning level signal of this stage; the output of the pull-up control module and the pull-up module, the download module, and the pull-down
  • the pull-up control module includes: an eleventh thin film transistor, a gate of the eleventh thin film transistor receives the n-1th stage signal, and the source is electrically The drain is connected to the output terminal of the pull-up control module, and the drain receives the n-1th scanning signal.
  • the pull-up module includes: a twenty-first thin film transistor, a gate of the twenty-first thin film transistor is electrically connected to an output terminal of the pull-up control module, and a drain
  • the source is electrically connected to the clock signal source, and the source is electrically connected to the output terminal of the scanning signal of the current stage.
  • the download module includes a twenty-second thin film transistor, and a gate of the twenty-second thin film transistor is electrically connected to an output terminal of the pull-up control module.
  • the electrode receives the n-th stage transmission signal, and the drain is electrically connected to the clock signal source.
  • the pull-down module includes: a thirty-first thin film transistor and a forty-first thin film transistor; a gate of the thirty-first thin film transistor is electrically connected to the n + 1th
  • the output terminal of the first-stage scanning signal is electrically connected to the second voltage source signal of the constant-voltage low-level source, and the drain is electrically connected to the output terminal of the current-stage scanning signal; the fortieth
  • the gate of a thin film transistor is electrically connected to the output terminal of the n + 1th stage scanning signal, the source is electrically connected to the first voltage source signal of the constant voltage low-level source, and the drain is electrically connected to the first voltage source signal. Pull up the output of the control module.
  • the pull-down maintaining module further includes: a fifty-first thin film transistor, a fifty-second thin film transistor, a fifty-third thin film transistor, a fifty-fourth thin film transistor, a A forty-second thin film transistor and a thirty-second thin film transistor; a gate and a drain of the fifty-first thin film transistor receive a high-level signal, and a source is electrically connected to the fifty-second thin film transistor And the gate of the 53rd thin film transistor; the gate of the 52nd thin film transistor is electrically connected to the output terminal of the pull-up control module, and the source is electrically connected to the constant A first voltage source signal of a low-level source; the drain of the fifty-third thin film transistor receives the high-level signal, and the source is electrically connected to the drain, The gate of the forty-second thin film transistor and the gate of the thirty-second thin film transistor; the gate of the fifty-fourth thin film transistor is electrically connected to the output terminal and the source of the pull-up control module Electrically connected
  • the high level when the external circuit control signal is turned to a high level, the high level is 30 volts, and when the external circuit control signal is turned to a low level, the low level is -8 Volt.
  • the first predetermined time is 5 milliseconds.
  • the present invention provides a liquid crystal panel including the GOA circuit according to any one of the above.
  • the GOA circuit changes a constant voltage low-level signal line into a first voltage source signal line and a second voltage source signal on the basis of the original circuit, and adds a first thin film transistor and a second thin film transistor and an external circuit. Control signals to achieve effective charge release when the LCD panel is turned on or off, thereby improving the stability and reliability of the LCD panel.
  • the design of the GOA circuit can ensure that the potential signals of the GOA circuit region require that all GOA control signals are low-potential signals in order to ensure that the TFT device in the entire GOA circuit is in an off state to prevent charge from remaining.
  • FIG. 1 is a schematic circuit structure diagram of a GOA circuit structural unit in the prior art.
  • FIG. 2 is a schematic diagram of a Darlington structure inverter.
  • FIG. 3 is a schematic diagram of a unipolar GOA circuit structure in the prior art.
  • FIG. 4 is a connection schematic diagram of a GOA circuit in the embodiment of the present invention.
  • FIG. 5 is a timing diagram of a first voltage source signal, a second voltage source signal, and an external circuit control signal when the liquid crystal panel is turned off in the embodiment of the present invention.
  • FIG. 6 is a timing diagram of a first voltage source signal, a second voltage source signal, and an external circuit control signal when the liquid crystal panel is turned on in the embodiment of the present invention.
  • Embodiments of the present invention provide a GOA circuit and a liquid crystal panel. Each will be described in detail below.
  • a GOA circuit is provided, which is suitable for a liquid crystal panel.
  • the GOA circuit includes a plurality of cascaded GOA units.
  • this embodiment uses multiple cascaded GOA units as an example, and the GOA circuit contains N multiple single-stage GOA units.
  • the structure of all single-stage GOA units is almost the same, and only the first and last stages are fine. Differences, these differences are not related to this application, and therefore will not be described in detail here.
  • the n-th GOA unit includes: a clock signal source CK / XCK, a pull-up control module 401, a pull-up module 402, a download module 403, a pull-down module 404, a pull-down maintenance module 405, a bootstrap capacitor Cbt, and a constant voltage low power Flat source VSS.
  • the clock signal source is used to provide a clock signal CK / XCK of this stage.
  • the pull-up control module 401 is configured to receive the scanning signal G (N-1) of the n-1th stage, and generate the scanning level signal of the current stage under the control of the transmission signal ST (N-1) of the n-1th stage. .
  • the pull-up module 402 is configured to output the clock signal CK / XCK of the current stage to the output terminal of the scanning signal G (N) of the current stage under the control of the scanning level signal of the current stage;
  • the download module 403 is configured to receive the clock signal CK / XCK of the current stage, and generate the n-th stage transmission signal ST (N) under the control of the scan level signal of the current stage;
  • the pull-down module 404 is configured to output a first low level provided by a constant-voltage low-level source to the scanning signal G (N) of the current stage according to the scanning signal G (N + 1) of the n + 1th stage. Output.
  • the pull-down maintaining module 405 is configured to maintain a low level of the scanning level signal G (N) of the current stage.
  • the bootstrap capacitor Cbt is used to generate a high level of the scanning level signal of the current stage.
  • the constant voltage low-level source VSS is used to provide a low level when the liquid crystal panel works normally.
  • the output of the pull-up control module 401 is electrically connected to the pull-up module 402, the download module 403, the pull-down module 404, the pull-down maintenance module 405, and the bootstrap capacitor Cbt;
  • the constant-voltage low-level source VSS is electrically connected to the pull-down maintaining module 405 and the pull-down module 404;
  • the clock signal source CK / XCK is electrically connected to the pull-up module 402 and the download module 403, respectively.
  • the constant voltage low-level source VSS includes a first voltage source signal VSSQ and a second voltage source signal VSSG.
  • the design of the second voltage source signal VSSG of the first voltage source signal VSSQ will be described in detail below.
  • the pull-up control module 401 includes: an eleventh thin-film transistor T11, a gate of the eleventh thin-film transistor T11 receives the n-1th stage signal, and a source is electrically connected to the pull-up The drain of the output terminal of the control module 401 receives the n-1th stage scanning signal.
  • the pull-up module 402 includes: a twenty-first thin film transistor T21, a gate of the twenty-first thin film transistor T21 is electrically connected to an output terminal of the pull-up control module 401, and a drain is electrically connected to all
  • the clock signal source CK / XCK is electrically connected to the output terminal of the scanning signal of the current stage.
  • the download module 403 includes: a twenty-second thin film transistor T22, a gate of the twenty-second thin film transistor T22 is electrically connected to an output terminal of the pull-up control module 401, and a source receives the first N-stage signals are transmitted, and the drain is electrically connected to the clock signal source CK / XCK.
  • the pull-down module 404 includes: a thirty-first thin film transistor T31 and a forty-first thin film transistor T41; the gate of the thirty-first thin film transistor T31 is electrically connected to the output of the n + 1th stage scan signal Terminal, the source is electrically connected to the second voltage source signal VSSG of the constant-voltage low-level source VSS, and the drain is electrically connected to the output terminal of the scanning signal of this stage; the forty-first thin film transistor The gate of T41 is electrically connected to the output terminal of the n + 1th stage scanning signal, the source is electrically connected to the first voltage source signal VSSQ of the constant voltage low-level source VSS, and the drain is electrically connected to the first voltage source signal VSSQ. An output terminal of the pull-up control module 401.
  • the pull-down maintaining module 405 includes a fifty-first thin film transistor T51, a fifty-second thin film transistor T52, a fifty-third thin film transistor T53, a fifty-fourth thin film transistor T54, and a forty-second thin film.
  • the drain and the gate of the 53rd thin film transistor T53; the gate of the 52nd thin film transistor T52 is electrically connected to the output terminal of the pull-up control module 401, and the source is electrically connected to The first voltage source signal VSSQ of the constant-voltage low-level source VSS; the drain of the fifty-third thin-film transistor T53 receives the high-level signal, and the source is electrically connected to the fifty-fourth thin-film transistor
  • the drain of T54, the gate of the 42nd thin film transistor T42, and the gate of the 32nd thin film transistor T32; the gate of the 54th thin film transistor T54 is electrically connected to the upper Pull the output of the control module 401, the source is electrically connected A first voltage source signal VSSQ to the constant voltage low level source VSS; a source of the forty-second thin film transistor T42 is electrically connected to the first voltage source signal VSSQ of the constant voltage low level source VSS A drain is electrically connected to the output terminal of the pull-up control module 401; a
  • the first voltage source signal VSSQ is set when the liquid crystal panel is turned off (turn off), the first voltage source signal VSSQ changes from a low level L to a high level H, and after a first predetermined time, it turns to a zero level GND; when the liquid crystal panel is turned on (turn When on), the first voltage source signal VSSQ is changed from a zero-level GND to a high-level H, and after a second predetermined time, it is changed to a low-level L.
  • the first predetermined time is 5 milliseconds.
  • the second predetermined time is 5 milliseconds, and of course, the first predetermined time and the second predetermined time are not limited thereto.
  • the second voltage source signal VSSG is set such that when the liquid crystal panel is turned off, the second voltage source signal VSSG maintains a low level and turns to a zero level after the first predetermined time; When the LCD panel is turned on (turn When on), the second voltage source signal VSSG changes from a zero level to a low level.
  • the pull-down maintaining module 405 further includes a first thin film transistor and a second thin film transistor, and an external circuit control signal.
  • a first thin film transistor is represented by a thirty-fourth thin film transistor T34
  • a second thin film transistor is represented by a forty-fourth thin film transistor T44.
  • the gate of the thirty-fourth thin film transistor T34 is electrically connected to the gate of the forty-fourth thin film transistor T44
  • the drain of the thirty-fourth thin film transistor T34 is electrically connected to the main body.
  • An output terminal of the scanning signal, the source of the thirty-fourth thin film transistor T34 is electrically connected to the second voltage source signal VSSG of the constant voltage low-level source VSS; the forty-fourth thin film transistor T44 Is electrically connected to the output terminal of the pull-up control module 401, and the source of the forty-fourth thin film transistor T44 is electrically connected to the first voltage source signal VSSQ of the constant-voltage low-level source VSS. .
  • the external circuit control signal Discharge is set such that when the liquid crystal panel is turned off, the external circuit control signal Discharge is changed from a low level L to a high level H, and is changed after the first predetermined time. Is a zero-level GND; when the liquid crystal panel is powered on, the external circuit control signal is changed from a zero-level GND to a high-level H, and after a second predetermined time, the external-circuit control signal is changed to a low-level L.
  • the high level is 30 volts
  • the external circuit control signal Discharge changes to a low level L the low level It is -8 volts.
  • the 34th thin film transistor T34 and the 44th thin film transistor T44 are turned off because the external circuit control signal Discharge is a low potential signal. Therefore, the level transmission of the GOA circuit in this embodiment is not affected by the newly added TFT device.
  • the external circuit control signal Discharge is pulled up to a high potential signal, so that the thirty-fourth thin film transistor T34 and the forty-fourth thin film transistor T44 are turned on.
  • the reference point G (N) set at the output end of the scanning signal at this stage is pulled up to a high potential signal by the second voltage source signal VSSG through the thirty-fourth thin film transistor T34.
  • the gates in the display area are all output High-level signal to effectively discharge the charge stored in the pixel through the data line.
  • the reference point Q (N) provided at the output of the pull-up control module 401 is pulled to a low-potential signal by the 44th thin-film transistor T44.
  • all GOA control signals in the GOA circuit area are low-potential signals, so that Ensure that the TFT device in the entire GOA circuit is turned off to prevent charge from remaining.
  • the second voltage source signal VSSG is at zero potential GND when the power is turned off. After the power is turned on, the second voltage source signal VSSG is first pulled up to a high potential (H) signal, and after a second predetermined time, outputs a low potential (L) signal.
  • the first voltage source signal VSSQ is at zero potential GND when the power is turned off. After the power-on operation is performed, it is first pulled to a low potential (L) signal and maintains the low potential (L) signal output.
  • the external circuit control signal is at zero potential GND at the time of shutdown, and is first pulled up to a high potential (H) signal after the start-up action is performed, and after a second predetermined time is maintained, a low potential (L) signal is output.
  • the external circuit control signal is pulled up to a high potential (H) signal, so the 34th thin film transistor T34 and the 44th thin film transistor T44 are turned on.
  • the reference point G (N) set at the output end of the scanning signal at this stage is pulled up to a high potential (H) signal by the second voltage source signal VSSG through the 34th thin film transistor T34.
  • the gate in the display area Each pole outputs a high-level signal to effectively discharge the charge stored in the pixel through the data line.
  • the reference point Q (N) set at the output of the pull-up control module 401 is pulled to a low potential (L) signal by the 44th thin film transistor T44.
  • all GOA control signals in the GOA circuit area are low potential. Signal in order to ensure that the TFT device in the entire GOA circuit is in an off state to prevent charge from remaining.
  • the liquid crystal panel is effectively discharged when it is turned on or off, thereby improving the stability and reliability of the liquid crystal panel.
  • the design of the GOA circuit can ensure that the potential signals of the GOA circuit region require that all GOA control signals are low-potential signals in order to ensure that the TFT device in the entire GOA circuit is in an off state to prevent charge from remaining.
  • the present invention provides a liquid crystal panel including the GOA circuit according to any one of the above.
  • the GOA circuit for the structure and working principle of the GOA circuit, reference may be made to the implementation of the GOA circuit described above, and details are not described herein again.

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  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种GOA电路，适用于液晶面板， GOA电路包括级联的多个GOA单元。GOA电路通过在原有电路的基础上将恒压低电平信号线改成第一电压源信号线和第二电压源信号，并且新增第一薄膜晶体管（T34）和第二薄膜晶体管（T44）和一外电路控制信号（Discharge），以实现液晶面板在开机或关机时进行有效地电荷释放，从而提高液晶面板的稳定性和可靠性。

Description

GOA电路及液晶面板 技术领域
本发明涉及液晶面板技术领域，尤其涉及一种GOA电路以及采用该GOA电路的液晶面板。
 背景技术
现有的液晶显示装置的发展已呈现出窄边框、薄型化和低成本的发展趋势，在此其中， GOA(Gate Drive On Array，阵列基板行驱动)技术成为一项重要的技术。GOA的基本概念是将TFT LCD（薄膜晶体管液晶显示器）的栅极驱动电路集成在玻璃基板上，形成对液晶面板的扫描驱动。GOA相比传统的利用COF（覆盖薄膜）的驱动技术不但可以大幅度节约制造成本，而且省去了栅极侧的bonding（打线）制程，对产能提升也是极为有利的。因此，GOA是未来液晶面板发展的重点技术。
图1显示了一种基本的GOA电路结构单元。其中包括上拉控制单元101、上拉单元102、信号下传单元103、下拉单元104、下拉维持单元105以及自举电容Cbt，其中所述上拉控制单元101主要为Q(N)点实现预充电；所述上拉单元102主要为提高G（N）电位，控制栅极的打开；所述信号下传单元103主要为控制下一级信号的打开和关闭；所述下拉单元104主要为拉低Q（N）点、G（N）电位至VSS；所述下拉维持单元105主要为控制Q(N)点、G（N）电位维持在VSS不变；所述自举电容Cbt主要为提高并维持Q(N)点电位。
其中，下拉维持单元105中的电子元件实际上为一种反相器，其具体电路结构如图2所示。LC为高电平信号、VSS为低电平信号，当输入端Input输入高电位信号时，输出端Output输出低电位信号，当输入端输入低电位信号时，输出端输出高电位信号。因此，以2CK信号为例，单极GOA电路结构为图3所示，其包括上拉控制单元101、上拉单元102、信号下传单元103、下拉单元104、下拉维持单元105以及自举电容Cbt。
 技术问题
开机、关机时液晶面板的稳定性是十分重要的。通常情况下，采用GOA技术的液晶面板对此包含两部分内容，即区分为显示区域和GOA电路区域。这两个不同的区域对电位信号的要求也是不同的，显示区域对电位信号的要求是所有栅极均输出高电位信号以便将像素中存储的电荷通过数据线进行有效释放，GOA电路区域对电位信号的要求是所有GOA控制信号均为低电位信号以便保证整个GOA电路中的TFT器件处于关闭状态以防止电荷残留。然而，在实际使用过程中，开机或关机时未对液晶面板（包括像素显示区和GOA电路区）中的电荷做释放处理。
故，需提供一种GOA电路以解决现有技术中的问题。
 技术解决方案
本发明的目的在于，提供一种GOA电路，所述GOA电路通过在原有电路的基础上将恒压低电平信号线改成第一电压源信号线和第二电压源信号，并且新增第一薄膜晶体管和第二薄膜晶体管和一外电路控制信号，以实现液晶面板在开机或关机时进行有效地电荷释放，从而提高液晶面板的稳定性和可靠性。
本发明提供了一种GOA电路，适用于液晶面板，其中所述GOA电路包括级联的多个GOA单元，第n级GOA单元包括：一时钟信号源，用于提供本级的时钟信号；一上拉控制模块，用于接收第n-1级扫描信号，并受第n-1级级传信号的控制生成本级的扫描电平信号；一上拉模块，用于受所述本级的扫描电平信号的控制，将本级的时钟信号输出至本级的扫描信号的输出端；一下传模块，用于接收所述本级的时钟信号，并受所述本级的扫描电平信号的控制生成第n级级传信号；一下拉模块，用于根据第n+1级扫描信号，将恒压低电平源所提供的第一低电平输出至所述本级的扫描信号的输出端；一下拉维持模块，用于维持所述本级的扫描电平信号低电平；一自举电容，用于生成所述本级的扫描电平信号的高电平；一恒压低电平源，所述恒压低电平源包括第一电压源信号和第二电压源信号，所述第一电压源信号设置为当所述液晶面板关机时，所述第一电压源信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第一电压源信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平；所述第二电压源信号设置为当所述液晶面板关机时，维持低电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第二电压源信号由零电平转为一低电平；所述上拉控制模块的输出端与所述上拉模块、所述下传模块、所述下拉模块、所述下拉维持模块及所述自举电容电性连接；所述恒压低电平源与所述下拉维持模块和所述下拉模块电性连接；所述时钟信号源分别与所述上拉模块和所述下传模块电性连接；其中，所述下拉维持模块包括一第一薄膜晶体管和一第二薄膜晶体管以及一外电路控制信号；所述第一薄膜晶体管的栅极电性连接至所述第二薄膜晶体管的栅极，所述第一薄膜晶体管的漏极电性连接至所述本级的扫描信号的输出端，所述第一薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号；所述第二薄膜晶体管的漏极电性连接至所述上拉控制模块的输出端，所述第二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号；所述外电路控制信号设置为当所述液晶面板关机时，所述外电路控制信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述外电路控制信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平；所述第一预定时间为5毫秒。
本发明还提供了一种GOA电路，适用于液晶面板，所述GOA电路包括级联的多个GOA单元，其中，第n级GOA单元包括：一恒压低电平源，所述恒压低电平源包括第一电压源信号和第二电压源信号，所述第一电压源信号设置为当所述液晶面板关机时，所述第一电压源信号由低电平转为高电平，并且经过一第一预定时间后转为零电平；当所述液晶面板开机时，所述第一电压源信号由零电平转为高电平，并且经过一第二预定时间后转为一低电平；所述第二电压源信号设置为当所述液晶面板关机时，维持低电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第二电压源信号由零电平转为一低电平；一下拉维持模块，所述下拉维持模块包括一第一薄膜晶体管和一第二薄膜晶体管以及一外电路控制信号；所述第一薄膜晶体管的栅极电性连接至所述第二薄膜晶体管的栅极，所述第一薄膜晶体管的漏极电性连接至所述本级的扫描信号的输出端，所述第一薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号；所述第二薄膜晶体管的漏极电性连接至所述上拉控制模块的输出端，所述第二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号；其中，所述外电路控制信号设置为当所述液晶面板关机时，所述外电路控制信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述外电路控制信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平。
在本发明的一实施例中，所述第n级GOA单元还包括：时钟信号源，用于提供本级的时钟信号；上拉控制模块，用于接收第n-1级扫描信号，并受第n-1级级传信号的控制生成本级的扫描电平信号；上拉模块，用于受所述本级的扫描电平信号的控制，将本级的时钟信号输出至本级的扫描信号的输出端；下传模块，用于接收所述本级的时钟信号，并受所述本级的扫描电平信号的控制生成第n级级传信号；下拉模块，用于根据第n+1级扫描信号，将恒压低电平源所提供的第一低电平输出至所述本级的扫描信号的输出端；下拉维持模块，用于维持所述本级的扫描电平信号低电平；自举电容，用于生成所述本级的扫描电平信号的高电平；所述上拉控制模块的输出端与所述上拉模块、所述下传模块、所述下拉模块、所述下拉维持模块及所述自举电容电性连接；所述恒压低电平源与所述下拉维持模块和所述下拉模块电性连接；所述时钟信号源分别与所述上拉模块和所述下传模块电性连接。
在本发明的一实施例中，所述上拉控制模块包括：一第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收所述第n-1级级传信号，源极电性连接至所述上拉控制模块的输出端，漏极接收第n-1级扫描信号。
在本发明的一实施例中，所述上拉模块包括：一第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，漏极电性连接至所述时钟信号源，源极电性连接至所述本级的扫描信号的输出端。
在本发明的一实施例中，所述下传模块包括：一第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极接收所述第n级级传信号，漏极电性连接至所述时钟信号源。
在本发明的一实施例中，所述下拉模块包括：一第三十一薄膜晶体管和一第四十一薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源的第二电压源信号，漏极电性连接至所述本级的扫描信号的输出端；所述第四十一薄膜晶体管的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源的第一电压源信号，漏极电性连接至所述上拉控制模块的输出端。
在本发明的一实施例中，所述下拉维持模块还包括：一第五十一薄膜晶体管、一第五十二薄膜晶体管、一第五十三薄膜晶体管、一第五十四薄膜晶体管、一第四十二薄膜晶体管和一第三十二薄膜晶体管；所述第五十一薄膜晶体管的栅极以及漏极接收一高电平信号，源极电性连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；所述第五十二薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极电性连接于所述恒压低电平源的第一电压源信号；所述第五十三薄膜晶体管的漏极接收所述高电平信号，源极电性连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；所述第五十四薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极电性连接至所述恒压低电平源的第一电压源信号；所述第四十二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号，漏极电性连接至所述上拉控制模块的输出端；所述第三十二薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号，漏极接收所述本级的扫描信号。
在本发明的一实施例中，当所述外电路控制信号转为高电平时，所述高电平为30伏，当外电路控制信号转为低电平时，所述低电平为-8伏。
在本发明的一实施例中，所述第一预定时间为5毫秒。
另外，本发明提供一种液晶面板，其包括上述任一所述的GOA电路。
 有益效果
所述GOA电路通过在原有电路的基础上将恒压低电平信号线改成第一电压源信号线和第二电压源信号，并且新增第一薄膜晶体管和第二薄膜晶体管和一外电路控制信号，以实现液晶面板在开机或关机时进行有效地电荷释放，从而提高液晶面板的稳定性和可靠性。另外，所述GOA电路的设计能够保证GOA电路区域对电位信号的要求是所有GOA控制信号均为低电位信号以便保证整个GOA电路中的TFT器件处于关闭状态以防止电荷残留。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的GOA电路结构单元的电路结构示意图。
图2是达灵顿结构反相器的示意图。
图3是现有技术中的单极GOA电路结构示意图。
图4是本发明所述实施例中的GOA电路的连接示意图。
图5是本发明所述实施例中的液晶面板关机时的第一电压源信号、第二电压源信号和外电路控制信号的时序示意图。
图6是本发明所述实施例中的液晶面板开机时的第一电压源信号、第二电压源信号和外电路控制信号的时序示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本发明公开的原理的各实施例仅用于说明，而不应解释为限制本发明公开的范围。所属领域的技术人员将理解，本发明的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本发明说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本发明的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本发明说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本发明说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
本发明实施例提供一种GOA电路及液晶面板。以下将分别进行详细说明。
参见图4所示，在本发明的一实施例中，提供一种GOA电路，适用于液晶面板，所述GOA电路包括级联的多个GOA单元。
需注意的是，本实施例是以级联的多个GOA单元为例，而GOA电路中包含N个多单级GOA单元，所有单级GOA单元的结构几乎完全相同，仅在首尾级存在细微差异，这些差异与本申请无关，因此，在此不再详述。
其中，第n级GOA单元包括：时钟信号源CK/XCK、上拉控制模块401、上拉模块402、下传模块403、下拉模块404、下拉维持模块405、自举电容Cbt以及恒压低电平源VSS。
所述时钟信号源用于提供本级的时钟信号CK/XCK。
所述上拉控制模块401用于接收第n-1级扫描信号G(N-1)，并受第n-1级级传信号ST(N-1)的控制生成本级的扫描电平信号。
所述上拉模块402用于受所述本级的扫描电平信号的控制，将本级的时钟信号CK/XCK输出至本级的扫描信号G（N）的输出端；
所述下传模块403用于接收所述本级的时钟信号CK/XCK，并受所述本级的扫描电平信号的控制生成第n级级传信号ST(N)；
所述下拉模块404用于根据第n+1级扫描信号G(N+1)，将恒压低电平源所提供的第一低电平输出至所述本级的扫描信号G（N）的输出端。
所述下拉维持模块405用于维持所述本级的扫描电平信号G（N）低电平。
所述自举电容Cbt用于生成所述本级的扫描电平信号的高电平。
所述恒压低电平源VSS用于所述液晶面板正常工作时提供一低电平。
所述上拉控制模块401的输出端与所述上拉模块402、所述下传模块403、所述下拉模块404、所述下拉维持模块405及所述自举电容Cbt电性连接；所述恒压低电平源VSS与所述下拉维持模块405和所述下拉模块404电性连接；所述时钟信号源CK/XCK分别与所述上拉模块402和所述下传模块403电性连接。
以下将进一步说明每一个模块的结构。
所述恒压低电平源VSS包括第一电压源信号VSSQ和第二电压源信号VSSG。其中第一电压源信号VSSQ的第二电压源信号VSSG的设计将在下文中具体描述。
所述上拉控制模块401包括：一第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极接收所述第n-1级级传信号，源极电性连接至所述上拉控制模块401的输出端，漏极接收第n-1级扫描信号。
所述上拉模块402包括：一第二十一薄膜晶体管T21，所述二十一薄膜晶体管T21的栅极电性连接至所述上拉控制模块401的输出端，漏极电性连接至所述时钟信号源CK/XCK，源极电性连接至所述本级的扫描信号的输出端。
所述下传模块403包括：一第二十二薄膜晶体管T22，所述第二十二薄膜晶体管T22的栅极电性连接至所述上拉控制模块401的输出端，源极接收所述第n级级传信号，漏极电性连接至所述时钟信号源CK/XCK。
所述下拉模块404包括：一第三十一薄膜晶体管T31和一第四十一薄膜晶体管T41；所述第三十一薄膜晶体管T31的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源VSS的第二电压源信号VSSG，漏极电性连接至所述本级的扫描信号的输出端；所述第四十一薄膜晶体管T41的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源VSS的第一电压源信号VSSQ，漏极电性连接至所述上拉控制模块401的输出端。
所述下拉维持模块405包括：一第五十一薄膜晶体管T51、一第五十二薄膜晶体管T52、一第五十三薄膜晶体管T53、一第五十四薄膜晶体管T54、一第四十二薄膜晶体管T42和一第三十二薄膜晶体管T32；所述第五十一薄膜晶体管T51的栅极以及漏极接收一高电平信号，源极电性连接于所述第五十二薄膜晶体管T52的漏极以及所述第五十三薄膜晶体管T53的栅极；所述第五十二薄膜晶体管T52的栅极电性连接至所述上拉控制模块401的输出端，源极电性连接于所述恒压低电平源VSS的第一电压源信号VSSQ；所述第五十三薄膜晶体管T53的漏极接收所述高电平信号，源极电性连接至所述第五十四薄膜晶体管T54的漏极、所述第四十二薄膜晶体管T42的栅极以及所述第三十二薄膜晶体管T32的栅极；所述第五十四薄膜晶体管T54的栅极电性连接至所述上拉控制模块401的输出端，源极电性连接至所述恒压低电平源VSS的第一电压源信号VSSQ；所述第四十二薄膜晶体管T42的源极电性连接至所述恒压低电平源VSS的第一电压源信号VSSQ，漏极电性连接至所述上拉控制模块401的输出端；所述第三十二薄膜晶体管T32的源极电性连接至所述恒压低电平源VSS的第二电压源信号VSSG，漏极接收所述本级的扫描信号。
参见图5和图6所示，在本实施例中，所述第一电压源信号VSSQ设置为当所述液晶面板关机（turn off）时，所述第一电压源信号VSSQ由低电平L转为高电平H，并且经过一第一预定时间后转为零电平GND；当所述液晶面板开机（turn on）时，所述第一电压源信号VSSQ由零电平GND转为高电平H，并且经过一第二预定时间后转为一低电平L。在本实施例中，所述第一预定时间为5毫秒。所述第二预定时间为5毫秒，当然，所述第一预定时间和所述第二预定时间不限于此。
所述第二电压源信号VSSG设置为当所述液晶面板关机（turn off）时，所述第二电压源信号VSSG维持低电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机（turn on）时，所述第二电压源信号VSSG由零电平转为一低电平。
另外，所述下拉维持模块405还包括一第一薄膜晶体管和一第二薄膜晶体管以及一外电路控制信号。在本实施例中，以第三十四薄膜晶体管T34表示第一薄膜晶体管，以第四十四薄膜晶体管T44表示第二薄膜晶体管。其中，所述第三十四薄膜晶体管T34的栅极电性连接至所述第四十四薄膜晶体管T44的栅极，所述第三十四薄膜晶体管T34的漏极电性连接至所述本级的扫描信号的输出端，所述第三十四薄膜晶体管T34的源极电性连接至所述恒压低电平源VSS的第二电压源信号VSSG；所述第四十四薄膜晶体管T44的漏极电性连接至所述上拉控制模块401的输出端，所述第四十四薄膜晶体管T44的源极电性连接至所述恒压低电平源VSS的第一电压源信号VSSQ。
所述外电路控制信号Discharge设置为当所述液晶面板关机(Turn off)时，所述外电路控制信号Discharge由低电平L转为高电平H，并且经过所述第一预定时间后转为零电平GND；当所述液晶面板开机时，所述外电路控制信号由零电平GND转为高电平H，并且经过所述第二预定时间后转为一低电平L。
在本实施例中，当所述外电路控制信号Discharge转为高电平H时，所述高电平为30伏，当外电路控制信号Discharge转为低电平L时，所述低电平为-8伏。
如图6所示，在液晶面板正常显示时，由于外电路控制信号Discharge为一低电位信号，第三十四薄膜晶体管T34和第四十四薄膜晶体管T44处于关闭状态。因此，在本实施例中的GOA电路的级传并不会受到新增TFT器件的影响。当液晶面板执行关机动作后，所述外电路控制信号Discharge被拉升至一高电位信号，于是第三十四薄膜晶体管T34和第四十四薄膜晶体管T44处于开启状态。设置在本级的扫描信号的输出端的参考点G（N）通过第三十四薄膜晶体管T34被第二电压源信号VSSG拉升至一高电位信号，此时，显示区域所述栅极均输出高电平信号，以便将像素中存储的电荷通过数据线进行有效释放。而设置在所述上拉控制模块401的输出端的参考点Q（N）通过第四十四薄膜晶体管T44拉至一低电位信号，此时GOA电路区域所有GOA控制信号均为低电位信号，以便保证整个GOA电路中的TFT器件处于关闭状态，以防止电荷残留。
同样的，在液晶面板执行开机(Turn on)动作时，相应的信号波形如图6所示。在此设置下可以将液晶面板中残存的电荷或由于静电等方式积累的电荷在正常显示之前有效释放。
在液晶面板执行开机动作时，相应的信号波形如图6所示。第二电压源信号VSSG在关机时为零电位GND，执行开机后先拉升至一高电位(H)信号，在持续第二预定时间后，输出低电位(L)信号。第一电压源信号VSSQ在关机时为零电位GND，执行开机动作后先拉至一低电位(L)信号，并维持低电位(L)信号输出。外电路控制信号在关机时为零电位GND，执行开机动作后先拉升至一高电位(H)信号，维持一第二预定时间后，输出一低电位(L)信号。
当液晶面板执行开机动作后，所述外电路控制信号被拉升至一高电位(H)信号，于是第三十四薄膜晶体管T34和第四十四薄膜晶体管T44处于开启状态。设置在本级的扫描信号的输出端的参考点G（N）通过第三十四薄膜晶体管T34被第二电压源信号VSSG拉升至一高电位(H)信号，此时，显示区域所述栅极均输出高电平信号，以便将像素中存储的电荷通过数据线进行有效释放。而设置在所述上拉控制模块401的输出端的参考点Q（N）通过第四十四薄膜晶体管T44拉至一低电位(L)信号，此时GOA电路区域所有GOA控制信号均为低电位信号，以便保证整个GOA电路中的TFT器件处于关闭状态，以防止电荷残留。
因此，通过上述的GOA电路设计，实现液晶面板在开机或关机时进行有效地电荷释放，从而提高液晶面板的稳定性和可靠性。另外，所述GOA电路的设计能够保证GOA电路区域对电位信号的要求是所有GOA控制信号均为低电位信号以便保证整个GOA电路中的TFT器件处于关闭状态以防止电荷残留。
另外，本发明提供一种液晶面板，其包括上述任一所述的GOA电路。其中，所述GOA电路的结构及工作原理可以参见上述的GOA电路的实施所述，在此不再赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (11)

  1. 一种GOA电路，适用于液晶面板，其中所述GOA电路包括级联的多个GOA单元，第n级GOA单元包括：
    一时钟信号源，用于提供本级的时钟信号；
    一上拉控制模块，用于接收第n-1级扫描信号，并受第n-1级级传信号的控制生成本级的扫描电平信号；
    一上拉模块，用于受所述本级的扫描电平信号的控制，将本级的时钟信号输出至本级的扫描信号的输出端；
    一下传模块，用于接收所述本级的时钟信号，并受所述本级的扫描电平信号的控制生成第n级级传信号；
    一下拉模块，用于根据第n+1级扫描信号，将恒压低电平源所提供的第一低电平输出至所述本级的扫描信号的输出端；
    一下拉维持模块，用于维持所述本级的扫描电平信号低电平；
    一自举电容，用于生成所述本级的扫描电平信号的高电平；
    一恒压低电平源，所述恒压低电平源包括第一电压源信号和第二电压源信号，所述第一电压源信号设置为当所述液晶面板关机时，所述第一电压源信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第一电压源信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平；所述第二电压源信号设置为当所述液晶面板关机时，维持低电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第二电压源信号由零电平转为一低电平；
    所述上拉控制模块的输出端与所述上拉模块、所述下传模块、所述下拉模块、所述下拉维持模块及所述自举电容电性连接；所述恒压低电平源与所述下拉维持模块和所述下拉模块电性连接；所述时钟信号源分别与所述上拉模块和所述下传模块电性连接；
    其中，所述下拉维持模块包括一第一薄膜晶体管和一第二薄膜晶体管以及一外电路控制信号；所述第一薄膜晶体管的栅极电性连接至所述第二薄膜晶体管的栅极，所述第一薄膜晶体管的漏极电性连接至所述本级的扫描信号的输出端，所述第一薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号；所述第二薄膜晶体管的漏极电性连接至所述上拉控制模块的输出端，所述第二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号；所述外电路控制信号设置为当所述液晶面板关机时，所述外电路控制信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述外电路控制信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平；所述第一预定时间为5毫秒。
  2. 一种GOA电路，适用于液晶面板，其中所述GOA电路包括级联的多个GOA单元，第n级GOA单元包括：
    一恒压低电平源，所述恒压低电平源包括第一电压源信号和第二电压源信号，所述第一电压源信号设置为当所述液晶面板关机时，所述第一电压源信号由低电平转为高电平，并且经过一第一预定时间后转为零电平；当所述液晶面板开机时，所述第一电压源信号由零电平转为高电平，并且经过一第二预定时间后转为一低电平；所述第二电压源信号设置为当所述液晶面板关机时，维持低电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述第二电压源信号由零电平转为一低电平；
    一下拉维持模块，所述下拉维持模块包括一第一薄膜晶体管和一第二薄膜晶体管以及一外电路控制信号；所述第一薄膜晶体管的栅极电性连接至所述第二薄膜晶体管的栅极，所述第一薄膜晶体管的漏极电性连接至所述本级的扫描信号的输出端，所述第一薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号；所述第二薄膜晶体管的漏极电性连接至所述上拉控制模块的输出端，所述第二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号；其中，所述外电路控制信号设置为当所述液晶面板关机时，所述外电路控制信号由低电平转为高电平，并且经过所述第一预定时间后转为零电平；当所述液晶面板开机时，所述外电路控制信号由零电平转为高电平，并且经过所述第二预定时间后转为一低电平。
  3. 根据权利要求2所述的GOA电路，其特征在于，所述第n级GOA单元还包括：
    一时钟信号源，用于提供本级的时钟信号；
    一上拉控制模块，用于接收第n-1级扫描信号，并受第n-1级级传信号的控制生成本级的扫描电平信号；
    一上拉模块，用于受所述本级的扫描电平信号的控制，将本级的时钟信号输出至本级的扫描信号的输出端；
    一下传模块，用于接收所述本级的时钟信号，并受所述本级的扫描电平信号的控制生成第n级级传信号；
    一下拉模块，用于根据第n+1级扫描信号，将恒压低电平源所提供的第一低电平输出至所述本级的扫描信号的输出端；
    一下拉维持模块，用于维持所述本级的扫描电平信号低电平；
    一自举电容，用于生成所述本级的扫描电平信号的高电平；
    所述上拉控制模块的输出端与所述上拉模块、所述下传模块、所述下拉模块、所述下拉维持模块及所述自举电容电性连接；所述恒压低电平源与所述下拉维持模块和所述下拉模块电性连接；所述时钟信号源分别与所述上拉模块和所述下传模块电性连接。
  4. 根据权利要求3所述的GOA电路，其特征在于，所述上拉控制模块包括：一第十一薄膜晶体管，所述第十一薄膜晶体管的栅极接收所述第n-1级级传信号，源极电性连接至所述上拉控制模块的输出端，漏极接收第n-1级扫描信号。
  5. 根据权利要求3所述的GOA电路，其特征在于，所述上拉模块包括：一第二十一薄膜晶体管，所述二十一薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，漏极电性连接至所述时钟信号源，源极电性连接至所述本级的扫描信号的输出端。
  6. 根据权利要求3所述的GOA电路，其特征在于，所述下传模块包括：一第二十二薄膜晶体管，所述第二十二薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极接收所述第n级级传信号，漏极电性连接至所述时钟信号源。
  7. 根据权利要求3所述的GOA电路，其特征在于，所述下拉模块包括：一第三十一薄膜晶体管和一第四十一薄膜晶体管；所述第三十一薄膜晶体管的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源的第二电压源信号，漏极电性连接至所述本级的扫描信号的输出端；所述第四十一薄膜晶体管的栅极电性连接至第n+1级扫描信号的输出端，源极电性连接至所述恒压低电平源的第一电压源信号，漏极电性连接至所述上拉控制模块的输出端。
  8. 根据权利要求3所述的GOA电路，其特征在于，所述下拉维持模块还包括：一第五十一薄膜晶体管、一第五十二薄膜晶体管、一第五十三薄膜晶体管、一第五十四薄膜晶体管、一第四十二薄膜晶体管和一第三十二薄膜晶体管；所述第五十一薄膜晶体管的栅极以及漏极接收一高电平信号，源极电性连接于所述第五十二薄膜晶体管的漏极以及所述第五十三薄膜晶体管的栅极；所述第五十二薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极电性连接于所述恒压低电平源的第一电压源信号；所述第五十三薄膜晶体管的漏极接收所述高电平信号，源极电性连接至所述第五十四薄膜晶体管的漏极、所述第四十二薄膜晶体管的栅极以及所述第三十二薄膜晶体管的栅极；所述第五十四薄膜晶体管的栅极电性连接至所述上拉控制模块的输出端，源极电性连接至所述恒压低电平源的第一电压源信号；所述第四十二薄膜晶体管的源极电性连接至所述恒压低电平源的第一电压源信号，漏极电性连接至所述上拉控制模块的输出端；所述第三十二薄膜晶体管的源极电性连接至所述恒压低电平源的第二电压源信号，漏极接收所述本级的扫描信号。
  9. 根据权利要求2所述的GOA电路，其特征在于，当所述外电路控制信号转为高电平时，所述高电平为30伏，当外电路控制信号转为低电平时，所述低电平为-8伏。
  10. 根据权利要求2所述的GOA电路，其特征在于，所述第一预定时间为5毫秒。
  11. 一种液晶面板，其特征在于，包括权利要求2-10任一所述的GOA电路。
PCT/CN2019/072522 2018-09-03 2019-01-21 Goa 电路及液晶面板 Ceased WO2020048081A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN108962178B (zh) * 2018-09-03 2020-02-18 深圳市华星光电技术有限公司 Goa电路及液晶面板
CN109493783B (zh) * 2018-12-21 2020-10-13 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN109509459B (zh) * 2019-01-25 2020-09-01 深圳市华星光电技术有限公司 Goa电路及显示装置
CN111161689B (zh) * 2020-02-12 2021-07-06 武汉华星光电技术有限公司 一种goa电路及其显示面板
CN111402828A (zh) * 2020-04-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 Goa电路和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
CN105185293A (zh) * 2015-10-19 2015-12-23 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置
CN107146590A (zh) * 2017-07-06 2017-09-08 深圳市华星光电技术有限公司 Goa电路的驱动方法
CN108257568A (zh) * 2018-02-01 2018-07-06 京东方科技集团股份有限公司 移位寄存器、栅极集成驱动电路、显示面板及显示装置
CN108320717A (zh) * 2018-02-06 2018-07-24 深圳市华星光电技术有限公司 一种goa驱动电路及其制备的液晶显示面板
CN108962178A (zh) * 2018-09-03 2018-12-07 深圳市华星光电技术有限公司 Goa电路及液晶面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080064928A (ko) * 2007-01-06 2008-07-10 삼성전자주식회사 액정 표시 장치 및 액정 표시 장치의 잔상 제거 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164915A1 (en) * 2008-12-29 2010-07-01 Hak-Gyu Kim Gate driving circuit and display device having the gate driving circuit
CN105185293A (zh) * 2015-10-19 2015-12-23 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置
CN107146590A (zh) * 2017-07-06 2017-09-08 深圳市华星光电技术有限公司 Goa电路的驱动方法
CN108257568A (zh) * 2018-02-01 2018-07-06 京东方科技集团股份有限公司 移位寄存器、栅极集成驱动电路、显示面板及显示装置
CN108320717A (zh) * 2018-02-06 2018-07-24 深圳市华星光电技术有限公司 一种goa驱动电路及其制备的液晶显示面板
CN108962178A (zh) * 2018-09-03 2018-12-07 深圳市华星光电技术有限公司 Goa电路及液晶面板

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