WO2020042311A1 - 阵列基板、显示面板及显示器 - Google Patents

阵列基板、显示面板及显示器 Download PDF

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Publication number
WO2020042311A1
WO2020042311A1 PCT/CN2018/111486 CN2018111486W WO2020042311A1 WO 2020042311 A1 WO2020042311 A1 WO 2020042311A1 CN 2018111486 W CN2018111486 W CN 2018111486W WO 2020042311 A1 WO2020042311 A1 WO 2020042311A1
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WIPO (PCT)
Prior art keywords
layer
passivation layer
sub
array substrate
display area
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/111486
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English (en)
French (fr)
Inventor
杨艳娜
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US16/311,332 priority Critical patent/US20200127016A1/en
Publication of WO2020042311A1 publication Critical patent/WO2020042311A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G02F2201/501—Blocking layers, e.g. against migration of ions

Definitions

  • the present application relates to the field of display technology, and more particularly, to an array substrate, a display panel, and a display.
  • a liquid crystal display (Liquid Crystal Display, LCD) is a commonly used electronic device. Because of its low power consumption, small size, and light weight, it is widely favored by users.
  • the current liquid crystal display devices are mainly based on thin film transistor (TFT) liquid crystal displays (TFT-LCD).
  • the liquid crystal display mainly includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel is mainly composed of a thin film transistor substrate (Thin Film Transistor).
  • TFT substrate Substrate
  • CF substrate color filter substrate
  • liquid crystal layer sandwiched between the two substrates.
  • a frame adhesive is coated around the two substrates and a liquid crystal layer is injected into the frame adhesive.
  • the frame adhesive is cured to obtain a liquid crystal display panel structure.
  • a thin film transistor substrate that is, an array substrate 100 'is generally composed of a display area 10' and a non-display area 11 'around the display area 10'.
  • the display area 10 ' is provided with a plurality of scanning lines 113' and a plurality of data lines 114 '.
  • TCO Chip on Array
  • the WOA trace 112 ' is disposed on the substrate 12' and is composed of a first metal layer 1120 'and a second metal layer 1122', and one of the first metal layer 1120 'and the second metal layer 1122' There is an insulating layer 1121 'between them, and the second metal layer 1122' is also covered with a passivation layer (PV) 1123 '.
  • PV passivation layer
  • the overlap height of the overlapping area of the two-layer metal layer is so large that it is deposited on the second metal layer 1122'.
  • the upper passivation layer 1123 ' is thinly formed there.
  • the frame adhesive around the liquid crystal display panel is fixed.
  • the area of thin film formation of the passivation layer 1123' increased, and the overall film formation quality was reduced. It is easy to cause water vapor to invade due to environmental changes. In the two metal layers 1122 ', water vapor enters the array substrate 100' and generates bubbles, which causes the WOA trace 112 'and then the array substrate 100' to be severely corroded, which affects the quality of the panel.
  • the purpose of the embodiments of the present application is to provide an array substrate to solve the problem that WO A traces are easily eroded by water vapor and corroded.
  • the technical solution adopted in the embodiments of the present application is to provide an array substrate including a substrate base layer, wherein the substrate base layer is provided with a display area and a non-display area, and the non-display area Comprising a plurality of flip-chip thin film connection traces provided on the substrate base layer;
  • the chip-on-film connection traces include:
  • a surface of the passivation layer has a hydrophobic layer.
  • a flip-chip thin film connection trace of a non-display area includes a first metal layer provided on the substrate base layer and an insulating layer provided on the first metal layer.
  • the lower second metal layer further prevents corrosion of the flip-chip thin film connection traces in the non-display area and prevents water vapor from further invading the display area, ensuring that The display effect of the display area of the array substrate further ensures the display quality of the display panel and the display, and improves the service life.
  • An object of the embodiments of the present application is to provide a display panel including an array substrate
  • the array substrate includes a substrate base layer, and a display area and a non-display area are provided on the substrate base layer.
  • the non-display area includes a plurality of flip-chip thin film connection traces provided on the substrate base layer.
  • the flip-chip film connection trace includes:
  • a passivation layer provided on the second metal layer
  • a surface of the passivation layer has a hydrophobic layer
  • the passivation layer includes a first sub-passivation layer provided on the second metal layer and a second sub-passivation layer provided on the first sub-passivation layer, and the hydrophobic layer is provided On the surface of the second sub-passivation layer; the thickness of the first sub-passivation layer is 200-230 nm, and the thickness of the second sub-passivation layer is less than 230 nm.
  • a flip-chip thin film connection trace of a non-display area of an array substrate includes a first metal layer provided on the substrate base layer and a first metal layer provided.
  • the passivation layer, the thickness of the first sub-passivation layer is 200-230 nm, and the thickness of the second sub-passivation layer is less than 230 nm, which increases the thickness of the passivation layer and further ensures the display effect of the display area of the array substrate. , Thereby ensuring the display quality of the display panel and the monitor and improving the service life.
  • An object of the embodiments of the present application is to provide a display including a display panel, where the display panel includes an array substrate;
  • the array substrate includes a base substrate layer, and the base substrate layer is provided with a display area and a non-display area, and the non-display area includes a plurality of flip-chip thin film connection traces provided on the base substrate layer. ;
  • the flip-chip film connection trace includes: [0028] a first metal layer provided on the substrate base layer;
  • the surface of the passivation layer has a hydrophobic layer.
  • a flip-chip connection line of a non-display area in an array substrate of a display panel, includes a first metal layer provided on the substrate base layer, and a first metal layer provided on the substrate base layer.
  • the display quality of the display panel and the monitor improves the service life.
  • FIG. 1 is a structural diagram of an exemplary array substrate
  • FIG. 2 is an enlarged view of a structure of a flip-chip film connection trace in a dotted frame in FIG. 1;
  • FIG. 3 is a cross-sectional view of the flip-chip film connection trace in FIG. 2 along line A-A;
  • FIG. 4 is a schematic plan view of the array substrate provided by the first embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional structure view of the array substrate of FIG. 4 along line B-B;
  • FIG. 6 is a schematic cross-sectional structure diagram of an array substrate provided by a second embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structure diagram of an array substrate according to a third embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a liquid crystal display panel according to a fourth embodiment of the present application.
  • the present application provides an array substrate 100, which includes a substrate base layer 10, the substrate base layer 10 includes a display area 1 and a non-display area 2 disposed on the periphery of the display area 1, a display There are a plurality of data lines 12 and a plurality of scanning lines 11 in the area 1.
  • the plurality of data lines 12 extend in the column direction and are arranged at intervals in the row direction.
  • the plurality of scan lines 11 extend in the row direction and are arranged at intervals in the column direction.
  • the scanning lines 11 and the data lines 12 intersect to define a plurality of pixel regions.
  • the non-display area 2 includes a timing controller 21 configured to provide a data signal to the data line 12 and a scanning signal to the scanning line 11.
  • the timing controller 21 and the scanning line 11 and the data line 12 pass through a plurality of flip-chip films 22. (COF) signal.
  • At least one flip-chip film connection line 23 is provided in the non-display area 2, and a plurality of flip-chip films 22 are connected through the flip-chip film connection line 23.
  • the flip-chip thin film connection trace 23 includes a first metal layer 23 provided on the substrate base layer 10, an insulating layer 232 provided on the first metal layer 231, and The second metal layer 233 on the insulating layer 232 and the passivation layer 234 provided on the second metal layer 233 have a hydrophobic layer 2340 on the surface.
  • the flip-chip thin film connection wiring 23 of the non-display area 2 includes a first metal layer 231 and a second metal layer 233 separated by an insulating layer 232, and is disposed on the second metal.
  • the passivation layer 234 on the layer 233 can block the invasion route of water vapor by providing a hydrophobic layer 2340 on the surface of the passivation layer 234, even if the edges of the first metal layer 231 and the second metal layer 233 are aligned due to height.
  • the poor film thickness of the passivation layer 234 can also effectively prevent water vapor from penetrating the second metal layer 233 through the passivation layer 234 at the difference, and prevent the flip-chip thin film from connecting the wiring 23 and the display of the array substrate 100.
  • Water vapor in zone 1 Corrosion ensures the sealing effect of the array substrate 100 and the display quality in the display area 1.
  • the width of the flip-chip connection line 23 is 20-30 microns.
  • the non-display area 2 is also configured to be bonded to the array substrate 100 and the color filter substrate 200 through a frame adhesive 400 to form a liquid crystal display panel 60 (described in detail below).
  • the frame adhesive 400 is disposed above the flip-chip film connection line 23 There is at least a part of overlap with the flip-chip thin film connection traces 23.
  • a plurality of through-holes are provided on the flip-chip thin film connection traces 23, For ultraviolet radiation to pass through.
  • the width of the through hole (along the width direction of the flip-chip connection line 23) is 1-10 micrometers, and optionally, 1-6 micrometers.
  • the length of the through hole (along the length direction of the flip-chip film connection line 23) is 1-15 microns, and optionally, 1-10 microns.
  • the material of the passivation layer 234 is an inorganic material of silicon oxide (SiOx) or silicon nitride (SiNx), and the thickness of the passivation layer 234 is 200-230. Nanometer.
  • the passivation layer 234 is treated with fluorine ions to form a hydrophobic layer 2340 on the surface of the passivation layer 234. The specific steps are: ionizing a mixed gas obtained by mixing 0?
  • the ionized mixed gas performs dry etching on the surface of the passivation layer 234 of the inorganic material, and the surface of the passivation layer 234 forms a hydrophobic group, thereby obtaining a hydrophobic layer 2340.
  • a gate and a scan line 11 are formed on the substrate base layer 10
  • a gate insulating layer is formed on the gate and the scan line
  • an active layer is formed on the gate insulating layer.
  • the source / drain and data lines 12 are formed on the active layer.
  • the gate, the active layer and the source / drain constitute a TFT (thin film transistor, not shown), and a passivation layer is formed on the TFT.
  • the thickness of the passivation layer on the TFT located in the display area 1 is 200-200 nm, that is, the flip-chip film located in the non-display area 2 connects the passivation layer 2340 of the wiring 23 and the TFF located in the display area 1.
  • the passivation layer has the same thickness and can be formed by the same chemical vapor deposition process. After the deposition is formed, only the passivation layer 234 located in the non-display region can be subjected to hydrophobic treatment.
  • the material of the passivation layer 234 is an inorganic material of silicon oxide (SiOx) or silicon nitride (SiNx), and the thickness of the passivation layer 234 is greater than 230 nanometers.
  • the passivation layer 234 is processed with fluorine ions to form a hydrophobic layer 2340 on the surface of the passivation layer 234, and the specific steps are: CF 4 or SF 6 is mixed with.
  • the mixed gas obtained after the mixing is ionized, and the surface of the passivation layer 234 of the inorganic material is dry-etched using the ionized mixed gas, and hydrophobic groups are formed on the surface of the passivation layer 234 to obtain a hydrophobic layer 2340.
  • the thickness of the passivation layer 234 is larger, which can further improve the first gold
  • the film-forming quality of the passivation layer 234 at the overlapping edges of the metal layer 231 and the second metal layer 233 improves the water vapor barrier ability of the passivation layer 234.
  • the thickness of the passivation layer 234 is 230-300 nanometers, or 300-400 nanometers, or 400-460 nanometers.
  • the thickness of the passivation layer 234 in the non-display area 2 is greater than that of the T FT in the display area 1.
  • it can be formed by one chemical vapor deposition
  • the passivation layer portion on the TFT located in the display area 1 is removed, so that the thickness of the passivation layer 234 of the flip-chip thin film connection trace 23 is maintained above 230 nm, and The passivation layer on the TFT located in the display area 1 is maintained at 200-230 nm.
  • the passivation layer 234 includes a first sub-passivation layer 2341 provided on the second metal layer 233, and a The second sub-passivation layer 2342 and the hydrophobic layer 2340 are formed on the surface of the second sub-passivation layer 2342.
  • the sum of the thicknesses of the first sub-passivation layer 2341 and the second sub-passivation layer 2342 is greater than 230 nm.
  • the thickness of the first sub-passivation layer 2341 is 200-230 nm
  • the thickness of the second sub-passivation layer 2342 is 230 nm or less, such as 70 nm or less, 70-170 nm, or 170-230 nm
  • the thickness of the passivation layer 234 is 230-460 nm.
  • the material of the first sub-passivation layer 2341 is an inorganic material of silicon oxide (SiOx) or silicon nitride (SiNx), and the material of the second sub-passivation layer 2342 is an organic material, such as an organic photoresist material.
  • the first sub-passivation layer 2341 of the passivation layer 234 is performed according to a conventional manufacturing process of the array substrate 100.
  • the first sub-passivation layer 2341 is formed on the same layer as the passivation layer deposited on the TFT in the display area 1, and the second The sub-passivation layer 2342 is deposited on the first sub-passivation layer 2341 by depositing an organic photoresist material after exposure, development, and etching.
  • the method for hydrophobically treating the second sub-passivation layer 2342 of the organic photoresist material is: ionizing a mixed gas obtained by mixing CF 4 or SF 6 with 02 , and using the ionized mixture
  • the surface of the second sub-passivation layer 2342 of the organic photoresist material is dry-etched by a gas, and the surface of the second sub-passivation layer 2342 forms a hydrophobic group, thereby obtaining a hydrophobic layer 2340.
  • the materials of the first sub-passivation layer 2341 and the second sub-passivation layer 2342 are both inorganic materials of silicon oxide (SiOx) or silicon nitride (SiNx), and the first sub-passivation layer 2341 and The passivation layer deposited on the TFT in the display area 1 is formed in the same layer, which will not be described again. Then, the second sub-passivation layer 2341 performs another chemical treatment on the non-display area 2 only. Obtained by a vapor deposition method.
  • the first metal layer 231, the insulating layer 232, and the second metal layer 23 in the flip-chip thin film connection line 23 are formed simultaneously with the scan lines 11 and the data lines 12 in the display area 1, that is, the first The metal layer 231 may be formed in the same layer as the gate of the TFT in the display region 1 and the scan line 11, the insulating layer 232 may be formed in the same layer as the gate insulating layer of the TFT in the display region 1, and the second metal layer 233 may be formed with the data Line 12, the source / drain of the TFT are formed in the same layer.
  • the first metal layer 231 does not have to be a metal, and may be a single metal layer, such as chromium (Cr), molybdenum (Mo), copper
  • the thickness of the first metal layer 231 is 200-800 nm, and optionally, it is 200-550 nm.
  • the second metal layer 233 also does not have to be a metal, and may be a single metal layer, such as a single metal layer of chromium (Cr), molybdenum (Mo), copper (Cu), or titanium (Ti) material. It can be a stack of the same metal material, or a composite metal layer of different metal materials, such as a molybdenum / stroke (Mo / Al) composite layer.
  • the thickness of the second metal layer 233 is 200-800 nm, and optionally, it is 200-550 nm.
  • the material of the insulating layer 232 is at least one of silicon oxide (SiOx) and silicon nitride (SiNx), and is deposited on the first metal layer 231 by a chemical vapor deposition method.
  • the thickness of the insulating layer 232 is 100-300 nm.
  • a fourth embodiment of the present application provides a liquid crystal display panel 60, which includes the array substrate 100 described in the first to third embodiments and a color filter substrate 200 disposed opposite the array substrate 100.
  • the peripheral region of the array substrate 100 is provided with a frame adhesive 400 which is arranged to be bonded to the color film substrate 200 and is located above the flip-chip thin film connection line 23.
  • the width of the flip-chip thin film connection line 23 is 20-30 micrometers.
  • the film connection wiring 23 is provided with a plurality of through-holes through which ultraviolet light is irradiated. The ultraviolet light is irradiated from the array substrate 100 to the frame adhesive 400.
  • the frame adhesive 400 is cured to obtain a liquid crystal display panel 60.
  • the surface of the passivation layer 234 of the flip-chip thin film connection wiring 23 in the non-display area 2 of the array substrate 100 has a hydrophobic layer 2340, which can prevent water vapor from being connected to the wiring 23 by the flip-chip film.
  • the present application further provides a liquid crystal display (not shown), which includes the liquid crystal display panel 60 described in the fourth embodiment and a backlight module provided on an array substrate 100 side.
  • a liquid crystal display (not shown), which includes the liquid crystal display panel 60 described in the fourth embodiment and a backlight module provided on an array substrate 100 side.
  • the surface of the passivation layer 234 in the non-display region 2 of the array substrate 100 of the liquid crystal panel has a hydrophobic layer 2340 on the surface of the passivation layer 234, which can prevent water vapor from being connected by the flip-chip film.
  • 23 double-layer metal overlapping edge regions
  • the passivation layer 234 of the domain penetrates, and has better sealing effect and display quality.

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Abstract

一种阵列基板(100)、显示面板(60)和显示器，包括覆晶薄膜连接走线(23)，覆晶薄膜连接走线(23)包括第一金属层(231)、绝缘层(232)、第二金属层(233)和钝化层(234)；钝化层(234)的表面具有疏水层(2340)。

Description

发明名称：阵列基板、 显示面板及显示器
技术领域
[0001] 本申请涉及显示技术领域， 更具体地说， 是涉及一种阵列基板、 显示面板及显 示器。
背景技术
[0002] 液晶显示器 (Liquid Crystal Display， LCD)是一种常用的电子设备， 由于其具有 功耗低、 体积小、 重量轻等特性， 因此广泛受到用户青睐。 目前的液晶显示装 置主要是以薄膜晶体管 (Thin Film Transistor, TFT)液晶显示器 (TFT-LCD)为主。
[0003] 液晶显示器主要包括液晶显示面板及背光模组。 其中， 液晶显示面板主要由一 薄膜晶体管基板 (Thin Film Transistor
Substrate, TFT基板)、 一彩色滤光基板 (Color Filter Substrate， CF基板)， 以及夹 设于两基板之间的一液晶层。 在对盒组装 (Cell)制程中， 会在两基板的四周涂布 框胶并于框胶内注入液晶层， 将框胶进行固化后得到一液晶显示面板结构。
[0004] 薄膜晶体管基板 (TFT基板)， 也即阵列基板 100’通常由显示区 10’及显示区 10’外 围的非显示区 11’构成。 显示区 10’内设有多条扫描线 113’和多条数据线 114’， 数 据线 114’和扫描线 113’的交叉设置限定多个像素区域， 设置为向数据线 114’提供 数据信号和向扫描线 113’提供扫描信号的时序控制器 (TC0N) 110’设置在非显示 区 11’， 并通过若干个覆晶薄膜 l l l’(ChiP on Film, COF)将数据信号和扫描信号传 输至显示区 10’， 如图 1所示。 WOA(Wire on Array)走线 112’设置为两 COF 111’之 间传递信号。 为了减小 WOA走线 112’的阻值， 以防止在两个 COF之间产生扫描 电压的降低， 一般采用双层金属互叠设计布线， 并且双层金属边切齐。 如图 3中 所示， WOA走线 112’设于衬底 12’上， 由第一金属层 1120’和第二金属层 1122’构 成， 第一金属层 1120’和第二金属层 1122’之间为绝缘层 1121’， 第二金属层 1122’ 上还覆盖有純化层 (Passivation layer， PV) 1123’， 双层金属层的互叠区边缘高度 差大， 致使沉积于第二金属层 1122’上的钝化层 1123’在该处成膜偏薄。 并且， 为 了能够从阵列基板 100’一侧对框胶进行紫外光照射使液晶显示面板四周的框胶固 化， WOA走线 112’与框胶重叠的部分要有一定的透光率， 因此， WOA走线 112’ 设置为镂空的形式， 形成多个孔 115’， 如图 2所示， 钝化层 1123’在孔 115’与孔 11 5’之间多次被抬升和降低， 钝化层 1123’成膜偏薄的区域增多， 整体成膜质量降 低， 很容易因为环境变化而使水汽攻入第二金属层 1122’， 水汽进入阵列基板 100 ’内部产生气泡， 使 WOA走线 112’进而阵列基板 100’受到严重腐蚀， 影响面板显 不品质。
[0005] 基于以上所述， 有必要提供一种能够防止水汽侵入 WOA走线处的金属层的阵 列基板结构。
发明概述
技术问题
[0006] 本申请实施例的目的在于提供一种阵列基板， 以解决 WO A走线容易受水汽侵 入而被腐蚀的问题。
问题的解决方案
技术解决方案
[0007] 为解决上述技术问题， 本申请实施例采用的技术方案是： 提供一种阵列基板， 包括衬底基层， 所述衬底基层上设有显示区和非显示区， 所述非显示区包括多 条设于所述衬底基层上的覆晶薄膜连接走线；
[0008] 所述覆晶薄膜连接走线包括：
[0009] 第一金属层， 设于所述衬底基层上；
[0010] 绝缘层， 设于所述第一金属层上；
[0011] 第二金属层， 设于所述绝缘层上； 以及
[0012] 钝化层， 设于所述第二金属层上；
[0013] 所述钝化层的表面具有疏水层。
[0014] 本申请实施例提供的一种阵列基板中， 非显示区的覆晶薄膜连接走线包括设于 所述衬底基层上的第一金属层、 设于第一金属层上的绝缘层、 设于所述绝缘层 上的第二金属层， 以及设于所述第二金属层上的钝化层， 所述钝化层的表面为 疏水层， 疏水层能够有效阻止水汽侵入钝化层下方的第二金属层， 进而防止了 非显示区的覆晶薄膜连接走线被腐蚀以及防止水汽进一步侵入显示区， 保证了 阵列基板的显示区的显示效果， 进而保证了显示面板和显示器的显示品质， 提 高使用寿命。
[0015] 本申请实施例的目的还在于提供一种显示面板， 包括阵列基板；
[0016] 所述阵列基板包括衬底基层， 所述衬底基层上设有显示区和非显示区， 所述非 显示区包括多条设于所述衬底基层上的覆晶薄膜连接走线；
[0017] 所述覆晶薄膜连接走线包括：
[0018] 第一金属层， 设于所述衬底基层上；
[0019] 绝缘层， 设于所述第一金属层上；
[0020] 第二金属层， 设于所述绝缘层上； 以及
[0021] 钝化层， 设于所述第二金属层上；
[0022] 所述钝化层的表面具有疏水层；
[0023] 所述钝化层包括设于所述第二金属层上的第一子钝化层以及设于所述第一子钝 化层上的第二子钝化层， 所述疏水层设于所述第二子钝化层的表面； 所述第一 子钝化层的厚度为 200-230纳米， 所述第二子钝化层的厚度为 230纳米以下。
[0024] 本申请实施例提供的一种显示面板中， 其阵列基板的非显示区的覆晶薄膜连接 走线包括设于所述衬底基层上的第一金属层、 设于第一金属层上的绝缘层、 设 于所述绝缘层上的第二金属层， 以及设于所述第二金属层上的钝化层， 所述钝 化层的表面为疏水层， 疏水层能够有效阻止水汽侵入钝化层下方的第二金属层 ， 进而防止了非显示区的覆晶薄膜连接走线被腐蚀以及防止水汽进一步侵入显 示区， 并且， 钝化层包括第一子钝化层和第二子钝化层， 第一子钝化层的厚度 为 200-230纳米， 第二子钝化层的厚度为 230纳米以下， 提高了钝化层的厚度， 进 一步保证了阵列基板的显示区的显示效果， 进而保证了显示面板和显示器的显 示品质， 提高使用寿命。
[0025] 本申请实施例的目的还在于提供一种显示器， 包括显示面板， 所述显示面板包 括阵列基板；
[0026] 所述阵列基板包括衬底基层， 所述衬底基层上设有显示区和非显示区， 所述非 显示区包括多条设于所述衬底基层上的覆晶薄膜连接走线；
[0027] 所述覆晶薄膜连接走线包括： [0028] 第一金属层， 设于所述衬底基层上；
[0029] 绝缘层， 设于所述第一金属层上；
[0030] 第二金属层， 设于所述绝缘层上； 以及
[0031] 钝化层， 设于所述第二金属层上；
[0032] 所述钝化层的表面具有疏水层。
[0033] 本申请实施例提供的一种显示器， 其显示面板的阵列基板中， 非显示区的覆晶 薄膜连接走线包括设于所述衬底基层上的第一金属层、 设于第一金属层上的绝 缘层、 设于所述绝缘层上的第二金属层， 以及设于所述第二金属层上的钝化层 ， 所述钝化层的表面为疏水层， 疏水层能够有效阻止水汽侵入钝化层下方的第 二金属层， 进而防止了非显示区的覆晶薄膜连接走线被腐蚀以及防止水汽进一 步侵入显示区， 保证了阵列基板的显示区的显示效果， 进而保证了显示面板和 显示器的显示品质， 提高使用寿命。
发明的有益效果
对附图的简要说明
附图说明
[0034] 为了更清楚地说明本申请实施例中的技术方案， 下面将对实施例或现有技术描 述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是 本申请的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性 的前提下， 还可以根据这些附图获得其他的附图。
[0035] 图 1是范例性的阵列基板的结构图；
[0036] 图 2是图 1中的虚线框内的覆晶薄膜连接走线的结构的放大图；
[0037] 图 3是图 2中的覆晶薄膜连接走线沿 A-A线的剖面图；
[0038] 图 4是本申请第一实施例提供的阵列基板的俯视结构示意图；
[0039] 图 5是图 4的阵列基板沿 B-B线的剖面结构示意图；
[0040] 图 6是本申请第二实施例提供的阵列基板的剖面结构示意图；
[0041] 图 7是本申请第三实施例提供的阵列基板的剖面结构示意图；
[0042] 图 8是本申请第四实施例提供的液晶显示面板的结构示意图。
发明实施例 本发明的实施方式
[0043] 为了使本申请所要解决的技术问题、 技术方案及有益效果更加清楚明白， 以下 结合附图及实施例， 对本申请进行进一步详细说明。 应当理解， 此处所描述的 具体实施例仅仅用以解释本申请， 并不用于限定本申请。
[0044] 需要说明的是， 当元件被称为“设置于”另一个元件， 它可以直接在另一个元件 上或者间接在该另一个元件上。 当一个元件被称为是“连接于”另一个元件， 它可 以是直接连接到另一个元件或间接连接至该另一个元件上。 此外， 术语“第一”、 “第二”仅用于描述目的， 而不能理解为指示或暗示相对重要性或者隐含指明所指 示的技术特征的数量。 由此， 限定有“第一”、 “第二”的特征可以明示或者隐含地 包括一个或者更多个该特征。 在本实用新型的描述中， “多个”的含义是两个或两 个以上， 除非另有明确具体的限定。
[0045] 请参阅图 4和图 5， 本申请提供一种阵列基板 100， 包括衬底基层 10， 衬底基层 1 0上包括显示区 1和设于显示区 1外围的非显示区 2, 显示区 1内设有多条数据线 12 和多条扫描线 11， 多条数据线 12沿列方向延伸并沿行方向间隔排列， 多条扫描 线 11沿行方向延伸并沿列方向间隔排列， 多条扫描线 11和多条数据线 12交叉限 定出多个像素区域。 非显示区 2内包括设置为向数据线 12提供数据信号和向扫描 线 11提供扫描信号的时序控制器 21， 时序控制器 21与扫描线 11和数据线 12之间 通过多个覆晶薄膜 22(COF)传递信号。 非显示区 2内设有至少一条覆晶薄膜连接 走线 23， 多个覆晶薄膜 22之间通过覆晶薄膜连接走线 23连接。
[0046] 如图 5至图 7所示， 覆晶薄膜连接走线 23包括设于衬底基层 10上的第一金属层 23 1、 设于第一金属层 231上的绝缘层 232、 设于绝缘层 232上的第二金属层 233， 以 及设于第二金属层 233上的钝化层 234， 钝化层 234的表面具有疏水层 2340。
[0047] 本申请提供的阵列基板 100, 其非显示区 2的覆晶薄膜连接走线 23包括由绝缘层 232间隔开的第一金属层 231和第二金属层 233， 以及设于第二金属层 233上的钝 化层 234, 通过在钝化层 234的表面上设置疏水层 2340, 能够阻断水汽的入侵路 线， 即使在第一金属层 231和第二金属层 233的边缘对齐处因高度差而造成钝化 层 234的成膜厚度偏薄， 也能够有效防止水汽经由该段差处的钝化层 234侵入第 二金属层 233 , 防止该覆晶薄膜连接走线 23和阵列基板 100的显示区 1内受到水汽 腐蚀， 保证了阵列基板 100的密封效果和显示区 1内的显示品质。
[0048] 如图 4所示， 覆晶薄膜连接走线 23的宽度为 20-30微米。 非显示区 2还设置为与 阵列基板 100与彩膜基板 200之间通过框胶 400粘接以形成液晶显示面板 60 (下文 会具体描述) ， 框胶 400设置于覆晶薄膜连接走线 23上方， 与覆晶薄膜连接走线 23有至少一部分重合， 为能够从阵列基板 100—侧对非显示区 2的框胶 400进行照 射固化， 覆晶薄膜连接走线 23上设有多个通孔， 供紫外线照射通过。
[0049] 通孔的宽度 (沿覆晶薄膜连接走线 23的宽度方向) 为 1-10微米， 可选地， 为 1-6 微米。 通孔的长度 (沿着覆晶薄膜连接走线 23的长度方向) 为 1-15微米， 可选地 ， 为 1-10微米。
[0050] 在本申请图 5所示的第一实施例中， 钝化层 234的材料为氧化硅 (SiOx)或氮化硅( SiNx)的无机材料， 钝化层 234的厚度为 200-230纳米。 具体地， 采用氟离子对钝 化层 234进行处理以在钝化层 234的表面形成疏水层 2340, 具体步骤为： 将 0? 4或 者 SF 6与0 2混合后得到的混合气体进行电离， 利用电离后的混合气体对无机材料 的钝化层 234表面进行干蚀刻， 钝化层 234的表面形成疏水基团， 从而得到疏水 层 2340。
[0051] 对于显示区 1而言， 在衬底基层 10上形成了栅极和扫描线 11， 在栅极和扫描线 上形成了栅极绝缘层， 在栅极绝缘层上形成了有源层， 在有源层上形成了源 /漏 极和数据线 12, 栅极、 有源层和源 /漏极构成了一个 TFT (薄膜晶体管， 未图示 ) ， 并在 TFT上形成了钝化层。 位于显示区 1内的 TFT上的钝化层的厚度为 200-23 0纳米， 即， 位于非显示区 2内的覆晶薄膜连接走线 23的钝化层 2340与位于显示 区 1内的 TFF上的钝化层厚度相同， 可由同一化学气相沉积工艺形成， 沉积形成 后仅对位于非显示区的钝化层 234进行疏水处理即可。
[0052] 在本申请图 6所示的第二实施例中， 钝化层 234的材料为氧化硅 (SiOx)或氮化硅( SiNx)的无机材料， 钝化层 234的厚度为大于 230纳米。 具体地， 采用氟离子对钝 化层 234进行处理以在该钝化层 234的表面形成疏水层 2340, 具体步骤为： 将 CF 4 或者 SF 6与。 2混合后得到的混合气体进行电离， 利用电离后的混合气体对无机材 料的钝化层 234表面进行干蚀刻， 钝化层 234的表面形成疏水基团， 从而得到疏 水层 2340。 相较于第一实施例， 钝化层 234的厚度更大， 能够进一步改善第一金 属层 231和第二金属层 233重叠边缘处钝化层 234的成膜质量， 提高钝化层 234对 水汽的阻挡能力。
[0053] 可选地， 钝化层 234的厚度为 230-300纳米， 或者为 300-400纳米， 或者为 400-46 0纳米。
[0054] 在第二实施例中， 位于非显示区 2内的钝化层 234的厚度大于位于显示区 1内的 T FT上的钝化层， 这种情况下， 可以通过一次化学气相沉积形成一层厚度大于 230 纳米的钝化层后， 将位于显示区 1的 TFT上的钝化层部分去除， 既使得覆晶薄膜 连接走线 23的钝化层 234的厚度保持在 230纳米以上， 又使得位于显示区 1的 TFT 上的钝化层保持在 200-230纳米。
[0055] 在本申请图 7所示的第三实施例中， 钝化层 234包括设于第二金属层 233上的第 一子钝化层 2341以及设于第一子钝化层 2341上的第二子钝化层 2342， 疏水层 234 0形成于第二子钝化层 2342的表面。 第一子钝化层 2341和第二子钝化层 2342的厚 度之和大于 230纳米。
[0056] 具体地， 第一子钝化层 2341的厚度为 200-230纳米， 第二子钝化层 2342的厚度 为 230纳米以下， 例如 70纳米以下、 70-170纳米或 170-230纳米， 钝化层 234的厚 度为 230-460纳米。
[0057] 可选地， 第一子钝化层 2341的材料为氧化硅 (SiOx)或氮化硅 (SiNx)的无机材料 ， 第二子钝化层 2342的材料为有机材料， 如有机光阻材料。 该钝化层 234的第一 子钝化层 2341按照阵列基板 100的常规制作过程进行， 例如， 第一子钝化层 2341 与显示区 1内 TFT上沉积的钝化层同层形成， 第二子钝化层 2342通过沉积一层有 机光阻材料， 经曝光、 显影和蚀刻后保留于第一子钝化层 2341上。
[0058] 具体地， 对该有机光阻材料的第二子钝化层 2342进行疏水处理的方式为： 将 CF 4或者 SF 6与0 2混合后得到的混合气体进行电离， 利用电离后的混合气体对有机 光阻材料的第二子钝化层 2342表面进行干蚀刻， 第二子钝化层 2342的表面形成 疏水基团， 从而得到疏水层 2340。
[0059] 可选地， 第一子钝化层 2341和第二子钝化层 2342的材料均为氧化硅 (SiOx)或氮 化硅 (SiNx)的无机材料， 第一子钝化层 2341与显示区 1内 TFT上沉积的钝化层同 层形成， 不再赘述。 然后， 第二子钝化层 2341为仅对非显示区 2进行另一次化学 气相沉积法而得到。
[0060] 具体地， 覆晶薄膜连接走线 23中的第一金属层 231、 绝缘层 232和第二金属层 23 3与显示区 1内的扫描线 11、 数据线 12同时形成， 即第一金属层 231可以与显示区 1内的 TFT的栅极、 扫描线 11同层形成， 绝缘层 232可以与显示区 1内的 TFT的栅 极绝缘层同层形成， 第二金属层 233可以与数据线 12、 TFT的源 /漏极同层形成。
[0061] 第一金属层 231并不必须是一层金属， 可以是单金属层， 如铬 (Cr)、 钼 (Mo)、 铜
(Cu)、 钛 (Ti)， 也可以是同一金属材料的叠层， 还可以是不同金属材料的复合金 属层， 如钼 /招 (Mo/Al)复合层。 第一金属层 231的厚度为 200-800纳米， 可选地， 为 200-550纳米。
[0062] 第二金属层 233同样并不必须是一层金属， 可以是单金属层， 如铬 (Cr)、 钼 (Mo) 、 铜 (Cu)、 钛 (Ti)材料的单金属层， 也可以是同一金属材料的叠层， 还可以是不 同金属材料的复合金属层， 如钼 /招 (Mo/Al)复合层。 第二金属层 233的厚度为 200- 800纳米， 可选地， 为 200-550纳米。
[0063] 绝缘层 232的材料为氧化硅 (SiOx)和氮化硅 (SiNx)的至少一种， 通过化学气相沉 积法沉积于第一金属层 231上。 绝缘层 232的厚度为 100-300纳米。
[0064] 如图 8所示， 本申请第四实施例提供一种液晶显示面板 60， 包括上述第一至三 实施例所说的阵列基板 100以及与该阵列基板 100相对设置的彩膜基板 200, 阵列 基板 100的外围区设有设置为与彩膜基板 200粘接且位于覆晶薄膜连接走线 23上 方的框胶 400， 覆晶薄膜连接走线 23的宽度为 20-30微米， 覆晶薄膜连接走线 23上 设有多个供紫外光照射通过的通孔， 紫外光从阵列基板 100—侧照射至框胶 400 ， 框胶 400固化后得到液晶显示面板 60。 本申请的液晶显示面板 60中， 阵列基板 100的非显示区 2内的覆晶薄膜连接走线 23的钝化层 234的表面具有疏水层 2340， 能够防止水汽由该覆晶薄膜连接走线 23的双层金属重叠的边缘区域的钝化层 234 侵入， 具有较佳的密封效果和显示品质。
[0065] 本申请还提供一种液晶显示器 (未图示)， 包括上述第四实施例所说的液晶显示 面板 60以及设于阵列基板 100—侧的背光模组。 本申请的液晶显示器中， 液晶面 板的阵列基板 100的非显示区 2内的覆晶薄膜连接走线 23的钝化层 234的表面具有 疏水层 2340， 能够防止水汽由该覆晶薄膜连接走线 23的双层金属重叠的边缘区 域的钝化层 234侵入， 具有较佳的密封效果和显示品质。
[0066] 以上所述仅为本申请的可选实施例而已， 并不用以限制本申请， 凡在本申请的 精神和原则之内所作的任何修改、 等同替换和改进等， 均应包含在本申请的保 护范围之内。

Claims

权利要求书
[权利要求 1] 一种阵列基板， 包括衬底基层， 所述衬底基层上设有显示区和非显示 区， 所述非显示区包括多条设于所述衬底基层上的覆晶薄膜连接走线 所述覆晶薄膜连接走线包括：
第一金属层， 设于所述衬底基层上；
绝缘层， 设于所述第一金属层上；
第二金属层， 设于所述绝缘层上； 以及
钝化层， 设于所述第二金属层上； 所述钝化层的表面具有疏水层。
[权利要求 2] 如权利要求 1所述的阵列基板， 所述钝化层的厚度为 200-460纳米。
[权利要求 3] 如权利要求 2所述的阵列基板， 所述钝化层的厚度为 200-230纳米。
[权利要求 4] 如权利要求 2所述的阵列基板， 所述钝化层的厚度为 230-300纳米， 或
300-400纳米， 或 400-460纳米。
[权利要求 5] 如权利要求 2所述的阵列基板， 所述钝化层的材料为氧化硅或氮化硅 中的至少一种。
[权利要求 6] 如权利要求 1所述的阵列基板， 所述钝化层包括设于所述第二金属层 上的第一子钝化层以及设于所述第一子钝化层上的第二子钝化层， 所 述疏水层设于所述第二子钝化层的表面。
[权利要求 7] 如权利要求 6所述的阵列基板， 所述第一子钝化层的厚度为 200-230纳 米， 所述第二子钝化层的厚度为 230纳米以下。
[权利要求 8] 如权利要求 6所述的阵列基板， 所述第二子钝化层的厚度为 70纳米以 下， 或 70- 170纳米， 或 170-230纳米。
[权利要求 9] 如权利要求 6所述的阵列基板， 所述第一子钝化层的材料为氧化硅或 氮化硅中的至少一种， 所述第二子钝化层的材料为有机光阻材料。
[权利要求 10] 如权利要求 6所述的阵列基板， 所述第一子钝化层的材料为氧化硅或 氮化硅中的至少一种， 所述第二子钝化层的材料为氧化硅或氮化硅中 的至少一种。
[权利要求 11] 如权利要求 1所述的阵列基板， 所述覆晶薄膜连接走线的宽度为 20-30 微米， 所述覆晶薄膜连接走线上设有多个供紫外光照射通过的通孔。
[权利要求 12] 如权利要求 11所述的阵列基板， 所述通孔的宽度为 1-10微米， 所述通 孔的长度为 1-15微米。
[权利要求 13] 如权利要求 1所述的阵列基板， 所述显示区内形成有扫描线和数据线
; 所述第一金属层与所述扫描线同层设置， 所述第二金属层与所述数 据线同层设置。
[权利要求 14] 如权利要求 1所述的阵列基板， 所述显示区内形成有薄膜晶体管， 所 述覆晶薄膜连接走线的绝缘层与所述薄膜晶体管的栅极绝缘层同层设 置。
[权利要求 15] 一种显示面板， 包括阵列基板；
所述阵列基板包括衬底基层， 所述衬底基层上设有显示区和非显示区 ， 所述非显示区包括多条设于所述衬底基层上的覆晶薄膜连接走线； 所述覆晶薄膜连接走线包括：
第一金属层， 设于所述衬底基层上；
绝缘层， 设于所述第一金属层上；
第二金属层， 设于所述绝缘层上； 以及
钝化层， 设于所述第二金属层上；
所述钝化层的表面具有疏水层；
所述钝化层包括设于所述第二金属层上的第一子钝化层以及设于所述 第一子钝化层上的第二子钝化层， 所述疏水层设于所述第二子钝化层 的表面； 所述第一子钝化层的厚度为 200-230纳米， 所述第二子钝化 层的厚度为 230纳米以下。
[权利要求 16] 一种显示器， 包括显示面板， 所述显示面板包括阵列基板；
所述阵列基板包括衬底基层， 所述衬底基层上设有显示区和非显示区 ， 所述非显示区包括多条设于所述衬底基层上的覆晶薄膜连接走线； 所述覆晶薄膜连接走线包括：
第一金属层， 设于所述衬底基层上；
绝缘层， 设于所述第一金属层上； 第二金属层， 设于所述绝缘层上； 以及 钝化层， 设于所述第二金属层上； 所述钝化层的表面具有疏水层。
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CN107608104A (zh) * 2017-11-03 2018-01-19 惠科股份有限公司 显示面板及其应用的显示装置

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