WO2020037497A1 - 电容器及其加工方法 - Google Patents

电容器及其加工方法 Download PDF

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Publication number
WO2020037497A1
WO2020037497A1 PCT/CN2018/101535 CN2018101535W WO2020037497A1 WO 2020037497 A1 WO2020037497 A1 WO 2020037497A1 CN 2018101535 W CN2018101535 W CN 2018101535W WO 2020037497 A1 WO2020037497 A1 WO 2020037497A1
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Prior art keywords
layer
capacitor
substrate
trench
conductor layer
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PCT/CN2018/101535
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English (en)
French (fr)
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陆斌
沈健
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深圳市为通博科技有限责任公司
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Priority to PCT/CN2018/101535 priority Critical patent/WO2020037497A1/zh
Priority to EP18915775.3A priority patent/EP3637448A4/en
Priority to CN201880001218.5A priority patent/CN111095450A/zh
Priority to US16/666,478 priority patent/US10910158B2/en
Publication of WO2020037497A1 publication Critical patent/WO2020037497A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/01—Form of self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers

Definitions

  • Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a capacitor and a processing method thereof.
  • Wafer-level 3D capacitors are a new type of capacitor that has appeared in recent years. This 3D capacitor is processed by means of advanced semiconductor processing technology. When manufacturing a 3D capacitor, it is necessary to first etch a 3D structure with an aspect ratio (AR) on the substrate, and then make electrodes and dielectric films of the 3D capacitor on the surface of the 3D structure to complete the processing of the 3D capacitor. Production.
  • AR aspect ratio
  • the capacitance of a capacitor is directly proportional to the contact area between the electrode and the dielectric. That is, the higher the AR of the 3D structure, the larger the contact area between the electrode and the dielectric, and the higher the capacitance of the 3D capacitor.
  • the purpose of the embodiments of the present application is to provide a capacitor and a method for processing the same, which are used to at least solve the problem of low capacitance density of 3D capacitors in the prior art.
  • the embodiments of the present application provide a capacitor including a structure for forming a three-dimensional capacitor, the structure is a convex structure or a trench structure; wherein, when the structure is a convex structure When the height ratio of the raised structure is greater than 10; when the structure is a trench structure, the capacitor further includes a substrate, and the trench structure passes the material on the surface of the basic trench provided on the substrate Layer formation, the aspect ratio of the trench structure is greater than 10.
  • a capacitor processing method for processing the above-mentioned capacitor.
  • the method includes: when the structure is a convex structure, processing a base protrusion on a substrate, and processing the base protrusion Etching processing is performed to form a convex structure with an aspect ratio greater than 10; or, when the structure is a trench structure, a basic trench is processed on a substrate, and a surface of the basic trench is covered with a material layer to form A trench structure having an aspect ratio greater than 10; a capacitor is formed by processing based on the raised structure or the trench structure.
  • Embodiments of the present application provide a capacitor and a method for processing the same.
  • the structure of the capacitor for forming a three-dimensional capacitor may be not only a trench structure provided on a substrate, but also a convex structure. Because it is more convenient to generate and process the convex structure, it is possible to process the convex structure with a large aspect ratio (AR) at a lower cost, ensuring that the aspect ratio of the convex structure can reach more than 10, thereby overcoming the existing structure.
  • AR aspect ratio
  • the formation of three-dimensional capacitors by trenches is limited by the processing technology and cost. It is difficult to process ultra-high aspect ratio capacitors, which improves the density of the capacitors.
  • the aspect ratio (AR) of the trench structure formed based on the material layer is increased compared to the base trench, and the depth is not increased, ensuring In order to improve the aspect ratio without the problem that the depth is too deep to be processed, the aspect ratio of the trench structure is greater than 10, thereby ensuring that the capacitance density of the capacitor based on this trench structure is improved.
  • FIG. 1 is a schematic structural diagram of a first capacitor according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a second capacitor according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a third capacitor according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a fourth capacitor according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a fifth capacitor according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a sixth capacitor according to an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a first capacitor processing method according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of processing a first base layer of a first capacitor according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a prefabricated groove of the first capacitor of the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a processed base protrusion of a first capacitor according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a processed bump structure of a first capacitor according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a processed intermediate protective layer of a first capacitor according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of processing a second conductive layer on a substrate of a first capacitor of an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a processed glass protective layer of a first capacitor according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a first electrode of a first capacitor in accordance with an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of a processed second electrode of a first capacitor according to an embodiment of the present application.
  • FIG. 17 is a schematic flowchart of a third capacitor processing method according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a processed basic trench of a third capacitor according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a processed material layer of a third capacitor according to an embodiment of the present application.
  • 20 is a schematic structural diagram of a processed dielectric layer of a third capacitor according to an embodiment of the present application.
  • 21 is a schematic structural diagram of a processed upper electrode of a third capacitor according to an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a processed lower electrode of a third capacitor according to an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a processed material layer of a fourth capacitor according to an embodiment of the present application.
  • 24 is a schematic structural diagram of a processed upper electrode and a dielectric layer of a fourth capacitor according to an embodiment of the present application.
  • FIG. 25 is a schematic structural diagram of punching a fourth capacitor according to an embodiment of the present application.
  • 26 is a schematic structural diagram of a processed lower electrode of a fourth capacitor according to an embodiment of the present application.
  • FIG. 27 is a schematic structural diagram of a processed material layer of a fifth capacitor according to an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of a processed dielectric layer of a fifth capacitor according to an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of a processed upper electrode and a lower electrode of a fifth capacitor according to an embodiment of the present application.
  • substrate 2. first conductor layer; 2a, raised structure; 2b, trench structure; 2c, seed layer; 2d, first isolation layer; 3, basic trench; 4, material layer; An insulating layer; 7, a second conductor layer; 7a, a second isolation layer; 8, a first electrode; 9, a second electrode; 10, a barrier layer; 11, a third conductor layer; 12a, an upper electrode; 12b, a lower Electrodes; 13, second insulating layer; 14a, third isolation layer; 14c, fourth isolation layer; 15, foundation protrusion; 16, adhesion layer; 18, sacrificial material layer; 19, pre-groove; 35, glass protection Floor.
  • the capacitor includes a structure for forming a three-dimensional capacitor, and the structure is a convex structure 2 a or a trench structure 2 b; wherein, when the structure is In the case of the protruding structure 2a, the aspect ratio of the protruding structure 2a is greater than 10; when the structure is a trench structure 2b, the capacitor further includes a substrate 1, and the trench structure 2b is disposed on the substrate The material layer 4 on the surface of the basic trench 3 on 1 is formed, and the aspect ratio of the trench structure 2b is greater than 10.
  • three-dimensional capacitors are processed with a certain aspect ratio (AR) trench on the substrate during the processing process, and then the trench is filled with an insulating substance and a conductive substance to form a capacitor.
  • AR aspect ratio
  • a structure for forming a three-dimensional capacitor may be not only a trench structure 2b provided on a substrate, but also a raised structure 2a. Since it is convenient to generate and process the convex structure 2a, it is possible to process the convex structure 2a with a large aspect ratio (AR) at a lower cost, so that the aspect ratio of the convex structure 2a can reach more than 10, thereby overcoming In the prior art, there is no problem that it is difficult to process ultra-high aspect ratio capacitors, and the capacitance density of the processed capacitors is improved.
  • AR aspect ratio
  • the depth structure ratio (AR) of the trench structure 2b formed based on the material layer 4 compared with the base trench 3 is increased. No increase (decreased width) ensures that both the aspect ratio can be improved without the problem that the depth is too deep to be processed, and the aspect ratio of the trench structure 2b is greater than 10, so as to ensure that based on this trench structure
  • the 2b capacitor has a higher capacitance density.
  • the convex structure 2a may be a suitable structure such as a columnar protrusion, a wall-like protrusion (such as a strip-shaped protrusion with a rectangular cross section), and a tapered protrusion, which is not limited in this embodiment.
  • the trench structure 2b may be a suitable structure such as a trench (Trench) or a hole (TSV, through-silicon-via) formed on the substrate 1, which is not limited in this embodiment.
  • the aspect ratio of the raised structure 2a referred to in this embodiment refers to the ratio of the height (H) to the width (L) of the raised structure 2a in FIG. 11.
  • the aspect ratio of the trench structure 2b refers to the ratio of the depth to the width of the trench structure 2b.
  • the aspect ratio of the raised structure 2a is greater than 10 and less than or equal to 500
  • the aspect ratio of the groove structure 2b is greater than 10 and less than or equal to 500.
  • the value range of the aspect ratio of the raised structure 2a and the value range of the aspect ratio of the groove structure 2b are a relatively preferable range based on factors such as technology realization, processing production cost, and processing efficiency.
  • the aspect ratio of the raised structure 2a or the aspect ratio of the trench structure 2b may be 10, 14, 15, 20, 21, 25, 50, 51, 55, 100, 150, 200, 250, 300, 350 , 400, 450, 500 and so on.
  • the aspect ratio of the protruding structure 2a and the aspect ratio of the trench structure 2b may be greater than 500.
  • the three-dimensional capacitors whose structures used to form the three-dimensional capacitors are the convex structure 2a and the trench structure 2b are described in detail below.
  • the capacitor when the structure is a convex structure 2 a, the capacitor includes a first conductor layer 2, a first insulation layer 6, and a second conductor layer 7, which are on the substrate 1.
  • the surface is sequentially stacked to form a capacitor.
  • the first conductor layer 2, the first insulating layer 6, and the second conductor layer 7 are not necessarily stacked in close proximity to each other, and may be provided between the first conductor layer 2 and the first insulating layer 6 as required. For other structures, other structures may be provided between the first insulating layer 6 and the second conductor layer 7.
  • the substrate 1 may select different structures and materials.
  • the substrate 1 may be a silicon wafer as a substrate or glass as a substrate.
  • the substrate 1 may be removed during the processing of the capacitor to form a substrateless capacitor.
  • the second electrode 9 is manufactured, the glass substrate 1 is removed.
  • the first conductor layer 2 is disposed close to the substrate 1 and includes the protruding structure 2 a, and at least partially covers the substrate 1.
  • the first conductor layer 2 includes a seed layer 2 c in addition to the convex structure 2 a having a high aspect ratio.
  • the seed layer 2c may be connected to the substrate 1 through the adhesion layer 16.
  • the adhesion layer 16 may be a material with good adhesion without affecting the performance of the capacitor.
  • the adhesive layer 16 may be UV glue, so that the substrate 1 can be removed more conveniently in subsequent processes.
  • the first conductor layer 2 formed by combining the raised structure 2a and the seed layer 2c has a large area, which can greatly increase the capacity of the capacitor and reduce the size of the capacitor.
  • the material of the first conductor layer 2 may be a conductor of various materials, and is preferably a metal conductor having a relatively low resistivity, such as copper or other materials having a low resistivity.
  • the material of the seed layer 2c and the protruding structure 2a of the first conductor layer 2 may be copper (Cu), tin (Sn), nickel (Ni), or the like.
  • Cu copper
  • tin Sn
  • Ni nickel
  • both are copper.
  • copper has good electrical conductivity; on the other hand, the cost of copper is relatively low.
  • the seed layer 2 c is connected to the substrate 1 through the adhesive layer 16.
  • the main function of the adhesive layer 16 is to improve the adhesion between the substrate 1 and the seed layer 2c.
  • the material of the adhesive layer 16 can be determined as required.
  • the adhesion layer 16 can be preferably selected from a material having a low resistivity and capable of preventing copper from diffusing into the substrate 1, for example, titanium nitride (TiN), Tantalum (Ta), tantalum nitride (TaN), or a combination thereof.
  • the adhesive layer 16 can be made of UV glue.
  • the material of the seed layer 2c may also be nickel. If a non-diffusible material such as nickel is used, the adhesion layer 16 may be selected from other materials, or the adhesion layer 16 may be omitted as required.
  • the first insulating layer 6 is mainly used to form a dielectric layer of a capacitor.
  • a high dielectric constant material such as alumina, hafnium oxide, zirconia, titanium dioxide, lead zirconate titanate, etc. is used as the first insulating layer 6 to Increase the capacity of the capacitor to make it better.
  • the first insulating layer 6 covers the first conductor layer 2.
  • the material of the first conductor layer 2 is copper
  • a first isolation layer is provided between the first insulating layer 6 and the first conductor layer 2. 2d.
  • the material of the second conductive layer 7 is copper
  • a first conductive layer 7 may be provided between the first insulating layer 6 and the second conductive layer 7. Two isolation layers 7a.
  • the first isolation layer 2d and the second isolation layer 7a are used to prevent the substances (such as copper, etc.) of the first conductor layer 2 and the second conductor layer 7 from diffusing to the first insulation layer 6, so as to ensure its insulation performance, thereby ensuring the capacitor's performance.
  • the first isolation layer 2d and the second isolation layer 7a may be made of titanium nitride or the like.
  • the low resistivity titanium nitride can prevent copper from diffusing to the first insulating layer 6.
  • the first isolation may be omitted.
  • the layer 2d and the second isolation layer 7a make the first insulating layer 6 directly contact the first conductor layer 2 and cover the first conductor layer 2, and the second conductor layer 7 directly covers the surface of the first insulating layer 6. It should be noted that the coverage may be full coverage or partial coverage.
  • the capacitor further includes a first electrode 8 and a second electrode 9 for connecting the capacitor to other structures or components.
  • the first electrode 8 is electrically connected to the second conductor layer 7, and the second electrode 9 is electrically connected to the first conductor layer 2.
  • the second electrode 9 is electrically connected to the first conductor layer 2.
  • the second electrode 9 may be adhered to the surface of the seed layer 2c through the adhesive layer 16, as shown in FIG. 2.
  • the capacitor when the structure is a trench structure 2b, the capacitor includes the upper electrode 12a, the second insulating layer 13 and the lower electrode 12b in addition to the substrate 1 and the trench structure 2b.
  • the structure of the substrate 1 may be the same as or similar to the structure of the substrate 1 when the structure is a convex structure 2a, and therefore will not be repeated here.
  • the material layer 4 includes a barrier layer 10 and a third conductor layer 11 which are sequentially stacked, and the barrier layer 10 is disposed next to the substrate 1.
  • the barrier layer 10 includes at least one of a titanium layer (Ti), a titanium nitride layer (TiN), a tantalum layer (Ta), and a tantalum nitride layer (TaN).
  • the barrier layer 10 may be one layer or may be Multi-layer, the material of each layer may be different or partially the same when it is multi-layer.
  • the third conductor layer 11 includes a copper layer, and the copper layer is formed by electroplating.
  • the material of the barrier layer 10 may be the same as that of the first isolation layer 2d and the second isolation layer 7a, such as using a titanium nitride layer; different materials may also be used, such as the barrier layer 10 using a titanium nitride layer, and the first isolation As the layer 2d and the second isolation layer 7a, a tantalum nitride layer or the like is used.
  • the material layer 4 covers the upper surface of the substrate 1 and the inner wall of the base trench 3 (refer to FIG. 18 together), and the thickness of the material layer 4 everywhere is uniform to ensure the performance of the capacitor.
  • a second insulating layer 13 is provided between the third conductor layer 11 and the upper electrode 12 a.
  • the role of the second insulating layer 13 is similar to that of the first insulating layer 6.
  • a third isolation layer 14 a is provided between the second insulation layer 13 and the third conductor layer 11.
  • a fourth isolation layer 14c is provided between the second insulating layer 13 and the upper electrode 12a.
  • the material of the second insulating layer 13 may be hafnium dioxide (HfO2) as a dielectric of the capacitor.
  • the third isolation layer 14a and the fourth isolation layer 14c may be titanium nitride (TiN) to prevent the substances of the third conductor layer 11 and the upper electrode 12a from diffusing to the second insulation layer 13 and affect its insulation performance, thereby ensuring the capacitor's performance.
  • the upper electrode 12a includes an upper electrode body and an upper electrode leg, the upper electrode body covers the third conductor layer 11, and the upper electrode leg extends Into the trench structure 2b.
  • the material of the upper electrode 12a may be a tungsten material.
  • a lower electrode 12 b may be provided on the lower surface of the substrate 1, and the lower electrode 12 b is connected to the third conductor layer 11 through the substrate 1.
  • the material layer 4 when a three-dimensional capacitor is formed based on the trench structure 2 b on the substrate, the material layer 4 includes a silicon dioxide layer, which can be formed on the substrate 1 by a thermal oxidation method. The surface and the inner wall of the base groove 3 are uniformly grown.
  • a third isolation layer 14a, a second insulation layer 13 and a fourth isolation layer 14c, and an upper electrode 12a are sequentially stacked on the silicon dioxide layer. Due to the poor conductivity of the silicon dioxide layer, in order to make the lower electrode 12b and electrically communicate the lower electrode 12b with the third isolation layer 14a, through holes are provided at the bottom of the substrate 1 and the bottom of the material layer 4, and the lower electrode 12b is penetrated. The via is electrically connected to the third isolation layer 14a.
  • the upper electrode 12 a and the lower electrode 12 b of the capacitor are on the same side, and the material layer 4 of the capacitor also includes a silicon dioxide layer.
  • a third isolation layer 14a, a second insulation layer 13 and a fourth isolation layer 14c are sequentially stacked on the material layer 4. The difference is that the areas of the second insulating layer 13 and the fourth isolation layer 14c are different from the areas of the third isolation layer 14a, and a part of the third isolation layer 14a is not covered by the fourth isolation layer 14c and the second insulation layer 13. In order to expose a portion of the third isolation layer 14a, the electrodes are easily connected to it.
  • a polyimide layer is covered on the fourth isolation layer 14c and the exposed third isolation layer 14a, and at least two openings are provided on the polyimide layer to expose the fourth isolation layer 14c and the third isolation layer, respectively.
  • the upper electrode 12a is connected to the fourth isolation layer 14c through one of the openings
  • the lower electrode 12b is connected to the third isolation layer 14a through the other opening.
  • a capacitor processing method for processing the above-mentioned capacitor.
  • the method includes:
  • the base protrusion 15 is processed on the substrate 1, and the base protrusion 15 is processed to form a protrusion structure 2a with an aspect ratio greater than 10; or, the base groove 3 is processed on the substrate 1, and the base
  • the surface of the trench 3 is covered with the material layer 4 and a trench structure 2b having an aspect ratio greater than 10 is formed; a capacitor is formed based on the protruding structure 2a or the trench structure 2b.
  • the base protrusion 15 having a relatively small height and width or the base groove 3 having a relatively small depth and width are processed on the substrate 1, and then the base protrusion 15 is processed to reduce the width of the base protrusion 15 by more than the height.
  • a small amount so that the height-to-width ratio of the processed protruding structure 2a is increased to be greater than 10, thereby improving the performance of the capacitor without enlarging the volume of the capacitor; or, covering the material layer 4 in the basic trench 3 to pass the material
  • the layer 4 forms a trench structure 2b with an aspect ratio greater than 10, thereby increasing the capacitance density of the capacitor processed based on this.
  • Step S201 Select the substrate 1.
  • a silicon wafer with a low resistivity is selected as a substrate.
  • glass can be selected as the substrate.
  • Step S202 The base protrusion 15 is processed on the substrate 1.
  • processing the base protrusion 15 includes:
  • Sub-step S2021 depositing an adhesion layer 16 on the upper surface of the substrate 1.
  • a seed layer 2c may be provided on the adhesion layer 16.
  • the deposited adhesion layer 16 may be a different material, such as a titanium (Ti) layer, a titanium nitride layer, or other materials. Wait. It is mainly used to connect the substrate 1 to the seed layer 2c.
  • the adhesion layer 16 may be a titanium nitride layer. If the substrate 1 is glass, in order to facilitate the removal of the substrate 1 in subsequent processes, the adhesive layer 16 may be a UV glue.
  • a layer and a base protrusion can be deposited on the adhesion layer 16
  • the same material as 15 is used as the seed layer 2c to facilitate subsequent electroplating.
  • the specific process can be as follows: a plating seed layer is deposited on the adhesion layer 16, and then a copper layer grown by whole-surface electroplating is used as the seed layer 2c, and the thickness can be determined according to needs, such as 10 microns, and the structure after plating is as follows Figure 8 shows.
  • the step of depositing the seed layer may be omitted.
  • the material of the seed layer 2c is a conductor, such as copper. Since the resistivity of copper is low, the performance of the capacitor can be well guaranteed, and the cost of the capacitor can be effectively reduced.
  • Sub-step S2022 covering the adhesive layer 16 with a sacrificial material layer 18, and forming a prefabricated groove 19 on the sacrificial material layer 18 for generating the base protrusion 15.
  • the pre-groove 19 penetrates the sacrificial material layer 18.
  • the sacrificial material layer 18 is disposed on the seed layer 2 c. If the seed layer 2 c is not present, the sacrificial material layer 18 may be disposed directly on the adhesion layer 16.
  • the sacrificial material of the sacrificial material layer 18 may be an organic substance such as a photoresist or polyimide (PI), or an inorganic substance such as glass, silicon oxide, or silicon nitride.
  • Methods for making the sacrificial material layer 18 include spray coating, spin coating, adhesion, oxidation, plasma-assisted deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.
  • a 50 micron-thick sacrificial material layer 18 may be formed on the surface of the seed layer 2c by spin coating or the like. Two pre-grooves 19 having a width of 10 micrometers are obtained through exposure, development, and the like.
  • the structure after fabrication is shown in Figure 9.
  • a photoresist SU-8 may be selected, and JSR151 is a sacrificial material.
  • the method for removing the sacrificial material layer 18 can also be a solution dissolution, wet etching, plasma etching, or the like.
  • Step S2023 Fill the pre-groove with a conductive substance and form a base protrusion 15.
  • a conductive substance such as the substance of the seed layer 2 c
  • the base protrusion 15 is formed.
  • copper is grown in the pre-groove 19 by electroplating to form the base protrusion 15.
  • the sacrificial material layer 18 is removed to obtain a copper pillar with a width of 10 micrometers and a height of 50 micrometers as the base protrusion 15. The structure after fabrication is shown in FIG. 10.
  • the stability of the processed base protrusion 15 can be improved by adjusting the shape of the pre-groove 19.
  • the prefabricated groove 19 is a "H” shape, a "T” shape groove, etc.
  • a "H” shape or a “T” shape base protrusion 15 is processed correspondingly, and a "H” shape protrusion structure 2a or " Cross-shaped raised structure 2a.
  • Step S203 The base protrusion 15 is processed, and a protrusion structure 2a having an aspect ratio greater than 10 is formed.
  • an etching process may be adopted, and the etching process includes isotropic wet etching or isotropic dry etching. These two etching methods can effectively adjust the aspect ratio of the base protrusion 15 to increase its aspect ratio. The cost of processing the raised structure 2a by this method is lower and the processing speed is faster.
  • the structure after fabrication is shown in Figure 11.
  • a wet etching method is adopted, so that multiple substrates 1 can be processed at the same time, which further reduces the cost.
  • the seed layer 2c cooperates with the raised structure 2a to form a first conductor layer 2.
  • the conductive material of the first conductor layer 2 may be metal, silicon, carbon-based material, titanium nitride, or It is a combination of the above materials.
  • the manufacturing method includes electroplating, evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.
  • Step S204 processing the raised structure 2a to form a capacitor.
  • Sub-step S2041 fabricating a first insulating layer 6 and a second conductor layer 7 on the first conductor layer 2 including the raised structure 2a.
  • the 4 micrometer-thick copper on the first conductor layer 2 can be removed by using a copper etching solution to obtain a 6 micrometer-thick first conductor layer 2.
  • the protruding structure 2 a is 2 micrometers wide and 50 micrometers high. If the material of the first conductor layer 2 and the second conductor layer 7 is copper, titanium nitride is deposited on the surface of the first conductor layer 2 as a first isolation layer 2d by atomic layer deposition (ALD) to isolate the first The conductive layer 2 and the first insulating layer 6 prevent copper from diffusing into the first insulating layer 6. After that, hafnium oxide is deposited as the first insulating layer 6.
  • titanium nitride is deposited on the first insulating layer 6 as the second isolation layer 7a.
  • low-resistivity titanium nitride serves as a barrier layer to prevent copper from diffusing into the hafnium oxide layer and affect device performance.
  • Hafnium oxide is a high dielectric constant dielectric. The structure after fabrication is shown in Figure 12.
  • the first insulating layer 2d may not be provided between the first conductive layer 2 and the first insulating layer 6, but directly A first insulating layer 6 is processed on the first conductor layer 2.
  • the insulating material of the first insulating layer 6 may be other materials, such as silicon oxide, silicon nitride, metal oxide, metal nitride, and the like.
  • the insulating material may be one or more layers.
  • Methods for making insulating dielectric films include atomic layer deposition (ALD), physical vapor deposition (PVD), and chemical vapor deposition (CVD).
  • a layer of copper can be deposited on the surface of the second isolation layer 7a as a seed layer for electroplating by means of physical vapor deposition (PVD).
  • PVD physical vapor deposition
  • a copper layer with a thickness of 10 micrometers is deposited by electroplating as the second conductor layer 7.
  • the structure after fabrication is shown in FIG. 13.
  • the second isolation layer 7a may not be provided between the second conductor layer 7 and the first insulating layer 6.
  • Sub-step S2042 making a first electrode 8 on the second conductor layer 7 and making a second electrode 9 on the substrate 1.
  • a glass protective layer 35 is generated by spin-on-glass (Spin-on-glass) coating, and the multilayer 3D structure manufactured above is covered.
  • the fabricated structure is shown in Figure 14.
  • the substrate 1 is a silicon wafer, the substrate 1 is thinned to 100 micrometers by back grinding and polishing.
  • a second electrode 9 with a layer of titanium and a layer of copper as a capacitor is deposited on the back surface of the substrate 1, and the second electrode 9 is electrically connected to the first conductor layer 2 through the substrate 1.
  • the structure after fabrication is shown in FIG. 16.
  • the substrate 1 includes glass, after the first electrode 8 is fabricated on the second conductor layer 7, the glass of the substrate 1 is removed, and the second electrode 9 is fabricated on the exposed seed layer 2c. .
  • the structure after fabrication is shown in Figure 2.
  • the glass can be removed by irradiating the back of the glass with UV (ultraviolet rays) to remove the UV adhesive and then removing the glass. This way the substrate can be reused to reduce costs.
  • UV ultraviolet
  • Step S301 a silicon wafer with a low resistivity (for example, 0.001 ⁇ .cm) is selected as the substrate 1, and a basic trench 3 is formed by processing.
  • a silicon wafer with a low resistivity for example, 0.001 ⁇ .cm
  • a DRIE (Deep Reactive Ion Etching) method is used to form a basic trench 3 with a width of 10 microns and a depth of 100 microns on the surface of the substrate 1.
  • the structure after fabrication is shown in FIG. 18.
  • Step S302 Cover the surface of the base trench 3 with a material layer 4.
  • the material layer 4 may be a conductive material or an insulating material.
  • covering the material layer 4 includes:
  • a barrier layer 10 and a plating seed layer are deposited in the base trench 3, a third conductor layer 11 is plated on the plating seed layer, and the material layer 4 is formed, wherein the substance of the third conductor layer 11 is The same material as the plating seed layer.
  • the barrier layer 10 may be formed by depositing a layer of titanium nitride (TiN) on the surface of the substrate 1 and the inner wall of the base trench 3 by a PVD (physical vapor deposition) method, and the plating seed layer may be a layer of several tens To a few hundred nanometers thick copper layer. Thereafter, a copper layer with a thickness of 2 micrometers is uniformly grown on the surface of the substrate 1 and the inner wall of the base trench 3 by electroplating to form a third conductor layer 11. The structure after fabrication is shown in FIG. 19.
  • the covering material layer 4 includes:
  • a silicon dioxide layer is grown in the base trench 3 as the material layer 4 by a thermal oxidation method.
  • step S303 the trench structure 2b is processed, and a capacitor is formed.
  • the material layer 4 is formed, if the material layer 4 is a conductive material, the trench structure 2b is processed, and when forming a capacitor, a second insulating layer 13 and a conductive layer need to be made at least on the surface of the material layer 4 as a capacitor dielectric and an upper electrode 12a . If the material layer 4 is an insulating material, when processing the trench structure 2b and forming a capacitor, a conductive layer, a second insulating layer 13 and a conductive layer need to be sequentially formed on the surface of the material layer 4 as the lower electrode, the dielectric, and the upper electrode of the capacitor.
  • the method for forming the second insulating layer 13 may be ALD (atomic layer deposition). If the third conductor layer 11 is copper, etc., to prevent copper diffusion, A 15 nm thick titanium nitride layer (as the third isolation layer 14a), a 10 nm thick hafnium dioxide (HfO2) layer (as the second insulating layer 13), and a 15 nm thick layer were deposited on the surface of the third conductor layer 11 in this order. Another titanium nitride layer (as the fourth isolation layer 14c). The structure after fabrication is shown in Figure 20.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • Al aluminum
  • a layer of silicon dioxide can be uniformly grown on the inner wall of the base trench 3 as the material layer 4 by a thermal oxidation method. Since silicon dioxide is an insulating material, an additional photolithography step is performed when the lower electrode 12 b of the capacitor is manufactured, and the electrode is led out from the back or front surface of the substrate 1.
  • the substrate is placed in a furnace tube, and a mixed gas of hydrogen and oxygen, or oxygen containing water vapor, is used to grow silicon dioxide under high temperature conditions.
  • a mixed gas of hydrogen and oxygen, or oxygen containing water vapor is used to grow silicon dioxide under high temperature conditions.
  • the structure after fabrication is shown in Figure 23.
  • an ALD method can be used to sequentially deposit a titanium nitride layer, a hafnium dioxide layer, and another titanium nitride layer on the surface of the silicon dioxide. Layer 14c, and two titanium nitride layers can be used as a conductor layer at the same time.
  • metal tungsten is filled as the upper electrode 12a by a CVD method.
  • the structure after fabrication is shown in Figure 24.
  • a method of dry etching and wet etching is used to open a hole on the back surface of the substrate to expose the lower titanium nitride layer.
  • the structure after fabrication is shown in FIG. 25.
  • the lower electrode is then made of a layer of PVD Al.
  • the structure after fabrication is shown in Figure 26.
  • the substrate 1 is placed in a furnace tube, and a mixed gas of hydrogen and oxygen, or oxygen containing water vapor, is used to grow silicon dioxide under high temperature conditions.
  • a mixed gas of hydrogen and oxygen, or oxygen containing water vapor is used to grow silicon dioxide under high temperature conditions.
  • the structure after fabrication is shown in Figure 27 Show.
  • a titanium nitride layer (as the third isolation layer 14a), a 10 nm thick hafnium oxide (HfO2) layer (as the second insulating layer 13), and a 15 nm thick A titanium nitride layer (as the fourth isolation layer 14c).
  • the upper part of the titanium nitride layer and the hafnium dioxide (HfO2) layer are removed to expose the lower titanium nitride layer.
  • the structure after fabrication is shown in Figure 28.
  • Polyimide (PI) is spin-coated to form a polyimide layer, and at least two windows are opened on the polyimide layer. Among them, at least one window exposes the lower titanium nitride layer, and the other window exposes the upper titanium nitride layer.
  • An Al (aluminum) layer is formed by the PVD method and patterned to fabricate an upper electrode 12a and a lower electrode 12b. The structure after fabrication is shown in Figure 29.
  • a low-AR columnar or wall-shaped foundation protrusion or foundation groove is first produced.
  • the isotropic dry / wet etching can be used.
  • the AR of the convex structure after the etching is increased, and the aspect ratio of the 3D structure can be simply improved.
  • the basic groove by depositing a material layer with a uniform thickness on the inner wall of the basic groove and the surface of the substrate, the aspect ratio of the formed trench structure can be easily increased. In this way, not only wafer-level 3D capacitors can be processed, but also the cost is low and the operation is easy. It is also possible to make 3D structures with large AR and 3D capacitors based on such structures.

Abstract

一种电容器及其加工方法。该电容器包括用于形成三维电容的结构，该结构为凸起结构或沟槽结构；其中，当该结构为凸起结构时，该凸起结构的高宽比大于10；当该结构为沟槽结构时，电容器还包括衬底，该沟槽结构通过设置在该衬底上的基础沟槽表面的物料层形成，该沟槽结构的深宽比大于10。该电容器的凸起结构的高宽比或者沟槽结构的深宽比可以大于10，使得电容器的性能更好。

Description

电容器及其加工方法 技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种电容器及其加工方法。
背景技术
晶圆级3D电容器(又称三维电容器)是近年来出现的一种新型电容器，这种3D电容器借助于先进的半导体加工技术加工而成。在制作3D电容器时，需要先在衬底上刻蚀出具有深宽比(Aspect Ratio，AR)的3D结构，接着在3D结构表面制作3D电容器的电极和电介质薄膜等，以完成3D电容器的加工制作。
众所周知，电容器的电容容量与电极和电介质之间的接触面积成正比。也即，3D结构的AR越高，电极和电介质之间的接触面积也越大，3D电容器的电容容量也越高。
然而，现有技术中，受制于技术能力和加工成本，直接加工高AR的3D结构工艺难度大且成本高昂，使得3D电容器的容值密度无法得到有效提升。
发明内容
本申请实施例的目的在于提供一种电容器及其加工方法，用以至少解决现有技术中的3D电容器容值密度低的问题。
为实现本申请实施例的目的，本申请实施例提供了一种电容器，包括用于形成三维电容的结构，所述结构为凸起结构或沟槽结构；其中，当所述结构为凸起结构时，所述凸起结构的高宽比大于10；当所述结构为沟槽结构时，电容器还包括衬底，所述沟槽结构通过设置在所述衬底上的基础沟槽表面的物料层形成，所述沟槽结构的深宽比大于10。
根据本申请实施例的另一方面，提供一种电容器加工方法用于加工上述的电容器，所述方法包括：当结构为凸起结构时，在衬底上加工基础凸起，对所述基础凸起进行刻蚀加工，形成高宽比大于10的凸起结构；或者，当结构为沟槽结构时，在衬底上加工基础沟槽，在所述基础沟槽的表面覆盖物料层，并形成深宽比大于10的沟槽结构；基于所述凸起结构或沟槽结构加工形成电容器。
本申请实施例提供了一种电容器及其加工方法，该电容器用于形成三维电容的结构不仅可以是设置在衬底上的沟槽结构，还可以是凸起结构。由于生成和加工凸起结构较为方便，使得可以以较低的成本加工具有较大高宽比(AR)的凸起结构，保证凸起结构的高宽比能够达到10以上，从而克服了现有技术中传统的通过沟槽形成三维电容器，受限于加工技术和成本难以加工出超大高宽比电容器的问题，提升了加工出的电容器的容值密度。另外，通过在衬底的基础沟槽内设置物料层，进而使基于物料层形成的沟槽结构相较于基础沟槽的深宽比(AR)增大，而深度并未有增大，保证了既能够提升深宽比，又不会存在深度过深无法加工的问题，使沟槽结构的深宽比大于10，从而保证基于此种沟槽结构的电容器的容值密度得以提升。
附图说明
为了更清楚地说明本实用新型实施例或现有技术中的技术方案，下面将对实施例 或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型实施例中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为本申请实施例的第一种电容器的结构示意图；
图2为本申请实施例的第二种电容器的结构示意图；
图3为本申请实施例的第三种电容器的结构示意图；
图4为本申请实施例的第四种电容器的结构示意图；
图5为本申请实施例的第五种电容器的结构示意图；
图6为本申请实施例的第六种电容器的结构示意图；
图7为本申请实施例的第一种电容器加工方法的流程示意图；
图8为本申请实施例的第一种电容器的加工第一基础层的结构示意图；
图9为本申请实施例的第一种电容器的加工预制凹槽的结构示意图；
图10为本申请实施例的第一种电容器的加工基础凸起的结构示意图；
图11为本申请实施例的第一种电容器的加工凸起结构的结构示意图；
图12为本申请实施例的第一种电容器的加工中间防护层的结构示意图；
图13为本申请实施例的第一种电容器的在衬底上加工第二导体层的结构示意图；
图14为本申请实施例的第一种电容器的加工玻璃防护层的结构示意图；
图15为本申请实施例的第一种电容器的加工第一电极的结构示意图；
图16为本申请实施例的第一种电容器的加工第二电极的结构示意图；
图17为本申请实施例的第三种电容器加工方法的流程示意图；
图18为本申请实施例的第三种电容器的加工基础沟槽的结构示意图；
图19为本申请实施例的第三种电容器的加工物料层的结构示意图；
图20为本申请实施例的第三种电容器的加工电介质层的结构示意图；
图21为本申请实施例的第三种电容器的加工上电极的结构示意图；
图22为本申请实施例的第三种电容器的加工下电极的结构示意图；
图23为本申请实施例的第四种电容器的加工物料层的结构示意图；
图24为本申请实施例的第四种电容器的加工上电极和电介质层的结构示意图；
图25为本申请实施例的第四种电容器的打孔的结构示意图；
图26为本申请实施例的第四种电容器的加工下电极的结构示意图；
图27为本申请实施例的第五种电容器的加工物料层的结构示意图；
图28为本申请实施例的第五种电容器的加工电介质层的结构示意图；
图29为本申请实施例的第五种电容器的加工上电极和下电极的结构示意图。
附图标记说明：
1、衬底；2、第一导体层；2a、凸起结构；2b、沟槽结构；2c、种子层；2d、第一隔离层；3、基础沟槽；4、物料层；6、第一绝缘层；7、第二导体层；7a、第二隔离层；8、第一电极；9、第二电极；10、阻挡层；11、第三导体层；12a、上电极；12b、下电极；13、第二绝缘层；14a、第三隔离层；14c、第四隔离层；15、基础凸起；16、黏附层；18、牺牲材料层；19、预制凹槽；35、玻璃防护层。
具体实施方式
以下将配合图示及实施例来详细说明本申请的实施方式，藉此对本申请如何应用技术手段来解决技术问题并达成技术功效的实现过程能充分理解并据以实施。
如图1－图5、图19所示，根据本申请的实施例，电容器包括用于形成三维电容的结构，所述结构为凸起结构2a或沟槽结构2b；其中，当所述结构为凸起结构2a时，所述凸起结构2a的高宽比大于10；当所述结构为沟槽结构2b时，电容器还包括衬底1，所述沟槽结构2b通过设置在所述衬底1上的基础沟槽3表面的物料层4形成，所述沟槽结构2b的深宽比大于10。
现有技术中三维电容器在加工过程中都是在衬底上加工出具有一定深宽比(AR)的沟槽，然后在沟槽内填充绝缘物质和导电物质形成电容器，为了提升电容器的容值密度，需要尽量提升沟槽的深宽比，以增大电极接触面积，但是由于加工技术的限制，很难直接加工出较大深宽比(AR)的沟槽，使得三维电容器的容值密度难以提升。
本申请的电容器中，用于形成三维电容的结构不仅可以是设置在衬底上的沟槽结构2b，还可以是凸起结构2a。由于生成和加工凸起结构2a较为方便，使得可以以较低的成本加工具有较大高宽比(AR)的凸起结构2a，使凸起结构2a的高宽比能够达到10以上，从而克服了现有技术无难以加工出超大高宽比电容器的问题，提升了加工出的电容器的容值密度。另外，通过在衬底1的基础沟槽3内设置物料层4，进而使基于物料层4形成的沟槽结构2b相较于基础沟槽3的深宽比(AR)增大，而深度并未有增大(宽度减少)，保证了既能够提升深宽比，又不会存在深度过深无法加工的问题，使沟槽结构2b的深宽比大于10，从而保证基于此种沟槽结构2b的电容器的容值密度更高。
需要说明的是，凸起结构2a可以是柱状凸起、墙状凸起(如横截面为矩形的条状凸起)、锥状凸起等适当的结构，本实施例对此不作限定。沟槽结构2b可以是在衬底1上形成的槽(Trench)、孔(TSV，through－silicon－via)等适当的结构，本实施例对此不作限定。
本实施例中所指的凸起结构2a的高宽比是指图11中的凸起结构2a的高度(H)与宽度(L)的比值。同理，沟槽结构2b的深宽比是指沟槽结构2b的深度与宽度的比值。
在本申请的实施例中，优选地，所述凸起结构2a的高宽比大于10且小于或等于500，所述沟槽结构2b的深宽比大于10且小于或等于500。这一凸起结构2a的高宽比的取值范围和沟槽结构2b的深宽比的取值范围为基于技术实现、加工生产成本以及加工效率等因素综合的较为优选的范围。例如，凸起结构2a的高宽比或者沟槽结构2b的深宽比可以是10、14、15、20、21、25、50、51、55、100、150、200、250、300、350、400、450、500等。
当然，在其他实施例中，凸起结构2a的高宽比和沟槽结构2b的深宽比可以大于500。
下面分别对用于形成三维电容器的结构为凸起结构2a和沟槽结构2b的三维电容器进行详细说明。
如图1和2所示，当所述结构为凸起结构2a时，所述电容器包括第一导体层2、第一绝缘层6和第二导体层7，这三者在衬底1的上表面依次层叠设置，以形成电容。需要说明的是，第一导体层2、第一绝缘层6和第二导体层7层叠设备并非必须三者紧贴层叠设置，根据需要第一导体层2与第一绝缘层6之间可以设置其他结构，第一绝缘层6与第二导体层7之间也可以设置其他结构。
根据需求和成本的不同，衬底1可以选择不同的结构和材质，例如，衬底1可以是硅晶圆作为衬底，也可以是玻璃作为衬底。当玻璃作为衬底1时，在加工电容器的过程中可以将衬底1去除，以形成无衬底的电容器，例如，在制作第二电极9时，将玻璃的衬底1去除。
在本实施例中，所述第一导体层2靠近所述衬底1设置并包括所述凸起结构2a，且至少覆盖部分所述衬底1。
具体地，如图1所示，第一导体层2除具有较高高宽比的凸起结构2a外还包括种子层2c。在一个实施例中，种子层2c可以通过黏附层16与衬底1连接，当衬底1为硅圆晶时，黏附层16可以是黏附性好又不会影响电容器性能的材料，当衬底1为玻璃时，黏附层16可以是UV胶，这样可以较为方便地在后续工序中将衬底1移除。凸起结构2a和种子层2c两者组合形成的第一导体层2具有较大的面积，可以极大地提升电容器的容量，且减少电容器的尺寸。第一导体层2的材质可以是各种材料的导体，优选为电阻率较低的金属导体，如铜或其他低电阻率的材料等。
在本实施例中，第一导体层2的种子层2c和凸起结构2a的材质可以是铜(Cu)、锡(Sn)、镍(Ni)等，例如，两者均为铜。一方面铜的导电性好，另一方面，铜的成本相对较低。
由于铜的性质较为活泼，容易扩散，为了防止铜扩散到衬底1或电容器的其他结构中影响电容器的性能，在本实施例中，种子层2c通过黏附层16与衬底1连接。黏附层16的主要作用是提升衬底1与种子层2c之间的附着力。黏附层16的材质可以根据需要确定。例如，衬底1的材料为硅，种子层2c是铜，那么黏附层16可以优先选用低电阻率且能阻止铜向衬底1内扩散的材料，例如，可以是氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或上述材料的组合。如果衬底1是玻璃，那么黏附层16可以选用UV胶。
种子层2c的材料也可以为镍等，若采用镍等不易扩散的材料，则黏附层16可以选择其他材料，或者根据需要可以省略黏附层16。
第一绝缘层6主要用于形成电容器的电介质层，通常使用高介电常数的材料，例如氧化铝、氧化铪、氧化锆、二氧化钛、锆钛酸铅等材料作为第一绝缘层6，用以提升电容器的容量，使其性能更好。
在本实施例中，如图1所示，第一绝缘层6覆盖在第一导体层2上。当第一导体层2的材质为铜时，为了防止第一导体层2中的铜向第一绝缘层6扩散，在第一绝缘层6与第一导体层2之间设置有第一隔离层2d。同理，若第二导体层7的材质为铜，则为了防止第二导体层7中的物质向第一绝缘层6扩散，在第一绝缘层6与第二导体层7之间可以设置第二隔离层7a。
第一隔离层2d和第二隔离层7a用于阻止第一导体层2和第二导体层7的物质(如铜等)向第一绝缘层6扩散，以确保其绝缘性能，从而保证电容器的性能。第一隔离 层2d和第二隔离层7a的材质可以为氮化钛等。低电阻率的氮化钛可以防止铜向第一绝缘层6扩散。
如图6所示，若第一导体层2的材质是铜之外的不易扩散的材质，如镍等，或者，第一绝缘层6的性能不受铜扩散的影响，则可以省略第一隔离层2d和第二隔离层7a，使第一绝缘层6直接与第一导体层2接触，并覆盖在第一导体层2上，而第二导体层7直接覆盖在第一绝缘层6表面。需要说明的是，覆盖可以是全部覆盖，也可以是部分覆盖。
可选地，在本实施例中，所述电容器还包括第一电极8和第二电极9，用于将电容器与其他结构或元器件连接。所述第一电极8与所述第二导体层7电连接，所述第二电极9与所述第一导体层2电连接，例如，当衬底1为硅圆晶时，第二电极9通过衬底1与第一导体层2电连接。当电容器不含有衬底的时候，第二电极9可以通过黏附层16黏合到种子层2c表面，可参看图2。
如图3－5及图19所示，当所述结构为沟槽结构2b时，电容器除了包括衬底1和沟槽结构2b外，还包括上电极12a、第二绝缘层13和下电极12b等，其中所述沟槽结构2b可以通过物料层4形成。衬底1的结构可以与结构为凸起结构2a时的衬底1的结构相同或相似，故在此不再赘述。
在一种可行方式中，当所述结构为沟槽结构2b时，所述物料层4包括依次层叠设置的阻挡层10和第三导体层11，所述阻挡层10紧邻所述衬底1设置且所述阻挡层10包括钛层(Ti)、氮化钛层(TiN)、钽层(Ta)，氮化钽层(TaN)中的至少之一，阻挡层10可以是一层也可以是多层，其为多层时各层的材料可以不同或部分相同。所述第三导体层11包括铜层，且所述铜层通过电镀成型。通过设置阻挡层10可以防止第三导体层11中的铜向衬底1扩散，避免由于铜扩散而影响电容器的性能。
阻挡层10的材质可以与第一隔离层2d和第二隔离层7a的材质相同，如都使用氮化钛层；也可以使用不同的材质，如阻挡层10采用氮化钛层，第一隔离层2d和第二隔离层7a使用氮化钽层等。
优选地，物料层4覆盖衬底1的上表面和基础沟槽3(可一并参考图18)的内壁，且各处的物料层4的厚度均匀，以保证电容器的性能。
结合参见图20，在第三导体层11和上电极12a之间设置第二绝缘层13，第二绝缘层13的作用与第一绝缘层6的作用类似。
在本实施例中，若为了防止第三导体层11中的铜向第二绝缘层13扩散，所述第二绝缘层13与第三导体层11之间设置有第三隔离层14a。同理，为了防止上电极12a中的物质向第二绝缘层13扩散，在第二绝缘层13与上电极12a之间设置有第四隔离层14c。
第二绝缘层13的材质可以是二氧化铪(HfO2)，以作为电容器的电介质。第三隔离层14a和第四隔离层14c可以是氮化钛(TiN)，以阻止第三导体层11和上电极12a的物质向第二绝缘层13扩散而影响其绝缘性能，从而保证电容器的性能。
在本实施例中，如图3所示，所述上电极12a包括上电极主体和上电极支腿，所述上电极主体覆盖在所述第三导体层11上，所述上电极支腿伸入所述沟槽结构2b内。上电极12a的材质可以是钨材质。衬底1的下表面可以设置下电极12b，下电极12b通过衬底1与第三导体层11连接。
如图4所示，在另一种电容器的结构中，当三维电容基于衬底上的沟槽结构2b 形成时，物料层4包括二氧化硅层，其可以通过热氧化法在衬底1的表面和基础沟槽3的内壁上均匀生长而成。在二氧化硅层上依次层叠设置第三隔离层14a、第二绝缘层13和第四隔离层14c以及上电极12a。由于二氧化硅层的导电性差，为了制作下电极12b，并使下电极12b与第三隔离层14a电连通，在衬底1的底部和物料层4的底部设置有通孔，下电极12b穿过通孔与第三隔离层14a电连接。
如图5所述，在另一种电容器的结构中，该电容器的上电极12a和下电极12b处于同一侧，该种电容器的物料层4也包括二氧化硅层。在物料层4上依次层叠设置第三隔离层14a、第二绝缘层13和第四隔离层14c。不同的是，该第二绝缘层13和第四隔离层14c的面积与第三隔离层14a的面积不同，有一部分第三隔离层14a未被第四隔离层14c和第二绝缘层13所覆盖，以露出部分第三隔离层14a，便于电极与其连接。在第四隔离层14c和露出的第三隔离层14a上覆盖有聚酰亚胺层，且该聚酰亚胺层上设置有至少两个开口，分别露出第四隔离层14c和第三隔离层14a，上电极12a通过其中一个开口与第四隔离层14c连接，下电极12b通过另一个开口与第三隔离层14a连接。
根据本申请的实施例，还提供一种电容器加工方法，用于加工上述的电容器，所述方法包括：
在衬底1上加工基础凸起15，对所述基础凸起15进行加工，形成高宽比大于10的凸起结构2a；或者，在衬底1上加工基础沟槽3，在所述基础沟槽3的表面覆盖物料层4，并形成深宽比大于10的沟槽结构2b；基于所述凸起结构2a或沟槽结构2b加工形成电容器。
先在衬底1上加工出高宽比较小的基础凸起15或深宽比较小的基础沟槽3，之后对基础凸起15进行加工，使基础凸起15的宽度减小量大于高度减小量，从而使加工出的凸起结构2a的高宽比增大且大于10，进而提升电容器的性能，而且无需扩大电容器的体积；或者，在基础沟槽3内覆盖物料层4，通过物料层4形成深宽比大于10的沟槽结构2b，从而提升基于此加工出的电容器的容值密度。
下面对该电容器加工方法和加工过程进行详细说明：
如图7－16所示，当用于形成三维电容的结构为凸起结构2a时，电容器的加工过程如下：
步骤S201：选取衬底1。
在一种可行方式中，选用低电阻率的硅晶圆作为衬底。在另一种可行方式中，可以选择玻璃作为衬底。
步骤S202：在衬底1上加工基础凸起15。
在一种可行实施方式中，加工基础凸起15包括：
子步骤S2021：在所述衬底1的上表面沉积黏附层16。
黏附层16上可以设置种子层2c，根据衬底1的材质以及种子层2c的材质不同，沉积的黏附层16可以是不同的材质，例如，钛(Ti)层、氮化钛层或其他材质等。其主要用于使衬底1与种子层2c连接。当衬底1为硅晶圆，而种子层2c的材质为铜时，为了防止铜扩散到衬底1内而影响加工出的电容器的性能，黏附层16可以是氮化钛层。若衬底1为玻璃，则为了后续工序中能够方便地去除衬底1，黏附层16可以是UV胶。
可选地，由于电镀加工的方式效率高，成本低，若后续加工形成基础凸起15时采 用电镀的方式，则在形成黏附层16后，可以在黏附层16上沉积一层与基础凸起15的材质相同的物质作为种子层2c，以方便后续在进行电镀。具体过程可以为：在黏附层16上沉积一层电镀种子层，之后采用整面电镀的方式生长的铜层作为种子层2c，其厚度可以根据需要确定，例如10微米等，电镀后的结构如图8所示。
若采用电镀之外的方式进行加工，则可以省略沉积种子层的步骤。
在本实施例中，种子层2c的物质为导体，例如为铜，由于铜的电阻率较低，可以很好地保证电容器的性能，且有效降低电容器的造价成本。
子步骤S2022：在所述黏附层16上覆盖牺牲材料层18，并在所述牺牲材料层18上形成用于生成所述基础凸起15的预制凹槽19。
其中，所述预制凹槽19贯穿所述牺牲材料层18。
若存在种子层2c，则牺牲材料层18设置在种子层2c上，若不存在种子层2c则牺牲材料层18可以直接设置在黏附层16上。
牺牲材料层18的牺牲材料可以是光刻胶、聚酰亚胺(polyimide，PI)等有机物，也可以是玻璃、硅的氧化物、硅的氮化物等无机物。制作牺牲材料层18的方法包括喷涂、旋涂、黏贴、氧化、等离子辅助沉积、化学气相沉积(CVD)、物理气相沉积(PVD)等。
例如，材料为光刻胶时，可以通过旋涂等方式在种子层2c的表面制作形成一层50微米厚的牺牲材料层18。通过曝光、显影等方式得到两个宽度为10微米的预制凹槽19。制作后结构如图9所示。优选地，可以选取光刻胶SU－8，JSR151为牺牲材料。
在其他实施例中，去除牺牲材料层18的方法还可以是溶液溶解，湿法腐蚀，等离子刻蚀等方式。
步骤S2023：在预制凹槽内填充导体物质，并形成基础凸起15。
形成预制凹槽19后，在所述预制凹槽19内填充导体物质(如所述种子层2c的物质)，并形成所述基础凸起15。具体例如，用电镀的方式在预制凹槽19内生长铜，形成基础凸起15。最后去除牺牲材料层18，得到宽10微米，高50微米的铜柱，作为基础凸起15，制作后的结构如图10所示。
可选地，为了提升基础凸起15的稳定性，以便于后续加工，故而可以通过调节预制凹槽19的形状使加工出的基础凸起15的稳定性更好。例如，使预制凹槽19为“井”字形、“十”字形槽等，对应加工出“井”字形或“十”字形基础凸起15，后续可以形成“井”字形凸起结构2a或“十”字形凸起结构2a。
步骤S203：对基础凸起15进行加工，并形成高宽比大于10的凸起结构2a。
对所述基础凸起15进行加工时，可以采用刻蚀加工方式，所述刻蚀加工包括各向同性湿法刻蚀或各向同性干法刻蚀。这两种刻蚀方法可以有效调整基础凸起15的高宽比，使其高宽比增大。采用此种方法加工生成凸起结构2a的成本更低，加工速度更快。制作后结构如图11所示。
优选地，采用湿法刻蚀方式，这样可以多片衬底1同时加工，进一步降低成本。
加工出凸起结构2a后，种子层2c与凸起结构2a配合形成第一导体层2，第一导体层2的所述导电材料可以为金属、硅、碳基材料、氮化钛，也可以是上述材料的组合。制作方法包括电镀、蒸镀、化学气相沉积(CVD)、物理气相沉积(PVD)等。
步骤S204：将所述凸起结构2a加工形成电容器。
在一种可行方式中，具体包括以下步骤：
子步骤S2041：在包括所述凸起结构2a的第一导体层2上制作第一绝缘层6和第二导体层7。
具体可以是：用铜腐蚀液去除第一导体层2上的4微米厚的铜，得到6微米厚的第一导体层2，其中，凸起结构2a宽2微米，高50微米。若第一导体层2和第二导体层7的材质为铜，则通过原子层沉积(ALD)的方式，在第一导体层2表面沉积氮化钛作为第一隔离层2d，以隔离第一导体层2和第一绝缘层6，防止铜向第一绝缘层6扩散。之后，沉积氧化铪作为第一绝缘层6。再在第一绝缘层6上沉积氮化钛作为第二隔离层7a。其中，低电阻率的氮化钛作为阻挡层，作用为防止铜扩散到氧化铪层中影响器件性能。氧化铪为高介电常数的电介质。制作后的结构如图12所示。
若第一导体层2的材质不是铜，或者铜对第一绝缘层6的性能没有影响，则第一导体层2与第一绝缘层6之间可以不设置第一隔离层2d，而直接在第一导体层2上加工第一绝缘层6。
当然，在其他实施例方式中，所述第一绝缘层6的绝缘材料可以为其他物质，例如硅的氧化物，硅的氮化物，金属的氧化物，金属的氮化物等。绝缘材料可以是一层或多层。制作绝缘电介质薄膜的方法包括原子层沉积(ALD)、物理气相沉积(PVD)、化学气相沉积(CVD)等方式。
加工第二导体层7时，可以用物理气相沉积(PVD)的方式在第二隔离层7a的表面沉积一层铜作为电镀的种子层。接着用电镀的方式沉积10微米厚的铜层作为第二导体层7。制作后的结构如图13所示。
第二导体层7的材质若不为铜，或者铜对第一绝缘层6的性能没有影响，则第二导体层7与第一绝缘层6之间可以不设置第二隔离层7a。
子步骤S2042：在所述第二导体层7上制作第一电极8，在所述衬底1上制作第二电极9。
具体地，在一种可行方式中，用旋涂SOG(spin－on－glass)的方式生成玻璃防护层35，将上述制作的多层3D结构包覆起来。制作后的结构如图14所示。
用光刻的方式，在玻璃防护层35上打开孔口露出第二导体层7。在孔口中沉积铜层作为电容器的第一电极8。制作后的结构如图15所示。
若衬底1为硅晶圆，则用背面研磨和抛光的方式，将衬底1减薄至100微米。在衬底1背面沉积一层钛和一层铜作为电容的第二电极9，第二电极9通过衬底1与第一导体层2电连接。制作后的结构如图16所示。
若所述衬底1包括玻璃，则在所述第二导体层7上制作第一电极8后，去除所述衬底1的玻璃，并在露出的种子层2c上制作所述第二电极9。制作后的结构如图2所示。去除玻璃的方式可以是用UV(紫外线)照射玻璃背面，使UV胶丧失粘性后，去除玻璃。这样衬底可以重复利用从而降低成本。
如图17－29所示，当用于形成三维电容的结构为沟槽结构2b时，电容器的加工过程如下：
步骤S301：选用低电阻率(例如，0.001Ω.cm)的硅晶圆作为衬底1，并加工形成基础沟槽3。
例如，用DRIE(深反应离子蚀刻)的方法，在衬底1表面制作宽10微米，深100微米的基础沟槽3。制作后的结构如图18所示。
步骤S302：在所述基础沟槽3的表面覆盖物料层4。
通过在基础沟槽3的表面覆盖物料层4可以形成深宽比更大的沟槽结构2b。该物料层4可以是导电材质，也可以是绝缘材料。
在一种可行的实施方式中，若物料层4为导电材料，则覆盖物料层4包括：
在所述基础沟槽3内沉积阻挡层10和电镀种子层，在所述电镀种子层上电镀第三导体层11，并形成所述物料层4，其中，所述第三导体层11的物质与所述电镀种子层的物质相同。
具体地，阻挡层10可以通过PVD(物理气相沉积)的方法，在衬底1的表面和基础沟槽3的内壁沉积一层氮化钛(TiN)形成，电镀种子层可以是一层几十到几百纳米厚的铜层。之后通过电镀的方式，在衬底1表面和基础沟槽3内壁均匀生长2微米厚的铜层，以形成第三导体层11。制作后的结构如图19所示。
若物料层4为绝缘材料，则覆盖物料层4包括：
在所述基础沟槽3内利用热氧化法生长一层二氧化硅层作为所述物料层4。
步骤S303，加工沟槽结构2b，并形成电容器。
形成物料层4后，若物料层4是导电材料，则加工沟槽结构2b，并形成电容器时，需要至少在物料层4表面制作第二绝缘层13和导电层作为电容的电介质和上电极12a。如果物料层4是绝缘材料，则加工沟槽结构2b，并形成电容器时，需要在物料层4表面依次制作导电层、第二绝缘层13和导电层作为电容的下电极、电介质和上电极。
当物料层4是导电材料时，形成第二绝缘层13的方式可以是，用ALD(原子层沉积)的方式，如果第三导体层11是铜等，为了防止铜扩散，在物料层4的第三导体层11的表面依次沉积15纳米厚的氮化钛层(作为第三隔离层14a)，10纳米厚的二氧化铪(HfO2)层(作为第二绝缘层13)和15纳米厚的另一氮化钛层(作为第四隔离层14c)。制作后结构如图20所示。制作上电极12a时可以用CVD(化学气相沉积)的方式，在沟槽结构2b内沉积金属钨作为电容的上电极12a。制作后结构如图21所示。用背面研磨并抛光的方式将衬底1减薄，并在衬底1背面沉积一层铝(Al)作为电容的下电极12b。制作后结构如图22所示。
当物料层4是绝缘材料时，可以用热氧化的方法，在基础沟槽3内壁均匀生长一层二氧化硅作为物料层4。由于二氧化硅为绝缘材料，因此在制作电容器的下电极12b时进行额外的光刻步骤从衬底1背面或正面引出电极。
具体地，在一种可行方式中，将衬底放入炉管中，通入氢气和氧气的混合气体，或含有水蒸气的氧气，在高温条件下生长二氧化硅。制作后结构如图23所示。
之后可以用ALD的方法，在二氧化硅表面依次沉积氮化钛层，二氧化铪层和另一氮化钛层，这三层作为第三隔离层14a、第二绝缘层13和第四隔离层14c，同时两个氮化钛层可以作为导体层使用。在沟槽结构2b内用CVD的方法填充金属钨作为上电极12a。制作后结构如图24所示。之后，在衬底1背面减薄抛光后，用干法刻蚀结合湿法腐蚀的方法，在衬底背面打开孔口露出下部的氮化钛层，制作后结构如图25所示。再通过PVD一层Al制作下电极。制作后结构如图26所示。
在另一种可行方式中，将衬底1放入炉管中，通入氢气和氧气的混合气体，或含 有水蒸气的氧气，在高温条件下生长二氧化硅，制作后结构如图27所示。用ALD的方法，在二氧化硅表面依次沉积氮化钛层(作为第三隔离层14a)，10纳米厚的二氧化铪(HfO2)层(作为第二绝缘层13)和15纳米厚的另一氮化钛层(作为第四隔离层14c)。去除部分上部的氮化钛层和二氧化铪(HfO2)层，露出下部氮化钛层。制作后结构如图28所示。旋涂聚酰亚胺(PI)形成聚酰亚胺层，并在聚酰亚胺层上打开至少两个窗口。其中，至少一个窗口露出下部的氮化钛层，另一个窗口露出上部的氮化钛层。通过PVD方式形成一层Al(铝)层，并图形化，以制作出上电极12a和下电极12b。制作后结构如图29所示。
该电容器加工方法先制作低AR的柱状或墙状基础凸起或基础凹槽。针对基础凸起可以利用速率为各向同性的干法/湿法刻蚀，通过调整刻蚀时间，使刻蚀后的凸起结构的AR提高，从而较为简单地提高3D结构的高宽比。针对基础凹槽，通过在基础凹槽内壁以及衬底表面沉积厚度一致的物料层，可以较为简便地提高形成的沟槽结构的深宽比。这样不仅可以加工晶圆级3D电容器，而且成本低且易操作，能够制作超大AR的3D结构，以及基于此类结构的3D电容器。
需要说明的是，上述对于数量的说明仅仅是为了对本申请实施例作出清楚地解释，并非特别性限定。
此外，本领域技术人员应该能够理解，上述的单元以及模块划分方式仅是众多划分方式中的一种，如果划分为其他单元或模块或不划分块，只要信息对象的具有上述功能，都应该在本申请的保护范围之内。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种电容器，包括用于形成三维电容的结构，所述结构为凸起结构或沟槽结构；
    其中，当所述结构为凸起结构时，所述凸起结构的高宽比大于10；当所述结构为沟槽结构时，所述电容器还包括衬底，所述沟槽结构通过设置在所述衬底上的基础沟槽表面的物料层形成，所述沟槽结构的深宽比大于10。
  2. 根据权利要求1所述的电容器，其中，所述凸起结构的高宽比大于10且小于或等于500，所述沟槽结构的深宽比大于10且小于或等于500。
  3. 根据权利要求1或2所述的电容器，其中，当所述结构为凸起结构时，所述电容器还包括衬底和依次层叠设置的第一导体层、第一绝缘层和第二导体层，所述第一导体层靠近所述衬底设置并包括所述凸起结构，且至少覆盖部分所述衬底。
  4. 根据权利要求3所述的电容器，其中，当所述第一导体层的材料为铜时，所述第一导体层与所述第一绝缘层之间设置有第一隔离层，所述第一隔离层用于防止所述第一导体层的物质向所述第一绝缘层扩散；和/或，所述第二导体层与所述第一绝缘层之间设置有第二隔离层，所述第二隔离层用于防止所述第二导体层的物质向所述第一绝缘层扩散。
  5. 根据权利要求3所述的电容器，其中，所述第一导体层的材料为镍，所述第一绝缘层与所述第一导体层接触，且覆盖在所述第一导体层上。
  6. 根据权利要求3所述的电容器，其中，所述电容器还包括第一电极和第二电极，所述第一电极与所述第二导体层电连接，所述第二电极与所述第一导体层电连接。
  7. 根据权利要求1或2所述的电容器，其中，所述电容器还包括衬底，所述凸起结构通过加工基础凸起形成，所述基础凸起位于所述衬底上，所述基础凸起通过在位于所述衬底上的牺牲材料层的预制凹槽内填充导体物质后去除所述牺牲材料层形成。
  8. 根据权利要求1或2所述的电容器，其中，当所述结构为沟槽结构时，所述物料层包括依次层叠设置的阻挡层和第三导体层，所述阻挡层紧邻所述衬底设置且所述阻挡层包括钽层、氮化钛层、氮化钽层中的至少一层，所述第三导体层包括铜层，且所述铜层通过电镀成型。
  9. 根据权利要求8所述的电容器，其中，所述电容器还包括上电极和第二绝缘层，所述第二绝缘层位于所述上电极与所述第三导体层之间，所述上电极包括上电极主体和上电极支腿，所述上电极主体覆盖在所述第三导体层上，所述上电极支腿伸入所述沟槽结构内。
  10. 根据权利要求9所述的电容器，其中，所述第二绝缘层与所述第三导体层之间设置有第三隔离层，所述第三隔离层用于防止所述第三导体层的物质向所述第二绝缘层扩散，和/或，所述第二绝缘层与所述上电极之间设置有第四隔离层，所述第四隔离层用于防止所述上电极的物质向所述第二绝缘层扩散。
  11. 一种电容器加工方法，用于加工权利要求1－10中任一项所述的电容器，所述方法包括：
    当所述结构为凸起结构时，在衬底上加工基础凸起，对所述基础凸起进行加工，形成高宽比大于10的凸起结构；或者，当所述结构为沟槽结构时，在衬底上加工基础沟槽，在所述基础沟槽的表面覆盖物料层，并形成深宽比大于10的沟槽结构；
    基于所述凸起结构或沟槽结构加工形成电容器。
  12. 根据权利要求11所述的方法，其中，在衬底上加工基础凸起包括：
    在所述衬底的上表面沉积黏附层；
    在所述黏附层上覆盖牺牲材料层，并在所述牺牲材料层上形成用于生成所述基础凸起的预制凹槽，所述预制凹槽贯穿所述牺牲材料层；
    在所述预制凹槽内填充导体物质，并形成所述基础凸起。
  13. 根据权利要求11或12所述的方法，其中，对所述基础凸起进行加工中，通过刻蚀加工所述基础凸起，所述刻蚀加工包括各向同性湿法刻蚀或各向同性干法刻蚀。
  14. 根据权利要求12所述的方法，其中，基于所述凸起结构加工形成电容器包括：
    在第一导体层上制作第一绝缘层和第二导体层，其中，所述第一导体层包括种子层和所述凸起结构；
    在所述第二导体层上制作第一电极，在所述衬底上制作第二电极；或者，当所述衬底包括玻璃时，在所述第二导体层上制作第一电极，去除所述衬底，并在所述种子层上制作所述第二电极。
  15. 根据权利要求11所述的方法，其中，在所述基础沟槽的表面覆盖物料层包括：
    在所述基础沟槽内沉积阻挡层，在所述阻挡层上电镀第三导体层，以形成所述物料层。
  16. 根据权利要求11所述的方法，其中，在所述基础沟槽的表面覆盖物料层包括：
    在所述基础沟槽内利用热氧化法生长一层二氧化硅层作为所述物料层。
  17. 根据权利要求15或16所述的方法，其中，所述加工所述沟槽结构，并形成电容器包括：
    通过原子层沉积法在所述物料层表面依次沉积第三隔离层、第二绝缘层和第四隔离层，其中，所述第三隔离层和所述第四隔离层的物质为导电物质。
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US10910158B2 (en) 2021-02-02
CN111095450A (zh) 2020-05-01
US20200066443A1 (en) 2020-02-27
EP3637448A1 (en) 2020-04-15

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