WO2011103735A1 - 形成带有mim电容器的铜互连结构的方法及所形成的结构 - Google Patents

形成带有mim电容器的铜互连结构的方法及所形成的结构 Download PDF

Info

Publication number
WO2011103735A1
WO2011103735A1 PCT/CN2010/075146 CN2010075146W WO2011103735A1 WO 2011103735 A1 WO2011103735 A1 WO 2011103735A1 CN 2010075146 W CN2010075146 W CN 2010075146W WO 2011103735 A1 WO2011103735 A1 WO 2011103735A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper
mim capacitor
forming
via plug
interconnect structure
Prior art date
Application number
PCT/CN2010/075146
Other languages
English (en)
French (fr)
Inventor
肖德元
黄晓橹
Original Assignee
中国科学院上海微系统与信息技术研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院上海微系统与信息技术研究所 filed Critical 中国科学院上海微系统与信息技术研究所
Priority to US12/937,264 priority Critical patent/US8409962B2/en
Publication of WO2011103735A1 publication Critical patent/WO2011103735A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a metal-insulator-metal (MIM) capacitor structure and a fabrication process thereof, and more particularly to a MIM capacitor structure and a manufacturing process thereof related to copper interconnection technology, and belongs to the technical field of semiconductor fabrication.
  • MIM metal-insulator-metal
  • MIM Capacitors are the key components.
  • the MIM capacitor is usually a sandwich structure in which the upper metal electrode and the lower metal electrode are separated by a thin insulating layer.
  • the metal electrode of the MIM capacitor used AlCu alloy material.
  • copper has replaced aluminum as the mainstream interconnect technology in the manufacture of very large scale integrated circuits. Therefore, the MIM capacitor structure of the copper electrode has been widely used. application.
  • the copper damascene process may include the following steps: 1) first depositing a thin etch stop layer (Si); Then depositing a certain thickness of the insulating layer (Si0 2 ) thereon; 3) then etching out the micro vias (Via); 4) partially etching the via holes; 5) then etching out the trenches (Trench) 6) continue to etch out the complete vias and trenches; 7) followed by a sputtering (PVD) diffusion barrier (TaN/Ta) and a copper seed layer.
  • PVD sputtering
  • the role of Ta is to enhance the adhesion to Cu, the seed layer is used as a conductive layer during electroplating; 8) is the electroplating process of copper interconnects; 9) Finally, annealing and chemical mechanical polishing (CMP), copper plating Flattening and cleaning.
  • CMP chemical mechanical polishing
  • the present invention discloses a method of forming a MIM capacitor structure and a formed structure, The method is compatible with the copper interconnect process, and can increase the capacitor capacity, simplify the process steps, and save production costs.
  • the technical problem to be solved by the present invention is to provide a method of forming a copper interconnect structure with a MIM capacitor and a structure formed.
  • the present invention uses the following technical solutions:
  • a method of forming a copper interconnect structure with a MIM capacitor includes the following steps: Step 1: fabricating a first copper conductive pattern in the first insulating layer;
  • Step 2 forming a first etch stop layer on the first insulating layer, forming a second insulating layer on the first etch stop layer, and fabricating at least one first copper pass in the second insulating layer a hole plug connected to the first copper conductive pattern;
  • Step 3 forming a second etch stop layer on the second insulating layer, and forming a third insulating layer on the second etch stop layer;
  • Step 4 etching the second and third insulating layers around the first copper via plug and the first and second etch stop layer materials from the third insulating layer downward to make the first copper pass
  • the upper surface, the side surface of the hole plug and a portion of the upper surface of the first copper conductive pattern are exposed to form a recessed area;
  • Step 5 forming a dielectric layer on the surface of the structure obtained in the fourth step, and then filling the recessed region covered with the dielectric layer with a protective material;
  • Step six etching down from the dielectric layer on the third insulating layer to form trenches required for other copper conductive patterns
  • Step seven removing the protective material
  • Step 8 plating a copper in the recessed region covered with the dielectric layer to form an upper electrode of the MIM capacitor, and simultaneously performing copper plating in the trench etched in step 6 to complete the other copper conductive pattern to obtain a capacitor with a MIM Copper interconnect structure.
  • the second step further includes: in the second insulating layer, the first copper through hole plug A second copper via plug is fabricated around the second copper via plug to connect to the first copper conductive pattern.
  • the side surface of the second copper via plug is adjacent to the portion of the first copper via plug, and is exposed after the etching in step four.
  • the second step further comprises manufacturing a third copper via plug in the second insulating layer, and connecting the third copper via plug to the first copper conductive pattern.
  • the present invention also provides three MIM capacitor structures prepared by the foregoing method:
  • the first type of MIM capacitor structure prepared by the foregoing method comprising the first copper via plug, the first copper via plug and The first copper conductive pattern connected thereto serves as a lower electrode.
  • the second MIM capacitor structure prepared by the foregoing method includes: the first copper via plug, the second copper via plug; the first copper via plug, the second copper via plug And the first copper conductive pattern connected to them as a lower electrode.
  • the third MIM capacitor structure prepared by the foregoing method includes: the first copper through hole plug, the second copper through hole plug, and the third copper through hole plug; the first copper through hole plug And the second copper via plug, the third copper via plug, and the first copper conductive pattern connected thereto are used as the lower electrode.
  • the present invention also provides a copper interconnect structure with a MIM capacitor prepared by the above method.
  • the method for forming a copper interconnect structure with a MIM capacitor disclosed in the present invention and the formed structure have the beneficial effects that: the method is compatible with the copper interconnect process and can further increase the capacitor within a limited electrode area. Capacity, simplifying process steps and saving production costs.
  • FIG. 1 is a schematic view of a copper damascene process in the background art
  • FIG. 2-7 are schematic views showing a method of forming a copper interconnect structure with a MIM capacitor according to the present invention:
  • FIG. 2 is a schematic cross-sectional view of the structure obtained after the first step, the second step, and the third step;
  • FIG. 3 is a structure obtained after the fourth step. Schematic diagram of the section;
  • FIG. 4 is a schematic cross-sectional view showing a structure obtained after forming a dielectric layer on the surface of the structure obtained in the fourth step;
  • Figure 5 is a schematic cross-sectional view showing the structure obtained after the fifth step;
  • Figure 6 is a schematic cross-sectional view showing the structure obtained after steps 6 and 7;
  • FIG. 8 is a schematic cross-sectional view of a copper interconnect structure with a MIM capacitor obtained in the first embodiment;
  • FIG. 8 is a perspective view of a MIM capacitor structure in which the first copper via plug is prismatic in the first embodiment;
  • FIG. A copper via plug is a perspective view of a cylindrical MIM capacitor structure.
  • a method of forming a copper interconnect structure with a MIM capacitor includes the following steps:
  • Step 1 in the first insulating layer 101, a first copper conductive pattern 400 is fabricated by a copper damascene process, that is, a double damascene process, and diffusion is prepared between the first copper conductive pattern 400 and the first insulating layer 101.
  • the barrier layer 300 isolates it.
  • Step 2 a first etch stop layer 201 is formed on the first insulating layer 101, a second insulating layer 102 is formed on the first etch stop layer 201, and the second insulating layer 102 is used in the second insulating layer 102.
  • the copper damascene process fabricates at least one first copper via plug 401 to be connected to the first copper conductive pattern 400.
  • the side and bottom surfaces of the first copper via plug 401 are provided with a diffusion barrier layer 300.
  • Step 3 forming a second etch stop layer 202 on the second insulating layer 102, and forming a third insulating layer 103 on the second etch stop layer 202.
  • the first, second, and third insulating layers 101, 102, and 103 are each made of a low-k (dielectric constant) dielectric material, and the first and second etch stop layers 201 and 202 are both nitrided. Silicon material.
  • the diffusion barrier layer 300 involved in the embodiment is made of a material such as Ta, TaN, TaS iN or the like. Step 4, as shown in FIG. 3, etching the insulating layer 102 around the first copper via plug 401 from the third insulating layer 103 by selective dry etching.
  • Step 5 as shown in FIG. 4, a dielectric layer 500 is formed on the surface of the structure obtained in the fourth step.
  • the material of the dielectric layer 500 is selected from the group consisting of silicon nitride, oxidized tantalum, titanium oxide, aluminum oxide, etc., and the embodiment is preferably Silicon nitride has a thickness of preferably 15 to 150 nm.
  • a protective material is filled in the recessed region covered with the dielectric layer 500, and the protective material is a bottom anti-reflective coating (BARC, Bot tom Ant i-ref lect ion Coating) The material protects the dielectric layer 500 covered by it from other etching processes.
  • BARC bottom anti-reflective coating
  • the BARC materials herein are materials commonly used by those skilled in the art and are commercially available.
  • the BARC material can be used as a photoresist, that is, a pattern can be formed by photolithography, and a pattern carved by photolithography can also be used as an etching mask.
  • Step 6 is performed by selective dry etching, etching down the dielectric layer 500 on the third insulating layer 103, and etching other copper conductive patterns 700. Grooves (or vias and trenches).
  • Step 7 As shown in Fig. 6, the BARC protective material is removed by a plasma degumming method.
  • the method of removing the glue is a technical means commonly used by those skilled in the art, and details are not described herein.
  • Step 8 as shown in FIG. 7, after removing the protective material, electroplating copper in a recessed region covered with the dielectric layer 500 to form an upper electrode 600 of the MIM capacitor; and simultaneously etching the trench in step 6. Copper is electroplated in the trench (or via and trench) to complete the other copper conductive pattern 700.
  • a diffusion barrier layer 300 is first formed by a copper damascene process, and then a copper seed layer is formed and copper is plated by electrochemical plating (ECP, e lectrochemica l pla ting).
  • ECP electrochemical plating
  • a diffusion barrier layer 300 prepared between the upper electrode 600 of the MIM capacitor and the dielectric layer 500 is used to isolate them.
  • the other copper conductive patterns 700 are also fabricated using a copper damascene process, and the side and bottom surfaces of the other copper conductive patterns 700 are provided with a diffusion barrier layer 300 to isolate them. Finally, the surface of the obtained structure is subjected to chemical mechanical polishing (CMP) to perform copper plating. The planarization process and cleaning result in a copper interconnect structure with a MIM capacitor.
  • CMP chemical mechanical polishing
  • a three-dimensional MIM capacitor is fabricated in the copper interconnect layer, and other copper interconnect conductive patterns can be completed under the protection of the BARC material, which is advantageous for simplifying the manufacturing process of the integrated circuit and saving production cost.
  • the MIM capacitor structure prepared by the method, the first copper via plug 401 and the first copper conductive pattern 400 connected thereto are used as the lower electrodes, and the perspective view thereof is as shown in FIG. 8 and FIG.
  • the first copper through hole plug may be prismatic or cylindrical.
  • the method further includes: manufacturing, in the second insulating layer 102, a second copper via plug 402 around the first copper via plug 401, so that The second copper via plug 402 is connected to the first copper conductive pattern 400, as shown in FIG.
  • the second copper via plug 402 is fabricated by a copper damascene process, and the side and bottom surfaces of the second copper via plug 402 are provided with a diffusion barrier layer 300 to isolate them.
  • the side of the second copper via plug 402 (including the diffusion barrier layer) and the portion of the first copper via plug 401 are exposed after the etching in the fourth step. Thereafter, a copper interconnect structure with a MIM capacitor was obtained in the same manner as in the first embodiment.
  • the first copper via plug 401, the second copper via plug 402, and the first copper conductive pattern 400 connected thereto are used as the lower electrodes.
  • part of the side surface of the second copper via plug 402 is in contact with the dielectric layer 500, which increases the capacitance area and increases the capacitance of the MIM capacitor.
  • the method further includes: using copper in the second insulating layer 102
  • the third copper via plug 403 is connected to the first copper conductive pattern 400, and the third copper via plug 403 and the second insulating layer 102 are formed by a damascene process.
  • a diffusion barrier 300 is prepared to isolate it, as shown in FIG. Thereafter, a copper interconnect structure with a MIM capacitor was obtained in accordance with the method of the second embodiment.
  • the MIM capacitor structure in this embodiment is electrically conductive with the first copper via plug 401, the second copper via plug 402, the third copper via plug 403, and the first copper connected thereto
  • the graphic 400 acts as a lower electrode.
  • the third copper via plug 403 can serve as an extraction electrode for the lower electrode of the MIM capacitor.
  • Other technologies involved in the present invention are within the scope familiar to those skilled in the art and will not be described herein. The technical solutions of the scope and scope should be covered by the scope of the patent application of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

形成带有 MIM电容器的铜互连结构的方法及所形成的结构
本发明涉及一种金属-绝缘体 -金属 （MIM, metal-insulator-metal ) 电 容器结构及其制作工艺， 尤其是一种涉及铜互连技术的 MIM 电容器结构及其 制造工艺， 属于半导体制造技术领域。
背景技术 随着超大规模集成电路的发展， 为了按照摩尔定律的缩放比例创建单元 面积增大的电容， 与此同时确保各种应用所需的高水平性能（泄漏、 击穿或电 压线性）， MIM电容器就是关键的元器件。 MIM电容器通常是一种三明治结构， 其上层金属电极和下层金属电极之间被一层薄绝缘层隔离。 在传统的铝互连 技术中 MIM电容器的金属电极曾釆用 AlCu合金材料， 如今铜已经取代铝成为 超大规模集成电路制造中的主流互连技术， 因此， 铜电极的 MIM 电容器结构 得到了广泛地应用。
在铜互连技术中 ， 釆用铜镶嵌工艺 ， 即双大马士革工艺 (Dual Damascene ) , 如图 1所示， 可包括如下步骤： 1 )首先沉积一层薄的 刻蚀停止层（Si ）； 2)接着在上面沉积一定厚度的绝缘层（Si02)； 3)然 后光刻出微通孔（Via ) ； 4 )对通孔进行部分刻蚀； 5 )之后再光刻出沟槽 (Trench) ； 6)继续刻蚀出完整的通孔和沟槽； 7)接着是溅射（ PVD )扩散 阻挡层 ( TaN/Ta )和铜种籽层 ( Seed Layer ) 。 Ta的作用是增强与 Cu的黏附 性， 种籽层是作为电镀时的导电层； 8 )之后就是铜互连线的电镀工艺； 9) 最后是退火和化学机械抛光（CMP) , 对铜镀层进行平坦化处理和清洗。 在制 作铜电极 MIM 电容器结构时需要其工艺与铜互连制程工艺兼容， 并且随着集 成电路集成度的进一步提高， 需要在有限的电极面积内， 进一步增大电容器 容量。
鉴于此， 本发明公开一种形成 MIM 电容器结构的方法及所形成的结构， 该方法与铜互连制程工艺兼容的同时， 可增大电容器容量， 简化工艺步骤， 节约生产成本。 发明内容 本发明要解决的技术问题在于提供一种形成带有 MIM 电容器的铜互连结 构的方法及所形成的结构。
为了解决上述技术问题， 本发明釆用如下技术方案：
一种形成带有 MIM电容器的铜互连结构的方法， 包括以下步骤： 步骤一， 在第一绝缘层中制造第一铜导电图形；
步骤二， 在所述第一绝缘层上形成第一刻蚀停止层， 在所述第一刻蚀停 止层上形成第二绝缘层， 在所述第二绝缘层中制造至少一个第一铜通孔栓使 之与所述第一铜导电图形相连；
步骤三， 在所述第二绝缘层上形成第二刻蚀停止层， 在所述第二刻蚀停 止层上形成第三绝缘层；
步骤四， 从所述第三绝缘层向下， 刻蚀掉所述第一铜通孔栓周围的第二、 三绝缘层及第一、 二刻蚀停止层材料， 使所述第一铜通孔栓的上表面、 侧面 及所述第一铜导电图形的部分上表面露出， 形成凹陷区域；
步骤五， 在步骤四所得结构表面形成介电层， 之后在覆盖有所述介电层 的凹陷区域内填充保护材料；
步骤六， 从所述第三绝缘层上的介电层向下刻蚀， 形成其他铜导电图形 所需的沟槽；
步骤七， 去除所述保护材料；
步骤八， 在覆盖有所述介电层的凹陷区域内镀铜形成 MIM 电容器的上电 极， 同时在步骤六刻蚀出的沟槽中镀铜完成所述其他铜导电图形， 得到带有 MIM电容器的铜互连结构。
进一步地， 步骤二还包括： 在所述第二绝缘层中， 于所述第一铜通孔栓 周围制造第二铜通孔栓， 使所述第二铜通孔栓与所述第一铜导电图形相连。 其中， 所述第二铜通孔栓的侧面， 靠近所述第一铜通孔栓的部分， 经步骤四 的刻蚀后露出。
进一步地， 步骤二还包括于所述第二绝缘层中制造第三铜通孔栓， 使所 述第三铜通孔栓与所述第一铜导电图形相连。
另外， 本发明还提供三种釆用前述方法制备的 MIM电容器结构： 第一种釆用前述方法制备的 MIM 电容器结构， 包括所述第一铜通孔栓， 所述第一铜通孔栓及与之相连的所述第一铜导电图形作为下电极。
第二种釆用前述方法制备的 MIM电容器结构， 包括： 所述第一铜通孔栓、 所述第二铜通孔栓； 所述第一铜通孔栓、 所述第二铜通孔栓以及与它们相连 的所述第一铜导电图形作为下电极。
第三种釆用前述方法制备的 MIM电容器结构， 包括： 所述第一铜通孔栓、 所述第二铜通孔栓、 所述第三铜通孔栓； 所述第一铜通孔栓、 所述第二铜通 孔栓、 所述第三铜通孔栓以及与它们相连的所述第一铜导电图形作为下电极。
本发明还提供一种釆用上述方法制备的带有 MIM电容器的铜互连结构。 本发明公开的形成带有 MIM 电容器的铜互连结构的方法及所形成的结构 的有益效果在于： 该方法与铜互连制程工艺兼容的同时， 可在有限的电极面 积内， 进一步增大电容器容量， 简化工艺步骤， 节约生产成本。
附图说明 图 1为背景技术中铜镶嵌工艺的示意图；
图 2-7为本发明形成带有 MIM电容器的铜互连结构的方法示意图： 图 2为经步骤一、 步骤二和步骤三之后所得结构的剖面示意图； 图 3为经步骤四之后得到结构的剖面示意图；
图 4为在步骤四所得结构表面形成介电层之后所得结构剖面示意图； 图 5为经步骤五之后得到结构的剖面示意图；
图 6为经步骤六、 七之后得到结构的剖面示意图；
图 Ί为最终得到的带有 MIM电容器的铜互连结构的剖面示意图； 图 8为实施例一中第一铜通孔栓为棱柱形的 MIM电容器结构的立体图； 图 9为实施例一中第一铜通孔栓为圓柱形的 MIM电容器结构的立体图。
具体实施方式 下面结合附图进一步说明本发明， 为了示出的方便附图并未按照比例绘 制。
实施例一
请参看图 2-7 , —种形成带有 MIM电容器的铜互连结构的方法， 包括以下 步骤：
步骤一， 在第一绝缘层 101 中釆用铜镶嵌工艺， 即双大马士革工艺制造 第一铜导电图形 400 ,在所述第一铜导电图形 400与所述第一绝缘层 101之间 制备有扩散阻挡层 300将其隔离。
步骤二， 在所述第一绝缘层 101上形成第一刻蚀停止层 201 , 在所述第一 刻蚀停止层 201上形成第二绝缘层 102 ,在所述第二绝缘层 102中釆用铜镶嵌 工艺制造至少一个第一铜通孔栓 401使之与所述第一铜导电图形 400相连； 所述第一铜通孔栓 401的侧面及底面制备有扩散阻挡层 300。
步骤三， 在所述第二绝缘层 102上形成第二刻蚀停止层 202 , 在所述第二 刻蚀停止层 202上形成第三绝缘层 103。
经这三步后形成如图 1所示的结构。所述的第一、第二、第三绝缘层 101 , 102 , 103 均釆用低 k (介电常数） 的介质材料， 所述第一、 第二刻蚀停止层 201 , 202均釆用氮化硅材料。 实施例中涉及的扩散阻挡层 300釆用 Ta、 TaN、 TaS iN等材料。 步骤四， 如图 3 所示， 釆用选择性干法刻蚀的方法， 从所述第三绝缘层 103向下， 刻蚀掉所述第一铜通孔栓 401周围的绝缘层 102 , 103及刻蚀停止 层 201 , 202 , 使所述第一铜通孔栓 401的上表面、 侧面及所述第一铜导电图 形 400的部分上表面露出， 形成凹陷区域； 此时露出的所述第一铜通孔栓 401 的侧面覆盖有扩散阻挡层 300。
步骤五， 如图 4所示， 在步骤四所得结构表面形成介电层 500, 所述介电 层 500 的材料选自氮化硅、 氧化坦、 氧化钛、 氧化铝等， 本实施例优选为氮 化硅， 厚度优选为 15-150nm。 之后， 如图 5所示， 在覆盖有所述介电层 500 的凹陷区域内填充保护材料， 所述保护材料为底抗反射涂层 （BARC , Bot tom Ant i-ref lect ion Coa t ing )材料， 可保护被其覆盖的介电层 500免受其他刻 蚀等工艺的污染。 这里的 BARC材料是本领域技术人员常用的材料， 可以在市 面上购买获得。 BARC材料既可以当作光刻胶使用， 即可以通过光刻刻出图案， 同时还可以利用光刻刻出的图案作为腐蚀掩膜。
步骤六， 如图 6 所示， 釆用选择性干法刻蚀的方法， 从所述第三绝缘层 103上的介电层 500向下刻蚀， 刻蚀出其他铜导电图形 700所需的沟槽（或通 孔和沟槽） 。
步骤七， 如图 6所示， 釆用等离子去胶方法去除所述 BARC保护材料。 该 去胶方法是本领域技术人员常用的技术手段， 在此不再赘述。
步骤八， 如图 7 所示， 除去所述保护材料后， 在覆盖有所述介电层 500 的凹陷区域内电镀铜， 从而形成 MIM电容器的上电极 600; 同时在步骤六刻蚀 出的沟槽（或通孔和沟槽）中电镀铜， 完成所述其他铜导电图形 700。 制作所 述 MIM电容器的上电极 600时， 利用铜镶嵌工艺， 首先形成扩散阻挡层 300, 然后形成铜种籽层并釆用电化学电镀（ ECP , e lectrochemica l pla t ing ) 的 方法镀铜， 其中在所述 MIM电容器的上电极 600与所述介电层 500之间制备 的扩散阻挡层 300用于将它们隔离。 制作所述其他铜导电图形 700也釆用了 铜镶嵌工艺， 所述其他铜导电图形 700 的侧面及底面制备有扩散阻挡层 300 将其隔离。 最后， 对所得结构表面进行化学机械抛光（CMP ) , 对铜镀层进行 平坦化处理和清洗， 得到带有 MIM电容器的铜互连结构。
本方案在铜互连层中制作立体 MIM电容器的同时，在 BARC材料的保护下， 可完成其他铜互连导电图形， 有利于简化集成电路的制造工艺， 节约生产成 本。 釆用这种方法制备的 MIM电容器结构， 以所述第一铜通孔栓 401及与之 相连的所述第一铜导电图形 400作为下电极， 其立体图如图 8、 图 9所示， 其 中， 第一铜通孔栓可为棱柱或圓柱形。
实施例二
作为本发明的优选方案之一， 进行所述步骤二时， 还包括： 在所述第二 绝缘层 102中， 于所述第一铜通孔栓 401周围制造第二铜通孔栓 402 , 使所述 第二铜通孔栓 402与所述第一铜导电图形 400相连， 如图 2所示。
其中， 釆用铜镶嵌工艺制造所述第二铜通孔栓 402 , 所述第二铜通孔栓 402的侧面及底面制备有扩散阻挡层 300将其隔离。所述第二铜通孔栓 402的 侧面 （包括扩散阻挡层） ， 靠近所述第一铜通孔栓 401 的部分， 经步骤四的 刻蚀后露出。 之后， 按照实施例一中的方法得到带有 MIM 电容器的铜互连结 构。
本实施例中的 MIM电容器结构， 以所述第一铜通孔栓 401、 所述第二铜通 孔栓 402 以及与它们相连的所述第一铜导电图形 400作为下电极。 此时， 所 述第二铜通孔栓 402的部分侧面与介电层 500接触， 增加了电容面积， 增大 了 MIM电容器的电容量。
实施例三
作为本发明的另一优选方案， 进行所述步骤二时， 除了如实施例二所述 的制造第二铜通孔栓 402之外， 还包括： 在所述第二绝缘层 102 中釆用铜镶 嵌工艺制造第三铜通孔栓 403 ,使所述第三铜通孔栓 403与所述第一铜导电图 形 400相连， 所述第三铜通孔栓 403与所述第二绝缘层 102之间制备有扩散 阻挡层 300将其隔离， 如图 1所示。 之后， 按照实施例二中的方法得到带有 MIM电容器的铜互连结构。 本实施例中的 MIM电容器结构， 以所述第一铜通孔栓 401、 所述第二铜通 孔栓 402、 所述第三铜通孔栓 403以及与它们相连的所述第一铜导电图形 400 作为下电极。 所述第三铜通孔栓 403可以作为 MIM电容器下电极的引出电极。 本发明中涉及的其他技术属于本领域技术人员熟悉的范畴， 在此不再赘述。 和范围的技术方案均应涵盖在本发明的专利申请范围当中。

Claims

权利要 求书
1. 一种形成带有 MIM电容器的铜互连结构的方法， 其特征在于， 包括以 下步骤：
步骤一， 在第一绝缘层 （101 ) 中制造第一铜导电图形 （ 400 ) ； 步骤二，在所述第一绝缘层（ 101 )上形成第一刻蚀停止层（ 201 ) , 在所述第一刻蚀停止层（201 )上形成第二绝缘层（102 ) , 在所述第 二绝缘层（102 ) 中制造至少一个第一铜通孔栓（401 )使之与所述第 一铜导电图形 ( 400 )相连；
步骤三，在所述第二绝缘层（ 102 )上形成第二刻蚀停止层（ 202 ) , 在所述第二刻蚀停止层 （ 202 )上形成第三绝缘层 （103 ) ；
步骤四， 从所述第三绝缘层（ 103 )向下， 刻蚀掉所述第一铜通孔 栓（401 )周围的第二、 三绝缘层（ 1 02 , 103 )及第一、 二刻蚀停止层 ( 201 , 202 ) , 使所述第一铜通孔栓（401 )的上表面、 侧面及所述第 一铜导电图形 （ 400 ) 的部分上表面露出， 形成凹陷区域；
步骤五， 在步骤四所得结构表面形成介电层（ 500 ) , 之后在覆盖 有所述介电层（ 500 ) 的凹陷区域内填充保护材料；
步骤六， 从所述第三绝缘层（103 )上的介电层（ 500 )向下刻蚀， 形成其他铜导电图形 （ 700 )所需的沟槽；
步骤七， 去除所述保护材料；
步骤八， 在覆盖有所述介电层（ 500 )的凹陷区域内镀铜形成 MIM 电容器的上电极（ 600 ) , 同时在步骤六刻蚀出的沟槽中镀铜完成所述 其他铜导电图形 （ 700 ) , 得到带有 MIM电容器的铜互连结构。
2. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤八之后对所得结构表面进行化学机械抛光。
3. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤一中釆用铜镶嵌工艺制造所述第一铜导电图形 （ 400 ) , 所述第一铜导电图形 （ 400 ) 与所述第一绝缘层 （101 )之间制备有扩 散阻挡层 （ 300 )将其隔离。
4. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤二中釆用铜镶嵌工艺制造所述第一铜通孔栓（401 ) , 所 述第一铜通孔栓（401 ) 的侧面及底面制备有扩散阻挡层 （ 300 ) 。
5. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 所述介电层（ 500 )的材料选自氮化硅、 氧化坦、 氧化钛、 氧 化铝中的一种。
6. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 所述保护材料为 BARC材料。
7. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤八中， 制作所述 MIM电容器的上电极（ 600 )时， 首先形 成扩散阻挡层（ 300 ) , 然后形成铜种籽层并釆用电化学电镀的方法镀 铜形成所述 MIM电容器的上电极 ( 600 ) 。
8. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 釆用铜镶嵌工艺制作所述其他铜导电图形（ 700 ) , 所述其他 铜导电图形 （ 700 ) 的侧面及底面制备有扩散阻挡层（ 300 ) 。
9. 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤二还包括： 在所述第二绝缘层（102 ) 中， 于所述第一铜 通孔栓（401 )周围制造第二铜通孔栓（ 402 ) ， 使所述第二铜通孔栓
( 402 )与所述第一铜导电图形 （ 400 )相连。
10.根据权利要求 9所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于：所述第二铜通孔栓（ 402 )的侧面，靠近所述第一铜通孔栓（ 401 ) 的部分， 经步骤四的刻蚀后露出。 根据权利要求 9所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤二中釆用铜镶嵌工艺制造所述第二铜通孔栓（ 402 ) , 所 述第二铜通孔栓（ 402 ) 的侧面及底面制备有扩散阻挡层 （ 300 ) 。 根据权利要求 1所述形成带有 MIM电容器的铜互连结构的方法， 其特 征在于： 步骤二还包括于所述第二绝缘层（102 )中制造第三铜通孔栓
( 403 ) , 使所述第三铜通孔栓（ 403 ) 与所述第一铜导电图形 （ 400 ) 相连。 根据权利要求 12所述形成带有 MIM电容器的铜互连结构的方法，其特 征在于： 步骤二中釆用铜镶嵌工艺制造所述第三铜通孔栓（ 403 ) , 所 述第三铜通孔栓（ 403 ) 的侧面及底面制备有扩散阻挡层 （ 300 ) 。 一种釆用权利要求 1所述形成带有 MIM电容器的铜互连结构的方法制 备的带有 MIM电容器的铜互连结构。
PCT/CN2010/075146 2010-02-25 2010-07-14 形成带有mim电容器的铜互连结构的方法及所形成的结构 WO2011103735A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/937,264 US8409962B2 (en) 2010-02-25 2010-07-14 Manufacturing method of copper interconnection structure with MIM capacitor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010114118.9 2010-02-25
CN2010101141189A CN101807517B (zh) 2010-02-25 2010-02-25 形成铜互连mim电容器结构的方法

Publications (1)

Publication Number Publication Date
WO2011103735A1 true WO2011103735A1 (zh) 2011-09-01

Family

ID=42609253

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/075146 WO2011103735A1 (zh) 2010-02-25 2010-07-14 形成带有mim电容器的铜互连结构的方法及所形成的结构

Country Status (3)

Country Link
US (1) US8409962B2 (zh)
CN (1) CN101807517B (zh)
WO (1) WO2011103735A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9565766B2 (en) * 2011-10-07 2017-02-07 Intel Corporation Formation of DRAM capacitor among metal interconnect
FR2994019B1 (fr) * 2012-07-25 2016-05-06 Commissariat Energie Atomique Procede pour la realisation d'une capacite
US8772157B2 (en) * 2012-11-02 2014-07-08 Shanghai Huali Microelectronics Corporation Method of forming Cu interconnects
US9093386B2 (en) 2013-11-20 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer-damage-free etching
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
US9276057B2 (en) * 2014-01-27 2016-03-01 United Microelectronics Corp. Capacitor structure and method of manufacturing the same
JP7272098B2 (ja) * 2019-05-09 2023-05-12 富士通セミコンダクターメモリソリューション株式会社 半導体装置および半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1194418C (zh) * 2000-03-01 2005-03-23 因芬尼昂技术股份公司 一种集成元件的制造方法
CN1605113A (zh) * 2001-12-13 2005-04-06 因芬尼昂技术股份公司 包含金属－绝缘体－金属电容器之集成半导体产品
US7511327B2 (en) * 2002-02-14 2009-03-31 Renesas Technology Corp. Capacitive electrode having semiconductor layers with an interface of separated grain boundaries
CN101587891A (zh) * 2008-05-21 2009-11-25 海力士半导体有限公司 半导体存储器件及其电容器的形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252446A (ja) * 2001-02-23 2002-09-06 Sony Chem Corp フレキシブル配線基板の製造方法
US6593185B1 (en) * 2002-05-17 2003-07-15 United Microelectronics Corp. Method of forming embedded capacitor structure applied to logic integrated circuit
CN100536109C (zh) * 2003-12-30 2009-09-02 中芯国际集成电路制造(上海)有限公司 用铜制造高电容量电容器的方法及其结构
US7223654B2 (en) * 2005-04-15 2007-05-29 International Business Machines Corporation MIM capacitor and method of fabricating same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1194418C (zh) * 2000-03-01 2005-03-23 因芬尼昂技术股份公司 一种集成元件的制造方法
CN1605113A (zh) * 2001-12-13 2005-04-06 因芬尼昂技术股份公司 包含金属－绝缘体－金属电容器之集成半导体产品
US7511327B2 (en) * 2002-02-14 2009-03-31 Renesas Technology Corp. Capacitive electrode having semiconductor layers with an interface of separated grain boundaries
CN101587891A (zh) * 2008-05-21 2009-11-25 海力士半导体有限公司 半导体存储器件及其电容器的形成方法

Also Published As

Publication number Publication date
US20110291235A1 (en) 2011-12-01
US8409962B2 (en) 2013-04-02
CN101807517B (zh) 2011-09-21
CN101807517A (zh) 2010-08-18

Similar Documents

Publication Publication Date Title
US8841749B2 (en) Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
KR100532455B1 (ko) Ｍｉｍ 커패시터 및 배선 구조를 포함하는 반도체 장치의제조 방법
JP3895126B2 (ja) 半導体装置の製造方法
WO2011103735A1 (zh) 形成带有mim电容器的铜互连结构的方法及所形成的结构
JP2003282573A (ja) 半導体装置のボンディングパッド構造とその製造法
JP2002141417A (ja) 並列キャパシタの積層構造と製造方法
KR100806034B1 (ko) Ｍｉｍ 캐패시터를 가지는 반도체 소자 및 그 제조방법
JP4229642B2 (ja) 半導体集積回路用インダクタ及びその製造方法
TW201216429A (en) Conductive pillar structure
KR101385281B1 (ko) 공간 효율적 커패시터들을 구비한 집적 회로 및 그 제조 방법
US7709878B2 (en) Capacitor structure having butting conductive layer
JPH11274428A (ja) 半導体装置及びその製造方法
US7956398B2 (en) Capacitor of semiconductor device and method of fabricating the same
CN111785681B (zh) 存储器件及其制造方法
KR100720519B1 (ko) 반도체 소자 및 그 제조방법
JP2001203329A (ja) 半導体装置およびその製造方法
TWI701765B (zh) 電子裝置及其製造方法
KR20040061817A (ko) 반도체소자의 금속배선 형성방법
CN110767633A (zh) 一种不同深度的电容结构及制作方法
KR100800823B1 (ko) Ｍｉｍ 커패시터를 갖는 반도체 소자의 배선 제조 방법
JP2003031665A (ja) 半導体装置の製造方法
KR20040009749A (ko) 반도체 소자의 제조방법
JP2006253268A (ja) 半導体装置およびその製造方法
KR20020051350A (ko) 반도체장치의 배선 및 배선연결부 및 그 제조방법
CN114220917A (zh) 具有mim电容器的半导体器件及其制备方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 12937264

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10846358

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10846358

Country of ref document: EP

Kind code of ref document: A1