WO2020035008A1 - 一种走线结构及其制备方法、显示装置 - Google Patents

一种走线结构及其制备方法、显示装置 Download PDF

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WO2020035008A1
WO2020035008A1 PCT/CN2019/100659 CN2019100659W WO2020035008A1 WO 2020035008 A1 WO2020035008 A1 WO 2020035008A1 CN 2019100659 W CN2019100659 W CN 2019100659W WO 2020035008 A1 WO2020035008 A1 WO 2020035008A1
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Prior art keywords
layer
wiring
substrate
electrode
structure according
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PCT/CN2019/100659
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English (en)
French (fr)
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李海旭
曹占锋
王珂
汪建国
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京东方科技集团股份有限公司
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Priority to US16/643,919 priority Critical patent/US11650637B2/en
Publication of WO2020035008A1 publication Critical patent/WO2020035008A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component

Definitions

  • the present disclosure relates to the field of display, and in particular to a wiring structure, a method for manufacturing the same, and a display device.
  • the signal lines on the substrate can be prepared by electroplating.
  • the electroplating process has the advantages of fast deposition rate, low cost, and low deposition temperature (just room temperature).
  • the electroplated copper layer has the advantages of good electrical conductivity, thermal conductivity, and mechanical ductility. Therefore, the electroplated copper technology has become one of the essential key technologies in modern microelectronics manufacturing.
  • the principle of electroplating copper is Faraday's law of electrolysis: During electrolysis, the mass of the substance that precipitates or dissolves on the electrode is proportional to the amount of electricity passing through the electrode. On the anode copper block, copper atoms lose electrons and become copper ions. On the cathode wafer, on the other hand, copper ions gain electrons and become copper atoms.
  • Embodiments of the present disclosure provide a wiring structure, a manufacturing method thereof, and a display device.
  • a wiring structure which includes a base body; a pre-arranged layer located on the base body; an electrode wiring line covering the pre-arranged layer; an orthographic projection of the pre-arranged layer on the base body is located at The orthographic projection of the electrode traces on the substrate.
  • the wiring structure further includes a seed layer, and the seed layer is located between the pre-arranged layer and the electrode wiring.
  • the pre-arranged layer is axisymmetric about a center line of the electrode trace, and the center line is parallel to an extending direction of the electrode trace.
  • a cross section of the pre-arranged layer perpendicular to a plane on which the substrate is located and perpendicular to an extending direction of the electrode trace is trapezoidal.
  • the material of the pre-arranged layer is selected from one of a metal material, an organic material, or an inorganic material.
  • the included angle between the side surface of the pre-arranged layer and the plane on which the substrate is located is in a range of 15-60 °.
  • the thickness of the pre-arranged layer is greater than 0.01 um and less than 1/2 of the thickness of the seed layer.
  • a material of the electrode wiring is copper.
  • the material of the seed layer includes copper or molybdenum.
  • a display device including the above-mentioned wiring structure.
  • a method for preparing a wiring structure including:
  • the method further includes:
  • a seed layer is formed on the pre-arranged layer.
  • forming the electrode wiring at the wiring location includes:
  • An electric field is formed between the seed layer and the plating ion-containing solution, and the electrode wiring is formed at the wiring position.
  • forming a retaining wall structure on both sides of the pre-arranged layer includes:
  • two adjacent photoresist sub-patterns of the at least two photoresist sub-patterns are spaced apart to define the trace position, and the trace position exposes a surface of the seed layer.
  • it further includes:
  • FIG. 1 is a schematic structural diagram of electrode wiring in the related art
  • FIG. 2 is a cross-sectional view of the electrode trace in FIG. 1 along the AA ′ direction when electroplating is completed;
  • FIG. 3 is a cross-sectional view of a wiring structure according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a pre-arranged layer formed on a substrate in a method for manufacturing a wiring structure according to an embodiment of the present disclosure
  • FIG. 5 is a cross-sectional view of a substrate after forming a seed layer in a method for manufacturing a wiring structure according to an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional view after a retaining wall is formed in a method for manufacturing a wiring structure according to an embodiment of the present disclosure
  • FIG. 7 is a cross-sectional view of an electrode wiring formed in a method for manufacturing a wiring structure according to an embodiment of the present disclosure
  • FIG. 8 is a plan view before forming electrode wiring in a method for manufacturing a wiring structure according to an embodiment of the present disclosure
  • FIG. 9 is a plan view of an electrode wiring formed in a method for manufacturing a wiring structure according to an embodiment of the present disclosure.
  • the wiring structure includes a base 3, a pre-arranged layer 5 on a surface of the base 3, and an electrode trace 1 covering the pre-arranged layer 5.
  • the pre-arranged layer 5 can guide the growth direction of the electrode wiring 1 above, and give priority to copper ions. In the area where the pre-arranged layer is located, it is reduced to copper atoms, so that the inside of the finally formed electrode trace is dense and defect-free.
  • the material of the substrate 3 may be selected from any material such as glass, silicon, plastic, and polyimide.
  • the material of the electrode trace 1 is a metal, such as copper.
  • the electrode traces 1 are formed on the seed layer 4 by a plating process.
  • the material of the pre-arranged layer 5 may be an inorganic material, such as a nitrogen silicon compound or silicon monoxide; or the material of the pre-arranged layer 5 may be a metal material, such as molybdenum, copper, aluminum, etc .; or the material of the pre-arranged layer 5 may be Organic materials, such as resins.
  • the pre-arranged layer 5 is formed on the substrate 3 below the seed layer 4 that needs to be plated with the electrode wiring 1 before the seed layer 4 is formed.
  • the width of the pre-arranged layer 5 is not greater than the width of the electrode trace 1, that is, the orthographic projection of the pre-arranged layer 5 on the substrate 3 is located within the orthographic projection of the electrode trace 1 on the substrate, so that the electrode
  • the line 1 can form a structure covering the pre-arranged layer 5 under the guidance of the pre-arranged layer 5.
  • the pre-arrangement layer is axisymmetric about a center line of the electrode trace, and the center line is a center line parallel to an extending direction of the electrode trace.
  • the shape of the pre-arranged layer 5 is not limited, as long as the side surface of the pre-arranged layer 5 forms a certain angle with the base 3 so that the pre-arranged layer 5 can guide the growth direction of the electrode wiring 1.
  • the angle between the two sides of the pre-arranged layer 5 and the plane of the base 3 is 15-60 °
  • the cross-section of the pre-arranged layer 5 is trapezoidal, preferably an isosceles trapezoid. Reduction to copper atoms, so that the electrode traces finally formed are dense and defect-free inside.
  • the angle between the two sides of the pre-arranged layer 5 and the plane on which the substrate 3 is located is greater than 60 °, the growth direction of the pre-arranged layer 5 may be too large, resulting in poor growth of the outer side of the electrode wiring 1.
  • the angle between the side and the plane on which the substrate 3 is located is less than 15 °, the guide growth direction of the pre-arranged layer 5 is too small, and the guide effect of the pre-arranged layer 5 is lost.
  • the two wiring structures that are finally formed are an integrated structure, that is, the pre-arrangement layer also forms a part of the electrode wiring.
  • the wiring structure provided by the embodiment of the present disclosure may further include a seed layer 4, and the seed layer 4 is located between the pre-arranged layer 5 and the electrode wiring 1.
  • the material of the seed layer 4 may be a conductive metal material, such as a metal material such as molybdenum, copper, or a copper alloy.
  • the seed layer 4 is a metal material, the seed layer 4 is formed on the surface of the substrate 3 and the surface of the pre-arranged layer 5 by a magnetron sputtering process.
  • both of the finally formed wiring structure are an integrated structure, that is, the seed layer 4 also forms a part of the electrode wiring 1.
  • the thickness of the pre-arranged layer 5 is greater than 0.01 micrometer (um) and less than 1/2 of the thickness of the seed layer, so that the pre-arranged layer 5 can guide the formation of the electrode traces 1;
  • the thickness of 5 is less than 0.01um, the pre-arranged layer 5 is too thin, on the one hand, it is difficult to form on the substrate 3 in the production process; on the other hand, the pre-arranged layer 5 cannot effectively guide the formation of the electrode wiring 1;
  • the thickness of 5 is greater than 1/2 of the thickness of the seed layer 4, the pre-arranged layer 5 is too thick, which is not convenient for the formation of the seed layer 4, and it is easy to cause the seed layer 4 to overlap poorly on the pre-arranged layer 5 and cause the seed layer 4 to break. And other undesirable phenomena.
  • the length of the pre-arrangement layer 5 may be the same as the length of the electrode trace 1, or may be longer than the length of the electrode trace 1.
  • An embodiment of the present disclosure provides a display device including the above-mentioned wiring structure.
  • An embodiment of the present disclosure provides a method for preparing a wiring structure, including:
  • a base body 3 is provided; a pre-layout layer 5 is formed on the base body 3; the length of the pre-layout layer 5 is equal to the length of the wiring position, and the width of the pre-layout layer 5 is not greater than the width of the wiring position, that is, after the formation
  • the electrode traces cover the pre-arrangement layer 5 so that the electrode traces can be formed under the guidance of the pre-arrangement layer 5; and the width of the pre-arrangement layer 5 can be adjusted according to the current density and solute concentration in the specific plating to guide Formation of electrode traces 1; when the material of the pre-arrangement layer 5 is an inorganic material, such as a nitrogen silicon compound or silicon monoxide, the pre-arrangement layer 5 is formed on the trace position by a chemical vapor deposition process; The material is metal, such as molybdenum, copper, aluminum, etc., and the pre-arrangement layer 5 is formed on the wiring position by a magnetron sputtering process;
  • a seed layer 4 is formed on the surface of the substrate 3 and the surface of the pre-arranged layer 5.
  • the seed layer 4 may be a metal material such as molybdenum, copper, or a copper alloy, and the seed layer 4 may be formed by a magnetron sputtering process.
  • a retaining wall structure 6 is formed on both sides of the pre-arranged layer, and the retaining wall structure defines a routing position 7.
  • a photoresist layer may be first formed on the seed layer 4; thereafter, a patterning process is performed on the photoresist layer to form at least two photoresist sub-patterns,
  • the wall structure 6 includes the at least two photoresist sub-patterns; two adjacent photoresist sub-patterns are spaced apart to define a routing position 7, wherein the routing position 7 exposes a surface of the seed layer 4, and That is, a groove is formed between two adjacent photoresist sub-patterns through a patterning process, so as to limit the position where the electrode trace 1 grows during plating and to limit the thickness of the electrode trace 1.
  • an electrode trace 1 is formed on the seed layer 4 at the trace position by using an electroplating process.
  • the electrode trace 1 as a copper electrode trace as an example
  • the structure is placed in a solution containing copper ions, the seed layer 4 on the substrate 3 is used as a cathode, and the solution containing copper ions is used as an anode, and a voltage is applied to the anode and the cathode; Copper ions can only get electrons at trace position 7 of substrate 3 and are reduced to copper atoms, so they are gradually deposited on the seed layer 4 in the area of trace position 7.
  • pre-arranged layer 5 It can guide the direction of copper ion deposition so that copper ions are preferentially reduced to copper atoms in the area where the pre-arrangement layer 5 is located, so that the inside of the electrode trace 1 formed is dense and defect-free, and the internal plating of the electrode trace 1 is not complete.
  • the retaining wall 6 and the seed layer located outside the wiring position 7 are removed in order to complete the preparation of the wiring structure.
  • the electrode wiring 1 in the method for preparing a wiring structure provided by the present disclosure, by forming a pre-arranged layer 5 on a substrate 3, when the electrode wiring 1 is formed using an electroplating process, the electrode wiring 1 can be guided by the pre-arranged layer 5 to make copper
  • the ions are preferentially reduced to copper atoms in the area where the pre-arranged layer 5 is located, avoiding the preferential crystallization of the position of the edge of the retaining wall 6, causing the risk of holes in the middle of the electrode traces, thereby avoiding the formation of dense and defect-free electrode traces.
  • the method embodiments provided in the embodiments of the present disclosure can be cross-referenced with the corresponding wiring structure embodiments, which are not limited in the embodiments of the present disclosure.
  • the order of the steps of the method embodiments provided by the embodiments of the present disclosure can be appropriately adjusted, and the steps can be increased or decreased according to the situation. Any person skilled in the art can easily think of changes within the technical scope disclosed in the present disclosure. The methods should all be covered by the protection scope of the present disclosure, so they will not be described again.

Abstract

一种走线结构及其制备方法、显示装置，该走线结构包括基体（3）；预布置层（5），位于所述基体（3）上；电极走线（1），覆盖所述预布置层（5）；所述预布置层（5）在所述基体（3）上的正投影位于所述电极走线（1）在所述基体（3）上的正投影内。该走线结构的制备方法能够在基体（3）上形成致密且无缺陷的电极走线（1），避免电极走线（1）中出现孔洞。

Description

一种走线结构及其制备方法、显示装置
相关申请的交叉引用
本公开要求于2018年08月15日提交、申请号为201810928918.0、发明名称为“一种走线结构及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示领域，尤指一种走线结构及其制备方法、显示装置。
背景技术
位于基体上信号线可以采用电镀工艺制备而成，电镀工艺具有淀积速率快、费用较低、淀积温度较低(室温即可)等优点。特别是电镀铜层具有良好的导电性、导热性和机械延展性等优点，因此电镀铜技术己成为现代微电子制造中必不可少的关键技术之一。电镀铜原理是法拉第电解定律：电解时，在电极上析出或溶解的物质质量与通过电极的电量成正比。在阳极铜块上铜原子失去电子变成铜离子，相反在阴极晶片上，铜离子得到电子变成铜原子。
发明内容
本公开实施例提供了一种走线结构及其制备方法、显示装置。
第一方面，提供一种走线结构，包括基体；预布置层，位于所述基体上；电极走线，覆盖所述预布置层；所述预布置层在所述基体上的正投影位于所述电极走线在所述基体上的正投影。
可选地，所述走线结构还包括种子层，所述种子层位于所述预布置层与所述电极走线之间。
可选地，所述预布置层关于所述电极走线的中心线呈轴对称，所述中心线平行于所述电极走线的延伸方向。
可选地，所述预布置层在垂直于所述基体所在平面且垂直于所述电极走线延伸方向的横截面为梯形。
可选地，所述预布置层的材料选自金属材料、有机材料或无机材料中的一种。
可选地，所述预布置层的侧表面与所述基体所在平面的夹角在15-60°范围内取值。
可选地，所述预布置层的厚度大于0.01um，并小于所述种子层厚度的1/2。
可选地，所述电极走线的材料为铜。
可选地，所述种子层的材料包括铜或钼。
第二方面，提供一种显示装置，包括上述走线结构。
第三方面，提供一种走线结构的制备方法，包括：
提供基体；
在所述基体上形成预布置层；
在所述预布置层的两侧形成挡墙结构，所述挡墙结构限定出走线位置；
在所述走线位置形成电极走线；
去除所述挡墙结构。
可选地，在所述基体上形成预布置层之后，在所述预布置层的两侧形成挡墙结构之前，还包括：
在所述预布置层上形成种子层。
可选地，所述在走线位置形成电极走线，包括：
将所述基体放入含有镀层离子的溶液内；
将所述种子层和所述含有镀层离子的溶液之间形成电场，在所述走线位置形成所述电极走线。
可选地，所述在所述预布置层的两侧形成挡墙结构，包括：
在所述种子层上形成光刻胶层；
对所述光刻胶层进行构图工艺以形成至少两个光刻胶子图案，所述挡墙结构包括所述至少两个光刻胶子图案；
其中，所述至少两个光刻胶子图案中相邻的两个光刻胶子图案间隔设置以限定出所述走线位置，所述走线位置暴露出所述种子层的表面。
可选地，还包括：
去除位于所述走线位置之外的所述种子层。
附图说明
图1为相关技术中电极走线的结构示意图；
图2为图1中电极走线在电镀完成时沿AA’方向的剖视图；
图3为本公开实施例提供的一种走线结构的剖视图；
图4为本公开实施例提供的一种走线结构的制备方法中基体形成预布置层后的剖视图；
图5本公开实施例提供的一种走线结构的制备方法中基体形成种子层后的剖视图；
图6为本公开实施例提供的一种走线结构的制备方法中形成挡墙后的剖视图；
图7为本公开实施例提供的一种走线结构的制备方法中形成电极走线后的剖视图；
图8为本公开实施例提供的一种走线结构的制备方法中形成电极走线前的平面图；
图9为本公开实施例提供的一种走线结构的制备方法中形成电极走线后的平面图。
具体实施方式
为使本公开的原理、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
如图1和图2所示，在采用电镀工艺形成电极走线1过程中，首先在基体3上形成种子层4，再形成挡墙5，然后采用电镀工艺，在种子层4上形成电极走线1。发明人发现，由于电流的波动性以及溶液的不均匀性，铜离子会优先在挡墙5附近发生反应，容易导致电极走线1整体结构已封口，而内部却存在孔洞2的情况。
本公开实施例提供一种走线结构，如图3所示，该走线结构包括基体3，位于基体3表面上的预布置层5，和覆盖预布置层5的电极走线1。本公开实施例提供的走线结构，通过在基体3上形成预布置层5，使电极走线1在形成时，预布置层5能够引导上方的电极走线1的生长方向，使铜离子优先在预布置层所在区域被还原为铜原子，从而使最终形成的电极走线内部是致密无缺陷。
其中，基体3的材料可以选自玻璃，硅，塑料，聚酰亚胺等任意一种材质。
电极走线1的材料为金属，例如铜。电极走线1是通过电镀工艺形成于种子层4上。
预布置层5的材料可以为无机材料，例如氮硅化合物或一氧化硅等；或者预布置层5的材料可以为金属材料，例如钼、铜、铝等；或者预布置层5的材料可以为有机材料，例如树脂等。预布置层5是在形成种子层4之前，在需要电镀电极走线1的种子层4下方的基体3上形成。
在本实施例中，预布置层5的宽度不大于电极走线1的宽度，即预布置层5在基体3上的正投影位于电极走线1在基体上的正投影内，以使电极走线1能够在预布置层5的引导下形成覆盖预布置层5的结构。在一些实施例中，预布置层关于电极走线的中心线呈轴对称，该中心线为平行于所述电极走线的延伸方向的中心线。
在本实施例中，预布置层5的形状不进行限定，只要预布置层5的侧表面与基体3形成一定角度，使预布置层5能够引导电极走线1的生长方向即可。例如预布置层5的两侧与基体3所在平面的夹角为15-60°，且预布置层5的截面为梯形，最好为等腰梯形，使铜离子优先在预布置层所在区域被还原为铜原子，从而使最终形成的电极走线内部致密无缺陷。当预布置层5的两侧与基体3所在平面的夹角大于60°时，会使预布置层5引导生长方向过大，造成电极走线1的外侧生长不良；当预布置层5的两侧与基体3所在平面的夹角小于15°时，会使预布置层5引导生长方向过小，失去预布置层5的引导作用。
可以理解的是，当预布置层和电极走线的材质相同时，例如都采用铜，最终形成的走线结构中二者为一体结构，即预布置层也构成电极走线的一部分。
请继续参考图3，本公开实施例提供的走线结构还可以包括种子层4，种子层4位于所述预布置层5与所述电极走线1之间。其中种子层4的材料可以为导电的金属材料，例如钼、铜或者铜合金等金属材料。当种子层4为金属材料时，种子层4采用磁控溅射工艺形成于基体3的表面和预布置层5的表面。
可以理解的是，当种子层4和电极走线1的材质相同时，例如都采用铜，最终形成的走线结构中二者为一体结构，即种子层4也构成电极走线1的一部分。
在本实施例中，预布置层5的厚度大于0.01微米(um)，并小于所述种子层厚度的1/2，以使预布置层5能够引导电极走线1的形成；当预布置层5的厚 度小于0.01um时，预布置层5过薄，一方面在生产工艺中难以在基体3上形成；另一方面预布置层5无法有效的引导电极走线1的形成；当预布置层5的厚度大于种子层4厚度的1/2时，预布置层5过厚，不便于种子层4的形成，容易导致种子层4在预布置层5上搭接不良，使种子层4出现断裂等不良现象。
在本实施例中，预布置层5的长度与电极走线1的长度可以相同，也可以大于电极走线1的长度。
本公开实施例提供一种显示装置，包括上述的走线结构。
本公开实施例提供一种走线结构的制备方法，包括：
如图4所示，提供基体3；在基体3上形成预布置层5；预布置层5的长度等于走线位置的长度，预布置层5的宽度不大于走线位置的宽度，即形成后的电极走线覆盖预布置层5，使电极走线能够在预布置层5的引导下形成；并且预布置层5的宽度能够依据具体电镀中的电流密度以及溶解质浓度做相应调整，以引导电极走线1的形成；当预布置层5的材料为无机材料时，例如氮硅化合物或一氧化硅等，预布置层5采用化学气相沉积工艺在走线位置上形成；当预布置层5的材料为金属材料，例如钼、铜、铝等，预布置层5采用磁控溅射工艺在走线位置上形成；
如图5所示，在基体3的表面和预布置层5的表面上形成种子层4，种子层4可以为钼、铜或者铜合金等金属材料，种子层4可以采用磁控溅射工艺形成于基体3表面和预布置层5表面；
如图6和图8所示，在预布置层的两侧形成挡墙结构6，所述挡墙结构限定出走线位置7。在形成该挡墙结构6时，可以首先在所述种子层4上形成光刻胶层；之后，对所述光刻胶层进行构图工艺以形成至少两个光刻胶子图案，所述挡墙结构6包括所述至少两个光刻胶子图案；相邻的两个光刻胶子图案间隔设置以限定出走线位置7，其中走线位置7暴露出所述种子层4的表面，也即通过构图工艺在相邻的两个光刻胶子图案之间形成了槽沟，以限制电镀时电极走线1生长的位置并限定电极走线1的厚度。
如图7和图9所示，采用电镀工艺，在走线位置的种子层4上形成电极走线1；具体地，以电极走线1为铜电极走线为例，将图6所示的结构放入含有铜离子的溶液内，将基体3上的种子层4作为阴极，将含有铜离子的溶液作为阳极，对阳极和阴极施加电压；由于基板3涂覆有挡墙6的限定，使铜离子只能在基板3的走线位置7处得到电子被还原为铜原子，从而逐渐沉积在走线位置7 区域的种子层4上；在形成铜电极走线的过程中，预布置层5能够引导铜离子沉积的方向，使铜离子优先在预布置层5所在区域被还原为铜原子，从而使最终形成的电极走线1内部是致密无缺陷，避免电极走线1内部电镀的不完全。
电极走线1形成后，依次将挡墙6和位于所述走线位置7之外的所述种子层去除，以完成走线结构的制备。
本公开提供的走线结构的制备方法，通过在基体3上形成预布置层5，在采用电镀工艺形成电极走线1时，使电极走线1能够在预布置层5的引导下，使铜离子优先在预布置层5所在区域被还原为铜原子，避免挡墙6边缘的位置优先结晶，导致电极走线中部出现孔洞的风险，从而避免了形成致密且无缺陷的电极走线。
需要说明的是，本公开实施例提供的方法实施例能够与相应的走线结构实施例相互参考，本公开实施例对此不做限定。本公开实施例提供的方法实施例步骤的先后顺序能够进行适当调整，步骤也能够根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种走线结构，包括,
    基体；
    预布置层，位于所述基体上；
    电极走线，覆盖所述预布置层；
    所述预布置层在所述基体上的正投影位于所述电极走线在所述基体上的正投影内。
  2. 根据权利要求1所述的走线结构，还包括种子层，所述种子层位于所述预布置层与所述电极走线之间。
  3. 根据权利要求1-2任一项所述的走线结构，所述预布置层关于所述电极走线的中心线呈轴对称，所述中心线平行于所述电极走线的延伸方向。
  4. 根据权利要求1-3任一项所述的走线结构，其特征在于，所述预布置层的侧表面与所述基体所在平面的夹角在15-60°范围内取值。
  5. 根据权利要求1-4任一项所述的走线结构，其特征在于，所述预布置层在垂直于所述基体所在平面且垂直于所述电极走线延伸方向的横截面为梯形。
  6. 根据权利要求1-5任一所述的走线结构，其特征在于，所述预布置层的材料选自金属材料、有机材料或无机材料中的一种。
  7. 根据权利要求1-6任一所述的走线结构，其特征在于，所述预布置层的厚度大于0.01um，并小于所述种子层厚度的1/2。
  8. 根据权利要求1-7任一所述的走线结构，其特征在于，所述电极走线的材料为铜。
  9. 根据权利要求2-8任一所述的走线结构，其特征在于，所述种子层的材料包括铜或钼。
  10. 一种显示装置，其特征在于，包括如权利要求1-7任一所述的走线结构。
  11. 一种走线结构的制备方法，其特征在于，包括：
    提供基体；
    在所述基体上形成预布置层；
    在所述预布置层的两侧形成挡墙结构，所述挡墙结构限定出走线位置；
    在所述走线位置形成电极走线；
    去除所述挡墙结构。
  12. 根据权利要求11所述的走线结构的制备方法，在所述基体上形成预布置层之后，在所述预布置层的两侧形成挡墙结构之前，还包括：
    在所述预布置层上形成种子层。
  13. 根据权利要求12所述的走线结构的制备方法，所述在走线位置形成电极走线，包括：
    将所述基体放入含有镀层离子的溶液内；
    在所述种子层和所述含有镀层离子的溶液之间形成电场，在所述走线位置形成所述电极走线。
  14. 根据权利要求12或13所述的走线结构的制备方法，所述在所述预布置层的两侧形成挡墙结构，包括：
    在所述种子层上形成光刻胶层；
    对所述光刻胶层进行构图工艺以形成至少两个光刻胶子图案，所述挡墙结构包括所述至少两个光刻胶子图案；
    其中，所述至少两个光刻胶子图案中相邻的两个光刻胶子图案间隔设置以限定出所述走线位置，所述走线位置暴露出所述种子层的表面。
  15. 根据权利要求12-14任一所述的走线结构的制备方法，还包括：
    去除位于所述走线位置之外的所述种子层。
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