WO2020034466A1 - 制作导电线路的方法 - Google Patents

制作导电线路的方法 Download PDF

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WO2020034466A1
WO2020034466A1 PCT/CN2018/115415 CN2018115415W WO2020034466A1 WO 2020034466 A1 WO2020034466 A1 WO 2020034466A1 CN 2018115415 W CN2018115415 W CN 2018115415W WO 2020034466 A1 WO2020034466 A1 WO 2020034466A1
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film layer
metal film
conductive circuit
post
chamber
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PCT/CN2018/115415
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English (en)
French (fr)
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张朋宾
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武汉华星光电半导体显示技术有限公司
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Priority to US16/470,255 priority Critical patent/US10818513B2/en
Publication of WO2020034466A1 publication Critical patent/WO2020034466A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the technical field of conductive lines, and in particular, to a method for manufacturing a conductive line.
  • a titanium / aluminum / titanium (Ti / Al / Ti) film layer on the substrate is dry-etched in a chamber using chlorine gas (Cl 2 ) to pattern the titanium / aluminum / titanium film layer.
  • an after treatment (AT) step is generally performed, that is, CF 4 and O 2 are injected into the etching chamber, and CF 4 and O 2 are ionized under the application of chamber source power.
  • F * and O * plasmas are formed to prevent the reaction of AlCl 3 + H 2 O + O 2 ⁇ Al (OH) 3 ⁇ + HCl.
  • AlCl 3 is a molecular crystal and is easily soluble in water (45.8g / 100mL); AlF 3 is an ionic crystal and is difficult to dissolve in water. By F - + F * + AlCl 3 ⁇ AlF 3 + Cl - + Cl * this reaction occurs, can effectively prevent the occurrence of Al corrosion effects.
  • CF is a covalent bond
  • the binding force between C and F is particularly strong; if the CF covalent bond is to be broken, a high energy needs to be provided. Therefore, the etching chamber requires extremely high source power (approximately 15,000 watts) to dissociate and dissociate CF 4 , which uses higher power, that is, uses more power. At the same time, in order to ensure that sufficient F * can be generated, the etching chamber must be fed with a higher flow of CF 4 , which will undoubtedly increase manufacturing costs. The prior art cannot effectively protect aluminum from corrosion.
  • An object of the present invention is to provide a method for manufacturing a conductive circuit, so as to solve the technical problems that the prior art cannot effectively prevent aluminum from being corroded and has a high manufacturing cost.
  • the present invention provides a method for manufacturing a conductive circuit, the method includes the following steps:
  • C x H y F z and water vapor are injected into the chamber to perform a post-processing step on the patterned metal film layer, and the post-processing step avoids the patterned pattern.
  • the post-processing steps include the following steps:
  • C x H y F z and water vapor are decomposed and dissociated, so that the decomposed and dissociated C x H y F z and water vapor react with the patterned metal film layer.
  • the metal film layer is a titanium / aluminum / titanium film layer.
  • the metal film layer is etched using chlorine gas.
  • the chamber is an etching chamber.
  • the C x H y F z is CHF 3 , C 2 HF 5 , C 3 F 8 or C 4 F 8 .
  • the patterned metal film layer has smooth, non-recessed sidewalls.
  • the source power of the chamber is 6000 watts to 10,000 watts to perform the post-processing step.
  • the substrate is a low temperature polysilicon array substrate or an active matrix organic light emitting diode array substrate.
  • the conductive line is a driving line of a source and a drain on the low temperature polysilicon array substrate or the active matrix organic light emitting diode array substrate.
  • the present invention also provides a method for manufacturing a conductive circuit, the method includes the following steps:
  • C x H y F z and water vapor are injected into the chamber to perform a post-processing step on the patterned metal film layer, the post-processing step avoiding the being The patterned metal film layer is corroded.
  • the metal film layer is a titanium / aluminum / titanium film layer.
  • the metal film layer is etched using chlorine gas.
  • the chamber is an etching chamber.
  • the post-processing step includes the following steps:
  • C x H y F z and water vapor are decomposed and dissociated, so that the decomposed and dissociated C x H y F z and water vapor react with the patterned metal film layer to avoid the The patterned metal film layer is corroded.
  • the C x H y F z is CHF 3 , C 2 HF 5 , C 3 F 8 or C 4 F 8 .
  • the patterned metal film layer has smooth, non-recessed sidewalls.
  • the source power of the chamber is 6000 watts to 10,000 watts to perform the post-processing step.
  • the substrate is a low temperature polysilicon array substrate or an active matrix organic light emitting diode array substrate.
  • the conductive line is a driving line of a source and a drain on the low temperature polysilicon array substrate or the active matrix organic light emitting diode array substrate.
  • the present invention provides a method for manufacturing a conductive circuit.
  • C x H y F z and water vapor (H 2 O) in the after treatment (AT) step sufficient F *, H *, and O * are provided, and the technology to completely avoid aluminum corrosion is well achieved effect.
  • the source power of the etching chamber required to decompose and dissociate these gases is very low, and the raw material prices of these gases are very low, which significantly reduces the manufacturing cost of conductive circuits.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a conductive circuit according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional structure diagram of a conductive circuit manufactured according to the method of FIG. 1.
  • FIG. 3 is a schematic cross-sectional structure diagram of a conductive circuit manufactured without performing the post-processing step of the present invention.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a conductive circuit according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional structure diagram of a conductive circuit manufactured according to the method of FIG.
  • the method of the present invention is used to form, for example, driving lines of a source and a drain on a substrate of a display device, or other conductive lines having an electrical connection function.
  • the method includes the following steps.
  • step S100 a substrate 21 is provided.
  • the substrate 21 is an array substrate.
  • the substrate may be a low temperature polysilicon array substrate or an active matrix organic light emitting diode array substrate.
  • the present invention is not limited to this, as long as the substrate can be used as a base of a conductive circuit.
  • the substrate 21 may be a polymer substrate or a substrate made of other similar materials, such as a polyimide substrate.
  • step S200 a metal film layer 22 is formed on the substrate 21.
  • the metal film layer 22 includes an aluminum film layer.
  • the metal film layer 22 is a titanium / aluminum / titanium (Ti / Al / Ti) film layer. That is, as shown in FIG. 2, the metal film layer 22 includes a titanium sub-film layer 221, an aluminum sub-film layer 222, and a titanium sub-film layer 223, and the aluminum sub-film layer 222 is sandwiched between the Between the titanium sub-film layers 221 and 223.
  • the metal film layer 22 is composed of only one aluminum film layer.
  • step S300 a part of the metal film layer 22 is etched to pattern the metal film layer 22.
  • the metal film layer is etched using chlorine gas.
  • step S400 in a chamber, C x H y F z and water vapor are injected into the chamber to perform a post-processing step on the patterned metal film layer 23.
  • the post-processing step prevents the patterned metal film layer from being corroded. Thus, the production of the conductive line is completed.
  • the chamber is an etching chamber.
  • the post-processing steps include the following steps:
  • C x H y F z and water vapor are decomposed and dissociated, so that the decomposed and dissociated C x H y F z and water vapor react with the patterned metal film layer 22 to avoid The patterned metal film layer 22 is corroded.
  • the C x H y F z may be a fluorocarbon (C x H y F z ), such as CHF 3 , C 2 HF 5 , C 3 F 8, or C 4 F 8 .
  • C x H y F z and water vapor (H 2 O) are used instead of CF 4 and O 2 as F * and H * and O * particle source, a chemical reaction that F - + F * + AlCl 3 ⁇ AlF 3 + Cl - + Cl * to provide adequate F *; can also provide a sufficient amount of H * and O *, Cl * and Cl- binding to , the chemical reaction F - + F * + AlCl 3 ⁇ AlF 3 + Cl - + Cl * continues in the positive direction, adhering completely substituted Cl * out metal film layer surface to improve the displacement efficiency can be favorably To achieve the technical effect of completely avoiding aluminum corrosion.
  • the chemical bond of water vapor (H 2 O) is particularly easy to break, so it is used to decompose and dissociate C x H y F z (CHF 3 , C 2 HF 5 , C 3 F 8 or C 4 F 8 etc.) and water vapor (H 2 O) require very low energy, which is the etching cavity required to decompose and dissociate these gases
  • the source power of the chamber is very low. According to an embodiment, the source power applied by the etching chamber is 6000 to 10,000 watts to perform the post-processing step.
  • the patterned metal film layer 22 has smooth, non-recessed sidewalls 24.
  • the metal film layer 32 (including the titanium sub-film layer 321, the aluminum sub-film layer 322, and the titanium sub-film layer 323) is not subjected to the above-mentioned post-processing steps, Cl * on the surface of the aluminum sub-film layer 322 cannot be completely When replaced, the surface of the film layer will be uneven due to corrosion, and the sidewall 34 of the metal film layer 32 will be concave.
  • the present invention provides a method for manufacturing a conductive circuit.
  • C x H y F z and water vapor (H 2 O) in the after treatment (AT) step sufficient F *, H *, and O * are provided, and the technology to completely avoid aluminum corrosion is well achieved effect.
  • the source power of the etching chamber required to decompose and dissociate these gases is very low, and the raw material prices of these gases are very low, which significantly reduces the manufacturing cost of conductive circuits.

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Abstract

一种制作导电线路的方法。所述方法包括以下步骤：提供一基板(S100)；形成一金属膜层于所述基板上(S200)；对所述金属膜层的一部分进行蚀刻，以将所述金属膜层予以图案化(S300)；及在一腔室中，利用将CxHyFz和水蒸气注入至所述腔室，以对所述被图案化的金属膜层进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀(S400)。

Description

制作导电线路的方法 技术领域
本发明涉及导电线路的技术领域，特别涉及一种制作导电线路的方法。
背景技术
为了制作导电线路，例如为了制作低温多晶硅(LTPS)或主动矩阵有机发光二极管(AMOLED)阵列基板上的源极和漏极的驱动线路，一般是先沉积一钛/铝/钛(Ti/Al/Ti)膜层于基板上；然后，于腔室中使用氯气(Cl 2)对所述钛/铝/钛膜层的一部分进行干蚀刻，以将所述钛/铝/钛膜层予以图案化。
在使用氯气(Cl 2)对所述钛/铝/钛膜层进行干蚀刻后，Cl与Al会以AlCl X(以AlCl 3为主)的形式附着在钛/铝/钛膜层的表面。若钛/铝/钛膜层表面上的AlCl 3与大气中的水分接触，这会对钛/铝/钛膜层造成腐蚀现象。
以上过程，主要涉及的化学反应如下：
Figure PCTCN2018115415-appb-000001
Ti+Cl*+Cl -→TiCl X↑(其中TiCl X以TiCl 4为主，同时有过度态化合物)
Al+Cl*+Cl -→AlCl X↑(其中AlCl X以AlCl 3为主，同时有过度态化合物)
AlCl 3+H 2O+O 2→Al(OH) 3↓+HCl(应避免防止发生)
因此，在上述制作过程后，一般进行一后处理(After treatment，AT)步骤，即将CF 4和O 2注入至蚀刻腔室中，并在腔室源功率的施加下使CF 4和O 2电离形成F*和O*电浆，以防止 AlCl 3+H 2O+O 2→Al(OH) 3↓+HCl此反应的发生。
以上过程，主要涉及的化学反应如下：
Figure PCTCN2018115415-appb-000002
F -+F*+AlCl 3→AlF 3+Cl -+Cl*
AlCl 3属于分子晶体，极易溶解于水(45.8g/100mL)；AlF 3属于离子晶体，难溶于水。通过F -+F*+AlCl 3→AlF 3+Cl -+Cl*此反应的发生，可以有效防止Al腐蚀效应的发生。
然而，对CF 4这种化合物，C-F属于共价键，C、F之间结合力特别强；如果要打断C-F共价键，需要提供很高的能量。因此，蚀刻腔室需要极高的源功率(大约15000瓦)来分解和解离CF 4，这会使用较高的电力，即用电量较多。同时，为了确保可产生充足的F*，蚀刻腔室必须通入较高流量的CF 4，这样无疑会增加制造成本。现有技术无法有效地避免铝受到腐蚀。
因此，有必要提供一种制作导电线路的方法，以解决现有技术所存在的问题。
技术问题
本发明的目的在于提供一种制作导电线路的方法，以解决现有技术的无法有效地避免铝受到腐蚀与制造成本高的技术问题。
技术解决方案
为解决上述技术问题，本发明提供一种制作导电线路的方法，所述方法包括以下步骤：
提供一基板；
形成一金属膜层于所述基板上；
对所述金属膜层的一部分进行蚀刻，以将所述金属膜层予以图案化；及
在一腔室中，利用将C xH yF z和水蒸气注入至所述腔室以对所述被图案化的金属膜层进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀，
其中所述后处理步骤包括以下步骤：
将C xH yF z和水蒸气注入至所述腔室中；及
将C xH yF z和水蒸气予以分解和解离，以使所述被分解和解离的C xH yF z和水蒸气与所述被图案化的金属膜层发生反应。
根据本发明一优选实施例，所述金属膜层是钛/铝/钛膜层。
根据本发明一优选实施例，使用氯气对所述金属膜层进行蚀刻。
根据本发明一优选实施例，所述腔室是一蚀刻腔室。
根据本发明一优选实施例，所述C xH yF z是CHF 3、C 2HF 5、C 3F 8或C 4F 8。
根据本发明一优选实施例，在所述后处理步骤之后，所述被图案化的金属膜层具有光滑、无内凹的侧壁。
根据本发明一优选实施例，所述腔室的源功率为6000瓦至10000瓦，以执行所述后处理步骤。
根据本发明一优选实施例，所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
根据本发明一优选实施例，所述导电线路是所述低温多晶硅阵列 基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
本发明还提供一种制作导电线路的方法，所述方法包括以下步骤：
提供一基板；
形成一金属膜层于所述基板上；
对所述金属膜层的一部分进行蚀刻，以将所述金属膜层予以图案化；及
在一腔室中，利用将C xH yF z和水蒸气注入至所述腔室，以对所述被图案化的金属膜层进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。
根据本发明一优选实施例，所述金属膜层是钛/铝/钛膜层。
根据本发明一优选实施例，使用氯气对所述金属膜层进行蚀刻。
根据本发明一优选实施例，所述腔室是一蚀刻腔室。
根据本发明一优选实施例，所述后处理步骤包括以下步骤：
将C xH yF z和水蒸气注入至所述腔室中；及
将C xH yF z和水蒸气予以分解和解离，以使所述被分解和解离的C xH yF z和水蒸气与所述被图案化的金属膜层发生反应，以避免所述被图案化的金属膜层受到腐蚀。
根据本发明一优选实施例，所述C xH yF z是CHF 3、C 2HF 5、C 3F 8或C 4F 8。
根据本发明一优选实施例，在所述后处理步骤之后，所述被图案化的金属膜层具有光滑、无内凹的侧壁。
根据本发明一优选实施例，所述腔室的源功率为6000瓦至10000瓦，以执行所述后处理步骤。
根据本发明一优选实施例，所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
根据本发明一优选实施例，所述导电线路是所述低温多晶硅阵列基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
有益效果
相较于现有技术，本发明提出一种制作导电线路的方法。通过在后处理(After treatment，AT)步骤中使用C xH yF z和水蒸气(H 2O)，提供充足的F*、H*和O*，良好地达到彻底避免铝受到腐蚀的技术效果。此外，分解和解离这些气体所需要施加的蚀刻腔室的源功率很低，及这些气体的原料价格都很低，明显地降低导电线路制造成本。
附图说明
图1为根据本发明优选实施例的一种制作导电线路的方法的流程示意图。
图2为根据图1的方法所制作的导电线路的剖面结构示意图。
图3为未进行本发明后处理步骤所制作的导电线路的剖面结构示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、 「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1与图2。图1为根据本发明优选实施例的一种制作导电线路的方法的流程示意图；图2为根据图1的方法所制作的导电线路的剖面结构示意图。本发明方法用于形成例如显示装置的基板上的源极和漏极的驱动线路，或其他具有电性连接作用的导电线路。请参照图1与图2，所述方法包括以下步骤。
首先，在步骤S100中，提供一基板21。
较佳地，所述基板21是阵列基板，例如所述基板可以是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。然而，本发明不限于此，只要所述基板可作为导电线路的基底即可。举例而言，所述基板21可以是一聚合物基板或由其他类似材料所制成的基板，例如聚酰亚胺(polyimide)基板。
其次，在步骤S200中，形成一金属膜层22于所述基板21上。
根据本发明，所述金属膜层22包括一铝膜层。在一实施方式中，所述金属膜层22是一钛/铝/钛(Ti/Al/Ti)膜层。亦即，如图2所示，所述金属膜层22包括一个钛子膜层221、一个铝子膜层222与一个钛子膜层223，所述铝子膜层222被夹设在所述钛子膜层221、223之间。在另一实施方式中，所述金属膜层22仅由一个铝膜层所构成。
然后，在步骤S300中，对所述金属膜层22的一部分进行蚀刻，以将所述金属膜层22予以图案化。
较佳地，使用氯气对所述金属膜层进行蚀刻。
最后，在步骤S400中，在一腔室中，利用将C xH yF z和水蒸气注入至所述腔室，以对所述被图案化的金属膜层23进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。由此，完成了导电线路的制作。
在本实施例中，所述腔室是一蚀刻腔室。所述后处理步骤包括以下步骤：
将C xH yF z和水蒸气(H 2O)注入至所述腔室中；及
将C xH yF z和水蒸气予以分解和解离，以使所述被分解和解离的C xH yF z和水蒸气与所述被图案化的金属膜层22发生反应，以避免所述被图案化的金属膜层22受到腐蚀。
其中，所述C xH yF z可以是氟系碳氢化合物(C xH yF z)，例如CHF 3、C 2HF 5、C 3F 8或C 4F 8。
根据本发明，本发明是在后处理(After treatment，AT)步骤中使用C xH yF z和水蒸气(H 2O)来替代CF 4和O 2，作为F*和H*以及O*粒子源，以为化学反应F -+F*+AlCl 3→AlF 3+Cl -+Cl*提供充足的F*；同时，还可以提供足量的H*和O*，来结合Cl－和Cl*，而使化学反应F -+F*+AlCl 3→AlF 3+Cl -+Cl*持续向正方向进行，将附着在金属膜层表面的Cl*彻底地置换出来，提高置换效率，可以良好地达到彻底避免铝被腐蚀的技术效果。
又，根据本发明，在后处理步骤中使用C xH yF z和水蒸气(H 2O)来替代CF 4和O 2的另一个优点就CHF 3、C 2HF 5、C 3F 8或C 4F 8等气体系 列中的C-F键的结合力远低于CF 4中C-F的结合力，同时水蒸气(H 2O)的化学键也特别容易断裂，因此用以分解和解离C xH yF z(CHF 3、C 2HF 5、C 3F 8或C 4F 8等)和水蒸气(H 2O)所需要的能量很低，即分解和解离这些气体所需要施加的蚀刻腔室的源功率很低。根据一实施方式，所述蚀刻腔室所施加的源功率为6000瓦至10000瓦，以执行所述后处理步骤。
再者，C xH yF z(CHF 3、C 2HF 5、C 3F 8或C 4F 8等)和水蒸气(H 2O)的原料价格都很低，通过这两种气体的使用，可以明显地降低导电线路制造成本。
如图2所示，在所述后处理步骤之后，所述被图案化的金属膜层22具有光滑、无内凹的侧壁24。
参照图3，若金属膜层32(包括钛子膜层321、铝子膜层322与钛子膜层323)没有进行上述的后处理步骤，则铝子膜层322表面的Cl*无法彻底地被置换出来，膜层表面会因为受到腐蚀出现凹凸，且金属膜层32的侧壁34会内凹。
相较于现有技术，本发明提出一种制作导电线路的方法。通过在后处理(After treatment，AT)步骤中使用C xH yF z和水蒸气(H 2O)，提供充足的F*、H*和O*，良好地达到彻底避免铝受到腐蚀的技术效果。此外，分解和解离这些气体所需要施加的蚀刻腔室的源功率很低，及这些气体的原料价格都很低，明显地降低导电线路制造成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明 的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种制作导电线路的方法，包括以下步骤：
    提供一基板；
    形成一金属膜层于所述基板上；
    对所述金属膜层的一部分进行蚀刻，以将所述金属膜层予以图案化；及
    在一腔室中，利用将C xH yF z和水蒸气注入至所述腔室以对所述被图案化的金属膜层进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀，
    其中所述后处理步骤包括以下步骤：
    将C xH yF z和水蒸气注入至所述腔室中；及
    将C xH yF z和水蒸气予以分解和解离，以使所述被分解和解离的C xH yF z和水蒸气与所述被图案化的金属膜层发生反应。
  2. 根据权利要求1所述的制作导电线路的方法，其中所述金属膜层是钛/铝/钛膜层。
  3. 根据权利要求1所述的制作导电线路的方法，其中使用氯气对所述金属膜层进行蚀刻。
  4. 根据权利要求1所述的制作导电线路的方法，其中所述腔室是一蚀刻腔室。
  5. 根据权利要求1所述的制作导电线路的方法，其中所述C xH yF z是CHF 3、C 2HF 5、C 3F 8或C 4F 8。
  6. 根据权利要求1所述的制作导电线路的方法，其中在所述后 处理步骤之后，所述被图案化的金属膜层具有光滑、无内凹的侧壁。
  7. 根据权利要求1所述的制作导电线路的方法，其中所述腔室的源功率为6000瓦至10000瓦，以执行所述后处理步骤。
  8. 根据权利要求1所述的制作导电线路的方法，其中所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
  9. 根据权利要求8所述的制作导电线路的方法，其中所述导电线路是所述低温多晶硅阵列基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
  10. 一种制作导电线路的方法，包括以下步骤：
    提供一基板；
    形成一金属膜层于所述基板上；
    对所述金属膜层的一部分进行蚀刻，以将所述金属膜层予以图案化；及
    在一腔室中，利用将C xH yF z和水蒸气注入至所述腔室以对所述被图案化的金属膜层进行一后处理步骤，所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。
  11. 根据权利要求10所述的制作导电线路的方法，其中所述金属膜层是钛/铝/钛膜层。
  12. 根据权利要求10所述的制作导电线路的方法，其中使用氯气对所述金属膜层进行蚀刻。
  13. 根据权利要求10所述的制作导电线路的方法，其中所述腔室是一蚀刻腔室。
  14. 根据权利要求13所述的制作导电线路的方法，其中所述后处理步骤包括以下步骤：
    将C xH yF z和水蒸气注入至所述腔室中；及
    将C xH yF z和水蒸气予以分解和解离，以使所述被分解和解离的C xH yF z和水蒸气与所述被图案化的金属膜层发生反应，以避免所述被图案化的金属膜层受到腐蚀。
  15. 根据权利要求14所述的制作导电线路的方法，其中所述C xH yF z是CHF 3、C 2HF 5、C 3F 8或C 4F 8。
  16. 根据权利要求10所述的制作导电线路的方法，其中在所述后处理步骤之后，所述被图案化的金属膜层具有光滑、无内凹的侧壁。
  17. 根据权利要求10所述的制作导电线路的方法，其中所述腔室的源功率为6000瓦至10000瓦，以执行所述后处理步骤。
  18. 根据权利要求10所述的制作导电线路的方法，其中所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
  19. 根据权利要求18所述的制作导电线路的方法，其中所述导电线路是所述低温多晶硅阵列基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
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