CN109148288A - 制作导电线路的方法 - Google Patents
制作导电线路的方法 Download PDFInfo
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- 229910052719 titanium Inorganic materials 0.000 claims description 25
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- 229910052731 fluorine Inorganic materials 0.000 description 2
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种制作导电线路的方法。所述方法包括以下步骤:提供一基板;形成一金属膜层于所述基板上;对所述金属膜层的一部分进行蚀刻,以将所述金属膜层予以图案化;及在一腔室中,利用将CxHyFZ和水蒸气注入至所述腔室,以对所述被图案化的金属膜层进行一后处理步骤,所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。
Description
【技术领域】
本发明涉及导电线路的技术领域,特别涉及一种制作导电线路的方法。
【背景技术】
为了制作导电线路,例如为了制作低温多晶硅(LTPS)或主动矩阵有机发光二极管(AMOLED)阵列基板上的源极和漏极的驱动线路,一般是先沉积一钛/铝/钛(Ti/Al/Ti)膜层于基板上;然后,于腔室中使用氯气(Cl2)对所述钛/铝/钛膜层的一部分进行干蚀刻,以将所述钛/铝/钛膜层予以图案化。
在使用氯气(Cl2)对所述钛/铝/钛膜层进行干蚀刻后,Cl与 Al会以AlClX(以AlCl3为主)的形式附着在钛/铝/钛膜层的表面。若钛/铝/钛膜层表面上的AlCl3与大气中的水分接触,这会对钛/ 铝/钛膜层造成腐蚀现象。
以上过程,主要涉及的化学反应如下:
Ti+Cl*+Cl-→TiClX↑(其中TiClx以TiCl4为主,同时有过度态化合物)
Al+Cl*+Cl-→AlClX↑(其中AlClx以AlCl3为主,同时有过度态化合物)
AlCl3+H2O+O2→Al(OH)3↓+HCl(应避免防止发生)
因此,在上述制作过程后,一般进行一后处理(After treatment,AT)步骤,即将CF4和O2注入至蚀刻腔室中,并在腔室源功率的施加下使CF4加O2电离形成F*和O*电浆,以防止 AlCl3+H2O+O2→Al(OH)3↓+HCl此反应的发生。
以上过程,主要涉及的化学反应如下:
F-+F*+AlCl3→AlF3+Cl-+Cl*
AlCl3属于分子晶体,极易溶解于水(45.8g/100mL);AlF3属于离子晶体,难溶于水。通过F-+F*+AlCl3→AlF3+Cl- +Cl*此反应的发生,可以有效防止Al腐蚀效应的发生。
然而,对CF4这种化合物,C-F属于共价键,C、F之间结合力特别强;如果要打断C-F共价键,需要提供很高的能量。因此,蚀刻腔室需要极高的源功率(大约15000瓦)来分解和解离 CF4,这会使用较高的电力,即用电量较多。同时,为了确保可产生充足的F*,蚀刻腔室必须通入较高流量的CF4,这样无疑会增加制造成本。现有技术无法有效地避免铝受到腐蚀。
因此,有必要提供一种制作导电线路的方法,以解决现有技术所存在的问题。
【发明内容】
本发明的目的在于提供一种制作导电线路的方法,以解决现有技术的无法有效地避免铝受到腐蚀与制造成本高的技术问题。
为解决上述技术问题,本发明提供一种制作导电线路的方法,其特征在于,包括以下步骤:
提供一基板;
形成一金属膜层于所述基板上;
对所述金属膜层的一部分进行蚀刻,以将所述金属膜层予以图案化;及
在一腔室中,利用将CxHyFZ和水蒸气注入至所述腔室,以对所述被图案化的金属膜层进行一后处理步骤,所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。
根据本发明一优选实施例,所述金属膜层是钛/铝/钛膜层。
根据本发明一优选实施例,使用氯气对所述金属膜层进行蚀刻。
根据本发明一优选实施例,所述腔室是一蚀刻腔室。
根据本发明一优选实施例,所述后处理步骤包括以下步骤:
将CxHyFZ和水蒸气注入至所述腔室中;及
将CxHyFZ和水蒸气予以分解和解离,以使所述被分解和解离的CxHyFZ和水蒸气与所述被图案化的金属膜层发生反应,以避免所述被图案化的金属膜层受到腐蚀。
根据本发明一优选实施例,所述CxHyFZ是CHF3、C2HF5、 C3F8或C4F8。
根据本发明一优选实施例,在所述后处理步骤之后,所述被图案化的金属膜层具有光滑、无内凹的侧壁。
根据本发明一优选实施例,所述腔室的源功率为6000瓦至 10000瓦,以执行所述后处理步骤。
根据本发明一优选实施例,所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
根据本发明一优选实施例,所述导电线路是所述低温多晶硅阵列基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
相较于现有技术,本发明提出一种制作导电线路的方法。通过在后处理(Aftertreatment,AT)步骤中使用CxHyFZ和水蒸气 (H2O),提供充足的F*、H*和O*,良好地达到彻底避免铝受到腐蚀的技术效果。此外,分解和解离这些气体所需要施加的蚀刻腔室的源功率很低,及这些气体的原料价格都很低,明显地降低导电线路制造成本。
【附图说明】
图1为根据本发明优选实施例的一种制作导电线路的方法的流程示意图。
图2为根据图1的方法所制作的导电线路的剖面结构示意图。
图3为未进行本发明后处理步骤所制作的导电线路的剖面结构示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是以相同标号表示。
请参照图1与图2。图1为根据本发明优选实施例的一种制作导电线路的方法的流程示意图;图2为根据图1的方法所制作的导电线路的剖面结构示意图。本发明方法用于形成例如显示装置的基板上的源极和漏极的驱动线路,或其他具有电性连接作用的导电线路。请参照图1与图2,所述方法包括以下步骤。
首先,在步骤S100中,提供一基板21。
较佳地,所述基板21是阵列基板,例如所述基板可以是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。然而,本发明不限于此,只要所述基板可作为导电线路的基底即可。举例而言,所述基板21可以是一聚合物基板或由其他类似材料所制成的基板,例如聚酰亚胺(polyimide)基板。
其次,在步骤S200中,形成一金属膜层22于所述基板21 上。
根据本发明,所述金属膜层22包括一铝膜层。在一实施方式中,所述金属膜层22是一钛/铝/钛(Ti/Al/Ti)膜层。亦即,如图2所示,所述金属膜层22包括一个钛子膜层221、一个铝子膜层222与一个钛子膜层223,所述铝子膜层222被夹设在所述钛子膜层221、223之间。在另一实施方式中,所述金属膜层22 仅由一个铝膜层所构成。
然后,在步骤S300中,对所述金属膜层22的一部分进行蚀刻,以将所述金属膜层22予以图案化。
较佳地,使用氯气对所述金属膜层进行蚀刻。
最后,在步骤S400中,在一腔室中,利用将CxHyFZ和水蒸气注入至所述腔室,以对所述被图案化的金属膜层23进行一后处理步骤,所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。由此,完成了导电线路的制作。
在本实施例中,所述腔室是一蚀刻腔室。所述后处理步骤包括以下步骤:
将CxHyFZ和水蒸气(H2O)注入至所述腔室中;及
将CxHyFZ和水蒸气予以分解和解离,以使所述被分解和解离的CxHyFZ和水蒸气与所述被图案化的金属膜层22发生反应,以避免所述被图案化的金属膜层22受到腐蚀。
其中,所述CxHyFZ可以是氟系碳氢化合物(CxHyFZ),例如 CHF3、C2HF5、C3F8或C4F8。
根据本发明,本发明是在后处理(After treatment,AT)步骤中使用CxHyFZ和水蒸气(H2O)来替代CF4和O2,作为F*和H* 以及O*粒子源,以为化学反应F-+F*+AlCl3→AlF3+Cl-+Cl*提供充足的F*;同时,还可以提供足量的H*和O*,来结合Cl-和Cl*,而使化学反应 F-+F*+AlCl3→AlF3+Cl-+Cl*持续向正方向进行,将附着在金属膜层表面的Cl*彻底地置换出来,提高置换效率,可以良好地达到彻底避免铝被腐蚀的技术效果。
又,根据本发明,在后处理步骤中使用CxHyFZ和水蒸气(H2O) 来替代CF4和O2的另一个优点就是CHF3、C2HF5、C3F8或C4F8等气体系列中的C-F键的结合力远低于CF4中C-F的结合力,同时水蒸气(H2O)的化学键也特别容易断裂,因此用以分解和解离 CxHyFZ(CHF3、C2HF5、C3F8或C4F8等)和水蒸气(H2O)所需要的能量很低,即分解和解离这些气体所需要施加的蚀刻腔室的源功率很低。根据一实施方式,所述蚀刻腔室所施加的源功率为6000 瓦至10000瓦,以执行所述后处理步骤。
再者,CxHyFZ(CHF3、C2HF5、C3F8或C4F8等)和水蒸气(H2O) 的原料价格都很低,通过这两种气体的使用,可以明显地降低导电线路制造成本。
如图2所示,在所述后处理步骤之后,所述被图案化的金属膜层22具有光滑、无内凹的侧壁24。
参照图3,若金属膜层32(包括钛子膜层321、铝子膜层322 与钛子膜层323)没有进行上述的后处理步骤,则铝子膜层322 表面的Cl*无法彻底地被置换出来,膜层表面会因为受到腐蚀出现凹凸,且金属膜层32的侧壁34会内凹。
相较于现有技术,本发明提出一种制作导电线路的方法。通过在后处理(Aftertreatment,AT)步骤中使用CxHyFZ和水蒸气 (H2O),提供充足的F*、H*和O*,良好地达到彻底避免铝受到腐蚀的技术效果。此外,分解和解离这些气体所需要施加的蚀刻腔室的源功率很低,及这些气体的原料价格都很低,明显地降低导电线路制造成本。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种制作导电线路的方法,其特征在于,包括以下步骤:
提供一基板;
形成一金属膜层于所述基板上;
对所述金属膜层的一部分进行蚀刻,以将所述金属膜层予以图案化;及
在一腔室中,利用将CxHyFZ和水蒸气注入至所述腔室以对所述被图案化的金属膜层进行一后处理步骤,所述后处理步骤避免所述被图案化的金属膜层受到腐蚀。
2.根据权利要求1所述的制作导电线路的方法,其特征在于,所述金属膜层是钛/铝/钛膜层。
3.根据权利要求1所述的制作导电线路的方法,其特征在于,使用氯气对所述金属膜层进行蚀刻。
4.根据权利要求1所述的制作导电线路的方法,其特征在于,所述腔室是一蚀刻腔室。
5.根据权利要求4所述的制作导电线路的方法,其特征在于,所述后处理步骤包括以下步骤:
将CxHyFZ和水蒸气注入至所述腔室中;及
将CxHyFZ和水蒸气予以分解和解离,以使所述被分解和解离的CxHyFZ和水蒸气与所述被图案化的金属膜层发生反应,以避免所述被图案化的金属膜层受到腐蚀。
6.根据权利要求5所述的制作导电线路的方法,其特征在于,所述CxHyFZ是CHF3、C2HF5、C3F8或C4F8。
7.根据权利要求1所述的制作导电线路的方法,其特征在于,在所述后处理步骤之后,所述被图案化的金属膜层具有光滑、无内凹的侧壁。
8.根据权利要求1所述的制作导电线路的方法,其特征在于,所述腔室的源功率为6000瓦至10000瓦,以执行所述后处理步骤。
9.根据权利要求1所述的制作导电线路的方法,其特征在于,所述基板是一低温多晶硅阵列基板或一主动矩阵有机发光二极管阵列基板。
10.根据权利要求9所述的制作导电线路的方法,其特征在于,所述导电线路是所述低温多晶硅阵列基板或所述主动矩阵有机发光二极管阵列基板上的源极和漏极的驱动线路。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012514A (ja) * | 1998-06-19 | 2000-01-14 | Hitachi Ltd | 後処理方法 |
CN104599962A (zh) * | 2014-12-29 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | 厚铝刻蚀工艺中聚合物的去除方法 |
CN108400090A (zh) * | 2017-12-22 | 2018-08-14 | 信利(惠州)智能显示有限公司 | 防止Al腐的处理方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5599743A (en) * | 1994-04-07 | 1997-02-04 | Matsushita Electronics Corporation | Method of manufacturing a semiconductor device |
KR100268926B1 (ko) * | 1996-12-31 | 2000-10-16 | 김영환 | 반도체소자의 배선 형성방법 |
CN1186804C (zh) * | 2002-08-05 | 2005-01-26 | 统宝光电股份有限公司 | 金属薄膜干蚀刻后处理方法及蚀刻与去光刻胶的整合系统 |
US8101025B2 (en) * | 2003-05-27 | 2012-01-24 | Applied Materials, Inc. | Method for controlling corrosion of a substrate |
US7351663B1 (en) * | 2004-06-25 | 2008-04-01 | Cypress Semiconductor Corporation | Removing whisker defects |
US20160079088A1 (en) * | 2014-09-12 | 2016-03-17 | Applied Materials, Inc. | Method for etching a hardmask layer for an interconnection structure for semiconductor applications |
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CN106148960B (zh) * | 2016-08-24 | 2019-01-01 | 武汉华星光电技术有限公司 | 铝蚀刻的方法 |
CN106206290A (zh) * | 2016-08-24 | 2016-12-07 | 京东方科技集团股份有限公司 | 一种包含铝的膜层图案、其制作方法及其后处理方法 |
US10403504B2 (en) * | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
JP7179172B6 (ja) * | 2018-10-30 | 2022-12-16 | アプライド マテリアルズ インコーポレイテッド | 半導体用途の構造体をエッチングするための方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012514A (ja) * | 1998-06-19 | 2000-01-14 | Hitachi Ltd | 後処理方法 |
CN104599962A (zh) * | 2014-12-29 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | 厚铝刻蚀工艺中聚合物的去除方法 |
CN108400090A (zh) * | 2017-12-22 | 2018-08-14 | 信利(惠州)智能显示有限公司 | 防止Al腐的处理方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022011757A1 (zh) * | 2020-07-13 | 2022-01-20 | Tcl华星光电技术有限公司 | 显示面板制备方法及显示装置 |
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