CN1674250A - 半导体装置的制造方法 - Google Patents
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Abstract
一种半导体装置的制造方法,通过除去半导体晶片斜面部的蚀刻残留,抑制之后工序中的再粘附。本发明半导体装置的制造方法包括:在半导体晶片(1)上形成栅极绝缘膜或绝缘膜的工序;在所述栅极绝缘膜或绝缘膜上形成用于形成栅极电极或配线的导电膜的工序;通过反复腐蚀所述导电膜形成栅极电极或配线的工序,其中,所述反复腐蚀工序是各向同性蚀刻。
Description
技术领域
本发明涉及半导体装置的制造方法,特别是涉及介由栅极绝缘膜或绝缘膜在半导体晶片上形成栅极电极或配线的方法。
背景技术
在一般的半导体装置制的制造方法中,在构成如下半导体装置时,通过反复腐蚀栅极电极形成用导电膜而形成栅极电极52。而且,在其构图工序中进行各向异性蚀刻,所述半导体装置介由栅极绝缘膜51在图5所示的半导体晶片50上形成栅极电极52,并邻接该栅极电极52在所示晶片50表层形成源漏极区域53、54。
但是,在所示各向异性蚀刻中,保留栅极电极52,蚀刻除去半导体晶片50表层侧的栅极电极形成用导电膜,但所述晶片50背面侧的所述示导电膜52A保留。此时,在所述晶片50的斜面部,如图6所示,所述导电膜52a的蚀刻残留52b形成毛刺状态。因此,该蚀刻残留52b被之后的工序剥离而形成粉末。
这种粉末的产生是在半导体制造时形成产额降低或可靠性低下的重大问题。另外,在以下的公报中有涉及这种粉末问题的记载。
专利文献1:特开平5-41450号公报
发明内容
因此,本发明的目的在于提供半导体晶片斜面部不产生导电膜的蚀刻残留的蚀刻方法或通过除去该蚀刻残留来抑制在之后工序中的再粘附的栅极电极或配线的形成方法。
因此,本发明半导体装置的制造方法包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;通过反复腐蚀所述导电膜而形成电极或配线的工序,所述反复腐蚀工序是各向同性蚀刻。
本发明半导体装置的制造方法包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;在所述导电膜上形成涂敷膜的工序;在将所述涂敷膜和所述导电膜各向异性反复腐蚀到所述导电膜膜厚的规定位置后,各向同性蚀刻剩余的导电膜,形成电极或配线的工序。
本发明半导体装置的制造方法包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;各向异性反复腐蚀所述导电膜,形成电极或配线的工序;形成保护膜,以包覆所述晶片斜面部以外的区域的工序;以所述保护膜为掩膜,各向同性蚀刻所述晶片的整个面,除去该晶片斜面部的蚀刻残留的工序。
根据本发明,可通过半导体晶片斜面部不产生蚀刻残留的蚀刻方法或除去蚀刻残留来抑制之后工序中的再粘附引起的成品量或可靠性降低。
附图说明
图1是表示本发明实施例的半导体装置制造方法的剖面图;
图2(a)、(b)是表示本发明实施例的半导体装置制造方法的剖面图;
图3(a)、(b)是表示本发明实施例的半导体装置制造方法的剖面图;
图4(a)、(b)是表示本发明实施例的半导体装置制造方法的剖面图;
图5是表示现有半导体装置制造方法的剖面图;
图6是表示现有半导体装置制造方法的剖面图。
符号说明
1、10、20、30 半导体晶片
2、11、22、32 导电膜
12 涂敷膜
13 台阶
21 绝缘膜
21a 窄空间或接触孔
22a、22b 导电配线或导电塞
31 栅极电极或配线
32a 蚀刻残留
33 保护膜
具体实施方式
其次参照图1~图4说明本发明半导体装置的制造方法。另外,由于半导体装置的结构本身和图5所示的现有装置相同,故省略该说明,详细说明用于防止粉末产生的制造工艺。
图1是用于说明第一实施例的本发明特征的半导体晶片1的斜面部的剖面图,在于半导体芯片1上介由未图示的栅极绝缘膜或绝缘膜形成用于形成栅极电极或配线的导电膜(例如多晶硅膜或钨硅化物膜、或它们的层积膜等)后,进行各向同性蚀刻,形成未图示的栅极电极或配线。此时,由于在半导体晶片1的斜面部上各向同性蚀刻导电膜,故在保留了半导体晶片1背面侧的导电膜2时,如图1所示,以不产生形成粉末的原因的毛刺状态的蚀刻残留的方式在所示晶片1的斜面部进行蚀刻。并且,在本工序中,至少使用CF4、NF3、SF6的一种气体或包括它们中的某几种的混合气体。
另外,图2是用于说明作为第二实施例的本发明特征的半导体晶片10的斜面部的剖面图,在介由未图示的栅极绝缘膜或绝缘膜在半导体晶片10上形成用于形成栅极电极或配线的导电膜11(例如多晶硅膜或钨硅化物膜或它们的层积膜等)之后,在所述导电膜11上形成涂敷膜12(例如抗蚀剂膜、SOG(Spin On Glass)膜、BARC(Bottom Anti-Reflection Coating)膜等)。在此,涂敷膜12并不限于所述材料。但是,最好为所述导电膜11和涂敷膜12的腐蚀速率大致相同的材料。
然后,各向异性反复腐蚀所述涂敷膜12和导电膜11。此时,反复腐蚀至图12(a)所示的虚线位置的导电膜11的规定膜厚位置。利用该工序,为覆盖在所述晶片10上形成的台阶13上,即使对反映该台阶而形成鼓起状的导电膜11部分,也实现平坦化。另外,在本工序中,至少使用CL2和CF4的混合气体。
其次,将通过该上述工序平坦化的残留的导电膜11各向同性蚀刻至图2(b)所示的虚线位置,形成栅极电极及配线。即,本发明的特征在于,即使导电膜11的表面不平坦时,也可以通过形成涂敷膜12将整个面平坦化后,施行反复腐蚀工序,进行更均匀的反复腐蚀处理。
另外,图3(a)、(b)表示第三实施例,图3(a)中,在窄空间或接触孔21a局部埋入导电膜时也利用上述方法。此时,在包括在形成于半导体晶片20上的绝缘膜21上设置的窄空间或接触孔21a的整个面上形成导电膜22。然后,与所述的第二实施例相同,在对该导电膜22进行各向异性反复腐蚀至该导电膜22的规定膜厚位置后,各向同性反复腐蚀剩余的导电膜22,在窄空间或接触孔21a内形成导电配线或导电塞22a。另外,如图3(b)所示,也可以各向同性反复腐蚀整个导电膜22,形成导电配线或导电塞22b。
另外,图4表示第四实施例,在半导体晶片30上形成未图示的栅极绝缘膜或绝缘膜,在该栅极绝缘膜或绝缘膜上形成用于形成栅极电极或配线的导电膜之后,各向异性反复腐蚀所述导电膜,形成栅极电极或配线31。此时,如图4(a)所示,在所述晶片30的斜面部形成导电膜32的残留32a。然后,形成包覆所述晶片30斜面部以外区域的保护膜33。
在该状态下,如图4(b)所示,以所述保护膜33为掩膜,通过干蚀刻或采用液体的湿蚀刻各向同性蚀刻所述晶片30的整个面,除去所述晶片30斜面部的蚀刻残留32a。
在以上所述的本发明中,可利用半导体晶片斜面部不产生导电膜的蚀刻残留的蚀刻方法或除去蚀刻残留,抑制之后工序中的再粘附引起的成品量或可靠性降低。
Claims (3)
1、一种半导体装置的制造方法,其特征在于,包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;通过反复腐蚀所述导电膜形成电极或配线的工序,其中,所述反复腐蚀工序为各向同性蚀刻。
2、一种半导体装置的制造方法,其特征在于,包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;在所述导电膜上形成涂敷膜的工序;在将所述涂敷膜和所述导电膜各向异性反复腐蚀至所述导电膜膜厚的规定位置后,各向同性蚀刻剩余的导电膜,形成电极或配线的工序。
3、一种半导体装置的制造方法,其特征在于,包括:在半导体晶片上形成绝缘膜的工序;在所述绝缘膜上形成用于形成电极或配线的导电膜的工序;各向异性反复腐蚀所述导电膜,形成电极或配线的工序;形成覆盖所述晶片斜面部以外区域的保护膜的工序;以所述保护膜为掩膜,各向同性蚀刻所述晶片的整个面,除去该晶片斜面部的蚀刻残留的工序。
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CN106816368A (zh) * | 2015-12-01 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构和cmos晶体管的形成方法 |
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JP2009260128A (ja) * | 2008-04-18 | 2009-11-05 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2010047818A (ja) * | 2008-08-25 | 2010-03-04 | Toshiba Corp | 半導体製造装置および半導体製造方法 |
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KR910008983B1 (ko) * | 1988-12-20 | 1991-10-26 | 현대전자산업 주식회사 | 비등방성 식각을 이용한 잔유물 제거방법 |
JP2000012796A (ja) * | 1998-06-19 | 2000-01-14 | Hitachi Ltd | 半導体装置ならびにその製造方法および製造装置 |
JP4533522B2 (ja) * | 1999-10-29 | 2010-09-01 | ヒューレット・パッカード・カンパニー | インクジェットのダイ用の電気的相互接続 |
US6566231B2 (en) * | 2000-02-24 | 2003-05-20 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing high performance semiconductor device with reduced lattice defects in the active region |
JP4628644B2 (ja) * | 2001-10-04 | 2011-02-09 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
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CN106816368A (zh) * | 2015-12-01 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构和cmos晶体管的形成方法 |
CN106816368B (zh) * | 2015-12-01 | 2019-11-05 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构和cmos晶体管的形成方法 |
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