CN110676222A - 显示基板的制造方法、显示基板和显示装置 - Google Patents

显示基板的制造方法、显示基板和显示装置 Download PDF

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CN110676222A
CN110676222A CN201910958015.1A CN201910958015A CN110676222A CN 110676222 A CN110676222 A CN 110676222A CN 201910958015 A CN201910958015 A CN 201910958015A CN 110676222 A CN110676222 A CN 110676222A
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layer
passivation
sub
etching
photoresist pattern
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陈琳
杨成绍
马涛
王登峰
韩领
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US17/007,568 priority patent/US11682679B2/en
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Abstract

本发明提供一种显示基板的制造方法、显示基板和显示装置，属于显示技术领域，其可至少部分解决现有的显示基板中残沙不良的问题。本发明的显示基板的制造方法包括提供基底，在基底上形成有钝化层；在所述钝化层背向所述基底一侧形成非晶态的氧化物导电材料层；在氧化物导电材料层上形成光刻胶图案，光刻胶图案具有暴露区域；对光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀，以形成镂空位置；去除光刻胶图案的暴露区域内的部分厚度的钝化层材料。

Description

显示基板的制造方法、显示基板和显示装置
技术领域
本发明属于显示技术领域，具体涉及一种显示基板的制造方法、一种显示基板和一种显示装置。
背景技术
现有显示基板的结构通常是在玻璃或柔性基底上制造驱动电路层，随后在驱动电路层上制作电极。驱动电路层通常包含驱动晶体管，其最上层表面通常为钝化层。钝化层的上层表面通常会设置诸如氧化铟锡(ITO)等非晶态的透明氧化物导体材料作为电极。
非晶态的氧化物材料在制备过程中难免出现结晶的颗粒(称为残沙)。这些结晶的颗粒在通常的针对非晶态的氧化物材料的刻蚀工艺中是无法被去除的。残留的结晶态的颗粒会对显示效果造成不良影响，例如加剧残像不良等。
发明内容
本发明至少部分解决现有的非晶态氧化物材料在刻蚀时容易出现残沙不良的问题，提供一种显示基板的制造方法、一种显示基板和一种显示装置。
根据本发明第一方面，提供一种显示基板的制造方法，包括：
提供基底，在所述基底上形成有钝化层；
在所述钝化子层背向所述基底一侧形成非晶态的氧化物导电材料层；
在所述氧化物导电材料层上形成光刻胶图案，所述光刻胶图案具有暴露区域，所述暴露区域内的光刻胶被去除且暴露对应位置处的氧化物导电材料层；
对所述光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀，以形成镂空位置；
去除所述光刻胶图案的暴露区域内的部分厚度的钝化层材料。
可选地，所述钝化层包括叠置的第一钝化子层和第二钝化子层，所述第一钝化子层与所述第二钝化子层的材料相同且所述第二钝化子层比所述第一钝化子层结构致密，所述第一钝化子层比所述第二钝化子层更远离所述基底；所述去除所述光刻胶图案的暴露区域内的部分厚度的钝化层材料包括去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层，其中，保留所述光刻胶图案的暴露区域内部分厚度的第一钝化子层或者完全去除所述光刻图案的暴露区域内的第一钝化子层。
可选地，所述对所述光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀具体为采用第一刻蚀液进行湿法刻蚀。
可选地，所述去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层包括：采用第二刻蚀液对所述光刻胶图案的暴露区域内的第一钝化层进行湿法刻蚀。
可选地，所述钝化层的材料为硅的氧化物或者硅的氮化物，所述氧化物导电材料层采用所述第一刻蚀液进行湿法刻蚀，所述第一刻蚀液与所述第二刻蚀液的组分相同且包含氢氟酸。
可选地，在所述第二刻蚀液中，氢氟酸占所述第二刻蚀液的质量比a满足：0.15％≤a≤0.45％。
可选地，所述去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层包括：
采用各向异性等离子体刻蚀工艺对所述暴露区域内的所述第一钝化子层进行刻蚀至所述第一钝化子层内部设定深度后停止；
采用各向同性等离子体刻蚀工艺对残留的第一钝化子层进行刻蚀。
可选地，所述各向同性等离子体刻蚀和所述各向异性等离子体刻蚀的工艺气体相同；所述各向同性等离子体刻蚀的偏置功率小于源功率；所述各向异性等离子体刻蚀的偏置功率大于或等于源功率。
可选地，所述各向同性等离子体刻蚀和所述各向异性等离子体刻蚀的工艺气体相同，所述各向同性等离子体刻蚀与所述各向异性等离子体刻蚀的源功率相同，所述各向同性等离子体刻蚀比所述各向异性等离子体刻蚀的偏置功率小。
可选地，所述钝化层的材料包括硅的氧化物或者硅的氮化物，所述等离子体刻蚀工艺中的工艺气体包括SF6和Cl2。
可选地，所述源功率为30KW，所述各向异性等离子体刻蚀的偏置功率为30KW，所述各向同性等离子体刻蚀的偏置功率为15KW。
可选地，所述SF6和Cl2的气体流量分别为800sccm和8000sccm。
根据本发明第二方面，提供一种显示基板，包括基底、设置在所述基底上的钝化层、设置在所述钝化层背向所述基底一侧的氧化物导体材料层；所述氧化物半导体层具有图案化的镂空区域；所述钝化层对应所述氧化物半导体层的镂空区域的位置具有凹槽，所述凹槽的槽底形成在所述钝化层内。
可选地，所述钝化层具有叠置的第一钝化子层和第二钝化子层，所述第一钝化子层与所述第二钝化子层的材料相同且所述第二钝化子层比所述第一钝化子层结构致密，其中所述第一钝化子层比所述第二钝化子层更远离所述基底，所述凹槽的槽底形成在所述第一钝化子层与所述第二钝化子层的交界处或者形成在所述第一钝化子层内。以及提供一种由本发明第一方面的显示基板的制造方法制得的显示基板。
根据本发明第三方面，提供一种显示装置，包括根据本发明第二方面的显示基板。
附图说明
图1为本发明的实施例的一种在钝化层上形成非晶态氧化物图案的方法流程图；
图2a-图2d为本发明的实施例的一种在钝化层上形成非晶态氧化物图案的实例中不同阶段的产品截面图；
图3a-图3d为本发明的实施例的一种在钝化层上形成非晶态氧化物图案的实验例的产品显微镜视图；
图4a-图4b为本发明的实施例的一种在钝化层上形成非晶态氧化物图案的实验例的产品显微镜视图；
其中，附图标记为：1、基底；21、第一钝化子层；22、第二钝化子层；23、第三钝化子层；3、氧化物导电材料层；31、残沙；4、光刻胶图案。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
本实施例提供一种显示基板的制造方法，参见图1，包括以下步骤。
步骤S1、提供基底，在所述基底上形成有钝化层。
步骤S2、在所述钝化层背向所述基底一侧形成非晶态的氧化物导电材料层。
步骤S3、在所述氧化物导电材料层上形成光刻胶图案，所述光刻胶图案具有暴露区域，所述暴露区域内的光刻胶被去除且暴露对应位置处的氧化物导电材料层。
步骤S4、对所述光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀，以形成镂空位置。
步骤S5、去除所述光刻胶图案的暴露区域内的部分厚度的钝化层材料。
在步骤S4中无法避免会出现不同程度的残沙不良，而在步骤S5中把产生残沙不良区域(也即光刻胶图案的暴露区域)内的钝化层去除掉表面相对较薄的一层钝化层材料，从而残沙随表面的钝化层材料一起被去除。当然，为避免对钝化层的性能造成影响，被去除的钝化层材料应当相对钝化层的原始厚度较薄。
发明人研究发现，在基底上形成钝化层的工艺步骤中，可以控制工艺参数(例如沉积速率)使得表面的钝化层相对于表面以下的钝化层结构更加疏松，表面处的钝化层更容易被去除。以下基于该结构介绍如何去除部分厚度的钝化层材料。当然，即使钝化层的表面也是结构致密的，现有技术中也能实现去除部分厚度的钝化层材料。
结合图2a-图2d，钝化层包括叠置的第一钝化子层21和第二钝化子层22，第一钝化子层21与第二钝化子层22的材料相同且第二钝化子层22比第一钝化子层21结构致密，第一钝化子层21比第二钝化子层22更远离基底1；去除光刻胶图案4的暴露区域内的部分厚度的钝化层材料包括去除光刻胶图案4的暴露区域内的至少部分厚度的第一钝化子层21，其中，保留光刻胶图案4的暴露区域内的部分厚度的第一钝化子层21或者完全去除光刻胶图案4的暴露区域内的第一钝化子层21。
具体地，在步骤S1中，提供基底1，其中，在基底1上形成有钝化层，钝化层包括叠置的第一钝化子层21和第二钝化子层22，第一钝化子层21与第二钝化子层22的材料相同且第二钝化子层22比第一钝化子层21结构致密，第一钝化子层21比第二钝化子层22更远离基底1。
在显示基板的制造过程中，通常在基底1上形成驱动电路层(未示出)。驱动电路层的最上方的表面通常为钝化层。驱动电路层内设置有晶体管和线路，该部分可依据现有技术进行设置。故未特别示出。参照图2a，本实施例中，钝化层包含沿远离基底1的方向依次叠置的第三钝化子层23、第二钝化子层22、第一钝化子层21。第一钝化子层21的结构相对疏松，容易被刻蚀掉，可用作为对钝化层刻蚀时的刻蚀引导层。第二钝化子层22的结构致密，不容易被刻蚀掉。相对而言，第一钝化子层21更软且密度更低，而第二钝化子层22更硬且密度更高。可以通过控制形成钝化层时的沉积工艺的沉积速率的方式实现二者的差异。通常沉积速率更慢则形成的钝化层更致密。第三钝化子层23用于缓冲其之下结构(未示出)的不平整的表面，也可称为缓冲钝化子层。第一钝化子层21和第三钝化子层23相对于第二钝化子层22的厚度会小很多。在以下的各实验例中，第一钝化子层21的厚度是
Figure BDA0002228004440000061
第二钝化子层22的厚度是
Figure BDA0002228004440000062
第三钝化子层23的厚度是
具体地，在步骤S2中，在第一钝化子层21背向第二钝化子层22一侧形成非晶态的氧化物导电材料层3。
例如通过溅射的工艺形成一层非晶态的氧化铟锡(a-ITO)薄膜。当然，也可以是其他类型的透明的非晶态的氧化物导电薄膜。当然，该步骤中难免会形成少量结晶态的氧化铟锡颗粒(即残沙31)。
具体地，在步骤S3中，在氧化物导电材料层3上形成光刻胶图案4，光刻胶图案4具有暴露区域，暴露区域内的光刻胶被去除且暴露对应位置处的氧化物导电材料层3。暴露区域内的氧化物导电材料层3预期应被去除。该步骤完成后的产品形态参见图2a。
光刻胶图案4可以是通过涂覆光刻胶、曝光、显影的方式形成在氧化物导电材料层3之上。
具体地，在步骤S4中，对光刻胶图案4的暴露区域内的氧化物导电材料层3进行刻蚀。
可选地，对光刻胶图案4的暴露区域内的氧化物导电材料层3进行刻蚀具体为采用第一刻蚀液进行湿法刻蚀。
非晶态的氧化铟锡通常采用酸性溶液(例如硫酸溶液和/或硝酸溶液)进行湿法刻蚀。当然，即使是采用干法刻蚀，对于非晶态的氧化铟锡和结晶态的氧化铟锡，刻蚀的效率也是不一致的。如图2b所示，该步骤完成后会产生残沙31。
具体地，在步骤S5中，去除光刻胶图案4的暴露区域内的至少部分厚度的第一钝化子层21。
由于光刻胶图案4的暴露区域内的第一钝化子层21被去除或者被去除相对较薄的一层第一钝化子层21，依附在第一钝化子层21上的残沙31也便随之一起被去除。在液晶显示技术中，以对非晶态的氧化铟锡进行刻蚀而得到像素电极图案或者公共电极图案为例，像素电极之间后续还是会被其他绝缘物质(例如是取向层)隔开的，故像素电极之间的钝化层缺少了一层第一钝化子层21并不会对显示基板的功能造成影响。而如果该显示基板用于制造有机发光二极管显示面板，像素电极之间会被后续形成的像素界定层隔开。图2d示出的是光刻胶图案4的暴露区域内的第一钝化子层21被完全去除的情况。
可选地，在步骤S5中，采用第二刻蚀液对光刻胶图案4的暴露区域内的第一钝化层进行湿法刻蚀。参见图2d，由于湿法刻蚀具有一定的各向同性特点，残沙31下方的第一钝化子层21同样会被刻蚀掉，从而残沙31会脱落下来。
可选地，钝化层的材料为硅的氧化物或者硅的氮化物，氧化物导电材料层3采用第一刻蚀液进行湿法刻蚀，第一刻蚀液与第二刻蚀液的组分相同且包含氢氟酸。
即在对氧化物导电材料层3进行刻蚀的刻蚀液中即掺入用于刻蚀钝化层的氢氟酸。从而对氧化物导电材料层3的刻蚀和对第一钝化层的刻蚀可以在同一工艺腔室内，采用相同的刻蚀液先后完成，而无需更换刻蚀液。
需要说明的是，由于第二钝化子层22相对于第一钝化子层21结构致密，通常致密程度相差很大，只需要合理控制刻蚀的时间也即第二刻蚀液中酸性物质的浓度即可实现不对第二钝化子层22进行刻蚀。
可选地，在第二刻蚀液中，氢氟酸占第二刻蚀液的质量比a满足：0.15％≤a≤0.45％。氢氟酸浓度过低则对第一钝化子层21的刻蚀效率较低，氢氟酸浓度过高则不利于对刻蚀时间的把控，即容易对第二钝化子层22造成明显的刻蚀。
图3a为不采用上述方法，而仅对氧化物导电材料层3进行常规湿法刻蚀后的产品的显微镜视图。图3b-图3d按照本实施例的方法并且采HF的质量占比分别为0.15％、0.3％、0.45％的第二刻蚀液(与第一刻蚀液相同)对第一钝化子层21刻蚀后的显微镜视图。可以看到，随着第二刻蚀液中HF的含量的提高，残沙31的密度在减小。
可选地，在步骤S5中，采用各向异性等离子体刻蚀工艺对暴露区域内的第一钝化子层21进行刻蚀至第一钝化子层21内部设定深度后停止；随后采用各向同性等离子体刻蚀工艺对残留的第一钝化子层21进行刻蚀。
如图2c所示，各向异性等离子体刻蚀工艺可以将未附着残沙31的位置处的第一钝化子层21刻蚀掉一定深度，从而残沙31所在位置处形成一“孤岛”，残沙31下方的第一钝化子层21在水平方向上的尺寸较小。后续进行各向同性等离子体刻蚀工艺中，残沙31下方的第一钝化子层21得到暴露并且更容易地被去除。从而残沙31随之一起脱落。
可选地，各向同性等离子体刻蚀和各向异性等离子体刻蚀的工艺气体相同；各向同性等离子体刻蚀的偏置功率小于源功率；各向异性等离子体刻蚀的偏置功率大于或等于源功率。
工艺气体即用于激发等离子体的气体。源功率即激发等离子体的电场的功率。偏置功率即吸引等离子体中阳离子运动的电场的功率。即采用相同的工艺气体，仅改变偏置功率和源功率的大小关系实现不同性质的等离子体刻蚀。偏置功率越大，等离子体中正离子的定向运动越明显，物理性的轰击作用越明显，从而刻蚀的各向异性的特点越凸出。
可选地，各向同性等离子体刻蚀和各向异性等离子体刻蚀的工艺气体相同，各向同性等离子体刻蚀与各向异性等离子体刻蚀的源功率相同，各向同性等离子体刻蚀比各向异性等离子体刻蚀的偏置功率小。
如此，在同一工艺腔室内，仅改变偏置功率的大小，实现两种性质的等离子体刻蚀。
可选地，钝化层的材料包括硅的氧化物或者硅的氮化物，工艺气体包括SF6和Cl2。这种情况下，一个实验例子中，源功率为30KW，各向异性等离子体刻蚀的偏置功率为30KW，各向同性等离子体刻蚀的偏置功率为15KW。SF6和Cl2的气体流量分别为800sccm和8000sccm。工艺腔室内整体气压控制在20mtorr以内，优选为10mtorr。可以获得较佳的实验结果。图4a示出的是仅采用常规刻蚀液对非晶态氧化铟锡层刻蚀后的显微镜视图。图4b为采用上述参数配置采用两种不同性质的等离子体刻蚀工艺后获得的产品的显微镜视图。容易看到，采用本实施例所提供的方法，残沙31的数量和密度得到极大的减少。
需要说明的是，光刻胶图案4的暴露区域内的第一钝化子层21可以是被完全去除的，当然也可以保留一定厚度。应当保证第一钝化子层21被去除的部分连为一体且具有一定的深度，从而保证残沙31随被去除的第一钝化子层21的材料一起被去除。当然，出于工艺控制简化的目的，加之通常可将第一钝化子层设置的比较薄，故优选完全去除光刻胶图案4的暴露区域内的第一钝化子层21材料。
实施例2：
本实施例提供一种显示基板，包括根据实施例1的显示基板的制造方法制得的显示基板。
该类型的显示基板中，氧化物导电材料层3下方的钝化层相对较厚，而氧化物导电材料层3所覆盖区域的周边的区域内的钝化层则相对较薄。
由于残沙31数量和密度得到减少，由残沙31带来的显示不良也相应得到抑制。
本实施例还提供一种显示基板，结合图2d，其包括基底1、设置在基底1上的钝化层、设置在钝化层背向基底1一侧的氧化物导体材料层3，氧化物导体材料层3具有图案化的镂空区域；钝化层对应氧化物半导体层3的镂空区域的位置具有凹槽，凹槽的槽底形成在钝化层内。
可选地，钝化层具有叠置的第一钝化子层21和第二钝化子层22，第一钝化子层21与第二钝化子层22的材料相同且第二钝化子层22比第一钝化子层21结构致密，其中第一钝化子层21比第二钝化子层22更远离所述基底，凹槽的槽底形成在第一钝化子层21和第二钝化子层22的交界处或者形成在第一钝化子层内。
显然，该显示基板能够通过实施例1的制造方法制得，从而减少残沙不良。
实施例3：
本实施例提供一种显示装置，包括实施例2的显示基板。
具体的，该显示装置可为液晶显示面板、有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

1.一种显示基板的制造方法，其特征在于，包括：
提供基底，在所述基底上形成有钝化层；
在所述钝化层背向所述基底一侧形成非晶态的氧化物导电材料层；
在所述氧化物导电材料层上形成光刻胶图案，所述光刻胶图案具有暴露区域，所述暴露区域内的光刻胶被去除且暴露对应位置处的氧化物导电材料层；
对所述光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀，以形成镂空位置；
去除所述光刻胶图案的暴露区域内的部分厚度的钝化层材料。
2.根据权利要求1所述的制造方法，其特征在于，所述钝化层包括叠置的第一钝化子层和第二钝化子层，所述第一钝化子层与所述第二钝化子层的材料相同且所述第二钝化子层比所述第一钝化子层结构致密，所述第一钝化子层比所述第二钝化子层更远离所述基底；所述去除所述光刻胶图案的暴露区域内的部分厚度的钝化层材料包括：去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层，其中，保留所述光刻胶图案的暴露区域内部分厚度的第一钝化子层或者完全去除所述光刻图案的暴露区域内的第一钝化子层。
3.根据权利要求2所述的制造方法，其特征在于，所述对所述光刻胶图案的暴露区域内的氧化物导电材料层进行刻蚀具体为采用第一刻蚀液进行湿法刻蚀。
4.根据权利要求3所述的制造方法，其特征在于，所述去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层包括：采用第二刻蚀液对所述光刻胶图案的暴露区域内的第一钝化层进行湿法刻蚀。
5.根据权利要求4所述的制造方法，其特征在于，所述钝化层的材料为硅的氧化物或者硅的氮化物，所述氧化物导电材料层采用所述第一刻蚀液进行湿法刻蚀，所述第一刻蚀液与所述第二刻蚀液的组分相同且包含氢氟酸。
6.根据权利要求4所述的制造方法，其特征在于，在所述第二刻蚀液中，氢氟酸占所述第二刻蚀液的质量比a满足：0.15％≤a≤0.45％。
7.根据权利要求2所述的制造方法，其特征在于，所述去除所述光刻胶图案的暴露区域内的至少部分厚度的第一钝化子层包括：
采用各向异性等离子体刻蚀工艺对所述暴露区域内的所述第一钝化子层进行刻蚀至所述第一钝化子层内部设定深度后停止；
采用各向同性等离子体刻蚀工艺对残留的第一钝化子层进行刻蚀。
8.根据权利要求7所述的制造方法，其特征在于，所述各向同性等离子体刻蚀和所述各向异性等离子体刻蚀的工艺气体相同；所述各向同性等离子体刻蚀的偏置功率小于源功率；所述各向异性等离子体刻蚀的偏置功率大于或等于源功率。
9.根据权利要求7所述的制造方法，其特征在于，所述各向同性等离子体刻蚀和所述各向异性等离子体刻蚀的工艺气体相同，所述各向同性等离子体刻蚀与所述各向异性等离子体刻蚀的源功率相同，所述各向同性等离子体刻蚀比所述各向异性等离子体刻蚀的偏置功率小。
10.根据权利要求7所述的制造方法，其特征在于，所述钝化层的材料包括硅的氧化物或者硅的氮化物，所述等离子体刻蚀工艺中的工艺气体包括SF6和Cl2。
11.根据权利要求10所述的制造方法，其特征在于，所述源功率为30KW，所述各向异性等离子体刻蚀的偏置功率为30KW，所述各向同性等离子体刻蚀的偏置功率为15KW。
12.根据权利要求10所述的制造方法，其特征在于，所述SF6和Cl2的气体流量分别为800sccm和8000sccm。
13.一种显示基板，其特征在于，包括基底、设置在所述基底上的钝化层、设置在所述钝化层背向所述基底一侧的氧化物导体材料层；
所述氧化物半导体层具有图案化的镂空区域；
所述钝化层对应所述氧化物半导体层的镂空区域的位置具有凹槽，所述凹槽的槽底形成在所述钝化层内。
14.根据权利要求13所述的显示基板，其特征在于，所述钝化层具有叠置的第一钝化子层和第二钝化子层，所述第一钝化子层与所述第二钝化子层的材料相同且所述第二钝化子层比所述第一钝化子层结构致密，其中所述第一钝化子层比所述第二钝化子层更远离所述基底，所述凹槽的槽底形成在所述第一钝化子层与所述第二钝化子层的交界处或者形成在所述第一钝化子层内。
15.一种显示基板，其特征在于，采用根据权利要求1-12任意一项所述的显示基板的制造方法制得。
16.一种显示装置，其特征在于，包括根据权利要求13-14任意一项所述的显示基板。
CN201910958015.1A 2019-10-10 2019-10-10 显示基板的制造方法、显示基板和显示装置 Pending CN110676222A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114188388A (zh) * 2021-12-09 2022-03-15 深圳市华星光电半导体显示技术有限公司 显示面板、显示装置以及显示面板的制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1808709A (zh) * 2005-01-18 2006-07-26 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
CN103094204A (zh) * 2011-11-01 2013-05-08 乐金显示有限公司 制造液晶显示装置的阵列基板的方法
CN106847757A (zh) * 2017-03-09 2017-06-13 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009272108A (ja) * 2008-05-07 2009-11-19 Seiko Epson Corp 有機エレクトロルミネッセンス素子、有機エレクトロルミネッセンス素子の製造方法
US9985082B2 (en) * 2016-07-06 2018-05-29 Lg Display Co., Ltd. Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1808709A (zh) * 2005-01-18 2006-07-26 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
CN103094204A (zh) * 2011-11-01 2013-05-08 乐金显示有限公司 制造液晶显示装置的阵列基板的方法
CN106847757A (zh) * 2017-03-09 2017-06-13 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114188388A (zh) * 2021-12-09 2022-03-15 深圳市华星光电半导体显示技术有限公司 显示面板、显示装置以及显示面板的制作方法

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