WO2020020276A1 - Mosfet制作方法 - Google Patents

Mosfet制作方法 Download PDF

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Publication number
WO2020020276A1
WO2020020276A1 PCT/CN2019/097646 CN2019097646W WO2020020276A1 WO 2020020276 A1 WO2020020276 A1 WO 2020020276A1 CN 2019097646 W CN2019097646 W CN 2019097646W WO 2020020276 A1 WO2020020276 A1 WO 2020020276A1
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trench
oxide layer
well region
type well
conductivity type
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PCT/CN2019/097646
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English (en)
French (fr)
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罗泽煌
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无锡华润上华科技有限公司
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Priority to EP19841968.1A priority Critical patent/EP3832734A4/en
Priority to US17/263,207 priority patent/US11502194B2/en
Publication of WO2020020276A1 publication Critical patent/WO2020020276A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a MOSFET.
  • LDMOSFETs laterally diffused metal-oxide-semiconductor field-effect transistors
  • a side wall is generally formed at the drain end by a side wall process, and the side wall is used to increase the withstand voltage.
  • the sidewall is usually formed through photolithography and etching processes, and the alignment accuracy of the photolithography will have a certain deviation, which makes the thickness of the left and right sidewalls inconsistent, and the thickness of the sidewalls is asymmetric. Affects the performance of the device, such as changing the breakdown voltage of the device.
  • a method for manufacturing a MOSFET is provided according to various embodiments of the present application.
  • a MOSFET manufacturing method includes:
  • the first conductive type well region is etched by using the dielectric oxide layer as a mask to form a second trench communicating with the first trench, and a gate is formed on an inner wall of the second trench.
  • FIG. 1 is a sectional view of a side wall formed by a conventional process
  • FIG. 2 is a flowchart of a MOSFET manufacturing method according to an embodiment
  • 3a to 3f are schematic cross-sectional structural diagrams of the device after the completion of each intermediate step of manufacturing a MOSFET structure using a MOSFET manufacturing method in an embodiment.
  • the width of the dielectric oxide layer (side wall) 11 on the left side of the drain electrode 13 is larger than the width of the dielectric oxide layer (side wall) 12 on the right side by the conventional photolithography and etching processes. Asymmetry will affect the performance of the device, such as changing the breakdown voltage of the device.
  • FIG. 2 is a flowchart of a MOSFET manufacturing method according to an embodiment.
  • the MOSFET manufacturing method includes the following steps:
  • Step S110 providing a wafer having a first conductivity type well region formed on a substrate, and sequentially forming an oxide layer and a silicon nitride layer on the first conductivity type well region.
  • the semiconductor substrate can be made of undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), or germanium on insulator. Silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • a first conductivity type well region 20 is formed on a semiconductor substrate (not shown)
  • an oxide layer 30 is formed on the first conductivity type well region 20, and silicon nitride is formed on the oxide layer 30.
  • Layer 40 In one embodiment, the oxide layer 30 is obtained through an oxidation process.
  • the oxide layer is a silicon oxide layer, and a layer of silicon nitride 40 is formed on the silicon oxide layer 30 by a deposition process.
  • Step S120 Etching a part of the oxide layer and the silicon nitride layer to form an opening exposing the well region of the first conductivity type.
  • the specific process steps for forming the opening include: coating a layer of photoresist 50 on the surface of the silicon nitride layer 40, defining the opening position by photolithography and etching, and etching the silicon nitride layer 40 and the oxide layer 30 by reactive ions.
  • An opening 51 is formed, and the first conductive type well region at the opening 51 is exposed.
  • a plurality of openings 51 can be formed according to the structure of the device, and the width of the opening 51 can also be set as required, and only openings with different widths need to be defined in the photolithography step.
  • Step S130 Etching the first conductive type well region to form a first trench opposite to the opening in the first conductive type well region.
  • the first conductive type well region 20 is etched by an ion reaction, and a first trench opposite to the opening 51 can be formed under the opening 51.
  • the photoresist mask applied in step S120 is not removed, and the photoresist is used as a mask to etch the first conductive type well region 20, and the photoresist is removed after the first trench is formed.
  • the photoresist may be removed after the opening 51 is formed, and the first conductive type well region is etched by using silicon nitride as a mask. The depth and shape of the first trench can be changed by adjusting the etching parameters.
  • the distance between the sidewalls of the first trench decreases linearly from the opening of the first trench to the bottom of the first trench.
  • the first trench is an inverted trapezoid, and an inclination angle ⁇ of a sidewall of the first trench may be 78 ° to 90 °.
  • the method for forming the trapezoidal structure trench is anisotropic dry etching, wherein a halogen gas can be used as the etching gas, such as chlorine gas, hydrogen bromide, nitrogen trifluoride, and hexafluoride. Sulfur, etc., the etch gas reacts with silicon to generate volatile gases and is pumped away during the etching process to gradually etch the trench.
  • a halogen gas can be used as the etching gas, such as chlorine gas, hydrogen bromide, nitrogen trifluoride, and hexafluoride. Sulfur, etc., the etch gas reacts with silicon to generate volatile gases and is pumped away during the etching process to gradually etch the
  • an auxiliary gas needs to be added at the same time to continuously form a polymer on the side wall, so that the openings etched downward are getting smaller and smaller, so that the side wall of the groove is inclined.
  • tetrafluoromethane, helium, and oxygen are used as auxiliary gases.
  • tetrafluoromethane forms a polymer, which is deposited on the surface of the trench to protect the trench from further etching.
  • the helium and oxygen can react with the polymer to eliminate the polymer on the surface of the trench. The areas without polymer coverage will continue to be etched by the etching gas.
  • the opening of the mask has a width of 10
  • the trench 1 is formed by the downward reaction of the etching gas and silicon.
  • Hydrofluoromethane forms a polymer, which is deposited on the inner wall of the trench. Assuming a deposition thickness of 1, the polymer prevents the trench from being etched further, and helium and oxygen in the auxiliary gas are eliminated due to their anisotropy.
  • the polymer at the bottom of the trench, but the polymer at the sidewall of the trench will not be eliminated.
  • the polymer at the sidewall is used as a mask.
  • the opening width is 8 and the etching gas continues to etch down to form the trench 2. Repeat the above process. Until the formation of the trench N, during the downward etching process, the width of the mask opening is getting smaller and smaller, that is, the width from top to bottom trench 1 to trench N is getting smaller and smaller, and there are trenches 1 to trenches.
  • the first groove formed by the groove N has a ladder shape.
  • the rate of polymer formation and elimination the angle of inclination ⁇ of the sidewall can be controlled. The faster the elimination rate, the greater the angle of inclination ⁇ of the sidewall.
  • the depth of the trench can be controlled. In this embodiment, the depth of the first trench can range from 0.1 ⁇ m to 1 ⁇ m, but is not limited to this range.
  • Step S140 depositing a dielectric oxide layer on the inner surface of the first trench, anisotropically etching the dielectric oxide layer and retaining the dielectric oxide layer on the sidewall of the first trench.
  • a dielectric oxide layer 60 is formed on the surface of the structure formed in step S130 by a deposition process, and the dielectric oxide layer 60 specifically covers the upper surface of the silicon nitride layer 40 and the opening and the inside of the first trench.
  • the surface, that is, the dielectric oxide layer 60 fills the first trench, but does not fill the first trench.
  • the degree of reaction is the same everywhere on the surface of the semiconductor structure, so the thickness of the dielectric oxide layer 60 formed is uniform, that is, the thickness of the dielectric oxide layer 60 is the same.
  • the thickness range can be It is not limited to this range.
  • the thickness of the dielectric oxide layer 60 is The dielectric oxide layer 60 may be a silicon oxide layer.
  • the deposition process is specifically chemical vapor deposition. Monosilane (SiH 4 ) and oxygen (O 2 ) are input into the reaction chamber, and a reaction occurs to form a silicon dioxide (SiO 2 ) film.
  • the dielectric oxide layer 60 is etched downward by anisotropic etching. Since the anisotropic etching is performed, the etching direction is selected to be downward and the opposite side is selected. The etching rate of the edge dielectric oxide layer is almost zero, so the dielectric oxide layer on the sidewall of the first trench will remain after the etching is completed. Because the thickness of the dielectric oxide layer formed through the above-mentioned deposition process is the same, the dielectric oxide layers formed on the sidewalls of the first trench are symmetrical to each other. When the dielectric oxide layer 60 is etched under the same conditions, The dielectric oxide layers remaining on the sidewalls are also symmetrical to each other. In this embodiment, the anisotropic etching is selected from the anisotropic etching in the dry method.
  • Step S150 etching the first conductive type well region using the dielectric oxide layer as a mask to form a second trench communicating with the first trench, and forming a gate on an inner wall of the second trench.
  • a second conductive type well region is formed in the first conductive type well region at the bottom of the second trench, and a source electrode is formed in the second conductive type well region, and the source electrode has the first conductive type.
  • the method includes the following steps:
  • Step S151 The first conductive type well region 20 is etched downward with the remaining dielectric oxide layer 60 as a mask to form a second trench. Then, the first trench and the second trench in the same vertical direction communicate with each other, as shown in FIG. 3e.
  • the depth of the second trench is greater than the depth of the first trench, and the depth of the second trench may range from 0.5 ⁇ m to 8 ⁇ m, but is not limited to this range.
  • the second trench The depth of the trench is 2 ⁇ m.
  • Step S152 A gate oxide layer 71 is formed on the inner wall of the second trench.
  • the thickness of the gate oxide layer 71 is smaller than the thickness of the dielectric oxide layer 60.
  • the gate oxide layer 71 may be formed using a thermal oxidation process. This process only forms the gate oxide layer 71 on the inner wall of the second trench, that is, the surface of the first conductivity type well region (silicon) 20. The first trench side Since the dielectric oxide layer 60 is formed on the wall, the gate oxide layer 71 is not formed on the surface.
  • Step S153 forming a polysilicon gate 72 on the gate oxide layer 71, and filling the polysilicon gate 72 in the bottom trench and a part of the sidewall of the second trench.
  • a deposition process may be used to fill the trench with polysilicon, and then the polysilicon is etched to a predetermined thickness to form a polysilicon gate 72 with the predetermined thickness at the bottom of the trench.
  • a first insulating oxide layer 81 is formed on the surface of the polysilicon gate 72 and the sidewall of the trench.
  • the first insulating oxide layer 81 and the polysilicon gate 72 and the gate oxide layer 71 are etched downward through photolithography and etching processes, and leak out.
  • the polysilicon gate 72 and the first insulating oxide layer 81 at the sidewall of the trench remain.
  • Step S154 Through the above etching step, an opening is formed between the polysilicon gates 72 to expose the bottom of the trench.
  • a second conductivity type well region 21 is formed in the first conductivity type well region through the opening, and then A source electrode 22 is formed in the second conductivity type well region 21.
  • ions of a second conductivity type are implanted into the trench, and a second conductivity type well region 21 is formed below the second trench.
  • ions of the first conductivity type are implanted into the second conductivity type well.
  • a source electrode 22 is formed in the region 21.
  • the first insulating oxide layer 81 on the sidewall of the trench serves as a barrier layer.
  • the trench is filled with a second insulating oxide layer 82 to isolate the gate from the source.
  • the source electrode 22 leads out of the MOSFET surface through a conductive plug 90.
  • the conductive plug 90 penetrates the first trench, the second trench and the source electrode 22 and contacts the second conductive type well region 21.
  • Step S160 removing the oxide layer and the silicon nitride layer and forming a drain on a first conductive type well region outside the trench, the drain having a first conductive type and located between two dielectric oxide layers.
  • the oxide layer 30 and the silicon nitride layer 40 are removed by etching, and the first conductive type well region at the corresponding position is exposed.
  • the first conductive type ion is implanted to form the drain 23, and the drain 23 is located on the two dielectrics.
  • Between the oxide layers 60. at least two sets of trenches are formed, and a sidewall of each set of first trenches corresponds to a set of dielectric oxide layers, that is, there are at least four sets of symmetrical dielectric oxide layers between two adjacent trenches.
  • a drain electrode 23 is formed above the first conductive type well region, and a symmetrical dielectric oxide layer 60 is formed on both sides of the drain electrode 23, and the dielectric oxide layer 60 forms two walls of the drain electrode. Specifically, the drain 23 can also be pulled out of the surface of the MOSFET through a conductive plug.
  • the MOSFET obtained by the above method has its source terminal and drain terminal embedded in the device in a deep trench process to form a vertical channel region, which can minimize the lateral size required by the high-voltage device.
  • the channel region of the MOSFET includes a dielectric oxide layer 60, a gate oxide layer 71, a first insulating oxide layer 81, and a second insulating oxide layer 82. Because the dielectric oxide layer 60 is thicker, it has a greater effect on the on-resistance of the channel, that is, it has a greater impact on the breakdown voltage of the device.
  • the width of the wall because the wider the width of the side wall, the greater the breakdown voltage that can be withstood.
  • the left side wall width is greater than the right side wall width due to process deviations.
  • the withstand voltage level of the side channel is higher than that of the right channel.
  • the breakdown voltage on the left is 110V and the breakdown voltage on the right is 90V.
  • the overall breakdown voltage of the device is 90V.
  • the breakdown voltage of the device is less than the set breakdown voltage, so it cannot meet the actual needs.
  • the dielectric oxide layer is usually formed by photolithography and etching processes, that is, after the first trench is formed, the trench is filled with the dielectric oxide, and the portion to be etched is defined by photolithography.
  • This step Involving the alignment of the mask, the dielectric oxide in the middle part is etched away by an etching process, and the dielectric oxide on the sidewall of the first trench is protected by the photoresist and is retained. Due to the deviation of the alignment of the lithography machine, the dielectric oxide that is not etched is difficult to be completely symmetrical. As shown in FIG. 1, the width of the dielectric oxide layer 11 on the left side of the drain electrode 13 is greater than the width of the dielectric oxide layer 12 on the right side. , Which will affect the performance of the device.
  • the thickness of the dielectric oxide layer generated by the deposition is uniform.
  • the etching conditions are the same everywhere on the structure surface.
  • the dielectric oxide layers remaining on the two sidewalls of the first trench are symmetrical to each other. This step omits the step of lithographic symmetry, so there is no problem of asymmetry of dielectric oxides on both sides of the trench due to the deviation in alignment, so that the device has better symmetry, which guarantees good device performance.
  • the length of the sidewall dielectric oxide layer can be controlled by controlling the depth of the first trench
  • the thickness of the dielectric oxide layer can be controlled by controlling the deposition parameters
  • the sidewall dielectric can be adjusted by controlling the etching parameters. The thickness of the oxide.
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the second conductivity type well region 21 is a P well
  • the first conductivity type well region 20 is a high voltage N well.
  • the first conductivity type may be P type
  • the second conductivity type may be N type.

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Abstract

本申请涉及一种MOSFET制作方法，包括：刻蚀第一导电类型阱区(20)上的氧化层(30)和氮化硅层(40)，形成露出第一导电类型阱区(20)的开口；通过开口刻蚀第一导电类型阱区(20)，形成第一沟槽；淀积介质氧化层(60)并进行回蚀，保留第一沟槽侧壁上的介质氧化层(60)；刻蚀第一导电类型阱区(20)形成与第一沟槽相通的第二沟槽，在第二沟槽的内壁上形成栅极，在第二沟槽底部的第一导电类型阱区(20)内形成第二导电类型阱区(21)并在第二导电类型阱区(21)内形成源极(22)；去除氧化层(30)和氮化硅层(40)并在沟槽外的第一导电类型阱区(20)上形成漏极(23)。

Description

MOSFET制作方法
相关申请
本申请要求于2018年7月27日提交中国专利局的、申请号为201810846710.4、申请名称为“MOSFET制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制作领域，尤其涉及一种MOSFET制作方法。
背景技术
随着半导体集成电路集成度越来越高，对单个功率单元的尺寸要求越来严格，小型化设计已成为衡量电子元件技术发展水平的重要标志之一。传统的高压横向器件，如横向扩散金属氧化物半导体场效应管(LDMOSFET)，其源端和漏端并排于器件的同侧，使得器件尺寸较大。尤其当需要增大器件的耐压值或者导通电阻时，为了不再增大器件的尺寸，一般会通过侧墙工艺在漏端形成侧墙，利用侧墙提高耐压。但是目前通常是通过光刻、刻蚀的工艺流程来形成该侧墙，而光刻的对准精度会存在一定的偏差，使得漏端左右侧墙的厚度不一致，而侧墙厚度不对称又会影响器件的性能，如会改变器件的击穿电压。
发明内容
根据本申请的各种实施例提供一种MOSFET制作方法。
一种MOSFET制作方法，包括：
提供在衬底上形成有第一导电类型阱区的晶圆，在所述第一导电类型阱区上依次形成氧化层和氮化硅层；
刻蚀部分所述氧化层和氮化硅层以形成露出所述第一导电类型阱区的开口；
刻蚀所述第一导电类型阱区以在所述第一导电类型阱区内形成与所述开口相对的第一沟槽；
在所述第一沟槽内表面淀积一层介质氧化层，对所述介质氧化层进行各向异性刻蚀并保留所述第一沟槽侧壁上的介质氧化层；
以所述介质氧化层为掩膜刻蚀所述第一导电类型阱区形成与所述第一沟槽相通的第二沟槽，并在所述第二沟槽的内壁上形成栅极，在所述第二沟槽底部的第一导电类型阱区内形成第二导电类型阱区并在所述第二导电类型阱区内形成源极，所述源极具有第一导电类型；
去除所述氧化层和氮化硅层并在所述沟槽外的第一导电类型阱区上形成漏极，所述漏极具有第一导电类型且位于两介质氧化层之间。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为传统工艺形成的侧墙剖面图；
图2为一实施例中MOSFET制作方法流程图；
图3a～3f为一实施例中采用MOSFET制造方法制造MOSFET结构的各个中间步骤完成后器件的剖面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技 术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本申请，将在下列的描述中提出详细步骤以及结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
如图1所示，利用传统的光刻、刻蚀工艺在漏极13左侧的介质氧化层(侧墙)11的宽度大于右侧介质氧化层(侧墙)12的宽度，而侧墙厚度不对称又会影响器件的性能，如会改变器件的击穿电压。
如图2所示为一实施例中MOSFET制作方法的流程图，MOSFET制作方法包括以下步骤：
步骤S110：提供在衬底上形成有第一导电类型阱区的晶圆，在所述第一导电类型阱区上依次形成氧化层和氮化硅层。
提供半导体衬底，半导体衬底的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。如图3a所示，半导体衬底(图中未示出)上形成第一导电类型阱区20，在第一导电类型阱区20上形成氧化层30，并在氧化层30上形成氮化硅层40。在一个实施例中，通过氧化工艺得到该氧化层30，该氧化层为氧化硅层，再通过淀积工艺在氧化硅层30上形成一层氮化硅40。
步骤S120：刻蚀部分所述氧化层和氮化硅层以形成露出所述第一导电类型阱区的开口。
形成开口的具体工艺步骤包括：在氮化硅层40表面涂覆一层光刻胶50，通过光刻、刻蚀定义出开口位置，并通过反应离子刻蚀氮化硅层40和氧化层30，形成开口51，开口51处的第一导电类型阱区便暴露出来。可根据器件的结构形成多个开口51，开口51的宽度也可根据需要设定，只需在光刻步骤中定义出不同宽度的开口即可。
步骤S130：刻蚀所述第一导电类型阱区以在所述第一导电类型阱区内形成与所述开口相对的第一沟槽。
结合图3b所示，由于开口51下方的第一导电类型阱区被暴露在外，通过离子反应刻蚀第一导电类型阱区20，可在开口51下方形成与开口51相对的第一沟槽。在本实施例中，步骤S120涂覆的光刻胶掩膜并未去除，继续以该光刻胶作为掩膜刻蚀第一导电类型阱区20，形成第一沟槽后再去除光刻胶。在另一实施例中，也可在形成开口51后先去除光刻胶，以氮化硅作为掩膜刻蚀第一导电类型阱区。其中，可通过调节刻蚀参数改变第一沟槽的深度和形状。在本实施例中，第一沟槽侧壁间距自第一沟槽开口处至所述第一沟槽底部呈线性递减。第一沟槽呈倒梯形，第一沟槽侧壁的倾斜角度α可为78°～90°。在一实施例中，形成上述梯形结构沟槽的方法为各向异性的干法刻蚀，其中，可采用卤素气体作为刻蚀气体，如可氯气、溴化氢、三氟化氮、六氟化硫等，刻蚀气体与硅发生反应后生成易挥发气体并在刻蚀过程中被抽走，逐渐刻蚀出沟槽。同时，为了控制沟槽形状，如生成梯形槽，需要同时加入辅助气体不断在侧壁形成聚合物，使向下刻蚀的开口越来越小，从而使沟槽侧壁发生倾斜。在一实施例中，采用四氟甲烷、氦气和氧气作为辅助气体，在反应过程中，四氟甲烷形成聚合物，该聚合物会沉积在沟槽表面，保护沟槽不被继续刻蚀，而氦气和氧气可与聚合物发生反应而消除沟槽表面的聚合物，无聚合物覆盖的地方会继续被刻蚀气体刻蚀，通过控制聚合物的形成与消除速率，可得到不同倾斜角度的梯形槽。为方便理解，以具体的数字举例说明，在刻蚀之前，掩膜板的开口为宽度为10，通过刻蚀气体与硅反应向下刻蚀形成沟槽1，此时由于辅助气体中的四氟甲烷形成聚合物，该聚合物会沉积在沟槽内壁，假设沉积厚度为1，该聚合物阻止沟槽被继续刻蚀，而辅助气体中的氦气和氧气由于其各向异性性会消除沟槽底部的聚合物，但是不会消除沟槽侧壁的聚合物，侧壁的聚合物作为掩膜，其开口宽度为8，刻蚀气体继续往下刻蚀形成沟槽2，重复上述过程，直至形成沟槽N，在向下刻蚀的过程中，掩膜开口宽度越来越小，即从上至下沟槽1到沟槽N的宽度越来越小，有沟 槽1至沟槽N组成的第一沟槽即为梯形状。通过控制聚合物形成与消除的速率，可以控制侧壁倾斜的角度α，消除速率越快，侧壁倾斜角度α越大。同时，通过控制刻蚀速率与刻蚀时间，可以控制沟槽的深度，在本实施例中，第一沟槽的深度范围可为0.1μm～1μm，但不限于此范围。
步骤S140：在所述第一沟槽内表面淀积一层介质氧化层，对所述介质氧化层进行各向异性刻蚀并保留所述第一沟槽侧壁上的介质氧化层。
结合图3c所示，通过淀积工艺在步骤S130形成的结构表面形成一层介质氧化层60，该介质氧化层60具体覆盖在氮化硅层40的上表面以及开口和第一沟槽的内表面，即介质氧化层60填充于该第一沟槽内，但是未填满该第一沟槽。在淀积过程中，半导体结构表面各处反应程度相同，因此形成的介质氧化层60的厚度均匀，即介质氧化层60的厚度一致，其厚度范围可为
Figure PCTCN2019097646-appb-000001
但不限于此范围。同时，通过改变淀积工艺参数，如调节温度、压力等参数，可以得到不同厚度的介质氧化层。在本实施例中，介质氧化层60的厚度为
Figure PCTCN2019097646-appb-000002
介质氧化层60具体可为氧化硅层。在本实施例中，淀积工艺具体为化学气相淀积，在反应腔内输入甲硅烷(SiH 4)和氧气(O 2)，两者发生反应即可生成二氧化硅(SiO 2)薄膜。
结合图3d所示，生成介质氧化层60后，再通过各向异性刻蚀的方式向下刻蚀该介质氧化层60，由于进行各向异性刻蚀时，选择刻蚀方向向下，对侧边介质氧化层的刻蚀速率几乎为零，因此刻蚀完成后会保留第一沟槽侧壁上的介质氧化层。由于通过上述淀积工艺形成的介质氧化层的厚度一致，由此在第一沟槽侧壁上形成的介质氧化层是相互对称的，在相同的条件下刻蚀该介质氧化层60时，在侧壁处残留的介质氧化层也相互对称。在本实施例中，各向异性刻蚀选择干法中的各向异性刻蚀。
步骤S150：以所述介质氧化层为掩膜刻蚀所述第一导电类型阱区形成与所述第一沟槽相通的第二沟槽，并在所述第二沟槽的内壁上形成栅极，在所述第二沟槽底部的第一导电类型阱区内形成第二导电类型阱区并在所述第二导电类型阱区内形成源极，所述源极具有第一导电类型。在一实施例中，具 体包括以下步骤：
步骤S151：以残留的介质氧化层60为掩膜继续向下刻蚀第一导电类型阱区20，形成第二沟槽，则同一垂直方向的第一沟槽、第二沟槽相通，如图3e所示。其中，在一实施例中，第二沟槽的深度大于第一沟槽的深度，第二沟槽的深度范围可为0.5μm～8μm，但不限于此范围，在本实施例中，第二沟槽的深度为2μm。
步骤S152：在第二沟槽内壁形成一层栅氧化层71，栅氧化层71的厚度小于介质氧化层60的厚度。在具体工艺实现中，可以使用热氧化工艺形成栅氧化层71，该过程只会第二沟槽内壁即第一导电类型阱区(硅)20的表面形成栅氧化层71，第一沟槽侧壁由于形成有介质氧化层60，其表面不会形成栅氧化层71。
步骤S153：再在所述栅氧化层71上形成多晶硅栅72，多晶硅栅72填充于第二沟槽底部和侧壁的部分区域。在具体的工艺实现中，可以采用淀积工艺在沟槽内填充多晶硅，再刻蚀该多晶硅至预定厚度，在沟槽底部形成该预定厚度的多晶硅栅72。然后在多晶硅栅72表面和沟槽侧壁形成一层第一绝缘氧化层81，通过光刻、刻蚀工艺向下刻蚀该第一绝缘氧化层81和多晶硅栅72和栅氧化层71，漏出沟槽底部，保留沟槽侧壁处的多晶硅栅72和第一绝缘氧化层81。
步骤S154：通过上述刻蚀步骤，在多晶硅栅72之间形成有开口露出沟槽底部，结合图3f所示，通过该开口在第一导电类型阱区内形成第二导电类型阱区21，再在第二导电类型阱区21内形成源极22。在本实施例中，是向沟槽内注入第二导电类型的离子，在第二沟槽的下方形成第二导电类型阱区21；然后注入第一导电类型的离子，在第二导电类型阱区21内形成源极22。在第一、第二导电类型的离子注入时沟槽侧壁的第一绝缘氧化层81会作为阻挡层。在形成源极之后再向沟槽内填充第二绝缘氧化层82，以隔离栅极与源极。
在一实施例中，源极22通过一导电栓塞90引出MOSFET表面，导电栓 塞90贯穿第一沟槽、第二沟槽和源极22并与所述第二导电类型阱区21接触。
步骤S160：去除所述氧化层和氮化硅层并在所述沟槽外的第一导电类型阱区上形成漏极，所述漏极具有第一导电类型且位于两介质氧化层之间。
结合3f所示，腐蚀去除氧化层30和氮化硅层40，对应位置处的第一导电类型阱区便暴露在外，注入第一导电类型的离子，形成漏极23，漏极23位于两介质氧化层60之间。在本方案中，至少形成两组沟槽，每一组第一沟槽的侧壁上对应有一组介质氧化层，即至少有四组对称的介质氧化层，在相邻两沟槽之间的第一导电类型阱区上方形成漏极23，漏极23两侧则具有对称的介质氧化层60，介质氧化层60构成漏极的两侧墙。具体的，漏极23也可通过一导电栓塞引出MOSFET表面。
通过上述方法得到的MOSFET，其源端和漏端以深沟槽工艺埋入器件内部，形成垂直方向的沟道区，可以最大化降低高压器件所需要的横向尺寸。MOSFET的沟道区包括介质氧化层60、栅氧化层71、第一绝缘氧化层81和第二绝缘氧化层82。由于介质氧化层60较厚，对沟道的导通电阻影响较大，即对器件的击穿电压影响较大，若漏端两侧侧墙不对称，假设左侧侧墙宽度大于右侧侧墙宽度，由于侧墙宽度越宽，能承受的击穿电压越大，若需制备击穿电压为100V的器件，由于工艺的偏差，使得左侧侧墙宽度大于右侧侧墙宽度，则左侧沟道的耐压水平高于右侧沟道的耐压水平，比如左侧击穿电压为110V，右侧击穿电压为90V，则器件整体的击穿电压为90V，使得最终实际得到的器件的击穿电压小于设定的击穿电压，从而不能满足实际需求。
传统工艺中，通常是通过光刻、刻蚀工艺形成该介质氧化层，即在形成第一沟槽后在沟槽内填满介质氧化物，利用光刻定义成需要刻蚀的部位，此步骤涉及到掩膜版的对准，再通过刻蚀工艺将中间部位的介质氧化物刻蚀掉，第一沟槽侧壁的介质氧化物受光刻胶的保护被保留下来。由于光刻机对准会存在一定偏差，未被刻蚀掉的介质氧化物难以完全对称，如图1所示，漏极13左侧介质氧化层11的宽度大于右侧介质氧化层12的宽度，由此会影响器件的性能。
在本方案中，在第一沟槽表面淀积一层介质氧化层后，由于淀积生成的介质氧化层厚度均匀，在相同的刻蚀环境中，结构表面各处的刻蚀条件相同，由此残留在第一沟槽两侧壁的介质氧化层相互对称。此步骤省略了光刻对称的步骤，因此不会存在因对准存在偏差而使得沟槽两侧介质氧化物不对称的问题，使得器件具有较好的对称性，保证了器件的性能良好。同时，在本方案中，可以通过控制第一沟槽的深度控制其侧壁介质氧化层的长度，通过控制淀积的参数可以控制介质氧化层的厚度，通过控制刻蚀参数可以调节侧壁介质氧化物的厚度。
在本实施例中，第一导电类型为N型，第二导电类型为P型，相应地，第二导电类型阱区21为P阱，第一导电类型阱区20为高压N阱；在其他实施例中，也可以是第一导电类型为P型，第二导电类型为N型。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种MOSFET制作方法，包括：
    提供在衬底上形成有第一导电类型阱区的晶圆，在所述第一导电类型阱区上依次形成氧化层和氮化硅层；
    刻蚀部分所述氧化层和氮化硅层以形成露出所述第一导电类型阱区的开口；
    刻蚀所述第一导电类型阱区以在所述第一导电类型阱区内形成与所述开口相对的第一沟槽；
    在所述第一沟槽内表面淀积一层介质氧化层，对所述介质氧化层进行各向异性刻蚀并保留所述第一沟槽侧壁上的介质氧化层；
    以所述介质氧化层为掩膜刻蚀所述第一导电类型阱区形成与所述第一沟槽相通的第二沟槽，并在所述第二沟槽的内壁上形成栅极，在所述第二沟槽底部的第一导电类型阱区内形成第二导电类型阱区并在所述第二导电类型阱区内形成源极，所述源极具有第一导电类型；以及
    去除所述氧化层和氮化硅层并在所述沟槽外的第一导电类型阱区上形成漏极，所述漏极具有第一导电类型且位于两介质氧化层之间。
  2. 如权利要求1所述的MOSFET制作方法，其中，所述第一沟槽侧壁间距自所述第一沟槽开口处至所述第一沟槽底部呈线性递减。
  3. 如权利要求2所述的MOSFET制作方法，其中，所述第一沟槽侧壁倾斜角度为78°～90°。
  4. 如权利要求2或3所述的MOSFET制作方法，其中，所述刻蚀所述第一导电类型阱区形成第一沟槽具体为在刻蚀过程中通过不断在所述第一沟槽侧壁沉积聚合物以刻蚀出具有倾斜角度的侧壁。
  5. 如权利要求4所述的MOSFET制作方法，其中，所述聚合物为四氟甲烷。
  6. 如权利要求5所述的MOSFET制作方法，其中，所述不断在所述第 一沟槽侧壁沉积聚合物的步骤包括：
    在沟槽内壁沉积聚合物；以及
    利用氦气和氧气对所述聚合物进行各向异性刻蚀，消除沟槽底部的聚合物，保留沟槽侧壁的聚合物。
  7. 如权利要求1所述的MOSFET制作方法，其中，所述介质氧化层的厚度为
    Figure PCTCN2019097646-appb-100001
  8. 如权利要求1所述的MOSFET制作方法，其中，所述介质氧化层为氧化硅层。
  9. 如权利要求1所述的MOSFET制作方法，其中，所述在所述第一沟槽内表面形成一层介质氧化层具体为通过化学气相淀积的工艺在所述第一沟槽内淀积一层介质氧化层。
  10. 如权利要求1所述的MOSFET制作方法，其中，所述各向异性刻蚀为干法刻蚀。
  11. 如权利要求1所述的MOSFET制作方法，其中，所述第二沟槽的深度大于所述第一沟槽的深度。
  12. 如权利要求1所述的MOSFET制作方法，其中，所述在所述第二沟槽的内壁上形成栅极包括：
    在所述第二沟槽的内壁形成栅氧化层，所述栅氧化层的厚度小于所述介质氧化层的厚度；以及
    在所述栅氧化层上形成多晶硅栅，所述多晶硅栅填充于所述第二沟槽底部和侧壁的部分区域。
  13. 如权利要求12所述的MOSFET制作方法，其中，所述在所述栅氧化层上形成多晶硅栅，所述多晶硅栅填充于所述第二沟槽底部和侧壁的部分区域的步骤包括：
    采用淀积工艺在沟槽内填充多晶硅；以及
    刻蚀所述多晶硅至预定厚度，在沟槽底部形成预定厚度的多晶硅栅。
  14. 如权利要求13所述的MOSFET制作方法，其中，所述在所述第二 沟槽底部的第一导电类型阱区内形成第二导电类型阱区并在所述第二导电类型阱区内形成源极的步骤包括：
    在多晶硅栅表面和沟槽侧壁形成一层第一绝缘氧化层，通过光刻、刻蚀工艺向下刻蚀所述第一绝缘氧化层和多晶硅栅和栅氧化层，形成露出沟槽底部的开口，保留沟槽侧壁处的多晶硅栅和第一绝缘氧化层；
    通过所述露出沟槽底部的开口在第一导电类型阱区内形成第二导电类型阱区，再在第二导电类型阱区内形成源极；以及
    向沟槽内填充第二绝缘氧化层，以隔离栅极与源极。
  15. 如权利要求1所述的MOSFET制作方法，其中，所述源极通过一导电栓塞引出，所述导电栓塞贯穿所述第一沟槽、第二沟槽和所述源极并与所述第二导电类型阱区接触。
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