WO2020015174A1 - 像素电路及液晶显示面板 - Google Patents

像素电路及液晶显示面板 Download PDF

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WO2020015174A1
WO2020015174A1 PCT/CN2018/107772 CN2018107772W WO2020015174A1 WO 2020015174 A1 WO2020015174 A1 WO 2020015174A1 CN 2018107772 W CN2018107772 W CN 2018107772W WO 2020015174 A1 WO2020015174 A1 WO 2020015174A1
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region
liquid crystal
sub
film transistor
thin film
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PCT/CN2018/107772
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English (en)
French (fr)
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王金杰
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深圳市华星光电技术有限公司
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Priority to US16/319,313 priority Critical patent/US20210118385A1/en
Publication of WO2020015174A1 publication Critical patent/WO2020015174A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the invention relates to the technical field of liquid crystal display, and in particular to a pixel circuit and a liquid crystal display panel.
  • Liquid crystal display referred to as liquid crystal panel
  • LCD has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, such as: LCD TVs, smart phones, digital cameras, tablet computers, computers Screens, or laptop screens, dominate the flat panel display space.
  • the liquid crystal display panel is composed of a color filter substrate (CF), a thin film transistor array substrate (TFT array substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the liquid crystal display panel is provided with a plurality of pixels arranged in an array. When a driving voltage is applied to two substrates, each pixel is displayed under the driving of a pixel circuit.
  • the liquid crystal display panels in the mainstream market can be divided into three types: Twisted Nematic (TN) or Super Twisted Nematic (STN), and In-Plane Switching (IPS) type and Vertical Alignment (VA) type.
  • TN Twisted Nematic
  • STN Super Twisted Nematic
  • IPS In-Plane Switching
  • VA Vertical Alignment
  • the VA type liquid crystal display panel has higher contrast than other types of liquid crystal display panels, and has a very wide application in large-sized displays, such as liquid crystal televisions.
  • a pixel circuit with a 3T structure includes a first thin film transistor T100 disposed in a pixel main region PM, and a second thin film transistor T200 and a third thin film disposed in a pixel sub region PS.
  • Transistor T300 Transistor
  • the gate of the first thin film transistor T100 is electrically connected to the scanning line G (n) (n is a positive integer and represents the number of rows of pixels), and the source is electrically connected to the data line D (m) (m is a positive integer, (The number of columns where the pixels are located), the drain is electrically connected to the first storage capacitor Cst1 and the first liquid crystal capacitor Clc1; the gate of the second thin film transistor T200 is electrically connected to the scan line G (n), and the source is electrically connected
  • the data line D (m) has a drain electrically connected to the second storage capacitor Cst2 and a second liquid crystal capacitor Clc2; a gate of the third thin film transistor T300 is electrically connected to the scan line G (n), and a source is electrically connected to the first
  • the drain of the two thin film transistors T200 is directly and electrically connected to the common electrode Acom on the array substrate side.
  • the scanning signal transmitted by the scanning line G (n) functions: in the pixel main region PM, the first thin film transistor T100 is turned on, and the data signal transmitted by the data line D (m) is transmitted to the first storage capacitor Cst1 and the first liquid crystal capacitor Clc1 are charged; and in the pixel sub-region PS, the second thin film transistor T200 and the third thin film transistor T300 are both turned on, and the data signal transmitted on the data line D (m) is stored to the second storage.
  • the turned-on third thin film transistor T300 discharges to the common electrode Acom on the array substrate side; in this way, after the scanning signal transmitted by the scanning line G (n) is completed, the pixel times
  • the voltage on the second liquid crystal capacitor Clc2 in the region PS will be lower than the voltage on the first liquid crystal capacitor Clc1 in the pixel main region PM, which can achieve the effect of reducing color shift.
  • the channel length-to-width ratio of each thin film transistor, especially the third thin film crystal T300 in the above 3T pixel circuit is greatly different, causing its IV characteristics to fluctuate greatly, so the third thin film crystal T300
  • the discharge will have a greater impact on the common electrode Acom on the array substrate side, which will cause a voltage jump on the common electrode Acom on the array substrate side when the screen is displayed, and the difference in voltage jump will be large. Effect, the screen display will appear horizontal crosstalk (Crosstalk) phenomenon.
  • An object of the present invention is to provide a pixel circuit, which can not only significantly improve the color shift, but also eliminate the influence of the discharge of the third thin film transistor on the common electrode on the array substrate side in the existing pixel circuit of the 3T structure, and reduce the occurrence of horizontal crosstalk. And further increase the pixel aperture ratio.
  • Another object of the present invention is to provide a liquid crystal display panel with less color shift, less crosstalk, and higher pixel aperture ratio.
  • the present invention first provides a pixel circuit, which uses only two thin film transistors, including a pixel primary region and a pixel secondary region.
  • a main area thin film transistor, a main area storage capacitor, and a main area liquid crystal capacitor are provided in the pixel main area; a gate of the main area thin film transistor is electrically connected to a scan line, and a source is electrically connected to a data line; The drain is electrically connected to one end of the storage capacitor in the main area and one end of the liquid crystal capacitor in the main area; the other end of the storage capacitor in the main area is electrically connected to the common electrode on the array substrate side; the other end of the liquid crystal capacitor in the main area is electrically connected to the color Common electrode on the membrane substrate side;
  • a sub-region thin film transistor, a sub-region storage capacitor, a sub-region liquid crystal capacitor, and a voltage dividing capacitor connected in series with the sub-region liquid crystal capacitor are provided in the pixel sub-region;
  • the gate of the sub-region thin film transistor is electrically connected to scan Line, the source is electrically connected to the data line, the drain is electrically connected to one end of the voltage dividing capacitor and one end of the secondary storage capacitor;
  • the other end of the voltage dividing capacitor is electrically connected to one end of the liquid crystal capacitor in the secondary zone;
  • the other end of the liquid crystal capacitor in the sub-region is electrically connected to the common electrode on the color filter substrate side;
  • the other end of the sub-region storage capacitor is electrically connected to the common electrode on the array substrate side;
  • the voltage dividing effect of the voltage dividing capacitor makes the voltage on the liquid crystal capacitor in the secondary region smaller than the voltage on the liquid crystal capacitor in the primary region.
  • the data signal transmitted by the data line is used to charge the pixel main region and the pixel sub-region; after charging, the voltage on the liquid crystal capacitor in the sub-region and the voltage on the liquid crystal capacitor in the main region
  • the ratio is: Cs / (Cs + Clc2);
  • Cs represents a voltage-dividing capacitor
  • Clc2 represents a sub-region liquid crystal capacitor
  • the channel aspect ratio of the secondary region thin film transistor is smaller than the channel aspect ratio of the primary region thin film transistor, so that the charging rate of the secondary region thin film transistor is smaller than that of the primary region thin film transistor.
  • a main area thin film transistor, a main area storage capacitor, and a main area liquid crystal capacitor are provided in the pixel main area; a gate of the main area thin film transistor is electrically connected to a scan line, and a source is electrically connected to a data line; The drain is electrically connected to one end of the storage capacitor in the main area and one end of the liquid crystal capacitor in the main area; the other end of the storage capacitor in the main area is electrically connected to the common electrode on the array substrate side; the other end of the liquid crystal capacitor in the main area is electrically connected to the color Common electrode on the membrane substrate side;
  • a sub-region thin film transistor, a sub-region storage capacitor, and a sub-region liquid crystal capacitor are provided in the pixel sub-region; the gate of the sub-region thin-film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected.
  • One end of the liquid crystal capacitor in the sub-region and one end of the storage capacitor in the sub-region; the other end of the liquid crystal capacitor in the sub-region is electrically connected to the common electrode on the color filter substrate side; the other end of the storage capacitor in the sub-region is electrically connected to the array substrate side Common electrode
  • the channel aspect ratio of the secondary region thin film transistor is smaller than the channel aspect ratio of the primary region thin film transistor, so that the charging rate of the secondary region thin film transistor is less than the charging rate of the primary region thin film transistor, so that the The voltage on the liquid crystal capacitor in the secondary region is smaller than the voltage on the liquid crystal capacitor in the primary region.
  • the charging rate of the thin film transistor in the secondary region is 70% to 80% of the charging rate of the thin film transistor in the primary region.
  • the present invention also provides a liquid crystal display panel including a pixel circuit.
  • the pixel circuit uses only two thin film transistors, including a pixel main area and a pixel sub area.
  • a main area thin film transistor is provided in the pixel main area.
  • the main area storage capacitor and the main area liquid crystal capacitor; the gate of the main area thin film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to one end of the main area storage capacitor and the main area liquid crystal capacitor.
  • the other end of the storage capacitor in the main area is electrically connected to the common electrode on the array substrate side; the other end of the liquid crystal capacitor in the main area is electrically connected to the common electrode on the color filter substrate side;
  • a sub-region thin film transistor, a sub-region storage capacitor, a sub-region liquid crystal capacitor, and a voltage dividing capacitor connected in series with the sub-region liquid crystal capacitor are provided in the pixel sub-region;
  • the gate of the sub-region thin film transistor is electrically connected to scan Line, the source is electrically connected to the data line, the drain is electrically connected to one end of the voltage dividing capacitor and one end of the secondary storage capacitor;
  • the other end of the voltage dividing capacitor is electrically connected to one end of the liquid crystal capacitor in the secondary zone;
  • the other end of the liquid crystal capacitor in the sub-region is electrically connected to the common electrode on the color filter substrate side;
  • the other end of the sub-region storage capacitor is electrically connected to the common electrode on the array substrate side;
  • the voltage dividing effect of the voltage dividing capacitor makes the voltage on the liquid crystal capacitor in the secondary region smaller than the voltage on the liquid crystal capacitor in the primary region.
  • the data signal transmitted by the data line is used to charge the pixel main region and the pixel sub-region; after charging, the voltage on the liquid crystal capacitor in the sub-region and the voltage on the liquid crystal capacitor in the main region
  • the ratio is: Cs / (Cs + Clc2);
  • Cs represents a voltage-dividing capacitor
  • Clc2 represents a sub-region liquid crystal capacitor
  • the channel aspect ratio of the secondary region thin film transistor is smaller than the channel aspect ratio of the primary region thin film transistor, so that the charging rate of the secondary region thin film transistor is smaller than that of the primary region thin film transistor.
  • a main area thin film transistor, a main area storage capacitor, and a main area liquid crystal capacitor are provided in the pixel main area; a gate of the main area thin film transistor is electrically connected to a scan line, and a source is electrically connected to a data line; The drain is electrically connected to one end of the storage capacitor in the main area and one end of the liquid crystal capacitor in the main area; the other end of the storage capacitor in the main area is electrically connected to the common electrode on the array substrate side; the other end of the liquid crystal capacitor in the main area is electrically connected to the color Common electrode on the membrane substrate side;
  • a sub-region thin film transistor, a sub-region storage capacitor, and a sub-region liquid crystal capacitor are provided in the pixel sub-region; the gate of the sub-region thin-film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected.
  • One end of the liquid crystal capacitor in the sub-region and one end of the storage capacitor in the sub-region; the other end of the liquid crystal capacitor in the sub-region is electrically connected to the common electrode on the color filter substrate side; the other end of the sub-region storage capacitor is electrically connected to the array substrate side Common electrode
  • the channel aspect ratio of the secondary region thin film transistor is smaller than the channel aspect ratio of the primary region thin film transistor, so that the charging rate of the secondary region thin film transistor is less than the charging rate of the primary region thin film transistor, so that the The voltage on the liquid crystal capacitor in the secondary region is smaller than the voltage on the liquid crystal capacitor in the primary region.
  • the charging rate of the thin film transistor in the secondary region is 70% to 80% of the charging rate of the thin film transistor in the primary region.
  • the pixel circuit provided by the present invention adopts a 2T structure.
  • the channel aspect ratio makes the voltage on the liquid crystal capacitor in the secondary region smaller than the voltage on the liquid crystal capacitor in the primary region, which can significantly improve the color shift.
  • the third thin-film transistor with area discharge can eliminate the influence of the third thin-film transistor discharge on the common electrode on the array substrate side, reduce the occurrence of horizontal crosstalk, and further improve the pixel aperture ratio.
  • the liquid crystal display panel provided by the present invention adopts the pixel circuit, and the color shift is small, the crosstalk phenomenon is small, and the pixel aperture ratio is high.
  • FIG. 1 is a circuit diagram of a conventional pixel circuit with a 3T structure
  • FIG. 2 is a circuit diagram of a first embodiment of a pixel circuit of the present invention.
  • FIG. 3 is a circuit diagram of a second embodiment of a pixel circuit of the present invention.
  • FIG. 4 is a circuit diagram of a third embodiment of a pixel circuit of the present invention.
  • the invention provides a pixel circuit.
  • the first embodiment of the pixel circuit of the present invention uses 2T, that is, a structure using only two thin film transistors, including a pixel main region PM and a pixel sub-region PS.
  • the pixel main region PM is provided with a main region thin film transistor T1, a main region storage capacitor Cst1, and a main region liquid crystal capacitor Clc1.
  • the gate of the thin film transistor T1 in the main region is electrically connected to the scanning line G (n) (n is a positive integer and represents the number of rows of pixels), and the source is electrically connected to the data line D (m) (m is a positive integer, Indicates the number of columns in which the pixel is located), the drain is electrically connected to one end of the storage capacitor Cst1 in the main region and one end of the liquid crystal capacitor Clc1 in the main region (ie, the pixel electrode in the main region);
  • the common electrode Acom on the substrate side; the other end of the liquid crystal capacitor Clc1 in the main area is electrically connected to the common electrode CFcom on the color filter substrate side.
  • a sub-region thin film transistor T2, a sub-region storage capacitor Cst2, a sub-region liquid crystal capacitor Clc2, and a voltage dividing capacitor Cs connected in series with the sub-region liquid crystal capacitor Clc2 are disposed in the pixel sub-region PS.
  • the gate of the sub-region thin film transistor T2 is electrically connected to the scanning line G (n), the source is electrically connected to the data line D (m), and the drain is electrically connected to one end of the voltage division capacitor Cs and the sub-region storage capacitor Cst2.
  • One end; the other end of the voltage-dividing capacitor Cs is electrically connected to one end of the sub-region liquid crystal capacitor Clc2 (ie, the sub-region pixel electrode); the other end of the sub-region liquid crystal capacitor Clc2 is electrically connected to the common electrode on the color film substrate side CFcom; the other end of the secondary storage capacitor Cst2 is electrically connected to the common electrode Acom on the array substrate side.
  • the first embodiment of the pixel circuit of the present invention omits a third thin film transistor for discharging the pixel sub-region, and instead sets the voltage dividing capacitor Cs to communicate with the sub-region.
  • the liquid crystal capacitor Clc2 divides the voltage.
  • the scanning signal transmitted by the scanning line G (n) works: in the pixel main area PM, the main area thin film transistor T1 is turned on, and the data signal transmitted by the data line D (m) is stored in the main area Capacitance Cst1, the primary region liquid crystal capacitor Clc1 are charged; in the pixel sub-region PS, the sub-region thin film transistor T2 is turned on, and the data signal transmitted by the data line D (m) is sent to the sub-region storage capacitor Cst2, a voltage dividing capacitor Cs is charged with the sub-region liquid crystal capacitor Clc2.
  • V data the voltage of the data signal relative to the common electrode CFcom on the color filter substrate side
  • V data the voltage of the data signal relative to the common electrode CFcom on the color filter substrate side
  • V Clc1 V data (1)
  • liquid crystal capacitor Clc2 and subregion dividing completion of charging of capacitor Cs, and the secondary voltage V region Clc2 liquid crystal capacitor Clc2 on the divided voltage V Cs of the capacitance Cs and the pressure for the V data namely:
  • V Clc2 + V Cs V data ;
  • the voltage V Clc2 on the liquid crystal capacitor Clc2 in the sub-region is:
  • V Clc2 V data ⁇ Cs / (Cs + Clc2) (2)
  • V Clc2 / V Clc1 V data ⁇ Cs / (Cs + Clc2) / V data
  • the first embodiment of the pixel circuit of the present invention omits the third thin film transistor for discharging the pixel sub-region compared to the existing pixel circuit of the 3T structure, the discharge of the third thin film transistor to the array substrate side can be eliminated.
  • the effect of the electrode Acom reduces the occurrence of horizontal crosstalk and further improves the pixel aperture ratio.
  • a second embodiment of a pixel circuit of the present invention adopts a 2T structure, and includes a pixel main region PM and a pixel sub-region PS.
  • the pixel main region PM is provided with a main region thin film transistor T1, a main region storage capacitor Cst1, and a main region liquid crystal capacitor Clc1.
  • the gate of the thin film transistor T1 in the main region is electrically connected to the scanning line G (n), the source is electrically connected to the data line D (m), and the drain is electrically connected to one end of the storage capacitor Cst1 in the main region and the liquid crystal capacitor Clc1 in the main region.
  • the pixel electrode in the main area the other end of the storage capacitor Cst1 in the main area is electrically connected to the common electrode Acom on the array substrate side; the other end of the liquid crystal capacitor Clc1 in the main area is electrically connected to the common electrode CFcom on the color filter substrate side .
  • a sub-region thin film transistor T2, a sub-region storage capacitor Cst2, and a sub-region liquid crystal capacitor Clc2 are provided in the pixel sub-region PS.
  • the gate of the sub-region thin film transistor T2 is electrically connected to the scanning line G (n)
  • the source is electrically connected to the data line D (m)
  • the drain is electrically connected to one end of the sub-region liquid crystal capacitor Clc2 (ie, the sub-region pixel electrode).
  • the channel aspect ratio of the thin film transistor is an important factor that determines the charging rate of the thin film transistor.
  • a second embodiment of the pixel circuit of the present invention sets a channel aspect ratio of the thin film transistor T2 of the secondary region smaller than a channel aspect ratio of the thin film transistor T1 of the primary region (by increasing the The channel length is maintained without changing the channel width, or the channel length of the sub-region thin film transistor T2 is maintained without changing the channel width to achieve).
  • the scanning signal transmitted by the scanning line G (n) functions: in the pixel main region PM, the thin film transistor T1 of the main region is turned on, and the data signal transmitted by the data line D (m) passes through the main
  • the thin film transistor T1 in the region charges the storage capacitor Cst1 and the liquid crystal capacitor Clc1 in the main region; in the pixel sub-region PS, the thin-film transistor T2 in the sub-region is turned on, and the data signal transmitted by the data line D (m) passes through the
  • the sub-region thin film transistor T2 charges the sub-region storage capacitor Cst2 and the sub-region liquid crystal capacitor Clc2; since the channel aspect ratio of the sub-region thin film transistor T2 is smaller than the channel aspect ratio of the main-region thin film transistor T1,
  • the charging rate of the thin film transistor T2 in the secondary region is smaller than the charging rate of the thin film transistor T1 in the primary region.
  • the charging rate of the thin film transistor T2 in the secondary region is 70% to that of the thin film transistor T1 in the primary region. 80%, so that the voltage on the liquid crystal capacitor Clc2 in the secondary region is smaller than the voltage on the liquid crystal capacitor Clc1 in the primary region after charging is completed, which can significantly improve the color shift.
  • the second embodiment of the pixel circuit of the present invention reduces the channel aspect ratio of the thin film transistor T2 in the sub-region to make the voltage on the liquid crystal capacitor Clc2 in the sub-region smaller than the voltage on the liquid crystal capacitor Clc1 in the main region to achieve the effect of improving color shift.
  • a third thin film transistor for discharging the pixel sub-region is omitted, which can eliminate the influence of the third thin film transistor discharge on the common electrode Acom on the array substrate side and reduce the occurrence of horizontal crosstalk. And further increase the pixel aperture ratio.
  • a third embodiment of the pixel circuit of the present invention is a combination of the first embodiment and the second embodiment described above, that is, a branch connected in series with the sub-region liquid crystal capacitor Clc2 is provided in the first embodiment.
  • the channel aspect ratio of the thin film transistor T2 of the sub-region is reduced at the same time, so that the channel aspect ratio of the thin film transistor T2 of the sub-region is smaller than that of the thin film transistor T1 of the main region.
  • the voltage on the liquid crystal capacitor Clc2 in the secondary region can be made smaller than the voltage on the liquid crystal capacitor Clc1 in the primary region to a greater extent to significantly improve the color shift, and the third embodiment is compared with the pixel circuit of the existing 3T structure.
  • the third thin film transistor for discharging the pixel sub-region is omitted, which can eliminate the influence of the third thin film transistor discharge on the common electrode on the array substrate side, reduce the occurrence of the horizontal crosstalk phenomenon, and further improve the pixel aperture ratio.
  • the present invention also provides a liquid crystal display panel using any of the above-mentioned pixel circuits, so the liquid crystal display panel has less color shift, less crosstalk, and higher pixel aperture ratio.
  • the pixel circuit of the present invention adopts a 2T structure.
  • a voltage dividing capacitor connected in series with the liquid crystal capacitor in the sub-region or by setting the channel aspect ratio of the thin-film transistor in the sub-region to be smaller than the channel length of the thin-film transistor in the main region The aspect ratio makes the voltage on the liquid crystal capacitor in the sub zone smaller than the voltage on the liquid crystal capacitor in the main zone, which can significantly improve the color shift.
  • it compared with the existing pixel circuit of the 3T structure, it is omitted to discharge the pixel sub zone.
  • the third thin film transistor can eliminate the influence of the third thin film transistor discharge on the common electrode on the array substrate side, reduce the occurrence of horizontal crosstalk, and further improve the pixel aperture ratio.
  • the liquid crystal display panel of the present invention adopts the pixel circuit, which has less color shift, less crosstalk phenomenon, and higher pixel aperture ratio.

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Abstract

一种像素电路及液晶显示面板。像素电路采用2T结构，一方面通过设置与次区液晶电容(Clc2)串联的分压电容(Cs)或设置次区薄膜晶体管(T2)的沟道长宽比小于主区(PM)薄膜晶体管(T1)的沟道长宽比，使得次区液晶电容(Clc2)上的电压小于主区液晶电容(Clc1)上的电压，能够明显改善色偏；另一方面，相比现有的3T结构的像素电路省去了用于为像素次区(PS)放电的第三薄膜晶体管(T300)，能够消除第三薄膜晶体管(T300)放电对阵列基板侧公共电极(Acom)的影响，减少水平串扰现象的发生，并进一步提高像素开口率。

Description

像素电路及液晶显示面板 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种像素电路及液晶显示面板。
背景技术
液晶显示面板(Liquid Crystal Display，LCD)，简称液晶面板，具有机身薄、省电、无辐射等众多优点，得到了广泛地应用，如：液晶电视、智能手机、数字相机、平板电脑、计算机屏幕、或笔记本电脑屏幕等，在平板显示领域中占主导地位。
液晶显示面板是由一彩膜基板(Color Filter，CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成。液晶显示面板内设有多个呈阵列式排布的像素(Pixel)，当在两片基板上施加驱动电压时，各个像素在像素电路的驱动下进行显示。
就目前主流市场上的液晶显示面板而言，可分为三种类型，分别是扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型、平面转换(In-Plane Switching，IPS)型及垂直配向(Vertical Alignment，VA)型。其中，VA型液晶显示面板相对其它种类的液晶显示面板具有更高的对比度，在大尺寸显示，如液晶电视等方面具有非常广地应用。
现有的VA型液晶显示面板大多采用3T(即三个薄膜晶体管)结构的像素电路。请参阅图1，3T结构的像素电路包括设于像素主(Main)区PM之内的第一薄膜晶体管T100及设于像素次(Sub)区PS之内的第二薄膜晶体管T200与第三薄膜晶体管T300。所述第一薄膜晶体管T100的栅极电性连接扫描线G(n)(n为正整数，表示像素所在的行数)，源极电性连接数据线D(m)(m为正整数，表示像素所在的列数)，漏极电性连接第一存储电容Cst1及第一液晶电容Clc1；所述第二薄膜晶体管T200的栅极电性连接扫描线G(n)，源极电性连接数据线D(m)，漏极电性连接第二存储电容Cst2及第二液晶电容Clc2；所述第三薄膜晶体管T300的栅极电性连接扫描线G(n)，源极电性连接第二薄膜晶体管T200的漏极，漏极直接电性连接在阵列基板侧公共电极Acom上。
当所述扫描线G(n)传输的扫描信号作用时：在像素主区PM内，所 述第一薄膜晶体管T100打开，所述数据线D(m)传输的数据信号会向第一存储电容Cst1及第一液晶电容Clc1充电；而在像素次区PS内，所述第二薄膜晶体管T200与第三薄膜晶体管T300均打开，在所述数据线D(m)传输的数据信号向第二存储电容Cst2及第二液晶电容Clc2充电的同时，打开的第三薄膜晶体管T300向阵列基板侧公共电极Acom实施放电；这样，待所述扫描线G(n)传输的扫描信号作用完毕后，像素次区PS内的第二液晶电容Clc2上的电压便会低于像素主区PM内的第一液晶电容Clc1上的电压，能够达到降低色偏(Color Shift)的效果。
受到制程稳定性等因素的影响，上述3T结构的像素电路中各个薄膜晶体管尤其是第三薄膜晶体T300的沟道长宽比差异较大，导致其IV特性浮动比较大，那么第三薄膜晶体T300放电对阵列基板侧公共电极Acom的影响就会较大，导致在显示画面时阵列基板侧公共电极Acom产生电压跳变，且电压跳变的差异较大，受阵列基板侧公共电极Acom电压跳变的影响，画面显示会出现水平串扰(Crosstalk)现象。
发明内容
本发明的目的在于提供一种像素电路，既能够明显改善色偏，又能够消除现有的3T结构的像素电路中第三薄膜晶体管放电对阵列基板侧公共电极的影响，减少水平串扰现象的发生，并进一步提高像素开口率。
本发明的另一目的在于提供一种液晶显示面板，色偏较小，串扰现象较少，像素开口率较高。
为实现上述目的，本发明首先提供一种像素电路，仅采用两个薄膜晶体管，包括像素主区及像素次区。
可选地：所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
所述像素次区内设有一个次区薄膜晶体管、次区存储电容、次区液晶电容及与所述次区液晶电容串联的分压电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接分压电容的一端及次区存储电容的一端；所述分压电容的另一端电性连接所述次区液晶电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
所述分压电容的分压作用使得所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
进一步地，所述数据线传输的数据信号用于向所述像素主区及所述像素次区充电；充电完毕后，所述次区液晶电容上的电压与所述主区液晶电容上的电压的比值为：Cs/(Cs+Clc2)；
其中，Cs表示分压电容，Clc2表示次区液晶电容。
所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率。
可选地：所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
所述像素次区内设有一个次区薄膜晶体管、次区存储电容及次区液晶电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接次区液晶电容的一端及次区存储电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率，从而所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
优选地，所述次区薄膜晶体管的充电率是所述主区薄膜晶体管的充电率的70％～80％。
本发明还提供一种液晶显示面板，包括像素电路；所述像素电路仅采用两个薄膜晶体管，包括像素主区及像素次区；可选地：所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
所述像素次区内设有一个次区薄膜晶体管、次区存储电容、次区液晶电容及与所述次区液晶电容串联的分压电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接分压电容的一端及 次区存储电容的一端；所述分压电容的另一端电性连接所述次区液晶电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
所述分压电容的分压作用使得所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
进一步地，所述数据线传输的数据信号用于向所述像素主区及所述像素次区充电；充电完毕后，所述次区液晶电容上的电压与所述主区液晶电容上的电压的比值为：Cs/(Cs+Clc2)；
其中，Cs表示分压电容，Clc2表示次区液晶电容。
所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率。
可选地：所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
所述像素次区内设有一个次区薄膜晶体管、次区存储电容及次区液晶电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接次区液晶电容的一端及次区存储电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率，从而所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
优选地，所述次区薄膜晶体管的充电率是所述主区薄膜晶体管的充电率的70％～80％。
本发明的有益效果：本发明提供的像素电路，采用2T结构，一方面通过设置与次区液晶电容串联的分压电容或设置次区薄膜晶体管的沟道长宽比小于主区薄膜晶体管的沟道长宽比，使得次区液晶电容上的电压小于主区液晶电容上的电压，能够明显改善色偏；另一方面，相比现有的3T结构的像素电路省去了用于为像素次区放电的第三薄膜晶体管，能够消除该第三薄膜晶体管放电对阵列基板侧公共电极的影响，减少水平串扰现象的发生，并进一步提高像素开口率。本发明提供的液晶显示面板采用所述像素 电路，色偏较小，串扰现象较少，像素开口率较高。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的3T结构的像素电路的电路图；
图2为本发明的像素电路的第一实施例的电路图；
图3为本发明的像素电路的第二实施例的电路图；
图4为本发明的像素电路的第三实施例的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种像素电路。
请参阅图2，本发明的像素电路的第一实施例采用2T，即仅采用两个薄膜晶体管的结构，包括像素主区PM及像素次区PS。
所述像素主区PM内设有主区薄膜晶体管T1、主区存储电容Cst1及主区液晶电容Clc1。所述主区薄膜晶体管T1的栅极电性连接扫描线G(n)(n为正整数，表示像素所在的行数)，源极电性连接数据线D(m)(m为正整数，表示像素所在的列数)，漏极电性连接主区存储电容Cst1的一端及主区液晶电容Clc1的一端(即主区像素电极)；所述主区存储电容Cst1的另一端电性连接阵列基板侧公共电极Acom；所述主区液晶电容Clc1的另一端电性连接彩膜基板侧公共电极CFcom。
所述像素次区PS内设有一个次区薄膜晶体管T2、次区存储电容Cst2、次区液晶电容Clc2及与所述次区液晶电容Clc2串联的分压电容Cs。
所述次区薄膜晶体管T2的栅极电性连接扫描线G(n)，源极电性连接数据线D(m)，漏极电性连接分压电容Cs的一端及次区存储电容Cst2的一端；所述分压电容Cs的另一端电性连接所述次区液晶电容Clc2的一端(即次区像素电极)；所述次区液晶电容Clc2的另一端电性连接彩膜基板侧公共电极CFcom；所述次区存储电容Cst2的另一端电性连接阵列基板侧公 共电极Acom。
相比现有的3T结构的像素电路，本发明的像素电路的第一实施例省去了用于为像素次区放电的第三薄膜晶体管，而是设置所述分压电容Cs来与次区液晶电容Clc2进行分压。当所述扫描线G(n)传输的扫描信号作用时：在所述像素主区PM内，所述主区薄膜晶体管T1打开，所述数据线D(m)传输的数据信号向主区存储电容Cst1、主区液晶电容Clc1充电；在所述像素次区PS内，所述次区薄膜晶体管T2打开，所述数据线D(m)传输的数据信号向次区存储电容Cst2、分压电容Cs与次区液晶电容Clc2充电。设所述数据信号相对于彩膜基板侧公共电极CFcom的电压为V data，那么待所述扫描线G(n)传输的扫描信号作用完毕后：所述主区液晶电容Clc1完成充电，且所述主区液晶电容Clc1上的电压V  Clc1为V data，即：
V  Clc1＝V data                                (1)
所述次区液晶电容Clc2与分压电容Cs完成充电，且所述次区液晶电容Clc2上的电压V  Clc2与所述分压电容Cs上的电压V  Cs之和为V data，即：
V  Clc2+V  Cs＝V data；
根据电容分压原理，所述次区液晶电容Clc2上的电压V  Clc2为：
V  Clc2＝V data×Cs/(Cs+Clc2)                  (2)
将(2)式与(1)式相除，可得所述次区液晶电容Clc2上的电压与所述主区液晶电容Clc1上的电压的比值为：
V  Clc2/V  Clc1＝V data×Cs/(Cs+Clc2)/V data
＝Cs/(Cs+Clc2)                  (3)
可见，由于设置了所述分压电容Cs，所述分压电容Cs的分压作用会使得所述次区液晶电容Clc2上的电压小于所述主区液晶电容Clc1上的电压，能够明显改善色偏。
由于本发明的像素电路的第一实施例相比现有的3T结构的像素电路省去了用于为像素次区放电的第三薄膜晶体管，能够消除该第三薄膜晶体管放电对阵列基板侧公共电极Acom的影响，减少水平串扰现象的发生，并进一步提高像素开口率。
请参阅图3，本发明的像素电路的第二实施例采用2T结构，包括像素主区PM及像素次区PS。
所述像素主区PM内设有主区薄膜晶体管T1、主区存储电容Cst1及主区液晶电容Clc1。所述主区薄膜晶体管T1的栅极电性连接扫描线G(n)，源极电性连接数据线D(m)，漏极电性连接主区存储电容Cst1的一端及主 区液晶电容Clc1的一端(即主区像素电极)；所述主区存储电容Cst1的另一端电性连接阵列基板侧公共电极Acom；所述主区液晶电容Clc1的另一端电性连接彩膜基板侧公共电极CFcom。
所述像素次区PS内设有一个次区薄膜晶体管T2、次区存储电容Cst2及次区液晶电容Clc2。所述次区薄膜晶体管T2的栅极电性连接扫描线G(n)，源极电性连接数据线D(m)，漏极电性连接次区液晶电容Clc2的一端(即次区像素电极)及次区存储电容Cst2的一端；所述次区液晶电容Clc2的另一端电性连接彩膜基板侧公共电极CFcom；所述次区存储电容Cst2的另一端电性连接阵列基板侧公共电极Acom。
特别需要说明的是：薄膜晶体管的沟道长宽比是决定薄膜晶体管充电率的重要因素，沟道长宽比越大则薄膜晶体管的充电率越高。本发明的像素电路的第二实施例设置所述次区薄膜晶体管T2的沟道长宽比小于所述主区薄膜晶体管T1的沟道长宽比(通过在制程时增加次区薄膜晶体管T2的沟道长度而保持沟道宽度不变，或保持次区薄膜晶体管T2的沟道长度不变而减小沟道宽度来实现)。当所述扫描线G(n)传输的扫描信号作用时：在所述像素主区PM内，所述主区薄膜晶体管T1打开，所述数据线D(m)传输的数据信号经由所述主区薄膜晶体管T1向主区存储电容Cst1、主区液晶电容Clc1充电；在所述像素次区PS内，所述次区薄膜晶体管T2打开，所述数据线D(m)传输的数据信号经由所述次区薄膜晶体管T2向次区存储电容Cst2、次区液晶电容Clc2充电；由于所述次区薄膜晶体管T2的沟道长宽比小于所述主区薄膜晶体管T1的沟道长宽比，所述次区薄膜晶体管T2的充电率便小于所述主区薄膜晶体管T1的充电率，优选地，所述次区薄膜晶体管T2的充电率是所述主区薄膜晶体管T1的充电率的70％～80％，进而使得在充电完成后所述次区液晶电容Clc2上的电压小于所述主区液晶电容Clc1上的电压，能够明显改善色偏。
本发明的像素电路的第二实施例通过降低次区薄膜晶体管T2的沟道长宽比来使得次区液晶电容Clc2上的电压小于主区液晶电容Clc1上的电压以达到改善色偏的效果，相比现有的3T结构的像素电路省去了用于为像素次区放电的第三薄膜晶体管，能够消除该第三薄膜晶体管放电对阵列基板侧公共电极Acom的影响，减少水平串扰现象的发生，并进一步提高像素开口率。
请参阅图4，本发明的像素电路的第三实施例是对上述第一实施例与第二实施例所做的组合，即在第一实施例设置与所述次区液晶电容Clc2串联的分压电容Cs的基础上，同时降低次区薄膜晶体管T2的沟道长宽比，使 得所述次区薄膜晶体管T2的沟道长宽比小于所述主区薄膜晶体管T1的沟道长宽比，能够在更大程度上使得所述次区液晶电容Clc2上的电压小于所述主区液晶电容Clc1上的电压以明显改善色偏，并且该第三实施例相比现有的3T结构的像素电路省去了用于为像素次区放电的第三薄膜晶体管，能够消除该第三薄膜晶体管放电对阵列基板侧公共电极的影响，减少水平串扰现象的发生，并进一步提高像素开口率。
本发明还提供一种液晶显示面板，采用任一种上述的像素电路，所以该液晶显示面板的色偏较小，串扰现象较少，像素开口率较高。
综上所述，本发明的像素电路，采用2T结构，一方面通过设置与次区液晶电容串联的分压电容或设置次区薄膜晶体管的沟道长宽比小于主区薄膜晶体管的沟道长宽比，使得次区液晶电容上的电压小于主区液晶电容上的电压，能够明显改善色偏；另一方面，相比现有的3T结构的像素电路省去了用于为像素次区放电的第三薄膜晶体管，能够消除该第三薄膜晶体管放电对阵列基板侧公共电极的影响，减少水平串扰现象的发生，并进一步提高像素开口率。本发明的液晶显示面板采用所述像素电路，色偏较小，串扰现象较少，像素开口率较高。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (8)

  1. 一种像素电路，仅采用两个薄膜晶体管，包括像素主区及像素次区；
    所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
    所述像素次区内设有一个次区薄膜晶体管、次区存储电容、次区液晶电容及与所述次区液晶电容串联的分压电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接分压电容的一端及次区存储电容的一端；所述分压电容的另一端电性连接所述次区液晶电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；所述分压电容的分压作用使得所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
  2. 如权利要求1所述的像素电路，其中，所述数据线传输的数据信号用于向所述像素主区及所述像素次区充电；充电完毕后，所述次区液晶电容上的电压与所述主区液晶电容上的电压的比值为：Cs/(Cs+Clc2)；
    其中，Cs表示分压电容，Clc2表示次区液晶电容。
  3. 如权利要求1所述的像素电路，其中，所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率。
  4. 一种液晶显示面板，包括像素电路；所述像素电路仅采用两个薄膜晶体管，包括像素主区及像素次区；
    所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
    所述像素次区内设有一个次区薄膜晶体管、次区存储电容、次区液晶电容及与所述次区液晶电容串联的分压电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接分压电容的一端及次区存储电容的一端；所述分压电容的另一端电性连接所述次区液晶电容 的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
    所述分压电容的分压作用使得所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
  5. 如权利要求4所述的液晶显示面板，其中，所述数据线传输的数据信号用于向所述像素主区及所述像素次区充电；充电完毕后，所述次区液晶电容上的电压与所述主区液晶电容上的电压的比值为：Cs/(Cs+Clc2)；
    其中，Cs表示分压电容，Clc2表示次区液晶电容。
  6. 如权利要求4所述的液晶显示面板，其中，所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率。
  7. 一种液晶显示面板，包括像素电路；所述像素电路仅采用两个薄膜晶体管，包括像素主区及像素次区；
    所述像素主区内设有主区薄膜晶体管、主区存储电容及主区液晶电容；所述主区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接主区存储电容的一端及主区液晶电容的一端；所述主区存储电容的另一端电性连接阵列基板侧公共电极；所述主区液晶电容的另一端电性连接彩膜基板侧公共电极；
    所述像素次区内设有一个次区薄膜晶体管、次区存储电容及次区液晶电容；所述次区薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接次区液晶电容的一端及次区存储电容的一端；所述次区液晶电容的另一端电性连接彩膜基板侧公共电极；所述次区存储电容的另一端电性连接阵列基板侧公共电极；
    所述次区薄膜晶体管的沟道长宽比小于所述主区薄膜晶体管的沟道长宽比，使得所述次区薄膜晶体管的充电率小于所述主区薄膜晶体管的充电率，从而所述次区液晶电容上的电压小于所述主区液晶电容上的电压。
  8. 如权利要求7所述的液晶显示面板，其中，所述次区薄膜晶体管的充电率是所述主区薄膜晶体管的充电率的70％～80％。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109377965B (zh) * 2018-12-21 2021-06-25 信利半导体有限公司 异形像素驱动单元、像素驱动阵列及显示设备
CN109375440A (zh) * 2018-12-21 2019-02-22 惠科股份有限公司 一种显示面板
TWI696991B (zh) * 2019-05-21 2020-06-21 友達光電股份有限公司 顯示裝置及其驅動方法
CN110570825A (zh) * 2019-08-08 2019-12-13 深圳市华星光电技术有限公司 一种像素电路及液晶显示面板
CN111308802B (zh) * 2020-03-12 2021-07-06 Tcl华星光电技术有限公司 一种阵列基板、显示面板
CN112068376A (zh) * 2020-09-28 2020-12-11 成都中电熊猫显示科技有限公司 阵列基板以及显示装置
CN113391490A (zh) * 2021-05-20 2021-09-14 北海惠科光电技术有限公司 显示面板驱动方法、显示面板和显示装置
CN113391491B (zh) * 2021-06-16 2023-11-28 惠州华星光电显示有限公司 液晶显示面板及显示装置
CN114002884B (zh) * 2021-09-30 2022-10-21 惠科股份有限公司 阵列基板、显示面板及显示器
CN114023256B (zh) * 2021-10-18 2023-06-13 云谷（固安）科技有限公司 显示面板、像素电路及显示装置
CN114355680A (zh) * 2022-01-06 2022-04-15 Tcl华星光电技术有限公司 像素结构、阵列基板以及显示面板
CN114815423B (zh) * 2022-04-29 2023-12-15 苏州华星光电技术有限公司 显示面板制作方法
CN114937442B (zh) * 2022-05-28 2023-05-26 长沙惠科光电有限公司 公共电压输出电路和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1687836A (zh) * 2005-05-20 2005-10-26 友达光电股份有限公司 低色偏液晶显示装置与其电极板形成方法
CN101281329A (zh) * 2007-04-04 2008-10-08 瀚宇彩晶股份有限公司 液晶显示器及其子像素
US20090128724A1 (en) * 2007-11-21 2009-05-21 Hannstar Display Corporation Liquid crystal display
CN101852955A (zh) * 2009-04-02 2010-10-06 华映视讯（吴江）有限公司 可消除残影的液晶显示装置及其方法
CN103576358A (zh) * 2012-07-31 2014-02-12 群康科技(深圳)有限公司 低色偏的液晶面板及显示器
CN104834138A (zh) * 2015-05-25 2015-08-12 深圳市华星光电技术有限公司 高画质液晶显示器像素电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1963647A (zh) * 2005-11-10 2007-05-16 群康科技(深圳)有限公司 液晶显示面板
TW201219944A (en) * 2010-11-10 2012-05-16 Chunghwa Picture Tubes Ltd Transistor array substrate
CN102508386B (zh) * 2011-11-28 2014-11-26 深圳市华星光电技术有限公司 液晶显示器
CN104698643A (zh) * 2015-03-23 2015-06-10 深圳市华星光电技术有限公司 电容分压式低色偏像素电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1687836A (zh) * 2005-05-20 2005-10-26 友达光电股份有限公司 低色偏液晶显示装置与其电极板形成方法
CN101281329A (zh) * 2007-04-04 2008-10-08 瀚宇彩晶股份有限公司 液晶显示器及其子像素
US20090128724A1 (en) * 2007-11-21 2009-05-21 Hannstar Display Corporation Liquid crystal display
CN101852955A (zh) * 2009-04-02 2010-10-06 华映视讯（吴江）有限公司 可消除残影的液晶显示装置及其方法
CN103576358A (zh) * 2012-07-31 2014-02-12 群康科技(深圳)有限公司 低色偏的液晶面板及显示器
CN104834138A (zh) * 2015-05-25 2015-08-12 深圳市华星光电技术有限公司 高画质液晶显示器像素电路

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