CN110570825A - 一种像素电路及液晶显示面板 - Google Patents
一种像素电路及液晶显示面板 Download PDFInfo
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- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
本发明实施例公开了一种像素电路及液晶显示面板。像素电路包括并联连接的主薄膜晶体管和次薄膜晶体管,所述主薄膜晶体管的电阻小于所述次薄膜晶体管的电阻;通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。液晶显示面板包括上述像素电路。本发明通过只用2个TFT就能够实现不同畴之间的亮度不同,从而改善面板色偏,在改善面板色偏的同时提升面板穿透率。
Description
技术领域
本发明涉及显示技术领域,特别涉及一种像素电路及液晶显示面板。
背景技术
液晶显示面板(Liquid Crystal Display,LCD),具有机身薄、省电、无辐射等众多优点,得到了广泛地应用,如:液晶电视、智能手机、数字相机、平板电脑、计算机屏幕、或笔记本电脑屏幕等,在平板显示领域中占主导地位。
液晶显示面板是由一彩膜基板(Color Filter,CF)、一薄膜晶体管阵列基板(ThinFilm Transistor Array Substrate,TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成。液晶显示面板内设有多个呈阵列式排布的像素(Pixel),当在两片基板上施加驱动电压时,各个像素在像素电路的驱动下进行显示。
为了解决在大视角下色偏(Color Shift)的现象,本领域技术人员设计了多种像素结构来实现降低色偏的目的。常见的针对大视角下色偏的对策是采用空间法,即将像素单元的ITO区域划分为若干个畴(Domain),通过设计多个TFT的方式令不同畴之间亮度不同,来达到大视角下低色偏的效果。
如图1所示,为现有一种像素电路的结构示意图,包括主TFT(main-TFT)10、次TFT(sub-TFT)20和共享TFT(share-TFT)30。如图2所示,为图1中的像素电路的等效电路图,扫描线Gate输出高电平时,通过主TFT(main-TFT)10向A区的主液晶电容(Clc-main)40和存储电容Cst-A进行充放电,通过次TFT(sub-TFT)20向B区的次液晶电容(Clc-sub)50和存储电容Cst-B进行充放电,同时通过共享TFT(share-TFT)30将亚像素(sub pixel)节点的电压拉低,为了实现像素电压VpA和像素电压VpB存在压差,通常需要通过模拟调整出合适的共享TFT(share-TFT)30的沟道长宽比值,使得不同畴之间的亮度差异达到目标水平,以实现大视角下低色偏的效果。
然而,要实现不同畴之间的亮度不同,需要至少用到3个TFT器件,以及3个通孔(via hole),上述设计会使得像素的开口率降低,进而引起液晶面板穿透率的降低,导致背光源成本的提高。
因此,如何解决上述问题,在不降低开口率和穿透率的情况下,实现大视角下低色偏显示效果,乃业界所致力的课题之一。
发明内容
本发明提出一种像素电路及液晶显示面板,以解决在不降低开口率和穿透率的情况下,实现大视角下低色偏显示效果的问题。
为了实现上述目的,本发明采用了如下的技术方案:
本发明的一实施例中,提供一种像素电路,包括并联连接的主薄膜晶体管和次薄膜晶体管,所述主薄膜晶体管的电阻小于所述次薄膜晶体管的电阻;通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
进一步的,其中所述主薄膜晶体管的栅极电性连接至一扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容的一端;所述主液晶电容的另一端电性连接至一彩膜基板侧公共电极。所述次薄膜晶体管的栅极电性连接至所述扫描线,源极电性连接至所述数据线,漏极电性连接至一次液晶电容的一端;所述次液晶电容的另一端电性连接至所述彩膜基板侧公共电极。通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
进一步的,其中所述次薄膜晶体管的沟道长宽比小于所述主薄膜晶体管的沟道长宽比,使得所述次薄膜晶体管的充电率小于所述主薄膜晶体管的充电率。
进一步的,其中通过调节所述主薄膜晶体管的沟道长宽比大小来调节所述主薄膜晶体管的电阻大小。
进一步的,其中通过调节所述次薄膜晶体管的沟道长宽比大小来调节所述次薄膜晶体管的电阻大小。
本发明又一实施例中还提供一种液晶显示面板,包括像素电路;所述像素电路包括并联连接的主薄膜晶体管和次薄膜晶体管,所述主薄膜晶体管的电阻小于所述次薄膜晶体管的电阻;通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
进一步的,其中所述主薄膜晶体管的栅极电性连接扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容的一端;所述主液晶电容的另一端电性连接至一彩膜基板侧公共电极。所述次薄膜晶体管的栅极电性连接至所述扫描线,源极电性连接至所述数据线,漏极电性连接至一次液晶电容的一端;所述次液晶电容的另一端电性连接至所述彩膜基板侧公共电极。通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
进一步的,其中所述次薄膜晶体管的沟道长宽比小于所述主薄膜晶体管的沟道长宽比,使得所述次薄膜晶体管的充电率小于所述主薄膜晶体管的充电率。
进一步的,其中通过调节所述主薄膜晶体管的沟道长宽比大小来调节所述主薄膜晶体管的电阻大小。
进一步的,其中通过调节所述次薄膜晶体管的沟道长宽比大小来调节所述次薄膜晶体管的电阻大小。
本发明提出一种像素电路及液晶显示面板,既能够明显改善色偏,又能够保证像素开口率。通过只用2个TFT就能够实现不同畴之间的亮度不同,从而改善面板色偏,在改善面板色偏的同时提升面板穿透率。
附图说明
下面结合附图,通过对本申请的具体实施方式详细描述,将使本申请的技术方案及其它有益效果显而易见。
图1为现有一种像素电路的透视结构示意图;
图2为图1中的像素电路的电路图;
图3为本发明一实施例的像素电路透视结构示意图;
图4为图3中的像素电路的电路图;
图5为图4中的像素电路的等效电路图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围,而是仅仅表示本发明的选定实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参照附图将对本申请的优选实施例进行说明。在整个说明书中,相同的附图标记表示相同的元素。然而,本申请不受这些实施例的限制,而是可以采用各种更改或变化而不改变技术精神。在以下实施例中,元素名称的选择是考虑到说明上的便利,其可能会与实际名称相异。
请参阅图3、图4所示,本发明的像素电路的主实施例采用2T,即仅采用两个薄膜晶体管的结构,包括并联连接的主薄膜晶体管1(图4中Main-TFT)和次薄膜晶体管2(图4中Sub-TFT),所述主薄膜晶体管1的电阻小于所述次薄膜晶体管2的电阻;通过所述主薄膜晶体管1与所述次薄膜晶体管2电阻分压作用,使得所述次薄膜晶体管2的电压小于所述主薄膜晶体管1的电压,实现所述主薄膜晶体管1与所述次薄膜晶体管2的电压差,从而实现不同畴之间的亮度不同,达到在大视角下低色偏的效果。
本实施例中,所述主薄膜晶体管1的栅极电性连接至一扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容3(图4、图5中Clc-main)的一端;所述主液晶电容3的另一端电性连接至一彩膜基板侧公共电极CF-com。所述次薄膜晶体管2的栅极电性连接至所述扫描线(Gate),源极电性连接至所述数据线(Data),漏极电性连接至一次液晶电容4(图4、图5中Clc-sub)的一端;所述次液晶电容4的另一端电性连接至所述彩膜基板侧公共电极CF-com。通过所述主薄膜晶体管1与所述次薄膜晶体管2电阻分压作用,使得所述次薄膜晶体管2的电压小于所述主薄膜晶体管1的电压。
本实施例中,所述次薄膜晶体管2的沟道长宽比小于所述主薄膜晶体管1的沟道长宽比,使得所述次薄膜晶体管2的充电率小于所述主薄膜晶体管1的充电率。
本实施例中,通过调节所述主薄膜晶体管1的沟道长宽比大小来调节所述主薄膜晶体管1的电阻大小。
本实施例中,通过调节所述次薄膜晶体管2的沟道长宽比大小来调节所述次薄膜晶体管2的电阻大小。
具体实现方法,通过调整所述主薄膜晶体管1与所述次薄膜晶体管2的沟道长宽比(W/L)值,改变所述主薄膜晶体管1与所述次薄膜晶体管2的电阻,通过电阻分压,实现所述主薄膜晶体管1与所述次薄膜晶体管2的电压差,达到与3TFT结构相同的低色偏(lowcolor)效果,等效电路如图4所示,将所述主薄膜晶体管1与所述次薄膜晶体管2比作电阻元件,通过设计使得所述次薄膜晶体管2的电阻大于所述主薄膜晶体管1的电阻,得到C点的电压小于B点电压,实现大视角下低色偏的效果。
为了达到与3TFT架构相同的低色偏(low color)效果,对2TFT架构的低色偏(lowcolor)效果进行了模拟,我们在保持所述主薄膜晶体管1与所述次薄膜晶体管2的L不变的前提下,改变所述主薄膜晶体管1与所述次薄膜晶体管2的W值,模拟结果表明,当所述次薄膜晶体管2的W值为所述主薄膜晶体管1的W值一半大小时,其低色偏(low color)效果与3TFT架构相当。
本发明又一实施例中还提供一种液晶显示面板,包括像素电路;所述像素电路包括并联连接的主薄膜晶体管1和次薄膜晶体管2,所述主薄膜晶体管1的电阻小于所述次薄膜晶体管2的电阻;通过所述主薄膜晶体管1与所述次薄膜晶体管2电阻分压作用,使得所述次薄膜晶体管2的电压小于所述主薄膜晶体管1的电压,实现所述主薄膜晶体管1与所述次薄膜晶体管2的电压差,从而实现不同畴之间的亮度不同,达到在大视角下低色偏的效果。
本实施例中,所述主薄膜晶体管1的栅极电性连接至一扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容3的一端;所述主液晶电容3的另一端电性连接至一彩膜基板侧公共电极CF-com。所述次薄膜晶体管2的栅极电性连接至所述扫描线,源极电性连接至所述数据线,漏极电性连接至一次液晶电容4的一端;所述次液晶电容4的另一端电性连接至所述彩膜基板侧公共电极CF-com。通过所述主薄膜晶体管1与所述次薄膜晶体管2电阻分压作用,使得所述次薄膜晶体管2的电压小于所述主薄膜晶体管1的电压。
本实施例中,所述次薄膜晶体管2的沟道长宽比小于所述主薄膜晶体管1的沟道长宽比,使得所述次薄膜晶体管2的充电率小于所述主薄膜晶体管1的充电率。
本实施例中,通过调节所述主薄膜晶体管1的沟道长宽比大小来调节所述主薄膜晶体管1的电阻大小。
本实施例中,通过调节所述次薄膜晶体管2的沟道长宽比大小来调节所述次薄膜晶体管2的电阻大小。
具体实现方法,通过调整所述主薄膜晶体管1与所述次薄膜晶体管2的沟道长宽比(W/L)值,改变所述主薄膜晶体管1与所述次薄膜晶体管2的电阻,通过电阻分压,实现所述主薄膜晶体管1与所述次薄膜晶体管2的电压差,达到与3TFT结构相同的低色偏(lowcolor)效果,等效电路如图5所示,将所述主薄膜晶体管1与所述次薄膜晶体管2比作电阻元件,通过设计使得所述次薄膜晶体管2的电阻大于所述主薄膜晶体管1的电阻,得到C点的电压UC小于B点电压UB,实现大视角下低色偏的效果。
为了达到与3TFT架构相同的低色偏(low color)效果,对2TFT架构的低色偏(lowcolor)效果进行了模拟,我们在保持所述主薄膜晶体管1与所述次薄膜晶体管2的L不变的前提下,改变所述主薄膜晶体管1与所述次薄膜晶体管2的W值,模拟结果表明,当所述次薄膜晶体管2的W值为所述主薄膜晶体管1的W值一半大小时,其低色偏(low color)效果与3TFT架构相当。
本发明提出一种像素电路及液晶显示面板,既能够明显改善色偏,又能够保证像素开口率。通过只用2个TFT就能够实现不同畴之间的亮度不同,从而改善面板色偏,在改善面板色偏的同时提升面板穿透率。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解,本申请中所涉及的发明范围,并不限于上述技术特征的特定组合而成的技术方案,同时也应涵盖在不脱离所述发明构思的情况下,由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (10)
1.一种像素电路,其特征在于,包括并联连接的主薄膜晶体管和次薄膜晶体管,所述主薄膜晶体管的电阻小于所述次薄膜晶体管的电阻;通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
2.根据权利要求1所述的像素电路,其特征在于,所述主薄膜晶体管的栅极电性连接至一扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容的一端;所述主液晶电容的另一端电性连接至一彩膜基板侧公共电极;
所述次薄膜晶体管的栅极电性连接至所述扫描线,源极电性连接至所述数据线,漏极电性连接至一次液晶电容的一端;所述次液晶电容的另一端电性连接至所述彩膜基板侧公共电极;
通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
3.根据权利要求1所述的像素电路,其特征在于,所述次薄膜晶体管的沟道长宽比小于所述主薄膜晶体管的沟道长宽比,使得所述次薄膜晶体管的充电率小于所述主薄膜晶体管的充电率。
4.根据权利要求1所述的像素电路,其特征在于,通过调节所述主薄膜晶体管的沟道长宽比大小来调节所述主薄膜晶体管的电阻大小。
5.根据权利要求1所述的像素电路,其特征在于,通过调节所述次薄膜晶体管的沟道长宽比大小来调节所述次薄膜晶体管的电阻大小。
6.一种液晶显示面板,其特征在于,包括像素电路;所述像素电路包括并联连接的主薄膜晶体管和次薄膜晶体管,所述主薄膜晶体管的电阻小于所述次薄膜晶体管的电阻;通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
7.根据权利要求6所述的液晶显示面板,其特征在于,所述主薄膜晶体管的栅极电性连接至一扫描线,源极电性连接至一数据线,漏极电性连接至一主液晶电容的一端;所述主液晶电容的另一端电性连接至一彩膜基板侧公共电极;
所述次薄膜晶体管的栅极电性连接至所述扫描线,源极电性连接至所述数据线,漏极电性连接至一次液晶电容的一端;所述次液晶电容的另一端电性连接至所述彩膜基板侧公共电极;
通过所述主薄膜晶体管与所述次薄膜晶体管电阻分压作用,使得所述次薄膜晶体管的电压小于所述主薄膜晶体管的电压。
8.根据权利要求6所述的液晶显示面板,其特征在于,所述次薄膜晶体管的沟道长宽比小于所述主薄膜晶体管的沟道长宽比,使得所述次薄膜晶体管的充电率小于所述主薄膜晶体管的充电率。
9.根据权利要求6所述的液晶显示面板,其特征在于,通过调节所述主薄膜晶体管的沟道长宽比大小来调节所述主薄膜晶体管的电阻大小。
10.根据权利要求6所述的液晶显示面板,其特征在于,通过调节所述次薄膜晶体管的沟道长宽比大小来调节所述次薄膜晶体管的电阻大小。
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Application publication date: 20191213 |