WO2019056441A1 - 阵列基板及其显示面板 - Google Patents

阵列基板及其显示面板 Download PDF

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Publication number
WO2019056441A1
WO2019056441A1 PCT/CN2017/107025 CN2017107025W WO2019056441A1 WO 2019056441 A1 WO2019056441 A1 WO 2019056441A1 CN 2017107025 W CN2017107025 W CN 2017107025W WO 2019056441 A1 WO2019056441 A1 WO 2019056441A1
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Prior art keywords
pixel
vertical alignment
polymer
array substrate
substrate
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PCT/CN2017/107025
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English (en)
French (fr)
Inventor
黄北洲
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惠科股份有限公司
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Priority to US15/738,775 priority Critical patent/US20190086752A1/en
Publication of WO2019056441A1 publication Critical patent/WO2019056441A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to a method of pixel design, and in particular to an array substrate and a display panel thereof.
  • the liquid crystal display panel is generally composed of a color filter substrate (CF), an active switch array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refract the light of the backlight module to generate a picture.
  • liquid crystal display panels on the mainstream market can be classified into the following types: Vertical Alignment (VA) type, Twisted Nematic (TN) or Super Twisted (Super Twisted). Nematic, STN) type, In-Plane Switching (IPS) type and Fringe Field Switching (FFS) type.
  • VA Vertical Alignment
  • TN Twisted Nematic
  • IPS In-Plane Switching
  • FFS Fringe Field Switching
  • the liquid crystal display of the Vertical Alignment (VA) mode such as a Pattern Vertical Alignment (PVA) liquid crystal display or a Multi-domain Vertical Alignment (MVA) liquid crystal display, wherein the PVA
  • the type uses the fringe field effect and the compensation plate to achieve a wide viewing angle.
  • the MVA type divides a single pixel into a plurality of regions, and uses a protrusion or a specific pattern structure to tilt liquid crystal molecules located in different regions toward different directions to achieve a wide viewing angle and enhance the transmittance.
  • Liquid crystal displays are currently the most widely used displays on the market, especially on LCD TVs. With the gradual increase of resolution, the size of the pixels will become smaller and smaller, and the aperture ratio will become smaller and smaller. Large-size products can watch more angles when viewed, so they will face color deviation when viewing large angles. phenomenon.
  • the main pixel and the sub pixel were designed to reduce the voltage of the sub pixel by changing the voltage of the sub pixel. Areas (8domain) to improve the perspective.
  • This design typically has three or more active switches to control.
  • an object of the present invention is to provide a pixel design method, and more particularly to an array substrate and the same for the display panel, which can effectively solve the color shift problem and effectively improve the large size and high resolution.
  • Rate of product The angle increases the penetration rate of large-size, high-resolution products.
  • An array substrate includes: a substrate having a display area and a wiring area; at least one active switch disposed on the substrate; and a plurality of scan lines and a plurality of data lines disposed on the substrate
  • the scan line is electrically connected to the control end of the active switch, the data line is electrically connected to the input end of the active switch; a plurality of pixel units are disposed in the display area, and the output of the active switch An electrical connection; wherein each pixel unit includes a first pixel and a second pixel, the pixel unit includes a vertical alignment pixel and a polymer-polymerized stable vertical alignment pixel; and the pixel element of the vertical alignment pixel and the pixel
  • the pixel electrodes of the molecular polymerization stable vertical alignment pixels are electrically coupled to the substrate, respectively.
  • an array substrate comprising: a substrate having a display area and a wiring area; at least one active switch disposed on the substrate; a plurality of scan lines and a plurality of data lines disposed on the substrate On the substrate, the scan line is electrically connected to the control end of the active switch, the data line is electrically connected to the input end of the active switch; a plurality of pixel units are disposed in the display area, and the active switch
  • the output terminal is electrically connected; wherein each pixel unit includes a first pixel and a second pixel, the pixel unit includes a vertical alignment pixel and a polymer-polymerized stable vertical alignment pixel; and the pixel element of the vertical alignment pixel
  • the pixel electrodes of the polymer-polymerically stable vertical alignment pixel are electrically coupled to the substrate, respectively; the vertical alignment pixels and the polymer-polymerically stable vertical alignment pixels are arranged in an array; the vertical alignment pixels and the vertical alignment pixels The polymer-polymerized stable vertical alignment pixel
  • a further object of the present application is a display panel comprising: a pair of substrates disposed opposite the array substrate; a color filter layer comprising a plurality of color resists; and the array substrate as described therein; The color filter layer is disposed on the opposite substrate or the array substrate.
  • each of the plurality of pixel units includes a first pixel and a second pixel.
  • the first pixel is a vertical alignment pixel
  • the second pixel is a polymer polymerization stable vertical alignment pixel
  • the first pixel is a polymer-polymerized stable vertical alignment pixel
  • the second pixel is a vertical alignment pixel
  • the first pixel is a main pixel
  • the second pixel is a sub-pixel
  • the first pixel is a sub-pixel
  • the second pixel is a main pixel
  • the data line electrically coupled to the polymer-stabilized vertical alignment pixel is electrically different from the scan line electrically coupled to the vertical alignment pixel, and the adjacent electrical properties are different.
  • the polymerizable stable vertical alignment pixel is electrically coupled to the scan line, and the vertical The scan lines electrically coupled to the pixels are different in electrical proximity.
  • the vertical alignment pixels and the polymer polymerization stable vertical alignment pixels are arranged in a spaced or staggered configuration.
  • the application of the present application can solve the problem of color shift of the liquid crystal display panel and improve the aperture ratio and transmittance of the pixel.
  • Figure 1a is a schematic diagram of a generalized 8-area pixel design.
  • Fig. 1b is a schematic diagram of a liquid crystal pixel circuit for solving the color shift problem.
  • FIG. 2 is a schematic diagram showing the arrangement of a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel according to an embodiment of the present application.
  • FIG. 2a is a schematic diagram showing the arrangement of a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel according to another embodiment of the present application.
  • FIG. 3a is a schematic diagram of a scan line waveform according to an embodiment of the present application.
  • FIG. 3b is a schematic diagram of a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel control driving according to an embodiment of the present application.
  • 4a is a schematic diagram of a scan line waveform of another embodiment of the present application.
  • FIG. 4b is a schematic diagram of a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel control driving according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a pixel arrangement according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a pixel arrangement of another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a pixel arrangement according to still another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a pixel arrangement according to still another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a pixel arrangement of still another embodiment of the present application.
  • FIG. 10 is a block diagram of a display panel according to an embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the display panel of the present application may include an LCD (Liquid Crystal Display) panel including: a thin film transistor (TFT) substrate, a color filter (CF) substrate, and a liquid crystal layer formed between the two substrates or It is an OLED (Organic Light-Emitting Diode) panel or a QLED (Quantum Dots Light-Emitting Diode) panel.
  • LCD Liquid Crystal Display
  • TFT thin film transistor
  • CF color filter
  • OLED Organic Light-Emitting Diode
  • QLED Quadantum Dots Light-Emitting Diode
  • the display panel of the present application may be a curved display panel.
  • the switch array (TFT) and the color filter layer (CF) of the present application may be formed on the same substrate.
  • FIG. 1a is a schematic diagram of a generalized 8-area pixel design
  • FIG. 1b is a schematic diagram of a liquid crystal pixel circuit for solving a color shift problem.
  • a liquid crystal display a plurality of capacitors in a pixel are subjected to charge sharing between each other, which is a technique derived from solving the color shift problem.
  • Figure 1b in the liquid crystal pixel circuit shown in FIG.
  • the pixel is controlled by the main scanning line G1, the transistor T 1 using the data acquired from the data lines D1 and stored into the storage capacitor C st1; sub-pixel in addition to the same scanning line G1 is controlled by the transistor T 2 acquired from the data line D1 and the data stored in the storage capacitor C st2 outside, is further controlled by the scanning line G2, in order to make use of the transistor T 3 and the storage capacitor C st2 storage capacitor C St3 performs charge sharing.
  • the liquid crystal pixel circuit shown in FIG. 1 can appropriately control the ratio of the voltage stored in the storage capacitor C st1 and the storage capacitor C st2 , thereby driving the liquid crystal capacitors C 1c1 and C 1c2 to be driven by default voltages.
  • the liquid crystal display has also improved in resolution or picture update frequency.
  • the amount of data in the pixel circuit is good, or even in the case where the resolution and the picture update frequency are increased together, it is necessary to update the data in more pixel circuits in a shorter time, in general, for each pixel circuit.
  • the charging time that can be used when storing the data on the data line D1 to the storage capacitors C st1 and C st2 is thus reduced.
  • the storage capacitors C st1 and C st2 may not be fully charged, and the storage voltages of the storage capacitors C st1 and C st2 may not reach the same level. .
  • the storage capacitor C st1 and C st2 storage is not the same, then when the storage capacitor C st2 and a charge storage capacitor C st3 shared by the storage capacitor C st2 voltage and the voltage maintained by the storage capacitor C st1 maintained The ratio can not reach the originally set ratio, so the color shift problem that you want to eliminate will appear again in the display process.
  • a pixel structure 10 for solving a large-view character bias is designed.
  • the main pixel and the sub pixel are designed to lower the voltage of the sub pixel by 4 pixels.
  • the area (4domain) becomes 8 areas (8domain) to improve the viewing angle.
  • a pixel structure unit 100 includes: scan lines G1 G G7 for providing scan signals; and data lines D1 D D12 for providing data signals, and the data lines D1 D D12 and The scan lines G1 G G7 define at least one pixel region 110, 120; the switching transistors T1, T2, T3 are electrically connected to the scan lines G1, G2 and the data line D1, and are in the first time period and in The data signal is transmitted under the control of the scan signal, the first time period corresponds to a data loading mode of the pixel structure unit 100; and the storage capacitors C st1 , C st2 , C st3 have a first connection end 101a, 201a, 301a and a second connection end, the first connection end 101a, 201a, 301a is electrically connected to the switching transistors T1,
  • the scan lines G1 G G7 control the voltage values of the vertical light alignment pixel 110 and the polymer polymerization stable vertical alignment pixel 120.
  • the indium tin oxide of the vertical light-aligning pixel 110 is not connected to the indium tin oxide of the polymer-polymerically stable vertical alignment pixel 120, thereby avoiding liquid crystal reverse chaos.
  • an array substrate 105 includes: a substrate having a display area and a wiring area; at least one active switch (not shown) disposed on the substrate; a plurality of scanning lines G1 G G6 and a plurality of The data lines D1 to D12 are disposed on the substrate, the scan lines G1 G G6 are electrically connected to the control end of the active switch, and the data lines D1 D D12 are electrically connected to the input end of the active switch;
  • the pixel units 110 and 120 are disposed in the display area and electrically connected to the output end of the active switch; wherein each pixel unit includes a first pixel and a second pixel, and the pixel unit includes a vertical alignment pixel 110.
  • an array substrate 105 includes a substrate having a display area and a wiring area.
  • the plurality of pixel units 110 and 120 are disposed in the display area and electrically coupled to the corresponding data lines D1 to D12.
  • each of the plurality of pixel units 110, 120 includes a first pixel and a second pixel.
  • the first pixel is a vertical alignment pixel 110
  • the second pixel is a polymer polymerization stable vertical alignment pixel 120, but the arrangement thereof is not limited to this manner.
  • the first pixel is a polymer-polymerically stable vertical alignment pixel 120
  • the second pixel is a vertical alignment pixel 110, but the arrangement thereof is not limited to this manner.
  • the first pixel 110 is a main pixel
  • the second pixel 120 is a sub-pixel.
  • the first pixel 110 is a sub-pixel
  • the second pixel 120 is a main pixel.
  • the vertical alignment pixels 110 and the polymer-polymerically stable vertical alignment pixels 120 are arranged in a spaced or staggered configuration.
  • an array substrate 105 includes: a substrate having a display area and a wiring area; at least one active switch (not shown) disposed on the substrate; and a plurality of scan lines G1 - G6 and a plurality of data lines D1 - D12 are disposed on the substrate, the scan lines G1 - G6 are electrically connected to the control end of the active switch, and the data lines D1 - D12 are electrically connected to the active An input end of the switch; the plurality of pixel units 110, 120 are disposed in the display area, and are electrically connected to the output end of the active switch; wherein each pixel unit includes a first pixel and a second pixel, the pixel The unit includes a vertical alignment pixel 110 and a polymer-polymerized stable vertical alignment pixel 120; the pixel electrode of the vertical alignment pixel 110 and the pixel electrode of the polymer polymerization-stabilized vertical alignment pixel 120 are electrically coupled to the substrate;
  • the first pixel is
  • an array substrate 101 includes a substrate having a display area and a wiring area.
  • the plurality of pixel units 110 and 120 are disposed in the display area and electrically coupled to the corresponding data lines D1 to D12.
  • each of the plurality of pixel units 110, 120 includes a first pixel and a second pixel.
  • the first pixel is a vertical alignment pixel 110
  • the second pixel is a polymer polymerization stable vertical alignment pixel 120.
  • the first pixel 110 is a main pixel
  • the second pixel 120 is a sub-pixel
  • the polymerizable stable vertical alignment pixel 120 is electrically coupled to the scan line G2.
  • G4 and G6 the scanning lines G1, G3, G5, and G7 electrically coupled to the vertical alignment pixels 110 are different in electrical proximity.
  • a waveform 111 of scan lines G1 to G7 having a vertical light alignment pixel 110 and a polymer polymerization stable vertical alignment pixel 120 is shown.
  • an array substrate 102 includes a substrate having a display area and a wiring area.
  • the plurality of pixel units 110 and 120 are disposed in the display area and electrically coupled to the corresponding data lines D1 to D12.
  • each of the plurality of pixel units 110, 120 includes a first pixel and a second pixel.
  • the first pixel is a vertical alignment pixel 110
  • the second pixel is a polymer polymerization stable vertical alignment pixel 120.
  • the first pixel 110 is a main pixel
  • the second pixel 120 is a sub-pixel
  • the polymer-stabilized vertical alignment pixel 120 is electrically coupled to the data lines D1, D2, D5, D6, D9, and D10, and the vertical alignment pixel 110 is electrically connected.
  • the coupled data lines D3, D4, D7, D8, D11, and D12 have adjacent electrical properties that are different.
  • a waveform 112 of the scanning lines G1 G G7 having the vertical light alignment pixel 110 and the polymer polymerization stable vertical alignment pixel 120 is shown.
  • FIG. 5 is a schematic diagram of a pixel arrangement according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a pixel arrangement according to another embodiment of the present application
  • FIG. 7 is a schematic diagram of a pixel arrangement according to still another embodiment of the present application
  • FIG. 8 is still another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a pixel arrangement according to still another embodiment of the present application. Referring to FIG.
  • a display panel 500 includes: a substrate (not shown); and a color filter layer including a plurality of color resists (red color resist 510, green color resist 520, blue) a color resist 530), and the array substrate 101, 102 as described; wherein the color resist is disposed on the substrate or the array substrate 101, 102.
  • the color resistance includes a first color resistance (red color resistance 510), a second color resistance (green color resistance 520), and a third color resistance (blue color resistance 530). And wherein the color resistance is configured in one-to-one correspondence with the pixel unit 110.
  • a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel are disposed in the color filter layer 600, including: a red photoresist layer 610 and a green photoresist layer 620. And a blue photoresist layer 630.
  • a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel are applied to an array substrate 700 on a color filter layer on a substrate, including: a red array substrate 710. , a green array substrate 720 And a blue array substrate 730.
  • a display panel 800 includes: a substrate (not shown); and a color filter layer including a plurality of color resists (red color resist 810 , green color resist 820 , blue Color resist 830, white color resist 840), and array substrates 101, 102 as described; wherein the color resist is disposed on the substrate or the array substrates 101, 102.
  • a color filter layer including a plurality of color resists (red color resist 810 , green color resist 820 , blue Color resist 830, white color resist 840), and array substrates 101, 102 as described; wherein the color resist is disposed on the substrate or the array substrates 101, 102.
  • the color resistance includes a first color resistance (red color resistance 810), a second color resistance (green color resistance 820), and a third color resistance (blue color resistance 830). And a fourth color resistance (white color resistance 840), wherein the fourth color resistance (white color resistance 840) is corresponding to the second pixel area 120 of the pixel unit, the first color resistance (red color)
  • the resistor 810), the second color resist (green color resist 820) and the third color resist (blue color resist 830) are disposed corresponding to the first pixel region 110.
  • FIG. 10 is a block diagram of a display panel according to an embodiment of the present application.
  • a display panel 109 includes: an array substrate 105, including: a substrate 106 having a display area and a wiring area; at least one active switch (not shown) disposed on On the substrate 106, a plurality of scan lines G1 G G6 and a plurality of data lines D1 D D12 are disposed on the substrate 106, and the scan lines G1 G G6 are electrically connected to the control end of the active switch.
  • the data lines D1 - D12 are electrically connected to the input end of the active switch; the plurality of pixel units 110, 120 are disposed in the display area, and are electrically connected to the output end of the active switch; wherein each pixel unit includes a first pixel and a second pixel, wherein the pixel unit includes a vertical alignment pixel 110 and a polymer polymerization stable vertical alignment pixel 120; a pixel electrode of the vertical alignment pixel 110 and the polymer polymerization stable vertical alignment pixel 120
  • the pixel electrodes are electrically coupled to the substrate; the pair of substrates 107 are disposed opposite the array substrate 105; and the color filter layer 108 includes a plurality of color resists; wherein the color filter layer 108 Configured in the pair On the substrate 107 or the array substrate 105.
  • a vertical light alignment pixel and a polymer polymerization stable vertical alignment pixel are applied to the color filter layer 900 in red, green, and white, including: a red photoresist layer 910.
  • the application of the present application can solve the problem of the display panel's large-view role bias, and enhance product competitiveness and consumer satisfaction.

Abstract

一种阵列基板(105)及其显示面板(109)，阵列基板(105)包括：一基底(106)，具有显示区及布线区；至少一主动开关，设置于此基底(106)上；多条扫描线(G1~G6)和多条数据线(D1~D12)，设置于此基底(106)上，此扫描线(G1~G6)电连接于此主动开关的控制端，此数据线(D1~D12)电连接于此主动开关的输入端；多个画素单元(110、120)，配置于此显示区，与此主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，此画素单元包括垂直配向画素(110)与高分子聚合稳定型垂直配向画素(120)；此垂直配向画素(110)的画素电极与此高分子聚合稳定型垂直配向画素(120)的画素电极分别电性耦接此基底(106)；且将可解决液晶显示面板(109)色偏问题及提升画素开口率与穿透率。

Description

阵列基板及其显示面板 技术领域
本申请涉及一种画素设计的方法，特别是涉及一种阵列基板及其显示面板。
背景技术
液晶显示面板通常是由一彩膜基板(Color Filter，CF)、一主动开关阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模块的光线折射出来产生画面。按照液晶的取向方式不同，目前主流市场上的液晶显示面板可以分为以下几种类型：垂直配向(Vertical Alignment，VA)型、扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型、平面转换(In-Plane Switching，IPS)型及边缘场开关(Fringe Field Switching，FFS)型。
所述垂直配向型(Vertical Alignment，VA)模式的液晶显示，例如图形垂直配向型(Patterned Vertical Alignment，PVA)液晶显示器或多区域垂直配向型(Multi-domain Vertical Alignment，MVA)液晶显示器，其中PVA型利用边缘场效应与补偿板达到广视角的效果。MVA型将一个画素分成多个区域，并使用突起物(Protrusion)或特定图案结构，使位于不同区域的液晶分子朝向不同方向倾倒，以达到广视角且提升穿透率的作用。
而液晶显示器目前是市场上运用最为广泛的显示器，特别是广泛应用在液晶电视上。随着分辨率的逐步提升，画素的尺寸会越来越小，开口率也越来越小，大尺寸产品在观看的时候可观看的角度比较多，因此在大视角的时候会面临色偏的现象。
以往在解决大视角色偏的时候，在设计上会有主画素(main pixel)和次画素(sub pixel)通过调低次画素(sub pixel)的电压，将4个区域(4domain)变为8个区域(8domain)来改善视角。这种设计一般都有3个或3个以上的主动开关来控制。
但是这种设计在随着分辨率越来越高，画素越来越小，主动开关占据的空间会越来越大，导致开口率变小。所以大尺寸高分辨率的产品为了获得高的开口率逐渐恢复4个区域(4domian)的设计，然后通过电学算法来改善视角，但是这种改善的方法会造成一些显示上的问题。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种画素设计的方法，特别是涉及一种阵列基板及其应用于显示面板，不仅可以有效解决色偏问题，同时可有效改善大尺寸高分辨率产品的视 角，提升大尺寸高分辨率产品的穿透率。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种阵列基板，包括：一基底，具有显示区及布线区；至少一主动开关，设置于所述基底上；多条扫描线和多条数据线，设置于所述基底上，所述扫描线电连接于所述主动开关的控制端，所述数据线电连接于所述主动开关的输入端；多个画素单元，配置于所述显示区，与所述主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素与高分子聚合稳定型垂直配向画素；所述垂直配向画素的画素电极与所述高分子聚合稳定型垂直配向画素的画素电极分别电性耦接所述基底。
本申请的目的及解决其技术问题还可采用以下技术措施进一步实现。
本申请的另一目的为一种阵列基板，包括：一基底，具有显示区及布线区；至少一主动开关，设置于所述基底上；多条扫描线和多条数据线，设置于所述基底上，所述扫描线电连接于所述主动开关的控制端，所述数据线电连接于所述主动开关的输入端；多个画素单元，配置于所述显示区，与所述主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素与高分子聚合稳定型垂直配向画素；所述垂直配向画素的画素电极与所述高分子聚合稳定型垂直配向画素的画素电极分别电性耦接所述基底；所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为阵列式排列；所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为矩形形状。
本申请的又一目的为一种显示面板，包括：一对向基板，与所述阵列基板对向设置；一彩色滤光层，包括多个色阻；以及如所述的阵列基板；其中，所述彩色滤光层配置于所述对向基板或所述阵列基板上。
本申请的的一实施例中，所述多个画素单元中，每一画素单元包括第一画素及第二画素。
在本申请的一实施例中，所述第一画素为垂直配向画素，所述第二画素为高分子聚合稳定型垂直配向画素。
在本申请的一实施例中，所述第一画素为高分子聚合稳定型垂直配向画素，所述第二画素为垂直配向画素。
在本申请的一实施例中，所述第一画素为主画素，所述第二画素为子画素；或所述第一画素为子画素，所述第二画素为主画素。
在本申请的一实施例中，所述高分子聚合稳定型垂直配向画素电性耦接的数据线，与所述垂直配向画素电性耦接的扫描线，其相邻电性为相异。
在本申请的一实施例中，所述高分子聚合稳定型垂直配向画素电性耦接的扫描线，与所述垂直 配向画素电性耦接的扫描线，其相邻电性为相异。
在本申请的一实施例中，所述垂直配向画素与所述高分子聚合稳定型垂直配向画素为间隔配置或交错配置。
本申请的将可解决液晶显示面板色偏问题及提升画素开口率与穿透率。
附图说明
图1a是范列性的8区域画素设计示意图。
图1b是范列性的为了解决色偏问题的液晶画素电路图。
图2是本申请一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素排列示意图。
图2a是本申请另一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素排列示意图。
图3a是本申请一实施例的扫描线波形示意图。
图3b是本申请一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素控制驱动示意图。
图4a是本申请另一实施例的扫描线波形示意图。
图4b是本申请另一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素控制驱动示意图。
图5是本申请一实施例的画素排列示意图。
图6是本申请另一实施例的画素排列示意图。
图7是本申请再一实施例的画素排列示意图。
图8是本申请又一实施例的画素排列示意图。
图9是本申请又一再一实施例的画素排列示意图。
图10是本申请一实施例的显示面板模块图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于 描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种阵列基板及其显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的显示面板可包括一LCD(Liquid Crystal Display)面板包括：开关阵列(thin film transistor，TFT)基板、彩色滤光层(color filter，CF)基板与形成于两基板之间的液晶层或为一OLED(Organic Light-Emitting Diode)面板或一QLED(Quantum Dots Light-Emitting Diode)面板。
在一实施例中，本申请的显示面板可为曲面型显示面板。
在一实施例中，本申请的开关阵列(TFT)及彩色滤光层(CF)可形成于同一基板上。
图1a是范列性的8区域画素设计示意图及图1b为范列性的为了解决色偏问题的液晶画素电路图。在液晶显示器中，使画素中的多个电容在彼此之间进行电荷分享，是一种为了解决色偏问题而衍生出来的技术。请参照图1b，在图1b所示的液晶画素电路中，主画素受到扫描线G1的控制，利用晶体管T1从数据线D1取得数据并储存到储存电容Cst1之中；而子画素除了同样受到扫描线G1的控制，利用晶体管T2从数据线D1取得数据并储存到储存电容Cst2之外，还进一步受到扫描线G2的控制，以利用晶体管T3使储存电容Cst2与储存电容Cst3进行电荷分享。藉由此种架构，图1所示的液晶画素电路可以适当控制储存电容Cst1与储存电容Cst2所储存电压的比例，以藉此使液晶电容C1c1与C1c2受到默认的电压驱动，进而得以消除显示时的色偏问题。然而，随着技术的更新，液晶显示器无论在分辨率或画面更新频率上也都随之提高。如此一来，无论是因为分辨率的增加而使得在同样的时间中必须更新更多画素电路中的数据也好，或者是因为画面更新频率的增加而使得必须在更短的时间内更新旧有数量的画素电路中的数据也好，甚或在分辨率与画面更新频率一起增加的状况下使得必须在更短的时间内更新更多画素电路中的数据也好，总之对于每一个画素电路来说，在将数据线D1上的数据储存至储存电容Cst1与Cst2时所能使用的充电时间都会因此减少。一旦画素电路所能使用的充电时间减少，那么储存电容Cst1与Cst2就可能无法被完全充饱，随之而来的就是储存电容Cst1与Cst2的储存电压未必能达至相同的水平。一旦储存电容Cst1与Cst2的储存电压不一样，那么当储存电容Cst2与储存电容Cst3共享电荷之后，由储存电容Cst2所维持的电压与由储存电容Cst1所维持的电压之间的比值也就无法达到原先设定的比例，因此原本想要消除的色偏 问题将再度出现在显示过程中。
请参照图1a，一种解决大视角色偏的画素结构10，在设计上会有主画素(main pixel)和次画素(sub pixel)通过调低次画素(sub pixel)的电压，将4个区域(4domain)变为8个区域(8domain)来改善视角。
图2为本申请一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素排列示意图。请参照图1b及图2，一种画素结构单元100，包括：扫描线G1～G7，用于提供扫描讯号；数据线D1～D12，用于提供数据讯号，所述数据线D1～D12与所述扫描线G1～G7定义出至少一个画素区110、120；开关晶体管T1、T2、T3，电性连接所述扫描线G1、G2与所述数据线D1，并在第一时间段内且在所述扫描讯号的控制下传输所述数据讯号，所述第一时间段对应所述画素结构单元100的数据加载模式；以及存储电容Cst1、Cst2、Cst3，具有第一连接端101a、201a、301a与第二连接端，所述第一连接端101a、201a、301a电性连接所述开关晶体管T1、T2、T3，用于在第一时间段接收所述数据讯号；其中所述画素区110、120可为一垂直光配向画素110或一高分子聚合稳定型垂直配向画素120。
在一实施例中，所述扫描线G1～G7控制垂直光配向画素110和高分子聚合稳定型垂直配向画素120的电压值。
在一实施例中，所述垂直光配向画素110的铟锡氧化物不与所述高分子聚合稳定型垂直配向画素120的铟锡氧化物连接，避免液晶倒向混乱。
图2a是本申请另一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素排列示意图。请参照图2a，一种阵列基板105，包括：一基底，具有显示区及布线区；至少一主动开关(图未示)，设置于所述基底上；多条扫描线G1～G6和多条数据线D1～D12，设置于所述基底上，所述扫描线G1～G6电连接于所述主动开关的控制端，所述数据线D1～D12电连接于所述主动开关的输入端；多个画素单元110、120，配置于所述显示区，与所述主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120；所述垂直配向画素110的画素电极与所述高分子聚合稳定型垂直配向画素120的画素电极分别电性耦接所述基底。
请参照图2a，一种阵列基板105，包括：一基底，具有显示区及布线区；多个画素单元110、120，配置于所述显示区，分别电性耦接对应的数据线D1～D12与扫描线G1～G6；其中，每一画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120中至少其一者。
请参照图2a，在一实施例中，所述多个画素单元110、120中，每一画素单元包括第一画素及第二画素。
请参照图2a，在一实施例中，所述第一画素为垂直配向画素110，所述第二画素为高分子聚合稳定型垂直配向画素120，但其排列不限于此方式。
请参照图2a，在一实施例中，所述第一画素为高分子聚合稳定型垂直配向画素120，所述第二画素为垂直配向画素110，但其排列不限于此方式。
请参照图2a，在一实施例中，所述第一画素110为主画素，所述第二画素120为子画素。亦可以是，所述第一画素110为子画素，所述第二画素120为主画素。
请参照图2a，在一实施例中，所述垂直配向画素110与所述高分子聚合稳定型垂直配向画素120为间隔配置或交错配置。
请参照图2a，在一实施例中，一种阵列基板105，包括：一基底，具有显示区及布线区；至少一主动开关(图未示)，设置于所述基底上；多条扫描线G1～G6和多条数据线D1～D12，设置于所述基底上，所述扫描线G1～G6电连接于所述主动开关的控制端，所述数据线D1～D12电连接于所述主动开关的输入端；多个画素单元110、120，配置于所述显示区，与所述主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120；所述垂直配向画素110的画素电极与所述高分子聚合稳定型垂直配向画素120的画素电极分别电性耦接所述基底；所述第一画素为垂直配向画素110，所述第二画素为高分子聚合稳定型垂直配向画素120；所述第一画素为高分子聚合稳定型垂直配向画素120，所述第二画素为垂直配向画素110；所述垂直配向画素110和所述高分子聚合稳定型垂直配向画素120为阵列式排列；所述垂直配向画素110和所述高分子聚合稳定型垂直配向画素120为矩形形状；所述垂直配向画素110和所述高分子聚合稳定型垂直配向画素120为间隔交叉配置。
图3a为本申请一实施例的扫描线波形示意图及图3b为本申请一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素控制驱动示意图。请参照图3b，一种阵列基板101，包括：一基底，具有显示区及布线区；多个画素单元110、120，配置于所述显示区，分别电性耦接对应的数据线D1～D12与扫描线G1～G7；其中，每一画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120中至少其一者。
请参照图3b，在一实施例中，所述多个画素单元110、120中，每一画素单元包括第一画素及第二画素。
请参照图3b，在一实施例中，所述第一画素为垂直配向画素110，所述第二画素为高分子聚合稳定型垂直配向画素120。
请参照图3b，在一实施例中，所述第一画素110为主画素，所述第二画素120为子画素。
请参照图3b，在一实施例中，所述高分子聚合稳定型垂直配向画素120电性耦接的扫描线G2、 G4、G6，与所述垂直配向画素110电性耦接的扫描线G1、G3、G5、G7，其相邻电性为相异。
请参照图3a及图3b，在一实施例中，一种具有垂直光配向画素110及高分子聚合稳定型垂直配向画素120的扫描线G1～G7波形111。
图4a为本申请另一实施例的扫描线波形示意图及图4b为本申请另一实施例的具有垂直光配向画素及高分子聚合稳定型垂直配向画素控制驱动示意图。请参照图4b，一种阵列基板102，包括：一基底，具有显示区及布线区；多个画素单元110、120，配置于所述显示区，分别电性耦接对应的数据线D1～D12与扫描线G1～G7；其中，每一画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120中至少其一者。
请参照图4b，在一实施例中，所述多个画素单元110、120中，每一画素单元包括第一画素及第二画素。
请参照图4b，在一实施例中，所述第一画素为垂直配向画素110，所述第二画素为高分子聚合稳定型垂直配向画素120。
请参照图4b，在一实施例中，所述第一画素110为主画素，所述第二画素120为子画素。
请参照图4b，在一实施例中，所述高分子聚合稳定型垂直配向画素120电性耦接的数据线D1、D2、D5、D6、D9、D10，与所述垂直配向画素110电性耦接的数据线D3、D4、D7、D8、D11、D12，其相邻电性为相异。
请参照图4a及图4b，在一实施例中，一种具有垂直光配向画素110及高分子聚合稳定型垂直配向画素120的扫描线G1～G7波形112。
图5为本申请一实施例的画素排列示意图、图6为本申请另一实施例的画素排列示意图、图7为本申请再一实施例的画素排列示意图、图8为本申请又一实施例的画素排列示意图及图9为本申请又一再一实施例的画素排列示意图。请参照图5，本申请一实施例中，一种显示面板500，包括：一基板(图未示)；彩色滤光层，包括多个色阻(红色色阻510、绿色色阻520、蓝色色阻530)，以及如所述的阵列基板101、102；其中所述色阻配置于所述基板或所述阵列基板101、102上。
请参照图2及图5，在一实施例中，所述色阻包括第一色阻(红色色阻510)，第二色阻(绿色色阻520)及第三色阻(蓝色色阻530)，其中，所述色阻与所述画素单元110一一对应配置。
请参照图6，本申请一实施例中，一种具有垂直光配向画素及高分子聚合稳定型垂直配向画素在彩色滤光层600，包括：一红色光阻层610、一绿色光阻层620及一蓝色光阻层630。
请参照图7，本申请一实施例中，一种具有垂直光配向画素及高分子聚合稳定型垂直配向画素适用于在彩色滤光层在基板上的阵列基板700，包括：一红色阵列基板710、一绿色阵列基板720 及一蓝色阵列基板730。
请参照图8，本申请一实施例中，一种显示面板800，包括：一基板(图未示)；彩色滤光层，包括多个色阻(红色色阻810、绿色色阻820、蓝色色阻830、白色色阻840)，以及如所述的阵列基板101、102；其中所述色阻配置于所述基板或所述阵列基板101、102上。
请参照图2及图8，在一实施例中，所述色阻包括第一色阻(红色色阻810)，第二色阻(绿色色阻820)，第三色阻(蓝色色阻830)及第四色阻(白色色阻840)，其中，所述第四色阻(白色色阻840)与所述画素单元的第二画素区120对应配置，所述第一色阻(红色色阻810)，所述第二色阻(绿色色阻820)及所述第三色阻(蓝色色阻830)与所述第一画素区110对应配置。
图10是本申请一实施例的显示面板模块图。请参照图10，在一实施例中，一种显示面板109，包括：一种阵列基板105，包括：一基底106，具有显示区及布线区；至少一主动开关(图未示)，设置于所述基底106上；多条扫描线G1～G6和多条数据线D1～D12，设置于所述基底106上，所述扫描线G1～G6电连接于所述主动开关的控制端，所述数据线D1～D12电连接于所述主动开关的输入端；多个画素单元110、120，配置于所述显示区，与所述主动开关的输出端电性连接；其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素110与高分子聚合稳定型垂直配向画素120；所述垂直配向画素110的画素电极与所述高分子聚合稳定型垂直配向画素120的画素电极分别电性耦接所述基底；一对向基板107，与所述阵列基板105对向设置；以及一彩色滤光层108，包括多个色阻；其中，所述彩色滤光层108配置于所述对向基板107或所述阵列基板105上。
请参照图9，本申请一实施例中，一种具有垂直光配向画素及高分子聚合稳定型垂直配向画素适用于在红绿蓝白色在彩色滤光层900，包括：一红色光阻层910、一绿色光阻层920、一蓝色光阻层930及一白色光阻层940。
本申请的将可解决显示面板大视角色偏问题，提升产品竞争力及消费者满意度。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    一基底，具有显示区及布线区；
    至少一主动开关，设置于所述基底上；
    多条扫描线和多条数据线，设置于所述基底上，所述扫描线电连接于所述主动开关的控制端，所述数据线电连接于所述主动开关的输入端；
    多个画素单元，配置于所述显示区，与所述主动开关的输出端电性连接；
    其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素与高分子聚合稳定型垂直配向画素；所述垂直配向画素的画素电极与所述高分子聚合稳定型垂直配向画素的画素电极分别电性耦接所述基底。
  2. 如权利要求1所述的阵列基板，其中，所述第一画素为垂直配向画素。
  3. 如权利要求1所述的阵列基板，其中，所述第二画素为高分子聚合稳定型垂直配向画素。
  4. 如权利要求1所述的阵列基板，其中，所述第一画素为高分子聚合稳定型垂直配向画素。
  5. 如权利要求1所述的阵列基板，其中，所述第二画素为垂直配向画素。
  6. 如权利要求1所述的阵列基板，其中，所述第一画素为主画素。
  7. 如权利要求1所述的阵列基板，其中，所述第二画素为子画素。
  8. 如权利要求1所述的阵列基板，其中，所述第一画素为子画素。
  9. 如权利要求1所述的阵列基板，其中，所述第二画素为主画素。
  10. 如权利要求1所述的阵列基板，其中，所述高分子聚合稳定型垂直配向画素电性耦接的数据线，与所述垂直配向画素电性耦接的数据线，其相邻电性为相异。
  11. 如权利要求1所述的阵列基板，其中，所述高分子聚合稳定型垂直配向画素电性耦接的扫描线，与所述垂直配向画素电性耦接的扫描线，其相邻电性为相异。
  12. 如权利要求1所述的阵列基板，其中，所述垂直配向画素与所述高分子聚合稳定型垂直配向画素为间隔配置。
  13. 如权利要求1所述的阵列基板，其中，所述垂直配向画素与所述高分子聚合稳定型垂直配向画素为交错配置。
  14. 如权利要求1所述的阵列基板，其中，所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为阵列式排列。
  15. 如权利要求1所述的阵列基板，其中，所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为矩形形状。
  16. 一种阵列基板，包括：
    一基底，具有显示区及布线区；
    至少一主动开关，设置于所述基底上；
    多条扫描线和多条数据线，设置于所述基底上，所述扫描线电连接于所述主动开关的控制端，所述数据线电连接于所述主动开关的输入端；
    多个画素单元，配置于所述显示区，与所述主动开关的输出端电性连接；
    其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素与至少一个高分子聚合稳定型垂直配向画素；所述垂直配向画素的画素电极与所述高分子聚合稳定型垂直配向画素的画素电极之间未电性连接；所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为阵列式排列；所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为矩形形状；所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为间隔交叉配置。
  17. 一种显示面板，包括：
    一阵列基板，包括：
    一基底，具有显示区及布线区；
    至少一主动开关，设置于所述基底上；
    多条扫描线和多条数据线，设置于所述基底上，所述扫描线电连接于所述主动开关的控制端，所述数据线电连接于所述主动开关的输入端；
    多个画素单元，配置于所述显示区，与所述主动开关的输出端电性连接；
    其中，每一画素单元包括第一画素及第二画素，所述画素单元包括垂直配向画素与高分子聚合稳定型垂直配向画素；所述垂直配向画素的画素电极与所述高分子聚合稳定型垂直配向画素的画素电极分别电性耦接所述基底；
    一对向基板，与所述阵列基板对向设置；以及
    一彩色滤光层，包括多个色阻；
    其中，所述彩色滤光层配置于所述对向基板或所述阵列基板上。
  18. 如权利要求17所述的显示面板，其中，所述第一画素为垂直配向画素，所述第二画素为高分子聚合稳定型垂直配向画素。
  19. 如权利要求17所述的显示面板，其中，所述第一画素为高分子聚合稳定型垂直配向画素，所述第二画素为垂直配向画素。
  20. 如权利要求17所述的显示面板，其中，所述垂直配向画素和所述高分子聚合稳定型垂直配向画素为间隔交叉配置。
PCT/CN2017/107025 2017-09-19 2017-10-20 阵列基板及其显示面板 WO2019056441A1 (zh)

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