WO2020001037A1 - 阵列基板及其驱动方法、显示面板 - Google Patents

阵列基板及其驱动方法、显示面板 Download PDF

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Publication number
WO2020001037A1
WO2020001037A1 PCT/CN2019/075026 CN2019075026W WO2020001037A1 WO 2020001037 A1 WO2020001037 A1 WO 2020001037A1 CN 2019075026 W CN2019075026 W CN 2019075026W WO 2020001037 A1 WO2020001037 A1 WO 2020001037A1
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Prior art keywords
sub
circuit
pixel
gate
driving
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PCT/CN2019/075026
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English (en)
French (fr)
Inventor
丛宁
玄明花
岳晗
杨明
陈小川
张粲
王灿
陈亮
赵德涛
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/610,007 priority Critical patent/US11315479B2/en
Publication of WO2020001037A1 publication Critical patent/WO2020001037A1/zh
Priority to US17/652,660 priority patent/US11869413B2/en

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a driving method thereof, and a display panel.
  • micro LEDs Compared with organic light emitting diodes (OLEDs), micro LEDs have the advantages of being completely solid, with a long life, and light emitting materials that are not easily affected by the external environment and are relatively stable.
  • micro LEDs which use micro LEDs with different light emission colors
  • the light emission efficiency of these micro LEDs with different light emission colors is also different, thereby affecting the display effect of the display screen.
  • An embodiment of the present disclosure provides an array substrate.
  • the array substrate includes a plurality of pixel units arranged in a matrix, and each of the pixel units includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel having different light emission colors.
  • a first sub-pixel in each row of the plurality of pixel units arranged in a matrix is electrically connected to a first one of the plurality of first grid lines, and each row of the plurality of pixel units arranged in a matrix
  • the second sub-pixel and the third sub-pixel in the pixel unit are each electrically connected to a second gate line of the plurality of second gate lines.
  • the plurality of first gate lines includes at least one gate line group, each gate line group includes at least two adjacent first gate lines, and each of the first gate lines in each gate line group The lines are configured to receive the same scan signal.
  • each of the first, second, and third sub-pixels includes a light-emitting device and a pixel circuit that controls the light-emitting device to emit light.
  • the pixel circuit includes a first gating sub-circuit, a gray-scale control sub-circuit, and a driving sub-circuit.
  • the gray-scale control sub-circuit is electrically connected, and the first gating sub-circuit is configured to transmit a data voltage output from the data line under the control of a scanning signal transmitted by the first gate line or the second gate line.
  • the driving sub-circuit is electrically connected to a first working voltage terminal, a second voltage terminal, and the gray-scale control sub-circuit.
  • the driving sub-circuit is configured to be controlled by a second voltage output from the second voltage terminal.
  • the light emitting device provides a constant driving current.
  • the gray-scale control sub-circuit is also electrically connected to the light-emitting device and the driving sub-circuit, and the gray-scale control sub-circuit is configured to control the duration of the driving current flowing through the light-emitting device according to the data voltage.
  • the array substrate further includes a plurality of third gate lines corresponding to each row of pixel units of the plurality of pixel units arranged in the matrix, wherein the pixel circuit further includes a second gating sub-circuit.
  • the second gating sub-circuit is electrically connected to the second voltage terminal, the driving sub-circuit, and a third gate line of the plurality of gate lines, and the second gating sub-circuit is configured The second voltage is transmitted to the driving sub-circuit under the control of a control signal transmitted by the third gate line.
  • the first gating sub-circuit includes a first transistor, a gate of the first transistor is electrically connected to the first gate line or a second gate line, and a first electrode is electrically connected to the data line.
  • the two poles are electrically connected to the grayscale control sub-circuit.
  • the gray-scale control sub-circuit includes a second transistor, a gate of the second transistor is electrically connected to the first gating sub-circuit, a first pole is electrically connected to the driving sub-circuit, and a second pole is electrically The light emitting device is connected.
  • the driving sub-circuit includes a driving transistor, a gate of the driving transistor is electrically connected to the second voltage terminal, a first electrode is electrically connected to the first working voltage terminal, and a second electrode is electrically connected to the gray voltage.
  • Order control sub-circuit includes a driving transistor, a gate of the driving transistor is electrically connected to the second voltage terminal, a first electrode is electrically connected to the first working voltage terminal, and a second electrode is electrically connected to the gray voltage.
  • the second gating sub-circuit includes a third transistor, a gate of the third transistor is electrically connected to the third gate line, a first electrode is electrically connected to the second voltage terminal, and a second electrode is electrically Connect the driving sub-circuit.
  • the light emitting device includes a micro light emitting diode, a first terminal of the micro light emitting diode is electrically connected to the grayscale control sub-circuit, and a second terminal of the micro light emitting diode is electrically connected to a reference voltage terminal.
  • the array substrate includes a gate driving circuit
  • the gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit, wherein the first gate driving sub-circuit and the A plurality of first gate lines are electrically connected to provide a first scan signal to the plurality of first gate lines; the second gate driving sub-circuit is electrically connected to the plurality of second gate lines to provide the The plurality of second gate lines provide a second scan signal.
  • the plurality of first gate lines includes at least one gate line group, and each gate line group includes at least two adjacent first gate lines.
  • the first gate driving sub-circuit includes a plurality of cascaded first shift registers, and each shift register is electrically connected to a gate line group to simultaneously provide each first gate line in the gate line group.
  • a first scan signal the second gate driving sub-circuit includes a plurality of cascaded second shift registers, each second shift register is electrically connected to a second gate line to provide a second gate line Scan signal.
  • the luminous efficiency of the first sub-pixel is lower than the second sub-pixel and the third sub-pixel.
  • Another embodiment of the present disclosure provides a display panel including the array substrate according to any one of the foregoing embodiments.
  • Yet another embodiment of the present disclosure provides a driving method for an array substrate according to any one of the foregoing embodiments, the driving method including: sequentially driving each of the plurality of first gate lines to a first The gate line provides a first scan signal, and simultaneously provides a second scan signal to each of the plurality of second gate lines in sequence.
  • the plurality of first gate lines includes a plurality of gate line groups, and each gate line group includes N adjacent first gate lines, where N is an integer greater than or equal to 2, at this time, the Providing a first scan signal to each of the plurality of first gate lines in sequence includes: sequentially providing a first scan signal to each of the plurality of gate line groups, to each Providing the first scan signal by a gate line group includes: simultaneously providing the first scan signal to N of the first gate lines in the gate line group.
  • the duration of the effective level of the second scan signal is 1 / N of the duration of the effective level of the first scan signal.
  • each of the first subpixel, the second subpixel, and the third subpixel includes a light emitting device and a pixel circuit that controls the light emitting device to emit light
  • the pixel circuit includes a first gate.
  • a sub-circuit, a gray-scale control sub-circuit, and a driving sub-circuit, the driving method includes: a first scanning signal or a second scanning signal transmitted by the first gating sub-circuit on the first gate line or the second gate line Transmitting the data voltage output from the data line to the gray-scale control sub-circuit; the driving sub-circuit generates a constant driving current provided to the light-emitting device; and the gray-scale control sub-circuit according to the data The voltage controls the duration of the driving current flowing through the light emitting device.
  • the array substrate further includes a plurality of third gate lines corresponding to each row of pixel units of the plurality of pixel units arranged in the matrix
  • the pixel circuit further includes a second gating sub-circuit.
  • a gating sub-circuit is electrically connected to a third gate line, a second voltage terminal, and the driving sub-circuit of the plurality of third gate lines, wherein the driving method further includes: Before the circuit transmits the data voltage output from the data line to the gray-level control sub-circuit, the second gating sub-circuit is under the control of a control signal transmitted by a third gate line among the plurality of third gate lines. Transmitting the second voltage output from the second voltage terminal to the driving sub-circuit to start the driving sub-circuit to generate the driving current.
  • the duration of the effective level of the first scan signal is greater than the duration of the effective level of the second scan signal.
  • FIG. 1 is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure
  • FIG. 2 is a schematic timing diagram of a scanning signal used in the array substrate of the embodiment shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic timing diagram of a scan signal used in the array substrate of the embodiment shown in FIG. 3;
  • FIG. 5 is a schematic timing diagram of a scan signal according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a pixel circuit provided according to some embodiments of the present disclosure.
  • FIG. 7 is a graph showing a relationship between current density and luminous efficiency of a MicroLED according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a driving method for an array substrate according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a specific structure of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a specific structure of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 12 is a schematic signal timing diagram of a control signal transmitted by a third gate line and a scan signal of the first or second gate line according to another embodiment of the present disclosure
  • FIG. 13 schematically illustrates a waveform diagram of a data signal for grayscale adjustment of a single sub-pixel provided according to another embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.
  • FIG. 1 illustrates a schematic diagram of an array substrate provided according to an embodiment of the present disclosure.
  • the array substrate 01 includes a plurality of pixel units 10 arranged in a matrix, and each pixel unit 10 includes at least a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 having different light emission colors.
  • the application does not limit the color of the light emitted by the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103.
  • the first sub-pixel 101 and the second sub-pixel in the same pixel unit 10 After the lights emitted by 102 and the third sub-pixel 103 are mixed, the pixel unit 10 emits white light.
  • the light emission efficiency of the first sub-pixel is lower than that of the second sub-pixel and the third sub-pixel.
  • the first sub-pixel 101 emits red light (R)
  • the second sub-pixel 102 emits green light (G)
  • the third sub-pixel 103 emits blue light (B).
  • the first subpixel, the second subpixel, and the third subpixel mentioned herein are not limited thereto.
  • the first sub-pixel may be any sub-pixel having a lower or higher luminous efficiency than the R sub-pixel
  • the second sub-pixel and the third sub-pixel may also be any sub-pixels having different luminous efficiencies than the G sub-pixel and the B sub-pixel, respectively Pixels.
  • the luminous efficiency of the first subpixel, the second subpixel, and the third subpixel in the array substrate may be completely different from each other, or may be partially the same.
  • any two of the first subpixel, the second subpixel, and the third subpixel have the same light emission efficiency, but are different from the light emission efficiency of the remaining one subpixel.
  • the array substrate further includes a plurality of first gate lines G1, G2, G3,... Corresponding to each row of pixel units of the plurality of pixel units arranged in a matrix, and a plurality of pixels arranged in a matrix.
  • a first sub-pixel in each row of pixel units in the plurality of pixel units arranged in a matrix is electrically connected to a first gate line
  • a second sub-pixel in each row of pixel units in the plurality of pixel units arranged in a matrix and The third sub-pixels are all electrically connected to the second gate line.
  • the array substrate mentioned herein includes, but is not limited to, an organic light emitting diode (OLED) array substrate, an LED array substrate, an array substrate in a liquid crystal display device, and the like.
  • OLED organic light emitting diode
  • the following method can be used to drive the array substrate for image display:
  • the first gate line G and the second gate line S of the row pixel unit 10 respectively provide a first scanning signal and a second scanning signal. As shown in FIG. 2, the duration T1 of the effective level of the first scanning signal is greater than the second scanning signal. Duration of the active level T2.
  • the light-emitting time of the first sub-pixel 101 in the same row of pixel units 10 can be made longer than the light-emitting time of the second and third sub-pixels 102 and 103, so that the light-emitting efficiency of the first sub-pixel 101 can be reduced.
  • the light emission time is extended to compensate the light emission brightness of the first sub-pixel 101, so that the light emission brightness of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are the same or approximately the same, thereby improving the display effect.
  • the following method may be used to drive the array substrate for image display: to the first electrically connected to the same row of pixel units 10
  • the gate lines G and the second gate lines S respectively provide a first scan signal and a second scan signal, and the duration of the effective level of the second scan signal is greater than the duration of the effective level of the first scan signal.
  • the light emission time of the second sub-pixel 102 and the third sub-pixel 103 in the pixel unit 10 in the same row can be made longer than the light-emitting time of the first sub-pixel 101, so that the second and third sub-pixels 101 with low light-emitting efficiency can be
  • the light emission brightness of the first sub-pixel 101 is compensated so that the light emission brightness of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are the same or approximately the same, thereby improving the display effect.
  • the plurality of first grid lines respectively corresponding to each row of pixel units in the plurality of pixel units arranged in a matrix include at least one grid line group, and each grid line group includes at least two adjacent grid lines.
  • a grid line, and each first grid line in each grid line group is configured to receive the same scan signal.
  • two gate line groups 20 are schematically shown, and each gate line group includes two adjacent first gate lines, that is, the first gate line G1 corresponding to the first row of pixel units.
  • the first gate lines included in any two different gate line groups are different from each other, that is, any one first gate line does not belong to more than two gate line groups at the same time.
  • all the first gate lines G in each gate line group 20 receive the same scan signal at the same time.
  • all the first gate lines G in each of the gate line groups 20 receive the above-mentioned first scanning signal at the same time.
  • all the first gate lines G in the same gate line group 20 can be scanned at the same time, and the first sub-pixels 101 electrically connected to each of the first gate lines G in the same gate line group 20 are turned on at the same time. And emit light for the same duration.
  • the N first gate lines G in a gate line group 20 can be provided with the above-mentioned first scanning signal (for example, the duration of its effective level is T1), N ⁇ 2, and N is a positive integer at the same time.
  • a second scan signal is sequentially provided to the N second gate lines S corresponding to the pixel units of each row of the N first gate lines G respectively electrically connected.
  • the second sub-pixels 102 and the third sub-pixels 103 electrically connected to the N second gate lines S are turned on row by row, and each of the first sub-pixels 101 electrically connected to the N first gate lines G is respectively opened.
  • the on state can be kept in the above-mentioned time period T1.
  • the light emission duration of the first sub-pixel 101 electrically connected to the first gate line in the gate line group 20 can be the second sub-pixel 102 and the third sub-pixel 103 in the same row as the first sub-pixel 101. N times the light emission duration.
  • the first scanning signal can be provided in the following manner to drive each pixel unit to display: sequentially supplying the first scanning signal to the plurality of gate line groups 20, that is, using the first scanning signal to each gate line group 20 Perform a scan by group.
  • the first gate lines G1 in the first row (L1) and the first gate lines G2 in the second row (L2) form two first lines in a gate line group 20 as shown in FIG. 3.
  • the gate lines G1 and G2 provide a first scan signal Scan_1_R as shown in FIG. 4.
  • the first gate line G3 in the third row (L3) and the first gate line G4 in the fourth row (L4) shown in FIG. 3 constitute two first gate lines G3 in a gate line group 20, G4 provides the above-mentioned first scan signal Scan_2_R, as shown in FIG. 4.
  • the scanning method of the subsequent raster line groups 20 is the same as described above.
  • the first scanning signals may be simultaneously provided to the N first gate lines G in the gate line group 20.
  • the first gate line G1 in the first row (L1) and the first gate line G2 in the second row (L2) are simultaneously provided with the first scan signal Scan_1 as shown in FIG. 4.
  • the first sub-pixels 101 in the first and second rows emit red light (R).
  • a second scan signal Scan_2 is sequentially provided to the N second gate lines G corresponding to the N rows of pixel units electrically connected to the N first gate lines G.
  • a second scan signal Scan_2 is first provided to the second gate line S1 corresponding to the first row of pixel units 10; then, a second gate line S2 corresponding to the second row of pixel units 10 is provided.
  • a second scan signal Scan_2 is provided.
  • the duration T2 of the effective level of the second scan signal Scan_2 is 1 / N of the duration T1 of the effective level of the first scan signal Scan_1.
  • a single gate line group 20 has adjacent first gate lines G1 and first gate lines G2.
  • the duration T2 of the effective level of the second scan signal Scan_2 is 1/2 of the duration T1 of the effective level of the first scan signal Scan_1.
  • the first row of the time when the first sub-pixel 101 in the first row of pixel units and the first sub-pixel 101 (R) in the second row of pixel units emit light the first row The second sub-pixel 102 (G) and the third sub-pixel 103 (B) in the pixel unit emit light.
  • the duration T2 of the effective level of the second scan signal Scan_2 is the effective voltage of the first scan signal Scan_1.
  • the flat time is 1/3 of T1.
  • the light-emission time of the second sub-pixel 102 (G) and the third sub-pixel 103 (B) in each row of pixel units is one third of the light-emission time of the first sub-pixel 101 (R).
  • first sub-pixel 101 (R ) Has the same or approximately the same light emission brightness as that of the second sub-pixel 102 (G) and the third sub-pixel 103 (B), which is beneficial to achieving the white balance state of the pixel unit 10.
  • the number of the first gate lines G in a single gate line group 20 can be increased, otherwise each gate line group can be reduced The number of first gate lines G in 20.
  • the above embodiment is described by taking a single gate line group 20 including two or three adjacent first gate lines G as an example.
  • a single raster line group 20 includes other numbers of first raster lines G, the first scan signal Scan_1 and the second scan signal Scan_2 are provided, and the first sub-pixel 101 (R), the second sub-pixel 102 ( G)
  • the control manners of the light-emission durations of the third sub-pixel 103 (B) are similar to this, and are not repeated here one by one.
  • each sub-pixel for example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 of the pixel unit of the array substrate includes a light emitting device D and a Pixel circuit for controlling light emitting device D to emit light.
  • the pixel circuit includes a first gating sub-circuit 30, a gray-scale control sub-circuit 31, and a driving sub-circuit 32.
  • the light emitting device D may include a micro light emitting diode (Micro LED). In other embodiments, the light emitting device D may be another type of diode, such as an organic light emitting diode (OLED).
  • the first gating sub-circuit 30 is electrically connected to the gate line (the first gate line or the second gate line) corresponding to the data line DL, the gray-scale control sub-circuit 31, and the sub-pixel in which the pixel circuit is located.
  • the first gate sub-circuit 30 in the pixel circuit is electrically connected to the first gate line G.
  • the first gate sub-circuit 30 in the pixel circuit is electrically connected to the second gate line S.
  • the first gating sub-circuit 30 is configured to transmit the data voltage Vdata output from the data line DL to the gray-scale control sub-circuit 31 under the control of the scanning signal received by the first gate line S or the second gate line G.
  • the driving sub-circuit 32 is also electrically connected to the second voltage terminal and the first working voltage terminal.
  • the other end of the light emitting device D is electrically connected to the reference voltage terminal VSS.
  • the driving sub-circuit 32 is configured to provide a constant driving current I to the light-emitting device D according to a voltage difference between the first operating voltage VDD and the second voltage Vp under the control of the second voltage output from the second voltage terminal Vp.
  • the first voltage provided by the first operating voltage terminal VDD and the reference voltage provided by the reference voltage terminal VSS are used to provide a potential difference to the current flowing path of the driving current I.
  • the magnitude of the driving current I is related to the magnitude of the voltage value output by the second voltage Vp and the first operating voltage VDD.
  • the light emitting device D emits light according to the driving current I.
  • the gray-scale control sub-circuit 31 is also electrically connected to the driving sub-circuit 32 and one end of the light emitting device D.
  • the gray-scale control sub-circuit 31 is configured to control the duration of the electrical connection between the driving sub-circuit 32 and the light-emitting device D according to the received data voltage Vdata. That is, the gray-scale control sub-circuit 31 controls the duration of the driving current I flowing through the light-emitting device D based on the data voltage Vdata.
  • the first voltage provided by the first operating voltage terminal VDD is a high level
  • the second voltage of the reference voltage terminal VSS is a low level or a ground voltage
  • the second voltage Vp may be a constant voltage, so that the driving sub-circuit 32 provides a constant driving current I to the light emitting device D, thereby further stabilizing the light emitting performance of the light emitting device D.
  • the second voltage Vp can also be changed manually or adjusted automatically in response to external conditions.
  • the relationship curve between the light-emitting efficiency of the light-emitting device and the current density can be obtained, which belongs to the nature of the light-emitting device and can be measured by experimental methods.
  • the current density is the ratio of the current passing through the light-emitting device to the light-emitting area of the light-emitting device, and the light-emitting efficiency can be the ratio of the light-emitting brightness of the light-emitting device to the current.
  • FIG. 7 is a schematic diagram showing a relationship curve between a light emitting efficiency and a current density of a micro light emitting diode.
  • the voltage value of the second voltage Vp provided by the second voltage terminal may be set. It is determined or adjusted so that the driving sub-circuit 32 provides an appropriate constant driving current to the micro light emitting diode, and the constant driving current makes the current density of the micro light emitting diode constant at the A position. Therefore, the micro light emitting diodes of each sub-pixel are made to work in a region with the highest light emitting efficiency, which is beneficial to improving the light emitting efficiency and light emitting stability of the light emitting device D.
  • FIG. 7 is merely an exemplary description for the relationship between the light emitting efficiency and the current density of the micro light emitting diode.
  • the above relationship curve may be different for different types or types of micro light emitting diodes.
  • the relationship between the light-emitting efficiency and the current density of micro-light-emitting diodes with different light-emitting colors may also be different.
  • the red light emitting diode (R) in the first sub-pixel 101, the green light emitting diode (G) in the second sub-pixel 102, and the blue light emitting diode (B) in the third sub-pixel 103 The current density corresponding to the high light emitting efficiency region of the micro light emitting diodes in the respective curves is also different. Therefore, the values of the second voltage for the pixel circuit in the first sub-pixel 101, the second voltage for the pixel circuit in the second sub-pixel 102, and the second voltage for the pixel circuit in the third sub-pixel 103 It can also be different.
  • pixel circuits in a plurality of sub-pixels having the same emission color may be electrically connected to the same second voltage terminal.
  • the pixel circuits in the first sub-pixel 101 located in the same column are electrically connected to the same second voltage terminal; the pixel circuits in the second sub-pixel 102 located in the same column are electrically connected to the same second voltage terminal;
  • the pixel circuits in the third sub-pixel 103 of the column are electrically connected to the same second voltage terminal.
  • the pixel circuit of each sub-pixel further includes a second gating sub-circuit 33.
  • the second gating sub-circuit 33 is electrically connected to the second voltage terminal, the driving sub-circuit 32 and the third gate line GL.
  • the second gating sub-circuit 33 is configured to transmit the second voltage Vp provided by the second voltage terminal to the driving sub-circuit under the control of the control signal transmitted by the third gate line GL.
  • the second voltage Vp can be transmitted to the driving sub-circuit 32 only when the second gating sub-circuit is turned on under the control of the control signal transmitted by the third gate line GL.
  • the driving sub-circuit 32 need not always be kept in the on state, but may receive the second voltage Vp after the second gating sub-circuit is turned on as needed, and then provide the driving current I to the light-emitting device D.
  • This application does not limit when the third gate line GL controls the second gate sub-circuit 33 to be turned on, at least to ensure that the signals on the first gate line G and the second gate line S turn on the first gate sub-circuit 30. Before, the third gate line GL can control the second gating sub-circuit 33 to be turned on.
  • some embodiments of the present application provide a method for driving an array substrate. As shown in FIG. 9, the above driving method includes steps S101-S104.
  • the above-mentioned first gating sub-circuit 30 transmits the data voltage Vdata output from the data line DL to the gray-scale control sub-circuit 31 under the control of the scanning signal transmitted by the first gate line G or the second gate line S.
  • the first gate line G or the second gate line S controls the first gating sub-circuit 30 to be turned on. After the first gating sub-circuit 30 is turned on, the data voltage Vdata can be transmitted to the gray-level controlling sub-circuit through the first gating sub-circuit 30. Circuit 31.
  • the driving sub-circuit 32 generates a constant driving current I to be provided to the light-emitting device D according to a voltage difference between the first operating voltage VDD and the second voltage Vp under the control of the second voltage Vp.
  • the grayscale control sub-circuit 31 controls the duration of the driving current flowing through the light-emitting device D according to the data voltage Vdata.
  • the data voltage Vdata controls the gray-scale control sub-circuit 31 to be turned on.
  • the driving sub-circuit 32 and the light emitting device D are electrically connected.
  • the driving sub-circuit 32 and the light emitting device D are electrically disconnected.
  • the driving method further includes:
  • the second gating sub-circuit 33 transmits a second voltage to the driving sub-circuit 32 under the control of the third gate line GL. In this way, under the control of the third gate line GL, when the second gating sub-circuit 33 is turned on, the driving sub-circuit 32 can be in an operating state and receive the second voltage.
  • the above-mentioned first gating sub-circuit 30 includes a first transistor M1.
  • the gate of the first transistor M1 is electrically connected to the first gate line G or the second gate line S, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the grayscale control sub-circuit 31.
  • the gray-scale control sub-circuit 31 includes a second transistor M2.
  • the gate of the second transistor M2 is electrically connected to the second pole of the first transistor M1, the first pole of the second transistor M2 is electrically connected to the driving sub-circuit 32, and the second pole of the second transistor M2 is electrically connected to the anode of the light emitting device D.
  • the driving sub-circuit 32 includes a driving transistor Md.
  • the gate of the driving transistor Md is electrically connected to the second voltage terminal
  • the first electrode is electrically connected to the first operating voltage terminal VDD
  • the second electrode is electrically connected to the second transistor M2 in the grayscale control sub-circuit 31.
  • FIG. 11 illustrates a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit includes a second gating sub-circuit 33.
  • the second gating sub-circuit 33 includes a third transistor M3.
  • the gate of the third transistor M3 is electrically connected to the third gate line GL
  • the first electrode is electrically connected to the second voltage terminal
  • the second electrode is electrically connected to the driving transistor Md in the driving sub-circuit 32.
  • the third transistor M3 when the third transistor M3 is turned on, the gate of the driving transistor Md is electrically connected to the second voltage terminal through the third transistor M3.
  • each of the above transistors may be an N-type transistor or a P-type transistor.
  • FIG. 10 and FIG. 11 are described by taking each of the foregoing transistors as a P-type transistor as an example.
  • the first electrode of each of the foregoing transistors may be a source electrode and a second electrode drain; or the first electrode is a drain electrode and the second electrode is a source electrode, which is not limited in this application.
  • the driving transistor Md can generate a driving current I for driving the light emitting device D to emit light, the driving transistor Md needs to have a certain load capacity. Therefore, the width-to-length ratio of the driving transistor Md is greater than the width-to-length ratio of the first transistor M1, the second transistor M2, and the third transistor M3.
  • the pixel circuit shown in FIG. 11 is taken as an example to describe the operation process of the pixel circuit in detail.
  • the third gate line GL receives a low-level signal.
  • the third transistor M3 is turned on, thereby transmitting a constant voltage output from the constant voltage source Vp to the gate of the driving transistor Md, and the driving transistor Md is turned on.
  • the driving transistor Md under the control of an appropriate second voltage output from the second voltage terminal, the driving transistor Md can be made to work in a saturation region, so that the driving transistor Md can be used to provide a constant driving current I to the light-emitting device D.
  • the driving The magnitude of the current I is related to the second voltage output from the second voltage terminal and the first voltage output from the first operating voltage terminal VDD.
  • the driving transistor Md is always operating in the above-mentioned saturation region, characteristics such as the threshold voltage (Vth) of the driving transistor Md will drift, thereby affecting the stability of the driving current I.
  • Vth threshold voltage
  • the third gate line GL can be used to control the on and off of the third transistor M3, so that only when the third transistor M3 is turned on, the driving transistor Md is turned on. It can work in the above-mentioned saturation region, thereby alleviating or reducing the problem that the threshold voltage of the driving transistor Md drifts.
  • the first gate line G or the second gate line S receives a low level.
  • the first transistor M1 is turned on, and the data voltage Vdata is transmitted to the gate of the second transistor M2, and the second transistor M2 is turned on.
  • the second transistor M2 is a switching transistor. When the second transistor M2 is turned on, the driving current I generated by the driving transistor Md can be transmitted to the light emitting device D through the second transistor M2, so that the light emitting device D receives the driving. After the current I, light is emitted.
  • the magnitude of the driving current I is related to the second voltage output from the second voltage terminal, so the second voltage output from the second voltage terminal can be set or adjusted to generate a corresponding driving current, so that the light emitting device After D receives the driving current I, its current density makes the light-emitting efficiency of the light-emitting device in a high range.
  • the signal output by the first gate line G or the second gate line S has a certain delay with respect to the control signal provided by the third gate line GL, as shown in FIG. 12.
  • the driving transistor Md after the driving transistor Md generates a stable driving current I, it can be transmitted to the light-emitting device D through the second transistor M2, thereby further ensuring that the current density of the light-emitting device D is in a range that generates high light-emitting efficiency.
  • the duration of the effective level of the data voltage Vdata provided by the data line DL may be modulated by using a PWM (Pulse Width Modulation) method.
  • PWM Pulse Width Modulation
  • the on-time of the first transistor M1 can be controlled, so as to control the effective time period during which the light-emitting device D receives the driving current I, thereby realizing the effective light-emitting brightness of the light-emitting device D and matching the effective light-emitting brightness. Adjust the gray scale.
  • the first sub-pixel 101 in the first sub-pixel 101 may be electrically connected to the gate of the first transistor M1 in the first sub-pixel 101.
  • a gate line G provides the above-mentioned first scan signal Scan_1 (taking low-level VGL as an example in FIG. 13) to turn on the first transistor M1.
  • Scan_1 taking low-level VGL as an example in FIG. 13
  • the duration of the low-level VGL in the data voltage Vdata provided by the data line DL to the gate of the second transistor M2 through the first transistor M1 during the on-time T of the first transistor M1 is the same as that of the first transistor.
  • the M1 on-time T is the same.
  • the data line DL may be provided to the gate of the second transistor M2 through the first transistor M1 during the on-time T of the first transistor M1.
  • the duration of the low-level VGL is about 50% of the on-time T of the first transistor M1 (for convenience of explanation, 50% is taken as an example below).
  • the data line DL may pass through the first transistor M1 to the gate of the second transistor M2 during the on-time T of the first transistor M1.
  • the duration of the low-level VGL is 0.
  • the data line DL may be routed to the first transistor M1 within the on-time T of the first transistor M1.
  • the duration P of the low-level VGL is 50% ⁇ T ⁇ P ⁇ 100% ⁇ T.
  • the data line DL may be routed to the first transistor M1 within the on-time T of the first transistor M1.
  • the duration P of the low-level VGL is 0 ⁇ T ⁇ P ⁇ 50% ⁇ T.
  • the above description is made by taking the first sub-pixel 101 as an example.
  • the gray levels of the second sub-pixel 102 and the third sub-pixel 103 are controlled, similarly, the first of the second sub-pixel 102 or the third sub-pixel 103 can be controlled.
  • an array substrate includes a gate driving circuit.
  • the gate driving circuit is disposed in a wiring region of the array substrate, and the wiring region may be located around the pixel region.
  • FIG. 14 schematically illustrates an example of a gate driving circuit including a first gate driving sub-circuit 40 and a second gate driving sub-circuit 41.
  • a first gate driving sub-circuit 40 is electrically connected to the plurality of first gate lines to provide a first scanning signal to the plurality of first gate lines
  • a second gate driving sub-circuit 41 is connected to the plurality of first gate lines.
  • the two gate lines are electrically connected to provide a second scan signal to the plurality of second gate lines.
  • the first gate driving sub-circuit 40 and the second gate driving sub-circuit 41 may be in the form of an integrated circuit (IC), and may be disposed in the wiring area through a bonding process. Alternatively, it can also be fabricated on the glass substrate of the array substrate 01 by means of a GOA (Gate Driver On Array). This application does not limit this.
  • IC integrated circuit
  • GOA Gate Driver On Array
  • the first gate driving sub-circuit 40 is electrically connected to a plurality of first gate lines G1 corresponding to each row of pixel units.
  • the plurality of first gate lines may include at least one gate line group, and each gate line group includes at least two adjacent first gate lines.
  • the first gate driving sub-circuit includes a plurality of cascaded first shift registers, and each shift register is electrically connected to a gate line group to simultaneously provide a first to each first gate line in the gate line group.
  • a scanning signal, the second gate driving sub-circuit includes a plurality of cascaded second shift registers, each second shift register is electrically connected to a second gate line to provide a second scanning signal to the second gate line .
  • the first gate driving sub-circuit 40 is configured to sequentially provide a plurality of gate line groups (each gate line group includes a first row of first gate lines G1 and a second row of first gate lines G2). First scan signal Scan_1.
  • the second gate driving sub-circuit 41 is electrically connected to the second gate lines (S1, S2, ).
  • the second gate driving sub-circuit 41 is configured to sequentially provide a second scan signal Scan_2 to a plurality of second gate lines (S1, S2,).
  • the first gate driving sub-circuit 40 includes a plurality of cascaded first shift registers (RS_G_1, RS_G_2,).
  • the first shift register of each stage is electrically connected to a group of gate line groups 20.
  • the gate line groups 20 electrically connected to different first shift registers are different.
  • the first scan signal Scan_1 output by a single first shift register may be simultaneously provided to all the first gate lines (for example, G1 and G2) in the gate line group 20 to which the first shift register is electrically connected. ).
  • the second scan signal Scan_2 output by a single second shift register (for example, RS_S_1) may be provided to a second gate line (for example, S1) electrically connected to the second shift register (for example, RS_S_1). .
  • the shift register mentioned here refers to a circuit that generates an output signal that is phase-shifted relative to the input signal based on the input signal.
  • the output signal provided by the shift register is The first scan signal or the second scan signal mentioned in the disclosure.
  • the circuit of a single shift register is known to those skilled in the art, and it will not be repeated here.
  • the first gate driving sub-circuit 40 and the second gate driving sub-circuit 41 are located on two sides of the display area, respectively.
  • the array substrate further includes a source driving circuit electrically connected to the data line DL. Since all the first grid lines G in the same grid line group 20 can be scanned at the same time, the sub-pixels controlled by each of the first grid lines G in the same grid line group 20 respectively receive different data lines DL output. Data voltage, so that the gray scale data displayed by the above-mentioned sub-pixels can be controlled independently.
  • Another embodiment of the present disclosure provides a display panel, which may include an array substrate according to any one of the foregoing embodiments.
  • the first sub-pixel with lower light-emitting efficiency in each row of pixel units is electrically connected to the first gate line
  • the second sub-pixel and third sub-pixel with high light-emitting efficiency are electrically connected to the second gate line.
  • the first scanning signal and the second scanning signal may be supplied to the first and second gate lines, respectively.
  • the duration of the effective level of the first scan signal is greater than the duration of the effective level of the second scan signal.
  • the light-emitting time of the first sub-pixel is longer than the light-emitting time of the second and third sub-pixels, so the light-emitting time of the first sub-pixel with low light-emitting efficiency can be extended to
  • the light emission brightness of the first sub-pixel is compensated, so that the light emission brightness of the first sub-pixel, the second sub-pixel, and the third sub-pixel are the same or approximately the same, thereby improving the display effect of the display device.
  • the display panel may be any product or component having a display function, such as an organic light emitting diode television, a digital photo frame, a mobile phone, or a tablet computer.
  • a display function such as an organic light emitting diode television, a digital photo frame, a mobile phone, or a tablet computer.
  • the above display panel has the same beneficial effects as the array substrate provided in the foregoing embodiment, and is not repeated here.

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Abstract

一种阵列基板（01），包括：矩阵排列的多个像素单元（10），每个像素单元（10）至少包括发光颜色不同的第一亚像素（101）、第二亚像素（102）和第三亚像素（103），第一亚像素（101）的发光效率低于第二亚像素（102）和第三亚像素（103）；与矩阵排列的多个像素单元（10）中的各行像素单元（10）分别对应的多条第一栅线（G1，G2，G3……）；与矩阵排列的多个像素单元（10）中的各行像素单元（10）分别对应的多条第二栅线（S1，S2，S3……）。矩阵排列的多个像素单元（10）中的每一行像素单元（10）中的第一亚像素（101）电连接多条第一栅线（G1，G2，G3……）中的一条第一栅线（G），矩阵排列的多个像素单元（10）中的每一行像素单元（10）中的第二亚像素（102）和第三亚像素（103）均电连接多条第二栅线（S1，S2，S3……）中的一条第二栅线（S）。

Description

阵列基板及其驱动方法、显示面板
相关申请的交叉引用
本申请要求于2018年6月28日向中国专利局提交的专利申请201810685556.7的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其驱动方法、显示面板。
背景技术
相对于有机发光二极管(OLED)而言，微型(Micro)LED具有全固态、寿命长、发光材料不容易受到外界环境影响而相对稳定的优势。
然而，对于应用微型LED的显示装置，其中采用发光颜色不一样的微型LED，这些发光颜色不同的微型LED的发光效率也不同，从而对显示画面的显示效果造成影响。
发明内容
本公开的实施例提供了一种阵列基板，该阵列基板包括：矩阵排列的多个像素单元，每个所述像素单元至少包括发光颜色不同的第一亚像素、第二亚像素和第三亚像素；与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第一栅线；以及与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第二栅线。矩阵排列的多个像素单元中的每一行像素单元中的第一亚像素电连接所述多条第一栅线中的一条第一栅线，所述矩阵排列的多个像素单元中的每一行像素单元中的第二亚像素和所述第三亚像素均电连接所述多条第二栅线中的一条第二栅线。
在一些实施例中，所述多条第一栅线包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线，每个栅线组中的各条第一栅线被配置成接收同一扫描信号。
在一些实施例中，所述第一亚像素、第二亚像素和第三亚像素中的每个亚像素包括发光器件以及控制所述发光器件发光的像素电路。所述像素电路包括第一选通子电路、灰阶控制子电路以及驱动子电路， 所述第一选通子电路与所述第一栅线和第二栅线中的一个、数据线、所述灰阶控制子电路电连接，所述第一选通子电路被配置成在所述第一栅线或第二栅线传输的扫描信号的控制下，将所述数据线输出的数据电压传输至所述灰阶控制子电路。所述驱动子电路与第一工作电压端、第二电压端和所述灰阶控制子电路电连接，所述驱动子电路被配置成在第二电压端输出的第二电压的控制下，向所述发光器件提供恒定的驱动电流。灰阶控制子电路还与所述发光器件和所述驱动子电路电连接，所述灰阶控制子电路被配置成根据所述数据电压而控制所述驱动电流流过所述发光器件的时长。
在一些实施例中，所述阵列基板还包括与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第三栅线，其中所述像素电路还包括第二选通子电路，所述第二选通子电路与所述第二电压端、所述驱动子电路以及所述多条栅线中的一条第三栅线电电连接，所述第二选通子电路被配置成在所述第三栅线传输的控制信号的控制下，将所述第二电压传输至所述驱动子电路。
在一些实施例中，第一选通子电路包括第一晶体管，所述第一晶体管的栅极电连接所述第一栅线或第二栅线，第一极电连接所述数据线，第二极与灰阶控制子电路电连接。
在一些实施例中，灰阶控制子电路包括第二晶体管，所述第二晶体管的栅极电连接所述第一选通子电路，第一极电连接所述驱动子电路，第二极电连接所述发光器件。
在一些实施例中，驱动子电路包括驱动晶体管，所述驱动晶体管的栅极电连接所述第二电压端，第一极电连接所述第一工作电压端，第二极电连接所述灰阶控制子电路。
在一些实施例中，第二选通子电路包括第三晶体管，所述第三晶体管的栅极电连接所述第三栅线，第一极电连接所述第二电压端，第二极电连接所述驱动子电路。
在一些实施例中，发光器件包括微型发光二极管，所述微型发光二极管第一端电连接至所述灰阶控制子电路，所述微型发光二极管的第二端电连接至参考电压端。
在一些实施例中，阵列基板包括栅极驱动电路，所述栅极驱动电路包括第一栅极驱动子电路和第二栅极驱动子电路、其中所述第一栅 极驱动子电路与所述多条第一栅线电连接，以向所述多条第一栅线提供第一扫描信号；所述第二栅极驱动子电路与所述多条第二栅线电连接，以向所述多条第二栅线提供第二扫描信号。
在一些实施例中，所述多条第一栅线包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线。所述第一栅极驱动子电路包括级联的多个第一移位寄存器，每个移位寄存器与一个栅线组电连接以向所述栅线组中的各条第一栅线同时提供第一扫描信号，所述第二栅极驱动子电路包括级联的多个第二移位寄存器，每个第二移位寄存器与一条第二栅线电连接以向第二栅线提供第二扫描信号。
在一些实施例中，第一亚像素的发光效率低于所述第二亚像素和所述第三亚像素。
本公开的另一实施例提供了一种显示面板，包括如前述实施例中任一实施例所述的阵列基板。
本公开的又一实施例提供了一种用于如前述的任一实施例所述的阵列基板的驱动方法，该驱动方法包括：依次向所述多条第一栅线中的各条第一栅线提供第一扫描信号，同时依次向所述多条第二栅线中的各条第二栅线提供第二扫描信号。
在一些实施例中，所述多条第一栅线包括多个栅线组，每个栅线组包括N条相邻的第一栅线，N为大于等于2的整数，此时，所述依次向所述多条第一栅线中的各条第一栅线提供第一扫描信号包括：依次向所述多个栅线组中的每个栅线组提供第一扫描信号，向每个栅线组提供所述第一扫描信号包括：同时向所述栅线组中的N条所述第一栅线提供所述第一扫描信号。第二扫描信号的有效电平的时长为所述第一扫描信号的有效电平的时长的1/N。
在一些实施例中，所述第一亚像素、第二亚像素和第三亚像素中的每个亚像素包括发光器件以及控制所述发光器件发光的像素电路，所述像素电路包括第一选通子电路、灰阶控制子电路以及驱动子电路，所述驱动方法包括：所述第一选通子电路在所述第一栅线或第二栅线传输的第一扫描信号或第二扫描信号的控制下，将数据线输出的数据电压传输至所述灰阶控制子电路；所述驱动子电路产生提供给所述发光器件的恒定驱动电流；以及所述灰阶控制子电路根据所述数据电压控制所述驱动电流流过所述发光器件的时长。
在一些实施例中，阵列基板还包括与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第三栅线，所述像素电路还包括第二选通子电路，第二选通子电路与所述多条第三栅线中的一条第三栅线、第二电压端和所述驱动子电路电连接，其中所述驱动方法还包括：在所述第一选通子电路将数据线输出的数据电压传输至所述灰阶控制子电路之前，所述第二选通子电路在所述多条第三栅线中的一条第三栅线传输的控制信号的控制下，将所述第二电压端输出的第二电压传输至所述驱动子电路以启动所述驱动子电路产生所述驱动电流。
在一些实施例中，第一扫描信号的有效电平的时长大于第二扫描信号的有效电平的时长。
在不产生矛盾或冲突的情况下，上述实施例以及这些实施例中的各个技术特征可以以任何适当的方式组合，从而得到另外的实施例，这些另外的实施例也落入本申请的保护范围。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对描述这些实施例所需要使用的附图作简单地介绍。下面描述中的附图仅仅表示本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据本公开的一些实施例提供的阵列基板的结构示意图；
图2为用于图1所示的实施例的阵列基板的扫描信号的示意性时序图；
图3为根据本公开另一实施例提供的阵列基板的结构示意图；
图4为用于图3所示的实施例的阵列基板的扫描信号的示意性时序图；
图5为根据本公开的另一实施例提供的扫描信号的示意性时序图；
图6为根据本公开的一些实施例提供的像素电路的结构示意图；
图7为根据本公开的一些实施例提供的一种Micro LED的电流密度与发光效率的关系曲线图；
图8为根据本公开的另一实施例提供的像素电路的结构示意图；
图9为根据本公开的另一实施例提供的用于阵列基板的驱动方法流程图；
图10为根据本公开的一些实施例的像素电路的具体结构示意图；
图11为根据本公开的另外的实施例的像素电路的具体结构示意图；
图12为根据本公开的另外的实施例的第三栅线传输的控制信号和第一或第二栅线的扫描信号的示意性信号时序图；
图13示意性地说明根据本公开的另外的实施例提供的用于单个亚像素的灰阶调节的数据信号的波形图；
图14为根据本公开的另外的实施例提供的显示面板的结构示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
图1示出了根据本公开的实施例提供的阵列基板的示意图。如图1所示，阵列基板01包括矩阵排列的多个像素单元10，每个像素单元10至少包括发光颜色不同的第一亚像素101、第二亚像素102和第三亚像素103。本申请对上述第一亚像素101、第二亚像素102和第三亚像素103发出的光线的颜色不做限定，在一些实施例中，同一像素单元10中第一亚像素101、第二亚像素102和第三亚像素103分别发出的光线混合后，使得该像素单元10发白光。
根据本公开的一些实施例，第一亚像素的发光效率低于第二亚像素和第三亚像素。例如，上述第一亚像素101发红光(R)、第二亚像素102发绿光(G)，第三亚像素103发蓝光(B)。但是，本文所提到的第一亚像素、第二亚像素、第三亚像素不限于此。第一亚像素可以是比R亚像素发光效率更低或更高的任何亚像素，第二压像素和第三亚像素也可以是分别具有与G亚像素和B亚像素不同的发光效率的 任何亚像素。本公开的实施例提供的阵列基板中的第一亚像素、第二亚像素和第三亚像素的发光效率可以彼此完全不同，也可以是部分相同。例如，第一亚像素、第二亚像素和第三亚像素中的任何两个具有相同的发光效率，但是不同于余下的一个亚像素的发光效率。
参见图1，阵列基板还包括与矩阵排列的多个像素单元中的各行像素单元分别对应的多条第一栅线G1，G2，G3......，以及与矩阵排列的多个像素单元中的各行像素单元分别对应的多条第二栅线S1，S2，S3......。而且，矩阵排列的多个像素单元中的每一行像素单元中的第一亚像素电连接第一栅线，所述矩阵排列的多个像素单元中的每一行像素单元中的第二亚像素和所述第三亚像素均电连接第二栅线。本文提到的阵列基板包括但不限于有机发光二极管(OLED)阵列基板、LED阵列基板、液晶显示装置中的阵列基板等。基于本公开实施例提供的阵列基板，在第一亚像素的发光效率低于第二亚像素和第三亚像素的情形下，可以采用以下方法来驱动阵列基板以进行图像显：向电连接至同一行像素单元10的第一栅线G和第二栅线S分别提供第一扫描信号和第二扫描信号，如图2所示，第一扫描信号的有效电平的时长T1大于第二扫描信号的有效电平的时长T2。
这样一来，可以使得同一行像素单元10中的第一亚像素101的发光时间大于第二亚像素102和第三亚像素103的发光时间，从而可以对发光效率较低的第一亚像素101的发光时间进行延长，以对该第一亚像素101的发光亮度进行补偿，使得第一亚像素101与第二亚像素102、第三亚像素103的发光亮度相同或近似相同，从而可以提高显示效果。
在第二亚像素和第三亚像素的发光效率均小于第一亚像素的发光效率的情况下，可以采用以下方法来驱动阵列基板以进行图像显：向电连接至同一行像素单元10的第一栅线G和第二栅线S分别提供第一扫描信号和第二扫描信号，第二扫描信号的有效电平的时长大于第一扫描信号的有效电平的时长。由此，可以使得同一行像素单元10中的第二亚像素102和第三亚像素103的发光时间大于第一亚像素101的发光时间，从而可以对发光效率较低的第二和第三亚像素101的发光亮度进行补偿，使得第一亚像素101与第二亚像素102、第三亚像素103的发光亮度相同或近似相同，从而可以提高显示效果。
为了简洁起见，在下面的描述中，仅以第一亚像素的发光效率低于第二亚像素和第三亚像素的情形为例对本公开实施例提供的阵列基板及其驱动方法进行说明。
根据本公开的一些实施例，与矩阵排列的多个像素单元中的各行像素单元分别对应的多条第一栅线包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线，每个栅线组中的各条第一栅线被配置成接收同一扫描信号。在图3的示例中，示意性地示出了两个栅线组20，每个栅线组包括2条相邻的第一栅线，即对应于第一行像素单元的第一栅线G1和对应于第二行像素单元的第一栅线G2，或者对应于第三行像素单元的第一栅线G3和对应于第四行像素单元的第一栅线G4。在一些实施例中，任意两个不同的栅线组中所包含的第一栅线彼此不同，即，任一条第一栅线不会同时属于两个以上的栅线组。如前所述，每个栅线组20中的所有第一栅线G同时接收同一扫描信号。例如，每个栅线组20中的所有第一栅线G同时接收上述第一扫描信号。在此情况下，位于同一栅线组20中的所有第一栅线G可以同时被扫描，与同一栅线组20中的各条第一栅线G相电连接的第一亚像素101同时开启并发光，且发光时长相同。
基于此，可以在同一时刻向一栅线组20中的N条第一栅线G提供上述第一扫描信号(例如，其有效电平的时长为T1)，N≥2，N为正整数。与此同时，依次向与上述N条第一栅线G分别电连接的各行像素单元对应的的N条第二栅线S提供第二扫描信号。在此情况下，与N条第二栅线S电连接的第二亚像素102和第三亚像素103逐行开启，而分别与上述N条第一栅线G电连接的各个第一亚像素101可以在上述时间段T1中一直保持开启状态。这样一来，与该栅线组20中的第一栅线电连接的第一亚像素101的发光时长可以为和该第一亚像素101位于同一行的第二亚像素102、第三亚像素103的发光时长的N倍。
基于此，可以通过以下方式来提供第一扫描信号，从而驱动各像素单元进行显示：依次向多个栅线组20提供第一扫描信号，即利用所述第一扫描信号对各个栅线组20进行逐组扫描。
示例性的，先向如图3所示的由第一行(L1)的第一栅线G1和第二行(L2)的第一栅线G2构成一栅线组20中的两条第一栅线G1、 G2提供如图4所示的第一扫描信号Scan_1_R。然后，再向图3所示的第三行(L3)的第一栅线G3和第四行(L4)的第一栅线G4构成一栅线组20中的两条第一栅线G3、G4提供上述第一扫描信号Scan_2_R，如图4所示。接下来的各组栅线组20的扫描方式同上所述。
因此，在对本公开实施例提出的阵列基板的像素单元进行驱动时，可同时向栅线组20中的N条第一栅线G提供第一扫描信号。示例性的，同时向第一行(L1)的第一栅线G1和第二行(L2)的第一栅线G2提供如图4所示的第一扫描信号Scan_1。此时，第一行和第二行的第一亚像素101，即发红光(R)。
同时，依次向与上述N条第一栅线G电连接的N行像素单元所对应的N条第二栅线G提供第二扫描信号Scan_2。示例性的，如图4所示，先向与第一行像素单元10对应的第二栅线S1提供第二扫描信号Scan_2；然后，向与第二行像素单元10对应的第二栅线S2提供第二扫描信号Scan_2。第二扫描信号Scan_2的有效电平的时长T2为与第一扫描信号Scan_1的有效电平的时长T1的1/N。
示例性的，如图3所示，单个的栅线组20具有相邻的第一栅线G1和第一栅线G2。此时，如图4所示，第二扫描信号Scan_2的有效电平的时长T2为与第一扫描信号Scan_1的有效电平的时长T1的1/2。
在此情况下，如图4所示，在第一行像素单元中的第一亚像素101以及第二行像素单元中的第一亚像素101(R)发光的前一半时间内，第一行像素单元中的第二亚像素102(G)和第三亚像素103(B)发光。在第一行像素单元中的第一亚像素101以及第二行像素单元中的第一亚像素101(R)发光的后一半时间内，第二行像素单元中的第二亚像素102(G)和第三亚像素103(B)发光。因此，每一行像素单元中第二亚像素102(G)和第三亚像素103(B)发光时长是第一亚像素101(R)的发光时长的二分之一。
同理，当一组栅线组20包括三条相邻的第一栅线G时，如图5所示，第二扫描信号Scan_2的有效电平的时长T2为与第一扫描信号Scan_1的有效电平的时长T1的1/3。在此情况下，每一行像素单元中第二亚像素102(G)和第三亚像素103(B)发光时长是第一亚像素101(R)的发光时长的三分之一。
本领域技术人员可以根据需要对单个栅线组20所包括的第一栅线 G的数量进行设定，以使得在一帧画面的显示时间内单个像素单元10中的第一亚像素101(R)的发光亮度与第二亚像素102(G)和第三亚像素103(B)的发光亮度相同或近似相同，从而有利于实现像素单元10的白平衡状态。
当第一亚像素101的发光效率与第二亚像素102、第三亚像素103相差较大时，可以增加单个栅线组20中第一栅线G的数量，反之可以减小每个栅线组20中第一栅线G的数量。
上述实施例是以单个的栅线组20包括两条或三条相邻的第一栅线G为例进行的说明。当单个的栅线组20包括其它数量的第一栅线G时，上述第一扫描信号Scan_1和第二扫描信号Scan_2的提供方式，以及第一亚像素101(R)、第二亚像素102(G)和第三亚像素103(B)的发光时长的控制方式与此类似，此处不再一一赘述。
如前所述，本公开实施例提供的阵列基板可应用于OLED显示面板或LED显示面板。根据本公开的一些实施例中，如图6所示，阵列基板的像素单元的各个亚像素(例如，第一亚像素101、第二亚像素102以及第三亚像素103)包括发光器件D和用于控制发光器件D发光的像素电路。该像素电路包括第一选通子电路30、灰阶控制子电路31、驱动子电路32。在本申请的一些实施例中，上述发光器件D可以包括微型发光二极管(Micro LED)。在其它实施例中，发光器件D可以为其它类型的二极管，例如有机发光二极管(OLED)。
第一选通子电路30与数据线DL、灰阶控制子电路31以及像素电路所在的亚像素对应的栅线(第一栅线或第二栅线)电连接。当像素电路位于第一亚像素101内时，该像素电路中的第一选通子电路30与第一栅线G电连接。当上述像素电路位于第二亚像素102或第三亚像素103内时，该像素电路中的第一选通子电路30与第二栅线S电连接。
第一选通子电路30用于在第一栅线S或第二栅线G所接收到的扫描信号的控制下，将数据线DL输出的数据电压Vdata传输至灰阶控制子电路31。
驱动子电路32还与第二电压端、第一工作电压端电连接。此外，发光器件D的另一端与参考电压端VSS电连接。驱动子电路32用于在第二电压端Vp输出的第二电压的控制下，根据第一工作电压VDD和第二电压Vp之间的压差，向发光器件D提供恒定的驱动电流I。第 一工作电压端VDD提供的第一电压和参考电压端VSS提供的参考电压用于向驱动电流I的电流流通路径提供电势差。此外，该驱动电流I的大小与第二电压Vp和第一工作电压VDD输出的电压值的大小有关。该发光器件D根据驱动电流I进行发光。
灰阶控制子电路31还与驱动子电路32和发光器件D的一端电连接。该灰阶控制子电路31用于根据接收到的数据电压Vdata，控制驱动子电路32和发光器件D电连接的时长。也就是说，灰阶控制子电路31基于数据电压Vdata控制驱动电流I流过发光器件D的时长。
在一些实施例中，上述第一工作电压端VDD提供的第一电压为高电平，而参考电压端VSS的第二电压为低电平或者接地电压。
第二电压Vp可以是恒定的电压，从而使得驱动子电路32向发光器件D提供恒定的驱动电流I，进而使得发光器件D的发光性能稳定。在一些实施例中，第二电压Vp也可以被人为改变，或者响应于外部条件而自动调节。
对于单个亚像素中的发光器件D，，可以获知该发光器件发光效率与电流密度的关系曲线，这属于发光器件自身的性质，可通过实验的方法测算得到。电流密度为通过发光器件的电流与发光器件的发光面积的比值，发光效率可以发光器件的发光亮度与电流的比值。示例性的，图7示出了微型发光二极管的发光效率和电流密度的关系曲线的示意图。可以看出，电流密度在A位置处时，该微型发光二极管的发光效率最高。因此为了使得第一亚像素101、第二亚像素102或者第三亚像素103中的微型发光二极管的具有较高的发光效率，可以对上述第二电压端提供的第二电压Vp的电压值进行设定或调节，从而使得驱动子电路32向微型发光二极管提供适当的恒定驱动电流，该恒定驱动电流使得该微型发光二极管的电流密度恒定的处于上述A位置。由此，使得各个亚像素的微型发光二极管工作在发光效率最高的区域，从而有利于提高发光器件D发光效率以及发光稳定性。
能够理解到的是，图7仅仅是针对微型发光二极管的发光效率和电流密度之间的关系的示例性说明。上述关系曲线对于不同种类或型号的微型发光二极管可以是不同的。
另外，对于不同发光颜色的微型发光二极管，其具有的发光效率与电流密度的关系曲线也可能不相同。在此情况下，第一亚像素101 中发红光(R)的微型发光二极管、第二亚像素102中发绿光(G)的微型发光二极管以及第三亚像素103中发蓝光(B)的微型发光二极管在各自曲线中的高发光效率区对应的电流密度也各不相同。因此，用于第一亚像素101中的像素电路的第二电压、用于第二亚像素102中的像素电路的第二电压以及用于第三亚像素103中的像素电路的第二电压的数值也可各不相同。
在一些实施例中，可以将发光颜色相同的多个亚像素中的像素电路电连接至相同的第二电压端。示例性的，位于同一列的第一亚像素101中的像素电路电连接相同的第二电压端；位于同一列的第二亚像素102中的像素电路电连接相同的第二电压端；位于同一列的第三亚像素103中的像素电路电连接相同的第二电压端。
根据本公开的另外的实施例，如图8所示，每个亚像素的像素电路还包括第二选通子电路33。
该第二选通子电路33与第二电压端、驱动子电路32以及第三栅线GL电连接。该第二选通子电路33用于在第三栅线GL传输的控制信号的控制下，将第二电压端提供的第二电压Vp传输至驱动子电路。
在此情况下，只有在第三栅线GL传输的控制信号控制下，将第二选通子电路开启时，上述第二电压Vp才能够传输至驱动子电路32。这样一来，驱动子电路32无需总是保持于开启状态，而可以根据需要在第二选通子电路开启后接收第二电压Vp，再向发光器件D提供驱动电流I。
本申请对第三栅线GL控制第二选通子电路33何时开启不做限制，至少能够保证，在第一栅线G和第二栅线S的信号将第一选通子电路30开启之前，第三栅线GL控制第二选通子电路33开启即可。
基于图6所示的像素电路的结构，本申请的一些实施例提供一种用于驱动阵列基板的方法，如图9所示，上述驱动方法包括步骤S101～S104。
S101、上述第一选通子电路30在第一栅线G或第二栅线S传输的扫描信号的控制下，将数据线DL输出的数据电压Vdata传输至灰阶控制子电路31。第一栅线G或第二栅线S控制第一选通子电路30开启，当第一选通子电路30开启后，数据电压Vdata可以通过第一选通子电路30传输至灰阶控制子电路31。
S102、驱动子电路32在第二电压Vp的控制下，根据第一工作电压VDD和第二电压Vp之间的压差，产生提供给发光器件D的恒定驱动电流I。
S103、灰阶控制子电路31根据数据电压Vdata，控制驱动电流流过发光器件D的时长。
数据电压Vdata控制灰阶控制子电路31开启，当灰阶控制子电路31开启时驱动子电路32和发光器件D电连接。当灰阶控制子电路31关闭后，驱动子电路32和发光器件D断开电连接。
能够理解到的是，图6中以S101、S102和S103标识了不同的步骤，但这并不限制这些步骤的执行顺序。这些步骤可以以不同的顺序被执行，或者其中的一些步骤可以被同时执行。
此外，在上述像素电路，如图8所示，还包括第二选通子电路33的情况下，S101之前，上述驱动方法还包括：
第二选通子电路33在第三栅线GL的控制下，将第二电压传输至驱动子电路32。这样一来，在第三栅线GL的控制下，当第二选通子电路33开启时，驱动子电路32才可以处于工作状态，并接收到第二电压。
以下对图6或图8中各个子电路的结构进行详细的说明。
示例性的，如图10所示，上述第一选通子电路30包括第一晶体管M1。该第一晶体管M1的栅极电连接第一栅线G或第二栅线S，第一极电连接数据线DL，第二极与灰阶控制子电路31电连接。
该灰阶控制子电路31包括第二晶体管M2。第二晶体管M2的栅极电连接第一晶体管M1的第二极，第二晶体管M2的第一极电连接驱动子电路32，第二晶体管M2的第二极电连接发光器件D的阳极。
驱动子电路32包括驱动晶体管Md。对于图6的示例而言，上述驱动晶体管Md的栅极电连接第二电压端，第一极电连接第一工作电压端VDD，第二极电连接灰阶控制子电路31中第二晶体管M2的第一极。
图11示出了根据本公开的另一实施例提供的像素电路，该像素电路包括第二选通子电路33，如图11所示，第二选通子电路33包括第三晶体管M3。第三晶体管M3的栅极电连接第三栅线GL，第一极电连接第二电压端，第二极电连接驱动子电路32中的驱动晶体管Md。在此情况下，当第三晶体管M3导通后，该驱动晶体管Md的栅极通过 第三晶体管M3与第二电压端电连接。
需要说明的是，上述各个晶体管可以为N型晶体管，也可以为P型晶体管。图10和图11是以上述各个晶体管为P型晶体管为例进行的说明。此外，上述各个晶体管的第一极可以为源极，第二极为漏极；或者，第一极为漏极，第二极为源极，本申请对此不做限定。
由于驱动晶体管Md能够生成用于驱动发光器件D进行发光的驱动电流I，因此该驱动晶体管Md需要具备一定的带载能力。所以驱动晶体管Md的宽长比大于上述第一晶体管M1、第二晶体管M2以及第三晶体管M3的宽长比。
以下，以图11所示的像素电路为例，对该像素电路的工作过程进行详细的说明。
首先，第三栅线GL接收低电平信号，此时，第三晶体管M3导通，从而将恒压源Vp输出的恒定电压传输至驱动晶体管Md的栅极，驱动晶体管Md导通。
在此情况下，在第二电压端输出的适当的第二电压的控制下，可以使得驱动晶体管Md工作在饱和区，从而可以通过驱动晶体管Md向发光器件D提供恒定的驱动电流I，该驱动电流I的大小与第二电压端输出的第二电压以及第一工作电压端VDD输出的第一电压相关。
如果驱动晶体管Md一直工作在上述饱和区，会导致驱动晶体管Md的阈值电压(Vth)等特性发生漂移，从而影响上述驱动电流I的稳定性。在图11所示的像素电路中，通过设置第三晶体管M3，可以利用第三栅线GL控制第三晶体管M3的导通和截止，使得只有在第三晶体管M3导通时，驱动晶体管Md才能够工作在上述饱和区，从而减缓或降低了驱动晶体管Md的阈值电压发生漂移的问题。
接下来，第一栅线G或第二栅线S接收低电平。此时，第一晶体管M1导通，将数据电压Vdata传输至第二晶体管M2的栅极，该第二晶体管M2导通。
该第二晶体管M2为开关晶体管，当该第二晶体管M2导通时，上述驱动晶体管Md产生的驱动电流I能够通过第二晶体管M2传输至发光器件D，从而使得发光器件D在接收到上述驱动电流I后进行发光。
如以上所讨论的，驱动电流I的大小与第二电压端输出的第二电压相关，因此可以对第二电压端输出的第二电压进行设置或调节，从而 产生相应的驱动电流，使得发光器件D在接收到上述驱动电流I后，其电流密度使得发光器件的发光效率处于较高的范围。
根据本公开的实施例，第一栅线G或第二栅线S输出的信号相对于第三栅线GL提供的控制信号而言具有一定的延时，如图12所示。这样一来，可以使得驱动晶体管Md产生稳定的驱动电流I后，再通过第二晶体管M2传输至发光器件D，从而进一步确保发光器件D的电流密度处于产生较高的发光效率的范围。
在一些实施例中，可以采用PWM(Pulse Width Modulation，脉冲宽度调节)的方式来调制数据线DL提供的数据电压Vdata的有效电平的时长。这样一来，可以控制第一晶体管M1的导通时长，从而对发光器件D接收上述驱动电流I的有效时长进行控制，进而实现对发光器件D有效发光亮度，以及与该有效发光亮度相匹配的显示灰阶的调节。
示例性的，如图13所示，当具有上述像素电路的第一亚像素101需要显示L255的灰阶时，可以向该第一亚像素101中的第一晶体管M1的栅极电连接的第一栅线G提供上述第一扫描信号Scan_1(图13中以低电平VGL为例)，以导通第一晶体管M1。在此情况下，在第一晶体管M1导通时间T内，数据线DL通过第一晶体管M1向第二晶体管M2的栅极提供的数据电压Vdata中，低电平VGL的时长与上述第一晶体管M1导通时间T相同。
或者，当具有上述像素电路的第一亚像素101需要显示L127的灰阶时，可以在第一晶体管M1导通时间T内，数据线DL通过第一晶体管M1向第二晶体管M2的栅极提供的数据电压Vdata中，低电平VGL的时长为上述第一晶体管M1导通时间T的50％左右(以下为了方便说明，以50％为例)。
又或者，当具有上述像素电路的第一亚像素101需要显示L0的灰阶时，可以在第一晶体管M1导通时间T内，数据线DL通过第一晶体管M1向第二晶体管M2的栅极提供的数据电压Vdata中，低电平VGL的时长为0。
又或者，当有上述像素电路的第一亚像素101需要显示的灰阶值L位于L127＜L＜L255时，可以在第一晶体管M1导通时间T内，数据线DL通过第一晶体管M1向第二晶体管M2的栅极提供的数据电压Vdata中，低电平VGL的时长P为50％×T＜P＜100％×T。
又或者，当有上述像素电路的第一亚像素101需要显示的灰阶值L位于L0＜L＜L127时，可以在第一晶体管M1导通时间T内，数据线DL通过第一晶体管M1向第二晶体管M2的栅极提供的数据电压Vdata中，低电平VGL的时长P为0×T＜P＜50％×T。
上述是以第一亚像素101为例进行的说明，当控制第二亚像素102和第三亚像素103的灰阶时，类似地，可以控制第二亚像素102或第三亚像素103中的第一晶体管M1的栅极所电连接的第二栅线S在一行像素单元10的扫描时间内输出的上述第二扫描信号Scan_2的占空比。
根据本公开的另外的实施例，阵列基板包括栅极驱动电路。在一些实施例中，栅极驱动电路设置于阵列基板的布线区，布线区可以位于像素区周围。图14示意性地示出了栅极驱动电路的一个示例，包括第一栅极驱动子电路40和第二栅极驱动子电路41。第一栅极驱动子电路40与所述多条第一栅线电连接，以向所述多条第一栅线提供第一扫描信号，第二栅极驱动子电路41与所述多条第二栅线电连接，以向所述多条第二栅线提供第二扫描信号。上述第一栅极驱动子电路40和第二栅极驱动子电路41可以成IC(Integrated Circuit集成电路)的形式，并通过绑定(Bonding)工艺在设置于上述布线区。或者，还可以通过GOA(Gate Driver on Array，阵列基板行驱动)的方式制作于阵列基板01的玻璃衬底上。本申请对此不做限定。
以下对上述第一栅极驱动子电路40和第二栅极驱动子电路41进行详细的说明。
如图14所示，第一栅极驱动子电路40与各行像素单元对应的多条第一栅线G1电连接。所述多条第一栅线可包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线。第一栅极驱动子电路包括级联的多个第一移位寄存器，每个移位寄存器与一个栅线组电连接以向所述栅线组中的各条第一栅线同时提供第一扫描信号，所述第二栅极驱动子电路包括级联的多个第二移位寄存器，每个第二移位寄存器与一条第二栅线电连接以向第二栅线提供第二扫描信号。
如图14所示，该第一栅极驱动子电路40用于依次向多个栅线组(每个栅线组包括第一行第一栅线G1和第二行第一栅线G2)提供第一扫描信号Scan_1。第二栅极驱动子电路41与第二栅线(S1、S2......)电 连接。该第二栅极驱动子电路41用于依次向多条第二栅线(S1、S2......)提供第二扫描信号Scan_2。
在本申请的一些实施例中，如图14所示，上述第一栅极驱动子电路40包括多个级联的第一移位寄存器(RS_G_1、RS_G_2......)。每一级第一移位寄存器与一组栅线组20相电连接。不同的第一移位寄存器电连接的栅线组20不同。在此情况下，单个第一移位寄存器输出的第一扫描信号Scan_1，可以同时提供至该第一移位寄存器相电连接的栅线组20中的全部第一栅线(例如，G1和G2)。
此外，第二栅极驱动子电路41包括多个级联的第二移位寄存器(RS_S_1、RS_S_2......)，每一第二移位寄存器电连接一条第二栅线(S1、S2......)。在此情况下，单个的第二移位寄存器(例如RS_S_1)输出的第二扫描信号Scan_2，可以提供至一条与该第二移位寄存器(例如RS_S_1)电连接第二栅线(例如，S1)。
这里提到的移位寄存器指的是基于输入信号而产生相对于输入信号发生相位偏移的输出信号的电路，当移位寄存器应用于本公开的阵列基板时，其提供的输出信号即为本公开提到的第一扫描信号或第二扫描信号等。单个的移位寄存器的电路对于本领域技术人员而言是已知的，在此不再对其进行赘述。
在此基础上，为了减小上述阵列基板的布线区的尺寸，且使得显示区两侧的布线区的面积大小相同或近似相同。在本申请的一些实施例中，上述第一栅极驱动子电路40和第二栅极驱动子电路41，如图14所示，分别位于显示区的两侧。
在另外的实施例中，上述阵列基板还包括与数据线DL相电连接的源极驱动电路。由于位于同一栅线组20中的所有第一栅线G可以同时被扫描，因此，同一栅线组20中的各条第一栅线G所控制的亚像素分别接收不同的数据线DL输出的数据电压，以使得上述亚像素显示的灰阶数据能够独立控制。
本公开的另外的实施例提供了一种显示面板，该显示面板可包括前述的任一实施例所述的阵列基板。
对于本公开实施例提供的阵列基板，每一行像素单元中发光效率较低的第一亚像素电连接第一栅线，发光效率较高的第二亚像素和第三亚像素电连接第二栅线。在此情况下，可以分别向第一栅线和第二 栅线提供第一扫描信号和第二扫描信号。第一扫描信号的有效电平的时长大于第二扫描信号的有效电平的时长。这样一来，同一行像素单元中，第一亚像素的发光时间大于第二亚像素和第三亚像素的发光时间，因此可以对发光效率较低的第一亚像素的发光时间进行延长，以对该第一亚像素的发光亮度进行补偿，使得第一亚像素与第二亚像素、第三亚像素的发光亮度相同或近似相同，从而可以提升显示装置的显示效果。
需要说明的是，上述显示面板可以为有机发光二极管电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。上述显示面板具有与前述实施例提供的阵列基板相同的有益效果，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，包括：
    矩阵排列的多个像素单元，每个所述像素单元至少包括发光颜色不同的第一亚像素、第二亚像素和第三亚像素；
    与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第一栅线；
    与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第二栅线；
    其中所述矩阵排列的多个像素单元中的每一行像素单元中的第一亚像素电连接所述多条第一栅线中的一条第一栅线，所述矩阵排列的多个像素单元中的每一行像素单元中的第二亚像素和所述第三亚像素电连接所述多条第二栅线中的一条第二栅线。
  2. 根据权利要求1所述的阵列基板，其中所述多条第一栅线包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线，每个栅线组中的各条第一栅线被配置成接收同一扫描信号。
  3. 根据权利要求1所述的阵列基板，其中所述第一亚像素、第二亚像素和第三亚像素中的每个亚像素包括发光器件以及控制所述发光器件发光的像素电路，
    其中所述像素电路包括第一选通子电路、灰阶控制子电路以及驱动子电路，
    所述第一选通子电路与所述第一栅线和第二栅线中的一个、数据线、所述灰阶控制子电路电连接，所述第一选通子电路被配置成在所述第一栅线或第二栅线传输的扫描信号的控制下，将所述数据线输出的数据电压传输至所述灰阶控制子电路；
    所述驱动子电路与第一工作电压端、第二电压端和所述灰阶控制子电路电连接，所述驱动子电路被配置成在第二电压端输出的第二电压的控制下，向所述发光器件提供恒定的驱动电流，
    所述灰阶控制子电路还与所述发光器件和所述驱动子电路电连接，所述灰阶控制子电路被配置成根据所述数据电压而控制所述驱动电流流过所述发光器件的时长。
  4. 根据权利要求3所述的阵列基板，其中所述阵列基板还包括与 所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第三栅线，其中所述像素电路还包括第二选通子电路，所述第二选通子电路与所述第二电压端、所述驱动子电路以及所述多条栅线中的一条第三栅线电电连接，所述第二选通子电路被配置成在所述第三栅线传输的控制信号的控制下，将所述第二电压传输至所述驱动子电路。
  5. 根据权利要求3所述的阵列基板，其中所述第一选通子电路包括第一晶体管，所述第一晶体管的栅极电连接所述第一栅线或第二栅线，第一极电连接所述数据线，第二极与灰阶控制子电路电连接。
  6. 根据权利要求3所述的阵列基板，其中所述灰阶控制子电路包括第二晶体管，所述第二晶体管的栅极电连接所述第一选通子电路，第一极电连接所述驱动子电路，第二极电连接所述发光器件。
  7. 根据权利要求3所述的阵列基板，其中所述驱动子电路包括驱动晶体管，所述驱动晶体管的栅极电连接所述第二电压端，第一极电连接所述第一工作电压端，第二极电连接所述灰阶控制子电路。
  8. 根据权利要求4所述的阵列基板，其中所述第二选通子电路包括第三晶体管，所述第三晶体管的栅极电连接所述第三栅线，第一极电连接所述第二电压端，第二极电连接所述驱动子电路。
  9. 根据权利要求3所述的阵列基板，其中所述发光器件包括微型发光二极管，所述微型发光二极管第一端电连接至所述灰阶控制子电路，所述微型发光二极管的第二端电连接至参考电压端。
  10. 根据权利要求1-9中任一项所述的阵列基板，其中所述阵列基板包括栅极驱动电路，所述栅极驱动电路包括第一栅极驱动子电路和第二栅极驱动子电路，
    其中所述第一栅极驱动子电路与所述多条第一栅线电连接，以向所述多条第一栅线提供第一扫描信号；
    所述第二栅极驱动子电路与所述多条第二栅线电连接，以向所述多条第二栅线提供第二扫描信号。
  11. 根据权利要求10所述的阵列基板，其中所述多条第一栅线包括至少一个栅线组，每个栅线组包括至少两条相邻的第一栅线，
    其中所述第一栅极驱动子电路包括级联的多个第一移位寄存器，每个移位寄存器与一个栅线组电连接以向所述栅线组中的各条第一栅线同时提供第一扫描信号，所述第二栅极驱动子电路包括级联的多个 第二移位寄存器，每个第二移位寄存器与一条第二栅线电连接以向第二栅线提供第二扫描信号。
  12. 根据权利要求1所述的阵列基板，其中所述第一亚像素的发光效率低于所述第二亚像素和所述第三亚像素。
  13. 一种显示面板，包括如权利要求1-12中任一项所述的阵列基板。
  14. 一种如权利要求1-12中任一项所述的阵列基板的驱动方法，包括：
    依次向所述多条第一栅线中的各条第一栅线提供第一扫描信号，同时依次向所述多条第二栅线中的各条第二栅线提供第二扫描信号，。
  15. 根据权利要求14所述的驱动方法，其中所述多条第一栅线包括多个栅线组，每个栅线组包括N条相邻的第一栅线，N为大于等于2的整数，其中所述依次向所述多条第一栅线中的各条第一栅线提供第一扫描信号包括：
    依次向所述多个栅线组中的每个栅线组提供第一扫描信号，
    向每个栅线组提供所述第一扫描信号包括：同时向所述栅线组中的N条所述第一栅线提供所述第一扫描信号，
    其中，所述第二扫描信号的有效电平的时长为所述第一扫描信号的有效电平的时长的1/N。
  16. 根据权利要求14所述的驱动方法，其中所述第一亚像素、第二亚像素和第三亚像素中的每个亚像素包括发光器件以及控制所述发光器件发光的像素电路，所述像素电路包括第一选通子电路、灰阶控制子电路以及驱动子电路，其中所述驱动方法包括：
    所述第一选通子电路在所述第一栅线或第二栅线传输的第一扫描信号或第二扫描信号的控制下，将数据线输出的数据电压传输至所述灰阶控制子电路；
    所述驱动子电路产生提供给所述发光器件的恒定驱动电流；以及
    所述灰阶控制子电路根据所述数据电压控制所述驱动电流流过所述发光器件的时长。
  17. 根据权利要求16所述的驱动方法，其中所述阵列基板还包括与所述矩阵排列的多个像素单元中的各行像素单元分别对应的多条第三栅线，所述像素电路还包括第二选通子电路，第二选通子电路与所 述多条第三栅线中的一条第三栅线、第二电压端和所述驱动子电路电连接，其中所述驱动方法还包括：
    在所述第一选通子电路将数据线输出的数据电压传输至所述灰阶控制子电路之前，所述第二选通子电路在所述多条第三栅线中的一条第三栅线传输的控制信号的控制下，将所述第二电压端输出的第二电压传输至所述驱动子电路以启动所述驱动子电路产生所述驱动电流。
  18. 根据权利要求14所述的驱动方法，其中所述第一扫描信号的有效电平的时长大于所述第二扫描信号的有效电平的时长。
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US11869413B2 (en) 2018-06-28 2024-01-09 Boe Technology Group Co., Ltd. Pixel circuit, array substrate comprising the same and display panel

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CN111968569A (zh) 2020-11-20
US11315479B2 (en) 2022-04-26
US20210335213A1 (en) 2021-10-28
CN110021261A (zh) 2019-07-16
US20220180802A1 (en) 2022-06-09
US11869413B2 (en) 2024-01-09
CN111968569B (zh) 2021-11-16
CN110021261B (zh) 2020-11-03

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