WO2020228062A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

Info

Publication number
WO2020228062A1
WO2020228062A1 PCT/CN2019/088831 CN2019088831W WO2020228062A1 WO 2020228062 A1 WO2020228062 A1 WO 2020228062A1 CN 2019088831 W CN2019088831 W CN 2019088831W WO 2020228062 A1 WO2020228062 A1 WO 2020228062A1
Authority
WO
WIPO (PCT)
Prior art keywords
input terminal
module
node
data signal
driving circuit
Prior art date
Application number
PCT/CN2019/088831
Other languages
English (en)
French (fr)
Inventor
嘎拉图 苏日
江博仁
陈书志
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020228062A1 publication Critical patent/WO2020228062A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit and a display panel.
  • the organic light-emitting display panel uses organic light-emitting diodes (English full name: Organic Lighting Emitting Diode, abbreviated as: OLED) to display images. It is a display panel that actively emits light. Its display mode is different from that of a traditional liquid crystal display panel without a backlight. , And has many advantages such as high contrast, fast response, thin and light. Therefore, the organic light emitting display panel is a new generation display panel that can replace the liquid crystal display panel.
  • OLED Organic Lighting Emitting Diode
  • organic light-emitting display panels rely on current-driven light emission.
  • an active matrix driving method must be adopted, that is, it is necessary to directly provide driving current to the OLED. Therefore, when the OLED needs to emit light for a long time, the switching transistor used to drive the OLED must be used for a long time Keep on, but the switching transistor stays on for a long time, it will produce electrical and thermal bias. Under the stress of the electrical and thermal bias, the electrical performance of the switching transistor will change, thus affecting the OLED Luminous quality, in actual applications, there will be a problem of image retention on the display.
  • the switch transistor used to drive the OLED stays on for a long time, it will generate an electric bias and a thermal bias, which will cause the performance of the switch transistor to change, affect the luminous quality of the OLED, and display image afterimages in practical applications.
  • the problem When the switch transistor used to drive the OLED stays on for a long time, it will generate an electric bias and a thermal bias, which will cause the performance of the switch transistor to change, affect the luminous quality of the OLED, and display image afterimages in practical applications. The problem.
  • the present application provides a pixel driving circuit, including:
  • the first input module
  • a first drive module connected to the first input module
  • a second drive module connected to the second input module
  • a light emitting diode connected to the first driving module and the second driving module
  • the first input module controls the first driving module to drive the light emitting diode to emit light
  • the second input module controls the second driving module to drive the light emitting diode to emit light.
  • the first input module is connected to a first scan signal input terminal, a first data signal input terminal, and a first node, and the first scan signal input terminal inputs to the first input module A first scan signal, the first data signal input terminal inputs a first data signal to the first input module, and the first scan signal controls the first input module to transmit the first data signal to the The first node.
  • the first driving module is connected to the first node, the first voltage input terminal and the anode of the light emitting diode, and the first data signal of the first node controls the first
  • the driving module transmits the voltage input from the first voltage input terminal to the anode of the light emitting diode.
  • the second input module is connected to a second scan signal input terminal, a second data signal input terminal, and a second node, and the second scan signal input terminal inputs to the second input module
  • the second scan signal, the second data signal input terminal inputs a second data signal to the second input module, and the second scan signal controls the second input module to transmit the second data signal to the The second node.
  • the second driving module is connected to the second node, the first voltage input terminal and the anode of the light emitting diode, and the second data signal of the second node controls the second
  • the driving module transmits the voltage input from the first voltage input terminal to the anode of the light emitting diode.
  • the cathode of the light emitting diode is connected to the second voltage input terminal.
  • a first storage capacitor is connected between the first node and the first voltage input terminal for storing the first data signal of the first node
  • a second storage capacitor is connected between the second node and the first voltage input terminal for storing the second data signal of the second node.
  • a third storage capacitor is connected between the first node and the second node for storing the first data signal of the first node or the second node of the second node. Data signal.
  • the first scan signal input terminal is connected to a first scan line
  • the second scan signal input terminal is connected to a second scan line
  • the first data signal input terminal is connected to the second scan line.
  • the data signal input terminals are all connected to the first data line.
  • the first scan signal input terminal and the second scan signal input terminal are both connected to a first scan signal line, the first data signal input terminal is connected to a first data line, and the The second data signal input terminal is connected to the second data line.
  • the first input module includes a first switching transistor, the gate of the first switching transistor is connected to the first scanning signal input terminal, and the source of the first switching transistor is connected to At the first data signal input terminal, the drain of the first switch transistor is connected to the first node.
  • the first switching transistor is an n-type transistor or a p-type transistor.
  • the second input module includes a second switch transistor, the gate of the second switch transistor is connected to the second scan signal input terminal, and the source of the second switch transistor is connected to At the second data signal input terminal, the drain of the second switch transistor is connected to the second node.
  • the second switch transistor is an n-type transistor or a p-type transistor.
  • the first driving module includes a third switching transistor, the gate of the third switching transistor is connected to the first node, and the source of the third switching transistor is connected to the first node.
  • a voltage input terminal, the drain of the third switching crystal is connected to the anode of the light emitting diode.
  • the third switch transistor is an n-type transistor or a p-type transistor.
  • the second drive module includes a fourth switch transistor, the gate of the fourth switch transistor is connected to the second node, and the source of the fourth switch transistor is connected to the first node.
  • a voltage input terminal, the drain of the fourth switch transistor is connected to the anode of the light emitting diode.
  • the fourth switch transistor is an n-type transistor or a p-type transistor.
  • the voltage of the first voltage input terminal is greater than the voltage of the second voltage input terminal.
  • the present application also provides a display panel including the pixel driving circuit described above.
  • the pixel driving circuit and the display panel provided by the present application include a first input module, a second input module, a first driving module, a second driving module, and a light emitting diode.
  • the first input module and the first driving module form a first A driving group.
  • the second input module and the second driving module form a second driving group.
  • the first driving group and the second driving group can separately drive the light emitting diode to emit light; When the diode needs to emit light for a long time, the first driving group and the second driving group work alternately to prevent driving abnormalities caused by a single driving module for a long time, such as image sticking.
  • FIG. 1 and 2 are schematic diagrams of the structure of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit shown in FIG. 1 includes a first storage capacitor and a second storage capacitor, and the pixel driving circuit shown in FIG. 2 includes a second storage capacitor.
  • 3 and 4 are schematic diagrams of the pixel drive circuit structure of the first embodiment based on the pixel drive circuit shown in FIG. 1;
  • 5 and 6 are drive timing diagrams of the pixel drive circuit in the first implementation manner provided by the embodiments of the present application.
  • FIG. 7 and 8 are schematic diagrams of the pixel drive circuit structure of the second embodiment based on the pixel drive circuit shown in FIG. 1;
  • 9 and 10 are drive timing diagrams of the pixel drive circuit of the second implementation manner provided by the embodiments of the present application.
  • the embodiment of the application provides a pixel driving circuit for driving light-emitting diodes to emit light.
  • the pixel driving circuit includes a first driving group composed of a first input module and a first driving module, and a second input module and a first driving group.
  • a second driving group composed of two driving modules.
  • the first driving group and the second driving group can individually drive the light emitting diode to emit light; when the light emitting diode needs to emit light for a long time, the first driving The group and the second driving group work alternately to prevent driving abnormalities caused by long-time operation of a single driving module, such as image sticking.
  • FIG. 1 it is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit includes a first input module 101, a second input module 102, a first driving module 103, a second driving module 104, and Light-emitting diode 105.
  • the first input module 101 is connected to the first driving module 103, and the first driving module 103 is connected to the light emitting diode 105; the first input module 101 provides a control signal to the first driving module 103 , The first driving module 103 drives the light emitting diode 105 to emit light under the control of the control signal.
  • the control signal provided by the first input module 101 to the first driving module 103 is a voltage signal.
  • the second input module 102 is connected to the second driving module 104, and the second driving module 104 is connected to the light emitting diode 105; the second input module 102 provides control signals to the second driving module 104 , The second driving module 104 drives the light emitting diode 105 to emit light under the control of the control signal.
  • the control signal provided by the second input module 102 to the second driving module 104 is a voltage signal.
  • the first input module 101 and the first drive module 103 form a first drive group
  • the second input module 102 and the second drive module 104 form a second drive group
  • the first driving group and the second driving group may separately drive the light emitting diode 105 to emit light; when the light emitting diode 105 needs to emit light for a long time, the first driving group and the second driving group alternate
  • the first driving group drives the light-emitting diode 105 to emit light during the first T/2
  • the second driving group does not During the next T/2, the first driving group stops driving, and the second driving group drives the light-emitting diode 105 to emit light, so as to prevent driving abnormalities caused by a single driving module working for a long time , Which in turn leads to the problem of abnormal display and avoids the problem of image sticking caused by this.
  • the first input module 101 is respectively connected to a first scanning signal input terminal S1, a first data signal input terminal D1, and a first node A, and the first scanning
  • the signal input terminal S1 can provide a first scan signal to the first input module 101
  • the first data signal input terminal D1 can provide a first data signal to the first input module 101
  • the first input module 101 The first data signal is transmitted to the first node A under the control of the first scan signal.
  • the second input module 102 is respectively connected to the second scanning signal input terminal S2, the second data signal input terminal D2, and the second node B.
  • the second scanning signal input terminal S2 can be connected to the second input module 102 Provide a second scan signal, the second data signal input terminal D2 can provide a second data signal to the second input module 102, the second input module 102 under the control of the second scan signal
  • the second data signal is transmitted to the second node B.
  • the first driving module 103 is respectively connected to the first node A, the first voltage input terminal VDD, and the anode of the light emitting diode 105, and the first voltage input terminal VDD can provide the first driving module 103 A voltage signal, the first driving module 103 can transmit the voltage provided by the first voltage input terminal VDD to the anode of the light emitting diode 105 under the control of the first data signal of the first node A.
  • the second driving module 104 is respectively connected to the second node B, the first voltage input terminal VDD, and the anode of the light emitting diode 105, and the first voltage input terminal VDD can provide the second driving module 104 A voltage signal, the second driving module 104 can transmit the voltage provided by the first voltage input terminal VDD to the anode of the light emitting diode 105 under the control of the second data signal of the second node B.
  • the cathode of the light emitting diode 105 is connected to the second voltage input terminal VSS, and the light emitting diode 105 uses the voltage provided by the first voltage input terminal VDD and the second voltage input terminal VSS to emit light.
  • the first input module 101 is used to control the driving function of the first driving module 103 by providing a first data signal to the first node A, thereby controlling the light emitting diode 105
  • Light-emitting action that is, the light-emitting diode 105 can be controlled by the first driving group to emit light
  • the second input module 102 provides a second data signal to the second node B to control the second driving module 104, and then control the light-emitting action of the light-emitting diode 105, that is, the light-emitting diode 105 can be controlled by the second driving group to emit light
  • the light-emitting action of the light-emitting diode 105 can be controlled by all
  • the completion of the driving of the first driving group can also be completed by the second driving group.
  • the second driving group stops the driving function, and vice versa, thereby shortening
  • the working time of a single drive group can avoid display abnormalities caused by a long time work of a single drive group.
  • the pixel driving circuit further includes a storage capacitor for storing the data signal of the first node A or the second node B to control the first driving module 103 and/or the
  • the driving function of the second driving module 104 can be implemented in two manners according to the number of storage capacitors in the pixel driving circuit and the connection relationship with other components. The two implementation manners are separately introduced below:
  • the first implementation of the storage capacitor is the circuit structure shown in FIG. 1.
  • the pixel driving circuit includes a first storage capacitor C1 and a second storage capacitor C2, and the first storage capacitor C1 is connected to the first node. Between A and the first voltage input terminal VDD, for storing the first data signal of the first node A; the second storage capacitor C2 is connected between the second node B and the first voltage input Between the terminals VDD, the second data signal of the second node B is stored.
  • the second implementation of the storage capacitor is the circuit structure shown in FIG. 2.
  • the pixel driving circuit only includes a third storage capacitor C3, and the first storage capacitor C3 is connected between the first node A and the first node A and the first node A. Between two nodes B, it is used to store the data signal of the first node A or the second node B; compared with the circuit structure shown in FIG. 1, the circuit structure shown in FIG. 2 reduces the number of storage capacitors Therefore, the space occupied by the pixel driving circuit shown in FIG. 2 can be reduced, and the same effect as the pixel driving circuit shown in FIG. 1 can be achieved. It should be understood that, in the pixel driving circuit shown in FIG.
  • the line connecting the first node A and the third storage capacitor C3 is connected to the first voltage input terminal VDD and the first driver.
  • the wiring of the module 103 is a hollow circle, which means that the wiring connecting the first node A and the third storage capacitor C3 and connecting the The first voltage input terminal VDD crosses the connection line of the first driving module 103 but does not conduct.
  • the difference between the pixel driving circuit shown in FIG. 1 and the pixel driving circuit shown in FIG. 2 is only in the number of storage capacitors and the connection relationship, and the two can achieve the same driving effect.
  • the pixel shown in FIG. 1 The advantages of the driving circuit can also be embodied in the pixel driving circuit shown in FIG. 2; the following uses the pixel driving circuit shown in FIG. 1 as a basis to further explain the pixel driving circuit provided in the embodiment of the present application. It should be understood that, It can also be explained on the basis of the pixel drive circuit shown in FIG. 2. The difference between the two is only limited to the difference between the pixel drive circuit shown in FIG. 1 and the pixel drive circuit shown in FIG. The pixel driving circuit based on Figure 2 is no longer a separate example.
  • the first implementation is a first implementation:
  • the first scan signal input terminal S1 is connected to the first scan line Gate1
  • the second scan signal input terminal S2 is connected to the second scan line Gate2
  • the first data signal input terminal D1 is connected to the The second data signal input terminals D2 are all connected to the first data line Data1.
  • the first scan line Gate1 provides a first scan signal to the first input module 101 through the first scan signal input terminal S1, and the first data line Data1 transmits a first scan signal to the first input module 101 through the first data signal input terminal D1.
  • the first input module 101 provides a first data signal, and the first input module 101 transmits the first data signal to the first node A under the control of the first scan signal.
  • the second scan line Gate2 provides a second scan signal to the second input module 102 through the second scan signal input terminal S2, and the first data line Data1 transmits a second scan signal to the second input module 102 through the second data signal input terminal D2.
  • the second input module 102 provides a first data signal, and the second input module 102 transmits the first data signal to the second node B under the control of the second scan signal.
  • the first input module 101 includes a first switching transistor T1
  • the second input module 102 includes a second switching transistor T2
  • the first driving module 103 includes a third switching transistor.
  • T3 the second driving module 104 includes a fourth switch transistor T4.
  • the gate of the first switch transistor T1 is connected to the first scan signal input terminal S1
  • the source of the first switch transistor T1 is connected to the first data signal input terminal D1
  • the first switch transistor T1 The drain is connected to the first node A.
  • the gate of the second switch transistor T2 is connected to the second scan signal input terminal S2, the source of the second switch transistor T2 is connected to the second data signal input terminal D2, and the second switch transistor T2 The drain is connected to the second node B.
  • the gate of the third switching transistor T3 is connected to the first node A, the source of the third switching transistor T3 is connected to the first voltage input terminal VDD, and the drain of the third switching transistor T3 is connected to the The anode of the light-emitting diode 105.
  • the gate of the fourth switching transistor T4 is connected to the second node B, the source of the fourth switching transistor T4 is connected to the first voltage input terminal VDD, and the drain of the fourth switching transistor T4 is connected to the The anode of the light-emitting diode 105.
  • the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are n-type transistors or p-type transistors.
  • the switching transistors are all n-type transistors as an example. That is, when the gate of the switching transistor is high, the source and drain of the switching transistor are turned on. When it is extremely low, the source and drain of the switching transistor are disconnected.
  • FIG. 4 The working principle of the pixel driving circuit shown in FIG. 4 is described below with reference to FIGS. 5 and 6.
  • FIG. 5 is The signal timing diagram of the first scan signal S1', the second scan signal S2', and the first data signal D1' when the Nth frame is displayed.
  • FIG. 6 shows the first scan signal S1' when the N+ith frame is displayed.
  • the timings of the first scan signal S1', the second scan signal S2', and the first data signal D1' include a first time period t1 and a second time period t2;
  • the first scan signal S1' is at a high level
  • the second scan signal S2' is at a low level
  • the The first data signal D1' is the on-state voltage VGH
  • the first data signal D1' is transmitted to the first node A through the first switching transistor T1
  • the third switching transistor T3 is at the on-state voltage It turns on under the action of VGH, and transmits the voltage input from the first voltage input terminal VDD to the anode of the light emitting diode 105, and the light emitting diode 105 emits light.
  • the first scan signal S1' is at a low level
  • the second scan signal S2' is at a high level
  • the first data signal D1' is an off-state voltage VGL
  • the first data signal D1' is transmitted to the second node B through the second switching transistor T2, the fourth switching transistor T4 is turned off under the use of the off-state voltage VGL, and the light emitting diode 105 remains Glow.
  • the first scan signal S1' is at a high level, and the second scan signal S2' is at a low level,
  • the first data signal D1' is an off-state voltage VGL, the first data signal D1' is transmitted to the first node A through the first switching transistor T1, and the third switching transistor T3 is in the off state. Closed under the action of the state voltage VGL.
  • the first scan signal S1' is at a low level
  • the second scan signal S2' is at a high level
  • the first data signal D1' is an on-state voltage VGH
  • the first data signal D1' is transmitted to the second node B through the second switching transistor T2, and the fourth switching transistor T4 is turned on under the use of the off-on voltage VGH, and the first The voltage input from the voltage input terminal VDD is transmitted to the anode of the light emitting diode 105, and the light emitting diode 105 emits light.
  • the third switching transistor T3 continues to work in the first i frame and remains off in the next i frame, and the fourth switching transistor T4 and the The working state of the third switching transistor T3 remains opposite. While ensuring that the light emitting diode continues to emit light, the working time of the third switching transistor T3 and the fourth switching transistor T4 is halved to prevent the third switch
  • the transistor T3 or the fourth switching transistor T4 has a problem of electrical bias or thermal bias due to long-time operation, which improves the display effect of the light emitting diode 105.
  • the working time of the third switching transistor T3 and the fourth switching transistor T4 are both set to half of the light-emitting time of the light-emitting diode 105 in the above embodiment, they are not limited to the above setting.
  • the operating time of the third switching transistor T3 and the fourth switching transistor T4 is set to be unequal.
  • the operating time of the third switching transistor T3 and/or the fourth switching transistor T4 can also be divided into multiple segments, as long as The third switching transistor T3 and the fourth switching transistor T4 only need to work alternately, which is not limited by the application and its embodiments. It should be understood that all of the above setting methods can be set by adjusting the timing of the first scan signal S1', the second scan signal S2', and the first data signal D1'.
  • the first scan signal input terminal S1 and the second scan signal input terminal S2 are both connected to the first scan line Gate1, and the first data signal input terminal D1 is connected to the first data line Data1, so The second data signal input terminal D2 is connected to the second data line Data2.
  • the first scan line Gate1 provides a first scan signal to the first input module 101 through the first scan signal input terminal S1, and the first data line Data1 transmits a first scan signal to the first input module 101 through the first data signal input terminal D1.
  • the first input module 101 provides a first data signal, and the first input module 101 transmits the first data signal to the first node A under the control of the first scan signal.
  • the first scan line Gate1 provides a first scan signal to the second input module 102 through the second scan signal input terminal S2, and the second data line Data2 transmits a first scan signal to the second input module 102 through the second data signal input terminal D2.
  • the second input module 102 provides a second data signal, and the second input module 102 transmits the second data signal to the second node B under the control of the first scan signal.
  • the first input module 101 includes a first switching transistor T1
  • the second input module 102 includes a second switching transistor T2
  • the first driving module 103 includes a third switching transistor.
  • T3 the second driving module 104 includes a fourth switch transistor T4.
  • the gate of the first switch transistor T1 is connected to the first scan signal input terminal S1
  • the source of the first switch transistor T1 is connected to the first data signal input terminal D1
  • the first switch transistor T1 The drain is connected to the first node A.
  • the gate of the second switch transistor T2 is connected to the second scan signal input terminal S2, the source of the second switch transistor T2 is connected to the second data signal input terminal D2, and the second switch transistor T2 is The drain of is connected to the second node B.
  • the gate of the third switching transistor T3 is connected to the first node A, the source of the third switching transistor T3 is connected to the first voltage input terminal VDD, and the drain of the third switching transistor T3 is connected to the The anode of the light-emitting diode 105.
  • the gate of the fourth switching transistor T4 is connected to the second node B, the source of the fourth switching transistor T4 is connected to the first voltage input terminal VDD, and the drain of the fourth switching transistor T4 is connected to the The anode of the light-emitting diode 105.
  • the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, and the fourth switch transistor T4 are n-type transistors or p-type transistors.
  • the switching transistors are all n-type transistors as an example. That is, when the gate of the switching transistor is high, the source and drain of the switching transistor are turned on. When it is extremely low, the source and drain of the switching transistor are disconnected.
  • FIG. 9 is The signal timing diagram of the first scan signal S1', the first data signal D1', and the second data signal D2' when the Nth frame is displayed.
  • FIG. 10 is the first scan signal S1' when the N+ith frame is displayed.
  • the signal timing of the first scan signal S1', the first data signal D1', and the second data signal D2' includes a first time period t1 and a second time period t2;
  • the first scan signal S1' is at a high level
  • the first data signal D1' is an on-state voltage VGH
  • the second data signal D2' is an off-state voltage VGL
  • the first data signal D1' is transmitted to the first node A through the first switching transistor T1
  • the third switching transistor T3 is in the on-state
  • the voltage input by the first voltage input terminal VDD is transmitted to the anode of the light emitting diode 105, and the light emitting diode 105 emits light
  • the second data signal D2' passes through the second switch
  • the transistor T2 is transmitted to the second node B, and the fourth switch transistor T4 is turned off under the action of the off-state voltage VGL.
  • the first scan signal S1' is at a low level, and the first switching transistor T1 and the second switching transistor T2 are both turned off.
  • the first scan signal S1' is at a high level, and the first data signal D1' is an off-state voltage VGL ,
  • the second data signal D2' is an on-state voltage VGH, the first data signal D1' is transmitted to the first node A through the first switching transistor T1, and the third switching transistor T3 is in the Turn off under the action of the off-state voltage VGL;
  • the second data signal D2' is transmitted to the second node B through the second switch transistor T2, and the fourth switch transistor T4 acts on the on-state voltage VGH Turning on downward, the voltage input by the first voltage input terminal VDD is transmitted to the anode of the light emitting diode 105, and the light emitting diode 105 emits light.
  • the first scan signal S1' is at a low level, and the first switching transistor T1 and the second switching transistor T2 are both turned off.
  • the third switching transistor T3 continues to work in the first i frame and remains off in the next i frame, and the fourth switching transistor T4 and the The working state of the third switching transistor T3 remains opposite. While ensuring that the light emitting diode 105 continues to emit light, the working time of the third switching transistor T3 and the fourth switching transistor T4 is halved to prevent the third The switch transistor T3 or the fourth switch transistor T4 has a problem of electric bias or thermal bias due to long-time operation, which improves the display effect of the light emitting diode 105.
  • the working time of the third switching transistor T3 and the fourth switching transistor T4 are both set to half of the light-emitting time of the light-emitting diode 105 in the above embodiment, they are not limited to the above setting.
  • the operating time of the third switching transistor T3 and the fourth switching transistor T4 is set to be unequal.
  • the operating time of the third switching transistor T3 and/or the fourth switching transistor T4 can also be divided into multiple segments, as long as The third switching transistor T3 and the fourth switching transistor T4 only need to work alternately, which is not limited by the application and its embodiments. It should be understood that all of the above-mentioned setting methods can be set by adjusting the timing of the first scan signal S1', the first data signal D1', and the second data signal D2'.
  • an embodiment of the present application also provides a display panel including the above-mentioned pixel driving circuit.
  • a display panel including the above-mentioned pixel driving circuit.
  • the pixel driving circuit and the display panel provided by the embodiments of the present application include a first driving group composed of a first input module and the first driving module, and a second driving group composed of a second input module and the second driving module.
  • a driving group, the first driving group and the second driving group can separately drive the light emitting diode to emit light; when the light emitting diode needs to emit light for a long time, the first driving group and the second driving group Groups work alternately, thereby shortening the working time of a single drive group and preventing drive abnormalities caused by a single drive module working for a long time, such as image sticking.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路及显示面板，包括第一输入模块（101）、第二输入模块（102）、第一驱动模块（103）、第二驱动模块（104）以及发光二极管（105）。第一输入模块（101）和第一驱动模块（103）组成第一驱动组，第二输入模块（102）和第二驱动模块（104）组成第二驱动组，第一驱动组和第二驱动组可以分别单独驱动发光二极管（105）发光。当发光二极管（105）需要进行长时间发光时，第一驱动组和第二驱动组交替工作，防止因单一驱动模块长时间工作产生驱动异常，如出现画面残影等问题。

Description

像素驱动电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及显示面板。
 背景技术
有机发光显示面板利用有机发光二极管（英文全称：Organic Lighting Emitting Diode，简称：OLED）显示图像，是一种主动发光的显示面板，其显示方式与传统的液晶显示面板的显示方式不同，无需背光灯，而且具有对比度高、响应速度快、轻薄等诸多优点。因此，有机发光显示面板为可以取代液晶显示面板的新一代显示面板。
与液晶显示面板的电压驱动发光不同，有机发光显示面板依靠电流驱动发光。为了达到更高的分辨率、亮度及画质，须采用主动矩阵的驱动方式，即需要直接向OLED提供驱动电流，因此，当需要OLED长时间发光时，用于驱动OLED的开关晶体管必须长时间保持开态，但开关晶体管长时间保持开态工作，会产生电偏压及热偏压，在电偏压及热偏压的应力作用下，开关晶体管的电学性能会发生改变，从而影响OLED的发光质量，在实际应用中会出现显示画面残影的问题。
 技术问题
用于驱动OLED的开光晶体管长时间保持开态工作时，会产生电偏压及热偏压，从而导致开关晶体管的性能发生改变，影响OLED的发光质量，在实际应用中会出现显示画面残影的问题。
 技术解决方案
为了解决上述技术问题，本申请提供的技术方案如下：
本申请提供了一种像素驱动电路，包括：
第一输入模块；
第一驱动模块，与所述第一输入模块连接；
第二输入模块；
第二驱动模块，与所述第二输入模块连接；以及
发光二极管，与所述第一驱动模块和所述第二驱动模块连接；
所述第一输入模块控制所述第一驱动模块驱动所述发光二极管发光；
所述第二输入模块控制所述第二驱动模块驱动所述发光二极管发光。
在本申请的像素驱动电路中，所述第一输入模块连接第一扫描信号输入端、第一数据信号输入端及第一节点，所述第一扫描信号输入端向所述第一输入模块输入第一扫描信号，所述第一数据信号输入端向所述第一输入模块输入第一数据信号，所述第一扫描信号控制所述第一输入模块将所述第一数据信号传输至所述第一节点。
在本申请的像素驱动电路中，所述第一驱动模块连接所述第一节点、第一电压输入端及所述发光二极管的阳极，所述第一节点的第一数据信号控制所述第一驱动模块将所述第一电压输入端输入的电压传输至所述发光二极管的阳极。
在本申请的像素驱动电路中，所述第二输入模块连接第二扫描信号输入端、第二数据信号输入端及第二节点，所述第二扫描信号输入端向所述第二输入模块输入第二扫描信号，所述第二数据信号输入端向所述第二输入模块输入第二数据信号，所述第二扫描信号控制所述第二输入模块将所述第二数据信号传输至所述第二节点。
在本申请的像素驱动电路中，所述第二驱动模块连接所述第二节点、第一电压输入端及所述发光二极管的阳极，所述第二节点的第二数据信号控制所述第二驱动模块将所述第一电压输入端输入的电压传输至所述发光二极管的阳极。
在本申请的像素驱动电路中，所述发光二极管的阴极连接第二电压输入端。
在本申请的像素驱动电路中，所述第一节点与所述第一电压输入端之间连接第一存储电容，用于存储所述第一节点的第一数据信号；
所述第二节点与所述第一电压输入端之间连接第二存储电容，用于存储所述第二节点的第二数据信号。
在本申请的像素驱动电路中，所述第一节点与所述第二节点之间连接第三存储电容，用于存储所述第一节点的第一数据信号或所述第二节点的第二数据信号。
在本申请的像素驱动电路中，所述第一扫描信号输入端连接第一扫描线，所述第二扫描信号输入端连接第二扫描线，所述第一数据信号输入端与所述第二数据信号输入端均连接第一数据线。
在本申请的像素驱动电路中，所述第一扫描信号输入端与所述第二扫描信号输入端均连接第一扫描信号线，所述第一数据信号输入端连接第一数据线，所述第二数据信号输入端连接第二数据线。
在本申请的像素驱动电路中，所述第一输入模块包括第一开关晶体管，所述第一开关晶体管的栅极连接所述第一扫描信号输入端，所述第一开关晶体管的源极连接所述第一数据信号输入端，所述第一开关晶体管的漏极连接所述第一节点。
在本申请的像素驱动电路中，所述第一开关晶体管为n型晶体管或p型晶体管。
在本申请的像素驱动电路中，所述第二输入模块包括第二开关晶体管，所述第二开关晶体管的栅极连接所述第二扫描信号输入端，所述第二开关晶体管的源极连接所述第二数据信号输入端，所述第二开关晶体管的漏极连接所述第二节点。
在本申请的像素驱动电路中，所述第二开关晶体管为n型晶体管或p型晶体管。
在本申请的像素驱动电路中，所述第一驱动模块包括第三开关晶体管，所述第三开关晶体管的栅极连接所述第一节点，所述第三开关晶体管的源极连接所述第一电压输入端，所述第三开关晶体的漏极连接所述发光二极管的阳极。
在本申请的像素驱动电路中，所述第三开关晶体管为n型晶体管或p型晶体管。
在本申请的像素驱动电路中，所述第二驱动模块包括第四开关晶体管，所述第四开关晶体管的栅极连接所述第二节点，所述第四开关晶体管的源极连接所述第一电压输入端，所述第四开关晶体管的漏极连接所述发光二极管的阳极。
在本申请的像素驱动电路中，所述第四开关晶体管为n型晶体管或p型晶体管。
在本申请的像素驱动电路中，所述第一电压输入端的电压大于所述第二电压输入端的电压。
本申请还提供了一种显示面板，包括如上所述的像素驱动电路。
 有益效果
本申请提供的像素驱动电路及显示面板，包括第一输入模块、第二输入模块、第一驱动模块、第二驱动模块以及发光二极管，所述第一输入模块和所述第一驱动模块组成第一驱动组，所述第二输入模块和所述第二驱动模块组成第二驱动组，所述第一驱动组和所述第二驱动组可以分别单独驱动所述发光二极管发光；当所述发光二极管需要进行长时间发光时，所述第一驱动组和所述第二驱动组交替工作，防止因单一驱动模块长时间工作产生驱动异常，如出现画面残影等问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1和图2是本申请实施例提供的像素驱动电路的结构示意图，其中，图1所示的像素驱动电路包括第一存储电容和第二存储电容，图2所示的像素驱动电路包括第三存储电容；
图3和图4是以图1所示的像素驱动电路为基础的第一种实施方式的像素驱动电路结构示意图；
图5和图6是本申请实施例提供的第一种实施方式的像素驱动电路的驱动时序图；
图7和图8是以图1所示的像素驱动电路为基础的第二种实施方式的像素驱动电路结构示意图；
图9和图10是本申请实施例提供的第二种实施方式的像素驱动电路的驱动时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供了一种像素驱动电路，用于驱动发光二极管发光，所述像素驱动电路包括由第一输入模块和第一驱动模块组成的第一驱动组，及由第二输入模块和第二驱动模块组成的第二驱动组，所述第一驱动组和所述第二驱动组可以分别单独驱动所述发光二极管发光；当所述发光二极管需要进行长时间发光时，所述第一驱动组和所述第二驱动组交替工作，防止因单一驱动模块长时间工作导致驱动异常，如出现画面残影等问题。
下面结合附图对本申请实施例提供的像素驱动电路进行具体说明：
如图1所示，是本申请一实施例提供的像素驱动电路示意图，所述像素驱动电路包括第一输入模块101、第二输入模块102、第一驱动模块103、第二驱动模块104、以及发光二极管105。
所述第一输入模块101与所述第一驱动模块103连接，所述第一驱动模块103与所述发光二极管105连接；所述第一输入模块101向所述第一驱动模块103提供控制信号，所述第一驱动模块103在所述控制信号的控制下驱动所述发光二极管105发光。可选地，所述第一输入模块101向所述第一驱动模块103提供的控制信号为电压信号。
所述第二输入模块102与所述第二驱动模块104连接，所述第二驱动模块104与所述发光二极管105连接；所述第二输入模块102向所述第二驱动模块104提供控制信号，所述第二驱动模块104在所述控制信号的控制下驱动所述发光二极管105发光。可选地，所述第二输入模块102向所述第二驱动模块104提供的控制信号为电压信号。
根据本申请一实施例，所述第一输入模块101与所述第一驱动模块103组成第一驱动组，所述第二输入模块102与所述第二驱动模块104组成第二驱动组，所述第一驱动组和所述第二驱动组可以分别单独驱动所述发光二极管105发光；当所述发光二极管105需要进行长时间发光时，所述第一驱动组与所述第二驱动组交替工作，例如，当所述发光二极管105需要进行的连续发光时间为T，在前T/2的时间内，由所述第一驱动组驱动所述发光二极管105发光，所述第二驱动组不进行驱动工作，在后T/2的时间内，所述第一驱动组停止驱动工作，由所述第二驱动组驱动所述发光二极管105发光，从而防止因单一驱动模块长时间工作产生驱动异常，进而导致显示异常的问题，避免因此而产生的画面残影的问题。
根据本申请一实施例，如图1所示，所述第一输入模块101分别与第一扫面信号输入端S1、第一数据信号输入端D1及第一节点A连接，所述第一扫描信号输入端S1可以向所述第一输入模块101提供第一扫描信号，所述第一数据信号输入端D1可以向所述第一输入模块101提供第一数据信号，所述第一输入模块101在所述第一扫描信号的控制下将所述第一数据信号传输至所述第一节点A。
所述第二输入模块102分别与第二扫面信号输入端S2、第二数据信号输入端D2及第二节点B连接，所述第二扫描信号输入端S2可以向所述第二输入模块102提供第二扫描信号，所述第二数据信号输入端D2可以向所述第二输入模块102提供第二数据信号，所述第二输入模块102在所述第二扫描信号的控制下将所述第二数据信号传输至所述第二节点B。
所述第一驱动模块103分别与所述第一节点A、第一电压输入端VDD及所述发光二极管105的阳极连接，所述第一电压输入端VDD可以向所述第一驱动模块103提供电压信号，所述第一驱动模块103可以在所述第一节点A的第一数据信号的控制下，将所述第一电压输入端VDD提供的电压传输至所述发光二极管105的阳极。
所述第二驱动模块104分别与所述第二节点B、第一电压输入端VDD及所述发光二极管105的阳极连接，所述第一电压输入端VDD可以向所述第二驱动模块104提供电压信号，所述第二驱动模块104可以在所述第二节点B的第二数据信号的控制下，将所述第一电压输入端VDD提供的电压传输至所述发光二极管105的阳极。
所述发光二极管105的阴极连接第二电压输入端VSS，所述发光二极管105利用所述第一电压输入端VDD及所述第二电压输入端VSS提供的电压进行发光。
根据本申请一实施例，所述第一输入模块101通过向所述第一节点A提供第一数据信号，用于控制所述第一驱动模块103的驱动功能，进而控制所述发光二极管105的发光动作，即所述发光二极管105可以被所述第一驱动组控制发光；所述第二输入模块102通过向所述第二节点B提供第二数据信号，用于控制所述第二驱动模块104的驱动功能，进而控制所述发光二极管105的发光动作，即所述发光二极管105可以被所述第二驱动组控制发光；综上所述，所述发光二极管105的发光动作，可以由所述第一驱动组驱动完成，也可以由第二驱动组驱动完成，当所述第一驱动组驱动所述发光二极管105发光时，所述第二驱动组停止驱动功能，反之亦然，从而缩短单一驱动组的工作时间，避免因单一驱动组长时间工作导致的显示异常。
根据本申请一实施例，所述像素驱动电路还包括存储电容，用于存储所述第一节点A或所述第二节点B的数据信号，以控制所述第一驱动模块103和/或所述第二驱动模块104的驱动功能，根据所述像素驱动电路中的存储电容的数量和与其它元件的连接关系可以有两种实施方式，下面对这两种实施方式分别进行介绍：
存储电容的第一种实施方式是如图1所示的电路结构，所述像素驱动电路包括第一存储电容C1和第二存储电容C2，所述第一存储电容C1连接在所述第一节点A和所述第一电压输入端VDD之间，用于存储所述第一节点A的第一数据信号；所述第二存储电容C2连接在所述第二节点B和所述第一电压输入端VDD之间，用于存储所述第二节点B的第二数据信号。
存储电容的第二种实施方式是如图2所示的电路结构，所述像素驱动电路仅包括第三存储电容C3，所述第一存储电容C3连接在所述第一节点A和所述第二节点B之间，用于存储所述第一节点A或所述第二节点B的数据信号；与图1所示的电路结构相比，图2所示的电路结构减少了存储电容的数量，从而可以减小图2所示的像素驱动电路所占据的空间，且可以达到与图1所示的像素驱动电路相同的效果。应当理解的是，图2所示的像素驱动电路中，连接所述第一节点A与所述第三存储电容C3的连线，与连接所述第一电压输入端VDD与所述第一驱动模块103的连线相较于第三节点C，所述第三节点C为空心圆圈，其意思表示是，连接所述第一节点A与所述第三存储电容C3的连线和连接所述第一电压输入端VDD与所述第一驱动模块103的连线相交但不导通。
需要说明的是，图1所示的像素驱动电路与图2所示的像素驱动电路的区别仅在于存储电容的数量和连接关系不同，二者可以达到相同的驱动效果，图1所示的像素驱动电路的优势在图2所述的像素驱动电路中同样可以体现；下面以图1所示的像素驱动电路为基础，对本申请实施例提供的像素驱动电路进行进一步的阐述，应当理解的是，同样可以以图2所示的像素驱动电路为基础进行阐述，二者的区别仅止于如上所述的图1所示的像素驱动电路与图2所示的像素驱动电路之间的区别，因此对于以图2为基础的像素驱动电路不再单独示例。
在以图1所示的像素驱动电路为基础的前提下，根据像素驱动电路与数据线和扫描线的连接关系，可以存在以下两种实施方式：
第一种实施方式：
如图3所示，所述第一扫描信号输入端S1连接第一扫描线Gate1，所述第二扫描信号输入端S2连接第二扫描线Gate2，所述第一数据信号输入端D1与所述第二数据信号输入端D2均连接第一数据线Data1。
所述第一扫描线Gate1通过所述第一扫描信号输入端S1向所述第一输入模块101提供第一扫描信号，所述第一数据线Data1通过所述第一数据信号输入端D1向所述第一输入模块101提供第一数据信号，所述第一输入模块101在所述第一扫描信号的控制下，将所述第一数据信号传输至所述第一节点A。
所述第二扫描线Gate2通过所述第二扫描信号输入端S2向所述第二输入模块102提供第二扫描信号，所述第一数据线Data1通过所述第二数据信号输入端D2向所述第二输入模块102提供第一数据信号，所述第二输入模块102在所述第二扫描信号的控制下，将所述第一数据信号传输至所述第二节点B。
可选地，如图4所示，所述第一输入模块101包括第一开关晶体管T1，所述第二输入模块102包括第二开关晶体管T2，所述第一驱动模块103包括第三开关晶体管T3，所述第二驱动模块104包括第四开关晶体管T4。
所述第一开关晶体管T1的栅极连接所述第一扫描信号输入端S1，所述第一开关晶体管T1的源极连接所述第一数据信号输入端D1，所述第一开关晶体管T1的漏极连接所述第一节点A。
所述第二开关晶体管T2的栅极连接所述第二扫描信号输入端S2，所述第二开关晶体管T2的源极连接所述第二数据信号输入端D2，所述第二开关晶体管T2的漏极连接所述第二节点B。
所述第三开关晶体管T3的栅极连接所述第一节点A，所述第三开关晶体管T3的源极连接所述第一电压输入端VDD，所述第三开关晶体T3的漏极连接所述发光二极管105的阳极。
所述第四开关晶体管T4的栅极连接所述第二节点B，所述第四开关晶体管T4的源极连接所述第一电压输入端VDD，所述第四开关晶体管T4的漏极连接所述发光二极管105的阳极。
可选地，所述第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3和第四开关晶体管T4为n型晶体管或p型晶体管。下面以所述开关晶体管均为n型晶体管为例进行说明，即，当所述开光晶体管的栅极为高电平时，所述开光晶体管的源极与漏极导通，当所述开关晶体管的栅极为低电平时，所述开关晶体管的源极与漏极断开。
下面结合图5、图6介绍图4所示的像素驱动电路的工作原理，以所述发光二极管105在第N帧开始发光，且持续发光至第N+2i帧为例，其中，图5为第N帧显示时所述第一扫描信号S1’、第二扫描信号S2’和第一数据信号D1’的信号时序图，图6为第N+i帧显示时所述第一扫描信号S1’、第二扫描信号S2’和第一数据信号D1’的信号时序图：
所述第一扫描信号S1’、所述第二扫描信号S2’和所述第一数据信号D1’的时序包括第一时间段t1和第二时间段t2；其中，
在第N帧时，如图5所示，在所述第一时间段t1内，所述第一扫描信号S1’为高电平，所述第二扫描信号S2’为低电平，所述第一数据信号D1’为开态电压VGH，所述第一数据信号D1’通过所述第一开关晶体管T1传输至所述第一节点A，所述第三开光晶体管T3在所述开态电压VGH的作用下开启，将所述第一电压输入端VDD输入的电压传输至所述发光二极管105的阳极，所述发光二极管105发光。
在所述第二时间段t2内，所述第一扫描信号S1’为低电平，所述第二扫描信号S2’为高电平，所述第一数据信号D1’为关态电压VGL，所述第一数据信号D1’通过所述第二开关晶体管T2传输至所述第二节点B，所述第四开光晶体管T4在所述关态电压VGL的所用下关闭，所述发光二极管105保持发光。
在第N+i帧时，如图6所示，在所述第一时间段t1内，所述第一扫描信号S1’为高电平，所述第二扫描信号S2’为低电平，所述第一数据信号D1’为关态电压VGL，所述第一数据信号D1’通过所述第一开关晶体管T1传输至所述第一节点A，所述第三开光晶体管T3在所述关态电压VGL的作用下关闭。
在所述第二时间段t2内，所述第一扫描信号S1’为低电平，所述第二扫描信号S2’为高电平，所述第一数据信号D1’为开态电压VGH，所述第一数据信号D1’通过所述第二开关晶体管T2传输至所述第二节点B，所述第四开光晶体管T4在所述关开态电压VGH的所用下开启，将所述第一电压输入端VDD输入的电压传输至所述发光二极管105的阳极，所述发光二极管105发光。
上述实施例中，在所述发光二极管105持续发光的2i帧时间内，所述第三开关晶体管T3在前i帧持续工作，在后i帧保持关闭，所述第四开关晶体管T4与所述第三开关晶体管T3的工作状态保持相反，在保证所述发光二极管持续发光的同时，将所述第三开关晶体管T3和所述第四开光晶体管T4的工作时间减半，防止所述第三开关晶体管T3或所述第四开关晶体管T4因长时间工作产生电偏压或热偏压的问题，提高所述发光二极管105的显示效果。
应当理解的是，虽然上述实施例将所述第三开关晶体管T3和第四开关晶体管T4的工作时间均设置为所述发光二极管105发光时间的一半，但并不仅限于上述设置，例如，还可以将所述第三开关晶体管T3和第四开关晶体管T4的工作时间设置为不相等，另外也可以将所述第三开关晶体管T3和/或第四开关晶体管T4的工作时间分为多段，只要满足所述第三开关晶体管T3和第四开关晶体管T4交替工作即可，本申请及其实施例对此不做限制。应当理解的是，上述设置方式均可以通过调整所述第一扫描信号S1’、第二扫描信号S2’和第一数据信号D1’的时序进行设置。
第二种实施方式：
如图7所示，所述第一扫描信号输入端S1与所述第二扫描信号输入端S2均连接第一扫描线Gate1，所述第一数据信号输入端D1连接第一数据线Data1，所述第二数据信号输入端D2连接第二数据线Data2。
所述第一扫描线Gate1通过所述第一扫描信号输入端S1向所述第一输入模块101提供第一扫描信号，所述第一数据线Data1通过所述第一数据信号输入端D1向所述第一输入模块101提供第一数据信号，所述第一输入模块101在所述第一扫描信号的控制下，将所述第一数据信号传输至所述第一节点A。
所述第一扫描线Gate1通过所述第二扫描信号输入端S2向所述第二输入模块102提供第一扫描信号，所述第二数据线Data2通过所述第二数据信号输入端D2向所述第二输入模块102提供第二数据信号，所述第二输入模块102在所述第一扫描信号的控制下，将所述第二数据信号传输至所述第二节点B。
可选地，如图8所示，所述第一输入模块101包括第一开关晶体管T1，所述第二输入模块102包括第二开关晶体管T2，所述第一驱动模块103包括第三开关晶体管T3，所述第二驱动模块104包括第四开关晶体管T4。
所述第一开关晶体管T1的栅极连接所述第一扫描信号输入端S1，所述第一开关晶体管T1的源极连接所述第一数据信号输入端D1，所述第一开关晶体管T1的漏极连接所述第一节点A。
所述第二开关晶体管T2的栅极连接所述第二扫描信号输入端S2，所述第二开关晶体管T2的源极连接所述第二数据信号输入端D2，所述第二开关晶体T2管的漏极连接所述第二节点B。
所述第三开关晶体管T3的栅极连接所述第一节点A，所述第三开关晶体管T3的源极连接所述第一电压输入端VDD，所述第三开关晶体T3的漏极连接所述发光二极管105的阳极。
所述第四开关晶体管T4的栅极连接所述第二节点B，所述第四开关晶体管T4的源极连接所述第一电压输入端VDD，所述第四开关晶体管T4的漏极连接所述发光二极管105的阳极。
可选地，所述第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3和第四开关晶体管T4为n型晶体管或p型晶体管。下面以所述开关晶体管均为n型晶体管为例进行说明，即，当所述开光晶体管的栅极为高电平时，所述开光晶体管的源极与漏极导通，当所述开关晶体管的栅极为低电平时，所述开关晶体管的源极与漏极断开。
下面结合图9、图10介绍图8所示的像素驱动电路的工作原理，以所述发光二极管105在第N帧开始发光，且持续发光至第N+2i帧为例，其中，图9为第N帧显示时所述第一扫描信号S1’、第一数据信号D1’和第二数据信号D2’的信号时序图，图10为第N+i帧显示时所述第一扫描信号S1’、第一数据信号D1’和第二数据信号D2’的信号时序图：
所述第一扫描信号S1’、第一数据信号D1’和第二数据信号D2’的信号时序包括第一时间段t1和第二时间段t2；其中，
在第N帧时，如图9所示，在所述第一时间段t1内，所述第一扫描信号S1’为高电平，所述第一数据信号D1’为开态电压VGH，所述第二数据信号D2’为关态电压VGL，所述第一数据信号D1’通过所述第一开关晶体管T1传输至所述第一节点A，所述第三开光晶体管T3在所述开态电压VGH的作用下开启，将所述第一电压输入端VDD输入的电压传输至所述发光二极管105的阳极，所述发光二极管105发光；所述第二数据信号D2’通过所述第二开关晶体管T2传输至所述第二节点B，所述第四开光晶体管T4在所述关态电压VGL的作用下关闭。
在所述第二时间段t2内，所述第一扫描信号S1’为低电平，所述第一开关晶体管T1和所述第二开关晶体管T2均关闭。
在第N+i帧时，如图10所示，在所述第一时间段t1内，所述第一扫描信号S1’为高电平，所述第一数据信号D1’为关态电压VGL，所述第二数据信号D2’为开态电压VGH，所述第一数据信号D1’通过所述第一开关晶体管T1传输至所述第一节点A，所述第三开光晶体管T3在所述关态电压VGL的作用下关闭；所述第二数据信号D2’通过所述第二开关晶体管T2传输至所述第二节点B，所述第四开光晶体管T4在所述开态电压VGH的作用下开启，将所述第一电压输入端VDD输入的电压传输至所述发光二极管105的阳极，所述发光二极管105发光。
在所述第二时间段t2内，所述第一扫描信号S1’为低电平，所述第一开关晶体管T1和所述第二开关晶体管T2均关闭。
上述实施例中，在所述发光二极管105持续发光的2i帧时间内，所述第三开关晶体管T3在前i帧持续工作，在后i帧保持关闭，所述第四开关晶体管T4与所述第三开关晶体管T3的工作状态保持相反，在保证所述发光二极管105持续发光的同时，将所述第三开关晶体管T3和所述第四开光晶体管T4的工作时间减半，防止所述第三开关晶体管T3或所述第四开关晶体管T4因长时间工作产生电偏压或热偏压的问题，提高所述发光二极管105的显示效果。
应当理解的是，虽然上述实施例将所述第三开关晶体管T3和第四开关晶体管T4的工作时间均设置为所述发光二极管105发光时间的一半，但并不仅限于上述设置，例如，还可以将所述第三开关晶体管T3和第四开关晶体管T4的工作时间设置为不相等，另外也可以将所述第三开关晶体管T3和/或第四开关晶体管T4的工作时间分为多段，只要满足所述第三开关晶体管T3和第四开关晶体管T4交替工作即可，本申请及其实施例对此不做限制。应当理解的是，上述设置方式均可以通过调整所述第一扫描信号S1’、第一数据信号D1’和第二数据信号D2’的时序进行设置。
基于同样的申请构思，本申请实施例还提供了一种显示面板，包括以上所述的像素驱动电路，具体可参照以上所述的像素驱动电路，在此不做赘述。
本申请实施例提供的像素驱动电路及显示面板，包括由第一输入模块和所述第一驱动模块组成的第一驱动组，及由第二输入模块和所述第二驱动模块组成的第二驱动组，所述第一驱动组和所述第二驱动组可以分别单独驱动所述发光二极管发光；当所述发光二极管需要进行长时间发光时，所述第一驱动组和所述第二驱动组交替工作，从而缩短单一驱动组的工作时间，防止因单一驱动模块长时间工作导致的驱动异常，如产生画面残影等问题。
综上所述，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定发范围为准。

Claims (20)

  1. 一种像素驱动电路，包括：
    第一输入模块；
    第一驱动模块，与所述第一输入模块连接；
    第二输入模块；
    第二驱动模块，与所述第二输入模块连接；以及
    发光二极管，与所述第一驱动模块和所述第二驱动模块连接；
    所述第一输入模块控制所述第一驱动模块驱动所述发光二极管发光；
    所述第二输入模块控制所述第二驱动模块驱动所述发光二极管发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第一输入模块连接第一扫描信号输入端、第一数据信号输入端及第一节点，所述第一扫描信号输入端向所述第一输入模块输入第一扫描信号，所述第一数据信号输入端向所述第一输入模块输入第一数据信号，所述第一扫描信号控制所述第一输入模块将所述第一数据信号传输至所述第一节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一驱动模块连接所述第一节点、第一电压输入端及所述发光二极管的阳极，所述第一节点的第一数据信号控制所述第一驱动模块将所述第一电压输入端输入的电压传输至所述发光二极管的阳极。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第二输入模块连接第二扫描信号输入端、第二数据信号输入端及第二节点，所述第二扫描信号输入端向所述第二输入模块输入第二扫描信号，所述第二数据信号输入端向所述第二输入模块输入第二数据信号，所述第二扫描信号控制所述第二输入模块将所述第二数据信号传输至所述第二节点。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第二驱动模块连接所述第二节点、第一电压输入端及所述发光二极管的阳极，所述第二节点的第二数据信号控制所述第二驱动模块将所述第一电压输入端输入的电压传输至所述发光二极管的阳极。
  6. 根据权利要求5所述的像素驱动电路，其中，所述发光二极管的阴极连接第二电压输入端。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第一节点与所述第一电压输入端之间连接第一存储电容，用于存储所述第一节点的第一数据信号；
    所述第二节点与所述第一电压输入端之间连接第二存储电容，用于存储所述第二节点的第二数据信号。
  8. 根据权利要求6所述的像素驱动电路，其中，所述第一节点与所述第二节点之间连接第三存储电容，用于存储所述第一节点的第一数据信号或所述第二节点的第二数据信号。
  9. 根据权利要求6所述的像素驱动电路，其中，所述第一扫描信号输入端连接第一扫描线，所述第二扫描信号输入端连接第二扫描线，所述第一数据信号输入端与所述第二数据信号输入端均连接第一数据线。
  10. 根据权利要求6所述的像素驱动电路，其中，所述第一扫描信号输入端与所述第二扫描信号输入端均连接第一扫描信号线，所述第一数据信号输入端连接第一数据线，所述第二数据信号输入端连接第二数据线。
  11. 根据权利要求6所述的像素驱动电路，其中，所述第一输入模块包括第一开关晶体管，所述第一开关晶体管的栅极连接所述第一扫描信号输入端，所述第一开关晶体管的源极连接所述第一数据信号输入端，所述第一开关晶体管的漏极连接所述第一节点。
  12. 根据权利要求11所述的像素驱动电路，其中，所述第一开关晶体管为n型晶体管或p型晶体管。
  13. 根据权利要求6所述的像素驱动电路，其中，所述第二输入模块包括第二开关晶体管，所述第二开关晶体管的栅极连接所述第二扫描信号输入端，所述第二开关晶体管的源极连接所述第二数据信号输入端，所述第二开关晶体管的漏极连接所述第二节点。
  14. 根据权利要求13所述的像素驱动电路，其中，所述第二开关晶体管为n型晶体管或p型晶体管。
  15. 根据权利要求6所述的像素驱动电路，其中，所述第一驱动模块包括第三开关晶体管，所述第三开关晶体管的栅极连接所述第一节点，所述第三开关晶体管的源极连接所述第一电压输入端，所述第三开关晶体的漏极连接所述发光二极管的阳极。
  16. 根据权利要求15所述的像素驱动电路，其中，所述第三开关晶体管为n型晶体管或p型晶体管。
  17. 根据权利要求6所述的像素驱动电路，其中，所述第二驱动模块包括第四开关晶体管，所述第四开关晶体管的栅极连接所述第二节点，所述第四开关晶体管的源极连接所述第一电压输入端，所述第四开关晶体管的漏极连接所述发光二极管的阳极。
  18. 根据权利要求17所述的像素驱动电路，其中，所述第四开关晶体管为n型晶体管或p型晶体管。
  19. 根据权利要求6所述的像素驱动电路，其中，所述第一电压输入端的电压大于所述第二电压输入端的电压。
  20. 一种显示面板，包括权利要求1-19任一项所述的像素驱动电路。
PCT/CN2019/088831 2019-05-14 2019-05-28 像素驱动电路及显示面板 WO2020228062A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910396574.8 2019-05-14
CN201910396574.8A CN110189691B (zh) 2019-05-14 2019-05-14 像素驱动电路及显示面板

Publications (1)

Publication Number Publication Date
WO2020228062A1 true WO2020228062A1 (zh) 2020-11-19

Family

ID=67716155

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/088831 WO2020228062A1 (zh) 2019-05-14 2019-05-28 像素驱动电路及显示面板

Country Status (2)

Country Link
CN (1) CN110189691B (zh)
WO (1) WO2020228062A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110675805A (zh) * 2019-09-30 2020-01-10 南京中电熊猫液晶显示科技有限公司 像素电路、显示装置及像素驱动方法
CN112712770A (zh) 2019-10-24 2021-04-27 华为终端有限公司 一种电子设备及其显示模组
CN110767160A (zh) * 2019-10-25 2020-02-07 深圳市华星光电半导体显示技术有限公司 像素单元及显示面板
CN110808010A (zh) * 2019-10-29 2020-02-18 深圳市华星光电半导体显示技术有限公司 像素驱动电路、显示面板、显示装置及像素驱动方法
CN110930943A (zh) 2019-12-02 2020-03-27 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路及显示面板
CN114038414A (zh) * 2021-12-09 2022-02-11 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组及显示面板
CN114333690A (zh) * 2021-12-28 2022-04-12 厦门天马微电子有限公司 驱动电路、显示面板及显示设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141646A1 (en) * 2007-07-23 2010-06-10 Pioneer Corporation Active matrix display device
CN104599634A (zh) * 2015-02-04 2015-05-06 友达光电股份有限公司 一种具有高开口率的主动矩阵有机发光显示器
CN107591125A (zh) * 2017-10-26 2018-01-16 京东方科技集团股份有限公司 一种电致发光元件的驱动电路和驱动方法、显示装置
CN107818759A (zh) * 2016-09-14 2018-03-20 合肥鑫晟光电科技有限公司 像素驱动电路及像素驱动方法、阵列基板以及显示装置
CN108717841A (zh) * 2018-05-29 2018-10-30 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法、oled显示面板及其驱动电路和驱动方法
CN109410841A (zh) * 2018-11-16 2019-03-01 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038392B2 (en) * 2003-09-26 2006-05-02 International Business Machines Corporation Active-matrix light emitting display and method for obtaining threshold voltage compensation for same
CN103383836B (zh) * 2013-07-02 2015-05-27 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板及显示装置
CN104021763B (zh) * 2014-06-11 2017-12-08 合肥鑫晟光电科技有限公司 像素电路、显示装置和像素电路的驱动方法
CN104732929A (zh) * 2015-04-16 2015-06-24 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN105139805B (zh) * 2015-10-19 2017-09-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN105609047B (zh) * 2016-01-04 2018-05-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN107507568B (zh) * 2017-08-24 2019-08-13 深圳市华星光电半导体显示技术有限公司 一种oled像素电路及减缓oled器件老化的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100141646A1 (en) * 2007-07-23 2010-06-10 Pioneer Corporation Active matrix display device
CN104599634A (zh) * 2015-02-04 2015-05-06 友达光电股份有限公司 一种具有高开口率的主动矩阵有机发光显示器
CN107818759A (zh) * 2016-09-14 2018-03-20 合肥鑫晟光电科技有限公司 像素驱动电路及像素驱动方法、阵列基板以及显示装置
CN107591125A (zh) * 2017-10-26 2018-01-16 京东方科技集团股份有限公司 一种电致发光元件的驱动电路和驱动方法、显示装置
CN108717841A (zh) * 2018-05-29 2018-10-30 京东方科技集团股份有限公司 像素驱动电路、像素驱动方法、oled显示面板及其驱动电路和驱动方法
CN109410841A (zh) * 2018-11-16 2019-03-01 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法

Also Published As

Publication number Publication date
CN110189691A (zh) 2019-08-30
CN110189691B (zh) 2021-03-16

Similar Documents

Publication Publication Date Title
WO2020228062A1 (zh) 像素驱动电路及显示面板
US20210201760A1 (en) Pixel circuit and driving method thereof, display panel and driving method thereof, and display device
CN111354307B (zh) 一种像素驱动电路及驱动方法、有机发光显示面板
WO2020151007A1 (zh) 像素驱动电路及其驱动方法、显示面板
WO2022226951A1 (zh) 像素电路及其驱动方法、显示装置
WO2021164732A1 (zh) 显示装置及其驱动方法
WO2020238490A1 (zh) 像素电路、显示基板、显示装置及驱动方法
WO2020001037A1 (zh) 阵列基板及其驱动方法、显示面板
US11217179B2 (en) Scan driver and display device including the same
US11783756B1 (en) Display driving circuit and display device
US10140922B2 (en) Pixel driving circuit and driving method thereof and display device
KR20210050626A (ko) 표시 장치 및 이를 이용한 표시 패널의 구동 방법
JP6196809B2 (ja) 画素回路及びその駆動方法
WO2023115533A1 (zh) 像素电路以及显示面板
US11682340B2 (en) Sub-pixel circuit, and active electroluminescence display and driving method thereof
WO2019061784A1 (zh) Amoled显示面板的扫描驱动系统
CN111653242A (zh) 显示面板、显示装置和显示面板的驱动方法
US11955058B2 (en) Display panel and driving method for the same, and display device
CN114299867B (zh) 一种显示面板及其驱动方法和显示装置
CN114512098B (zh) 显示装置
WO2022133800A1 (zh) 移位寄存器及其驱动方法、栅极驱动器、显示装置
CN111369949B (zh) 显示面板及其扫描驱动方法
TW202233016A (zh) 畫素電路及其驅動方法
WO2021027068A1 (zh) 一种阵列基板及显示面板
CN117423314B (zh) 像素电路及其驱动方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928527

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928527

Country of ref document: EP

Kind code of ref document: A1