WO2019237731A1 - 显示背板及其制造方法、显示面板和显示装置 - Google Patents

显示背板及其制造方法、显示面板和显示装置 Download PDF

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Publication number
WO2019237731A1
WO2019237731A1 PCT/CN2019/071004 CN2019071004W WO2019237731A1 WO 2019237731 A1 WO2019237731 A1 WO 2019237731A1 CN 2019071004 W CN2019071004 W CN 2019071004W WO 2019237731 A1 WO2019237731 A1 WO 2019237731A1
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Prior art keywords
thin film
film transistor
substrate
layer
backplane
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PCT/CN2019/071004
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English (en)
French (fr)
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梁志伟
刘英伟
李海旭
狄沐昕
刘清召
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京东方科技集团股份有限公司
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Priority to US16/468,240 priority Critical patent/US11239257B2/en
Publication of WO2019237731A1 publication Critical patent/WO2019237731A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display back plate and a manufacturing method thereof, a display panel, and a display device.
  • the gate driving circuit can be directly fabricated on the display backplane (also referred to as an array substrate) through a gate array driving (Array On Array (GOA)) technology.
  • Array On Array GAA
  • a display backboard including a first backboard and a second backboard.
  • the first backplane includes a first substrate and a first thin film transistor on the first substrate for driving a light emitting unit.
  • the second backplane is bonded to a side of the first substrate facing away from the first thin film transistor, and includes a second substrate and at least one second thin film transistor.
  • the second thin film transistor is located between the second substrate and the first thin film transistor. Between the first substrate.
  • a material of the active layer of the first thin film transistor and a material of the active layer of the second thin film transistor are different.
  • a material of the active layer of the first thin film transistor includes an oxide semiconductor
  • a material of the active layer of the second thin film transistor includes polysilicon
  • the first substrate includes a first substrate layer, the first substrate has a first connection member penetrating through the first substrate layer, and a gate of the first thin film transistor is passed through the first substrate.
  • the connection member is connected to a drain of one second thin film transistor of the at least one second thin film transistor.
  • the first substrate further includes an insulating protection layer located on a side of the first substrate layer facing away from the first thin film transistor
  • the second back plate further includes the at least one second substrate.
  • the thin film transistor faces away from the planarization layer on the side of the second substrate; wherein the first connection member passes through a contact electrode penetrating through the insulation protection layer and the planarization layer and the at least one second thin film transistor. The drain of a second thin film transistor is connected.
  • the first substrate includes a first substrate layer, and the first substrate has a second connection member penetrating through the first substrate layer; a source of the first thin film transistor is passed through the second substrate.
  • the connection member is connected to a drain of one second thin film transistor of the at least one second thin film transistor.
  • the first substrate further includes an insulating protection layer located on a side of the first substrate layer facing away from the first thin film transistor
  • the second back plate further includes the at least one second substrate.
  • the thin film transistor faces away from the planarization layer on the side of the second substrate; wherein the second connection member passes through a contact electrode penetrating through the insulation protection layer and the planarization layer and the at least one second thin film transistor. The drain of a second thin film transistor is connected.
  • the second substrate includes a second substrate layer, and the second substrate has a plurality of connectors penetrating through the second substrate layer; one or more of the at least one second thin film transistor The second thin film transistor is connected to an external circuit via the plurality of connecting members.
  • the plurality of connectors are disposed in a peripheral region of the second substrate layer.
  • the at least one second thin film transistor is a thin film transistor of a driving circuit.
  • the driving circuit includes at least one of a gate driving circuit and a source driving circuit.
  • the first substrate includes a first substrate layer, and the first substrate has a first connection member and a second connection member penetrating through the first substrate layer; a gate of the first thin film transistor Connected to the drain of one second thin film transistor of the at least one second thin film transistor through the first connection, and the source of the first thin film transistor is connected to the at least one first through the second connection The drain of the other second thin film transistor of the two thin film transistors is connected.
  • a gate of the first thin film transistor is connected to a drain of a second thin film transistor of a gate driving circuit through the first connection member, and a source of the first thin film transistor is connected to the drain through the first connection member.
  • the second connection member is connected to a drain of a second thin film transistor of the source driving circuit.
  • the first substrate further includes an insulating protection layer located on a side of the first substrate layer facing away from the first thin film transistor
  • the second back plate further includes the at least one second substrate.
  • the thin film transistor faces away from the planarization layer on the side of the second substrate; wherein the first connection member passes through a contact electrode penetrating the insulation protection layer and the planarization layer and a first contact electrode of the gate driving circuit.
  • the drains of the two thin film transistors are connected, and the second connection member is connected to the drain of a second thin film transistor of the source driving circuit through another contact electrode penetrating through the insulation protection layer and the planarization layer.
  • a display panel including: the display backplane according to any one of the above embodiments.
  • a display device including the display panel according to any one of the above embodiments.
  • a method for manufacturing a display backplane including: forming a first backplane, the forming the first backplane includes forming a first substrate for driving a light emitting unit on a first substrate; A thin film transistor; forming a second back plate, the forming the second back plate includes forming at least one second thin film transistor on a second substrate; and separating the second back plate from the first substrate from the first film One side of the transistor is bonded, and after the bonding, the at least one second thin film transistor is located between the second substrate and the first substrate.
  • a material of the active layer of the first thin film transistor and a material of the active layer of the second thin film transistor are different.
  • the first substrate includes a first substrate layer, a connector penetrating through the first substrate layer, and an insulating protection layer on a side of the first substrate layer facing away from the first thin film transistor,
  • the connecting member is connected to one of a gate and a source of the first thin film transistor;
  • the second backplane further includes a side of the at least one second thin film transistor facing away from the second substrate.
  • a planarization layer and a contact electrode penetrating the planarization layer, wherein the contact electrode is in contact with a drain of a second thin film transistor of the at least one second thin film transistor; and the second back plate Bonding to the side of the first substrate facing away from the first thin film transistor includes: forming an opening at a position corresponding to the connecting member of the insulating protection layer to expose at least a part of the connecting member; An electrode is aligned with the connection member; pressure is applied to at least one of the first back plate and the second back plate so that the contact electrode is in contact with the connection member, thereby being bonded together
  • a material of the contact electrode includes an Sn-Ag-Cu alloy or an In-Sn alloy; the applying pressure to at least one of the first back plate and the second back plate includes: In a temperature range of 160 ° C to 200 ° C, a pressure of less than 100 kPa is applied to at least one of the first back plate and the second back plate.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a display backplane according to an embodiment of the present disclosure
  • 2A-2I are schematic cross-sectional views of structures formed at different stages of forming a first backplane according to some implementations of the present disclosure
  • 3A-3I are schematic cross-sectional views of structures formed at different stages of forming a second backplane according to some implementations of the present disclosure
  • FIG. 4 is a schematic structural diagram of a display backplane according to an embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram illustrating a position of a connector in a second substrate according to an embodiment of the present disclosure
  • FIG. 5B is a schematic diagram illustrating a position of a connector in a second substrate according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • an intermediate component may or may not exist between the specific component and the first component or the second component.
  • the specific component may be directly connected to the other components without an intervening component, or may be directly connected to the other components without an intervening component.
  • the materials of the active layers of the two types of thin film transistors (Thin Film Transistor (TFT) used to drive the light-emitting unit and the thin film transistor of the gate drive circuit may be different, Therefore, these two types of thin film transistors need to be formed through different process flows.
  • TFT Thi Film Transistor
  • the inventors have discovered that after forming one of the two types of thin film transistors, one or some steps in the process flow of forming another thin film transistor may adversely affect the performance of the thin film transistor already formed.
  • the embodiments of the present disclosure provide a technical solution for a display backplane, which can avoid an adverse effect on the other in the process of forming one of the first thin film transistor and the second thin film transistor for driving the light emitting unit.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a display backplane according to an embodiment of the present disclosure.
  • step 102 a first backplane is formed.
  • the step of forming the first back plate includes forming a first thin film transistor on the first substrate for driving the light emitting unit.
  • the light emitting unit may be, for example, an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the light emitting unit emits light under the driving of the first thin film transistor.
  • the step of forming the first back plate may further include forming other components such as an anode.
  • a second backplane is formed.
  • the step of forming the second back plate includes forming at least one second thin film transistor on the second substrate.
  • the at least one second thin film transistor is a thin film transistor of a driving circuit.
  • at least one second thin film transistor forms a driving circuit or forms a part of a driving circuit.
  • the driving circuit includes at least one of a gate driving circuit and a source driving circuit.
  • at least one second thin film transistor may be a thin film transistor of another circuit.
  • the step of forming the second backplane may further include forming other components of the driving circuit.
  • the material of the active layer of the second thin film transistor and the material of the active layer of the first thin film transistor are different.
  • the material of the active layer of the first thin film transistor includes an oxide semiconductor, such as indium gallium zinc oxide (IGZO); the material of the active layer of the second thin film transistor includes polysilicon.
  • the material of the active layer of the first thin film transistor includes an oxide semiconductor, low-frequency driving of a pixel can be achieved, and power consumption of a display panel can be reduced.
  • the present disclosure is not limited to this.
  • the material of the active layer of the second thin film transistor and the material of the active layer of the first thin film transistor may be the same, for example, both are polysilicon or both are oxide semiconductors.
  • step 106 the second backplane and the side of the first substrate facing away from the first thin film transistor are bonded, such as bonding, bonding, and the like. After bonding, the second thin film transistor is located between the second substrate and the first substrate.
  • the first substrate includes a first surface and a second surface opposite to each other, the first thin film transistor is on the first surface, and the second backplane is bonded to the second surface.
  • the first back plate and the second back plate are formed separately, and then the two are joined together to form a display back plate.
  • This method prevents the process of forming the first thin film transistor and the process of forming the second thin film transistor from affecting each other, thereby avoiding the process of forming the first thin film transistor from adversely affecting the performance of the second thin film transistor and avoiding formation
  • the process of the second thin film transistor adversely affects the performance of the first thin film transistor and improves the yield of the display backplane.
  • 2A-2I are schematic cross-sectional views of structures formed at different stages of forming a first backplane according to some implementations of the present disclosure.
  • a first substrate 201 is provided.
  • the first substrate 201 includes a first substrate layer 211, such as a glass layer.
  • the first substrate 201 has a connection member, such as the first connection member 221 or the second connection member 231, penetrating the first substrate layer 211.
  • the first connector 221 and the second connector 231 may be other metal connectors such as copper.
  • the first substrate 201 may further include an insulating protection layer 241 on the upper and lower surfaces of the first substrate layer 211 and covering the connectors in the first substrate 201. The insulating protection layer 241 is used to prevent the connector in the first substrate 201 from being oxidized, and can protect the first substrate layer 211.
  • the first substrate 201 may be formed by a Through Glass (Through Glass Via) (TGV) technology.
  • TGV Through Glass Via
  • the first substrate 201 may also be referred to as a TGV substrate 201.
  • the first substrate layer 211 is first punched (for example, laser drilling), and the diameter of the hole formed after the punching may be, for example, about several tens to 100 micrometers.
  • a metal material such as copper or the like is formed (eg, plated) in the formed hole to form a connection member, such as the first connection member 221 and the second connection member 231.
  • an insulating protection layer 241 such as an oxide of silicon or an organic material, may be formed on the upper and lower surfaces of the first substrate layer 211 to cover the connector.
  • a source electrode 212 and a drain electrode 222 are formed on the first substrate 201, the source electrode 212 is in contact with the second connection member 231, and the drain electrode 222 is located on the first substrate layer 211.
  • the insulating protection layer 241 on one of the upper and lower surfaces of the first substrate layer 211 may be removed first, and then the source electrode 212 may be formed. And the drain 222.
  • an active layer 232 such as an oxide semiconductor, is formed.
  • the active layer 232 is in contact with the source electrode 212 and the drain electrode 222, respectively.
  • a gate insulating layer 242 is formed on the structure shown in FIG. 2C.
  • the gate insulating layer 242 has an opening 2421 through which at least a portion of the first connection member 221 is exposed.
  • a gate electrode 252 is formed.
  • the gate 252 is connected to the first connection member 221.
  • a part of the gate 252 is located on the gate insulating layer 242, and another part of the gate 252 fills the opening 2421 and contacts the first connection member 221.
  • a first thin film transistor 202 including a source 212, a drain 222, a gate insulating layer 242, and a gate 252 is formed.
  • a planarization layer 203 such as a resin material may be further formed on the structure shown in FIG. 2E.
  • a through hole 213 is formed to penetrate through the planarization layer 203 and the gate insulating layer 242 so that at least a part of the drain electrode 222 is exposed.
  • a first through hole penetrating the gate insulating layer 242 may be formed first, and after the planarization layer 203 is formed, a second through hole communicating with the first through hole is formed. Through holes, thereby obtaining through holes 213 penetrating the planarization layer 203 and the gate insulating layer 242.
  • an anode 204 is formed on the planarization layer 203.
  • the through hole 213 may be simultaneously filled so that the anode 204 is connected to the drain 222.
  • the material of the anode 204 may be indium tin oxide (ITO). In other implementations, the anode 204 may be a stack composed of two layers of ITO and Ag between the two layers of ITO.
  • ITO indium tin oxide
  • a pixel defining layer (PDL) 205 may be formed on the structure shown in FIG. 2H.
  • a photoresist support layer (not shown in the figure) may be formed on the PDL205.
  • the first backplane may be formed according to the processes shown in FIGS. 2A to 2I, and the first backplane is hereinafter referred to as the first backplane 200.
  • 3A-3I are schematic cross-sectional views of structures formed at different stages of forming a second backplane according to some implementations of the present disclosure.
  • a second substrate 301 is provided.
  • the second substrate 301 includes a second substrate layer 311, such as a glass layer.
  • the second substrate 301 has a plurality of connecting members penetrating through the second substrate layer 311, and the plurality of connecting members may include a third connecting member 321 and a fourth connecting member 331.
  • the plurality of connecting members may further include a fifth connecting member 351 and a sixth connecting member 361 penetrating through the second substrate layer 311.
  • the plurality of connectors may be other metal connectors such as copper, for example.
  • the second substrate 301 may further include an insulating protection layer 341 on the upper and lower surfaces of the second substrate layer 311 and covering a plurality of connectors, for preventing the plurality of connectors from oxidizing, and may Protects the second substrate layer 311.
  • the second substrate 301 may be formed by the TGV technology given above.
  • the second substrate 301 may be referred to as a TGV substrate 301.
  • an active layer 312 is formed on the insulating protection layer 341 on one side of the second substrate layer 311.
  • the active layer 312 may be, for example, an active layer of a second thin film transistor of a gate driving circuit.
  • the active layers of other thin film transistors may be formed at the same time, such as the active layer 312 'of the second thin film transistor of the source driving circuit.
  • polysilicon can be formed as the active layer 312 or the active layer 312 'by using Low Temperature Polysilicon (LTPS) technology.
  • LTPS Low Temperature Polysilicon
  • amorphous silicon can be formed on the insulating protection layer 341, and then the amorphous silicon is crystallized into polysilicon by using an excimer laser annealing (ELA) technique.
  • ELA excimer laser annealing
  • an excimer laser in the ultraviolet band can be irradiated onto the surface of the amorphous silicon. Amorphous silicon is rapidly heated after absorbing light in the ultraviolet band, and then gradually melted. Later, as the heat is gradually released, the molten silicon will gradually form polysilicon.
  • a gate insulating layer 322 covering the active layer 312 is formed.
  • the gate insulating layer 322 has an opening 3221 through which at least a part of the third connection member 321 is exposed.
  • a gate insulating layer 322 ' may be formed to cover the active layer 312', and the gate insulating layer 322 'has an opening 3221' through which at least a portion of the fifth connection member 341 is exposed.
  • the gate insulating layer 322 and the gate insulating layer 322 ' may be formed at the same time. In other embodiments, the gate insulating layer 322 and the gate insulating layer 322 'may be formed independently.
  • a gate electrode 332 is formed.
  • the gate 332 is connected to the third connection member 321.
  • a part of the gate electrode 332 is located on the gate insulating layer 322, and another part of the gate electrode 332 fills the opening 3221 and contacts the third connecting member 321.
  • a gate 332 ' may also be formed.
  • the gate 332 ' is connected to the fifth connection member 341.
  • a part of the gate electrode 332 ' is located on the gate insulating layer 322', and another part of the gate electrode 332 'fills the opening 3221' and is in contact with the fifth connection member 341.
  • an interlayer dielectric layer 303 such as an oxide of silicon, is formed to cover the gate electrode 332.
  • the interlayer dielectric layer 303 may also cover the gate 332 '(if any).
  • via holes 313 and via holes 323 penetrating the interlayer dielectric layer 303 and the gate insulating layer 322 are formed, and ⁇ ⁇ 333 ⁇ Through hole 333.
  • through-holes 313 'and through-holes 323' penetrating through the interlayer dielectric layer 303 and the gate insulating layer 322 ' can also be formed, and through-interlayer dielectric layers 303, the gate insulating layer 322', and The through hole 333 ′ of the insulating protection layer 341.
  • first and second through holes penetrating the gate insulating layer 322 may be formed first, and after the interlayer dielectric layer 303 is formed, the contact with The third through hole communicated with the first through hole and the fourth through hole communicated with the second through hole, thereby obtaining the through hole 313 and the through hole 323.
  • the through-holes 313 'and the through-holes 323' can also be formed in a similar manner, and will not be repeated here.
  • the through hole 333 and the through hole 333 ' may also be formed in a similar manner.
  • a source electrode 342 connected to the active layer 312 and the fourth connection member 331, and a drain electrode 352 connected to the active layer 312 are formed.
  • a source electrode 342 'connected to the active layer 312' and the sixth connection member 351, and a drain electrode 352 'connected to the active layer 312' may also be formed.
  • a planarization layer 304 such as a resin material, is formed on the structure shown in FIG. 3G.
  • the planarization layer 304 has an opening 314 that exposes at least a portion of the drain electrode 352.
  • the planarization layer 304 also has an opening 314 'that exposes at least a portion of the drain electrode 352'.
  • a contact electrode 305 filling the opening 314 is formed.
  • a contact electrode 305 ' may also be formed to fill the opening 314'.
  • the material of the contact electrode 305 and the contact electrode 305 ' may be, for example, a metal material such as tin.
  • the second backplane may be formed according to the processes shown in FIGS. 3A to 3I, and the second backplane is hereinafter referred to as the second backplane 300.
  • the second backplane 300 and the first substrate 200 facing away from the first thin film transistor 202 can be joined to obtain a graph. Display backplane shown at 4.
  • the insulating protection layer 241 on the side of the first substrate 200 facing away from the first thin film transistor 202 may be at a position corresponding to the connection member (such as the first connection member 221 or the second connection member 231) in the first backplane 200.
  • An opening is formed to expose at least a part of the connecting member. Then, the contact electrode (for example, the contact electrode 305 or the contact electrode 305 ') in the second backplane 300 is aligned with the connector in the first backplane 200.
  • a certain pressure is applied to at least one of the first back plate 200 and the second back plate 300 within a certain temperature range, so that the contact electrode (such as the contact electrode 305 or the contact electrode 305 ') and the connection member (such as the first The connection member 221 or the second connection member 231) is contacted, thereby being bonded together.
  • the side of the second back plate 300 and the first substrate 200 facing away from the first thin film transistor 202 can be pressed together.
  • the contact electrode 305 and the first connecting member 221 diffuse to each other, so as to be bonded together by an intermolecular bonding force.
  • the contact electrode 305 'and the second connection member 231 are mutually diffused, thereby being bonded together by an intermolecular bonding force.
  • the material of the contact electrode (for example, the contact electrode 305 in contact with the drain electrode 352) in the second backplane 300 may be an Sn-Ag-Cu alloy or an In-Sn alloy.
  • a pressure of less than 100 kPa may be applied to at least one of the first back plate 200 and the second back plate 300 in a temperature range of 160 ° C. to 200 ° C. (for example, 170 ° C., 180 ° C., etc.).
  • the side of the second back plate 300 and the first substrate 200 facing away from the first thin film transistor 202 is pressed together.
  • Such a pressing method will not easily cause the first substrate 201 and the second substrate 301 to be damaged by pressure, nor will it adversely affect the performance of the first thin film transistor 202 and the second thin film transistor 302 (302 ') due to excessive temperature. .
  • FIG. 4 is a schematic structural diagram of a display backplane according to an embodiment of the present disclosure. As shown in FIG. 4, the display backplane includes a first backplane 200 and a second backplane 300.
  • the first backplane 200 includes a first substrate 201 and a first thin film transistor 202 on the first substrate 201 for driving a light emitting unit. It should be understood that the first backplane 200 may further include other components, such as a planarization layer 203 covering the gate electrode 252, an anode 204 located on the planarization layer 203 and connected to the drain electrode 222, and the like.
  • the second backplane 300 includes a second substrate 301 and at least one second thin film transistor, such as a second thin film transistor 302 (302 ').
  • the second thin film transistor 302 (302 ') is located between the second substrate 301 and the first substrate 201.
  • the second backplane 300 is bonded to the side of the first substrate 201 facing away from the first thin film transistor 202, such as bonding or bonding.
  • the material of the active layer 232 of the first thin film transistor 202 and the material of the active layer 312 (312 ') of the second thin film transistor 302 (302') are different.
  • the material of the active layer 232 of the first thin film transistor 202 includes an oxide semiconductor
  • the material of the active layer 312 (312 ') of the second thin film transistor 302 (302') includes polysilicon.
  • the material of the active layer 232 of the first thin film transistor 202 and the material of the active layer 312 (312 ') of the second thin film transistor 302 (302') are the same.
  • the second thin film transistor 302 (302 ') is a thin film transistor of a driving circuit.
  • the driving circuit may include at least one of a gate driving circuit and a source driving circuit.
  • the second thin film transistor 302 (302 ') may also be a thin film transistor of other circuits.
  • the second backplane 300 shown in FIG. 4 includes the second thin film transistor 302 of the gate driving circuit and the second thin film transistor 302 'of the source driving circuit, it should be understood that this is not restrictive.
  • the second backplane 300 may include at least one of a plurality of second thin film transistors of a certain driving circuit. That is, for a certain driving circuit, part of the second thin film transistor of the driving circuit may be provided in the second back plate 300, or all the second thin film transistors of the driving circuit may be provided in the second back plate 300.
  • FIG. 4 schematically shows only the second thin film transistor 302 connected to the first backplane 200 in the gate driving circuit and the first thin film transistor 302 connected to the first backplane 200 in the source driving circuit.
  • the two thin film transistors 302 'do not show other second thin film transistors in the gate driving circuit and the source driving circuit.
  • the second backplane including at least one second thin film transistor and the first backplane including the first thin film transistor for driving the light-emitting unit are stacked and bonded together.
  • Such a display backplane helps to reduce the frame of the display panel.
  • the first substrate 201 includes a first substrate layer 211, and the first substrate 201 has at least one of a first connection member 221 and a second connection member 231 penetrating the first substrate layer 211.
  • the gate 252 of the first thin film transistor 202 is connected to the drain of one second thin film transistor of the at least one second thin film transistor via the first connection member 221, such as the second thin film of the gate driving circuit.
  • the drain 352 of the transistor 302 is connected.
  • the source 212 of the first thin film transistor 202 is connected to the drain of one second thin film transistor of the at least one second thin film transistor via the second connection member 231, for example, the second thin film transistor is connected to the second thin film transistor of the source driving circuit A drain 352 'of the thin film transistor 302' is connected.
  • the gate 252 of the first thin film transistor 202 is connected to one of the at least one second thin film transistor (eg, the second thin film transistor 302 of the gate driving circuit) via the first connection member 221 and at least one second thin film transistor.
  • the drain electrode of the first thin film transistor 202 is connected to another second thin film transistor of the at least one second thin film transistor (for example, the second thin film transistor 302 'of the source driving circuit) via the second connection member 231. Drain connection.
  • the first thin film transistor is connected to the second thin film transistor via a connection member in the first substrate.
  • a display backplane it is not necessary to connect the second thin film transistor and the first thin film transistor through additional peripheral leads, which helps to further reduce the frame of the display panel.
  • the first substrate 201 further includes an insulating protection layer 241 on a side of the first substrate layer 211 facing away from the first thin film transistor
  • the second back plate 300 further includes at least one second thin film transistor (202 or 202). ') The planarization layer 304 facing away from the second substrate 301.
  • the first connection member 221 may be connected to the drain of one of the at least one second thin film transistor 302 through the contact electrode 305 penetrating the insulating protection layer 241 and the planarization layer 304.
  • the second connection member 221 ′ may be connected to the drain of one second thin film transistor 302 ′ of the at least one second thin film transistor via the contact electrode 305 ′ penetrating the insulating protection layer 241 and the planarization layer 304. .
  • the first connection member 221 may be connected to a drain electrode of a second thin film transistor 302 of the gate driving circuit through a contact electrode 305 penetrating the insulation protection layer 241 and the planarization layer 304.
  • the second connection member 221 ' may be connected to the drain of a second thin film transistor 302' of the source driving circuit via another contact electrode 305 'penetrating the insulating protection layer 241 and the planarization layer 304.
  • the second substrate 300 includes a second substrate layer 301, and the second substrate 300 has a plurality of connection members penetrating through the second substrate layer 301, such as a third connection member 321, a fourth connection member 331, and a fifth connection.
  • One or more second thin film transistors of the at least one second thin film transistor are connected to the external circuit via a plurality of connecting members. It should be understood that, in a case where a plurality of second thin film transistors are connected to an external circuit via a plurality of connecting members, each second thin film transistor is connected to an external circuit via a plurality of connecting members.
  • the second thin film transistor of the gate driving circuit is connected to an external circuit via a part of the plurality of connectors, and the second thin film transistor of the source driving circuit is connected to the external circuit via another part of the plurality of connectors.
  • the external circuit may include, but is not limited to, a control circuit, a touch circuit, and the like.
  • the second thin film transistor 302 of the gate driving circuit is connected to the external circuit via the third connecting member 321 and the fourth connecting member 331, and the second thin film transistor 302 'of the source driving circuit is connected via the fifth connecting member 341 and the sixth connecting member. 351 is connected to an external circuit.
  • the gate electrode 332 of the second thin film transistor 302 of the gate driving circuit is connected to the external circuit via the third connection member 321, and the source electrode 342 of the second thin film transistor 302 of the gate driving circuit is connected to the external connection device 331 Connect with external circuit.
  • the gate 332 ′ of the second thin film transistor 302 ′ of the source driving circuit is connected to the external circuit via the fifth connection member 341, and the source 342 ′ of the second thin film transistor 302 ′ of the source driving circuit is connected via the first
  • the six connecting members 351 are connected to an external circuit.
  • other external circuits can be connected to the second substrate through the connecting members in the second substrate, which helps to further reduce the frame of the display panel, for example, helps reduce the frame around the display panel.
  • the positions of the connecting members in the first substrate 200 and the second substrate 300 can be set according to actual requirements.
  • the following uses the second substrate 300 as an example to give two ways of setting the connecting member.
  • FIG. 5A is a schematic diagram illustrating a position of a connector in a second substrate according to an embodiment of the present disclosure.
  • FIG. 5B is a schematic diagram illustrating a position of a connector in a second substrate according to another embodiment of the present disclosure.
  • the positions shown by the circles are the positions of the connecting members.
  • connection member 501 connected to the gate driving circuit and a connection member 502 connected to the source driving circuit may be disposed in a peripheral region of the second substrate layer 311.
  • connection link 501 arranged vertically is a connection piece connected to the gate driving circuit
  • connection link 502 arranged horizontally is a connection piece connected to the source driving circuit.
  • connection member 501 connected to the gate driving circuit and a connection member 502 connected to the source driving circuit may be disposed in a middle region of the second substrate layer 311.
  • the horizontally connected connection 501 is a connection connected to the gate driving circuit
  • the vertically aligned connection 502 is a connection connected to the source driving circuit.
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 600 may include the display back plate 500 of any one of the above embodiments.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device 700 may include the display panel 600 of any one of the above embodiments.
  • the display device may be, for example, any product or component having a display function, such as a mobile terminal, a television, a display, a notebook computer, a digital photo frame, a navigator, and an electronic paper.

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Abstract

一种显示背板及其制造方法、显示面板和显示装置，涉及显示技术领域。显示背板包括第一背板（200）和第二背板（300）。所述第一背板（200）包括第一基板（201）和位于所述第一基板（201）上用于驱动发光单元的第一薄膜晶体管（202）。所述第二背板（300）与所述第一基板（201）背离所述第一薄膜晶体管（202）的一面接合，包括第二基板（301）和至少一个第二薄膜晶体管（302，302'），所述至少一个第二薄膜晶体管（302，302'）位于所述第二基板（301）与所述第一基板（201）之间。

Description

显示背板及其制造方法、显示面板和显示装置
相关申请的交叉引用
本申请是以CN申请号为201810611465.9，申请日为2018年6月14日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示背板及其制造方法、显示面板和显示装置。
背景技术
为了减少制造工艺流程，提高显示面板的集成度，可以通过阵列基板栅极驱动(Gate On Array，GOA)技术将栅极驱动电路直接制作在显示背板(也称为阵列基板)上。
发明内容
根据本公开实施例的一方面，提供一种显示背板，包括第一背板和第二背板。所述第一背板包括第一基板和位于所述第一基板上用于驱动发光单元的第一薄膜晶体管。所述第二背板与所述第一基板背离所述第一薄膜晶体管的一面接合，包括第二基板和至少一个第二薄膜晶体管，所述第二薄膜晶体管位于所述第二基板与所述第一基板之间。
在一些实施例中，所述第一薄膜晶体管的有源层的材料和所述第二薄膜晶体管的有源层的材料不同。
在一些实施例中，所述第一薄膜晶体管的有源层的材料包括氧化物半导体，所述第二薄膜晶体管的有源层的材料包括多晶硅。
在一些实施例中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第一连接件；所述第一薄膜晶体管的栅极经由所述第一连接件与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背 离所述第二基板一侧的平坦化层；其中，所述第一连接件经由贯穿所述绝缘保护层和所述平坦化层的接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第二连接件；所述第一薄膜晶体管的源极经由所述第二连接件与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层；其中，所述第二连接件经由贯穿所述绝缘保护层和所述平坦化层的接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第二基板包括第二基板层，所述第二基板具有贯穿所述第二基板层的多个连接件；所述至少一个第二薄膜晶体管中的一个或多个第二薄膜晶体管经由所述多个连接件与外接电路连接。
在一些实施例中，所述多个连接件设置在所述第二基板层的周边区域。
在一些实施例中，所述至少一个第二薄膜晶体管为驱动电路的薄膜晶体管。
在一些实施例中，所述驱动电路包括栅极驱动电路和源极驱动电路中的至少一个。
在一些实施例中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第一连接件和第二连接件；所述第一薄膜晶体管的栅极经由所述第一连接件与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接，所述第一薄膜晶体管的源极经由所述第二连接件与所述至少一个第二薄膜晶体管中的另一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第一薄膜晶体管的栅极经由所述第一连接件与栅极驱动电路的一个第二薄膜晶体管的漏极连接，所述第一薄膜晶体管的源极经由所述第二连接件与源极驱动电路的一个第二薄膜晶体管的漏极连接。
在一些实施例中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层；其中，所述第一连接件经由贯穿所述绝缘保护层和所述平坦化层的一个接触电极与所述栅极驱动电路的一个第二薄膜晶体管的漏极连接，所述第二连接件经由贯穿所述绝缘保护层和所述平坦化层的另一个接触电极与所 述源极驱动电路的一个第二薄膜晶体管的漏极连接。
根据本公开实施例的另一方面，提供一种显示面板，包括：上述任意一个实施例所述的显示背板。
根据本公开实施例的又一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
根据本公开实施例的又一方面，提供一种显示背板的制造方法，包括：形成第一背板，所述形成第一背板包括在第一基板上形成用于驱动发光单元的第一薄膜晶体管；形成第二背板，所述形成第二背板包括在第二基板上形成至少一个第二薄膜晶体管；和将所述第二背板与所述第一基板背离所述第一薄膜晶体管的一面接合，其中，在所述接合后，所述至少一个第二薄膜晶体管位于所述第二基板与所述第一基板之间。
在一些实施例中，所述第一薄膜晶体管的有源层的材料和所述第二薄膜晶体管的有源层的材料不同。
在一些实施例中，所述第一基板包括第一基板层、贯穿所述第一基板层的连接件、以及位于所述第一基板层背离所述第一薄膜晶体管一侧的绝缘保护层，其中，所述连接件与所述第一薄膜晶体管的栅极和源极中的一个连接；所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层和贯穿所述平坦化层的接触电极，其中，所述接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极接触；所述将所述第二背板与所述第一基板背离所述第一薄膜晶体管的一面接合包括：在所述绝缘保护层与所述连接件对应的位置处形成开口，以露出所述连接件的至少一部分；将所述接触电极与所述连接件对齐；对所述第一背板和所述第二背板中的至少一个施加压力，以使得所述接触电极与所述连接件接触，从而键合在一起。
在一些实施例中，所述接触电极的材料包括Sn-Ag-Cu合金或者In-Sn合金；所述对所述第一背板和所述第二背板中的至少一个施加压力包括：在160℃至200℃的温度范围内，对所述第一背板和所述第二背板中的至少一个施加小于100kPa的压力。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开一个实施例的显示背板的制造方法的流程示意图；
图2A-2I示出了根据本公开一些实现方式的在形成第一背板的不同阶段所形成的结构的截面示意图；
图3A-3I示出了根据本公开一些实现方式的在形成第二背板的不同阶段所形成的结构的截面示意图；
图4是根据本公开一个实施例的显示背板的结构示意图；
图5A示出了根据本公开一个实施例的第二基板中的连接件的位置示意图；
图5B示出了根据本公开另一个实施例的第二基板中的连接件的位置示意图；
图6是根据本公开一个实施例的显示面板的结构示意图；
图7是根据本公开一个实施例的显示装置的结构示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通 技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，在某些情况下，用于驱动发光单元的薄膜晶体管(Thin Film Transistor，TFT)与栅极驱动电路的薄膜晶体管这两种类型的薄膜晶体管的有源层的材料可能不同，故需要通过不同的工艺流程来形成这两种类型的薄膜晶体管。
发明人发现，在形成这两种类型中的一种薄膜晶体管后，形成另一种薄膜晶体管的工艺流程中的某一或某些步骤可能会对已经形成的薄膜晶体管的性能造成不利影响。
本公开实施例提供了一种显示背板的技术方案，能够避免在形成用于驱动发光单元的第一薄膜晶体管和第二薄膜晶体管中的一个的过程中，对另一个造成的不利影响。
图1是根据本公开一个实施例的显示背板的制造方法的流程示意图。
在步骤102，形成第一背板。
这里，形成第一背板的步骤包括在第一基板上形成用于驱动发光单元的第一薄膜晶体管。发光单元例如可以是有机发光二极管(OLED)。发光单元在第一薄膜晶体管的驱动下发光。应理解，形成第一背板的步骤还可以包括形成阳极等其他部件。
在步骤104，形成第二背板。
这里，形成第二背板的步骤包括在第二基板上形成至少一个第二薄膜晶体管。在一些实施例中，至少一个第二薄膜晶体管为驱动电路的薄膜晶体管。例如，至少一个第二薄膜晶体管组成了驱动电路或组成了驱动电路的一部分。在一些实施例中，驱动电路包括栅极驱动电路和源极驱动电路中的至少一个。然而，本公开并不限于此，例如，至少一个第二薄膜晶体管也可以是其他电路的薄膜晶体管。另外，应理解，形成第二背板的步骤还可以包括形成驱动电路的其他部件。
在一些实施例中，第二薄膜晶体管的有源层的材料和第一薄膜晶体管的有源层的材料不同。例如，第一薄膜晶体管的有源层的材料包括氧化物半导体，例如铟镓锌氧化物(IGZO)；第二薄膜晶体管的有源层的材料包括多晶硅。在第一薄膜晶体管的有源层的材料包括氧化物半导体的情况下，可以实现像素的低频驱动，并降低显示面板的功耗。然而，本公开并不限于此。在其他的实施例中，第二薄膜晶体管的有源层 的材料和第一薄膜晶体管的有源层的材料也可以相同，例如均为多晶硅或均为氧化物半导体。
在步骤106，将第二背板与第一基板背离第一薄膜晶体管的一面接合，例如粘合、键合等。在接合后，第二薄膜晶体管位于第二基板与第一基板之间。
例如，第一基板包括相对的第一面和第二面，第一薄膜晶体管在第一面上，第二背板与第二面接合。
上述实施例中，分别独立地形成第一背板和第二背板，再将二者接合在一起，以形成显示背板。这样的方法使得形成第一薄膜晶体管的工艺流程和形成第二薄膜晶体管的工艺流程不会彼此影响，从而避免形成第一薄膜晶体管的过程对第二薄膜晶体管的性能造成不利影响，也避免了形成第二薄膜晶体管的过程对第一薄膜晶体管的性能造成不利影响，提高了显示背板的良率。
图2A-2I示出了根据本公开一些实现方式的在形成第一背板的不同阶段所形成的结构的截面示意图。
下面结合图2A-2I对形成第一背板的过程进行详细介绍。
首先，如图2A所示，提供第一基板201。
在一些实施例中，第一基板201包括第一基板层211，例如玻璃层。在一些实施例中，第一基板201具有贯穿第一基板层211的连接件，例如第一连接件221或第二连接件231。第一连接件221和第二连接件231例如可以是铜等其他金属连接件。在某些实施例中，第一基板201还可以包括在第一基板层211的上下两个表面上、且覆盖第一基板201中的连接件的绝缘保护层241。绝缘保护层241用于防止第一基板201中的连接件氧化，并且可以保护第一基板层211。
在一个或多个实施例中，可以通过玻璃通孔(Through Glass Via，TGV)技术来形成第一基板201。这种情况下，第一基板201也可以称为TGV基板201。例如，先对第一基板层211进行打孔(例如激光打孔)，打孔后所形成的孔的直径例如可以为约几十微米至100微米。然后，在所形成的孔中形成(例如电镀)金属材料，例如铜等，以形成连接件，例如第一连接件221和第二连接件231。之后，还可以在第一基板层211的上下表面形成覆盖连接件的绝缘保护层241，例如硅的氧化物或有机材料等。
然后，如图2B所示，在第一基板201上形成源极212和漏极222，源极212与第二连接件231接触，漏极222位于第一基板层211上。
需要说明的是，在第一基板201具有绝缘保护层241的情况下，可以先将第一基板层211的上下两个表面中的一个表面上的绝缘保护层241去除，然后再形成源极212和漏极222。
然后，如图2C所示，形成有源层232，例如氧化物半导体。有源层232分别与源极212和漏极222接触。
之后，如图2D所示，在图2C所示的结构上形成栅极绝缘层242。栅极绝缘层242具有使得第一连接件221的至少一部分露出的开口2421。
接下来，如图2E所示，形成栅极252。这里，栅极252与第一连接件221连接。例如，栅极252的一部分位于栅极绝缘层242上，栅极252的另一部分填充开口2421并与第一连接件221接触。
在形成栅极252后，即形成了包括源极212、漏极222、栅极绝缘层242和栅极252的第一薄膜晶体管202。
之后，如图2F所示，还可以在图2E所示的结构上形成平坦化层203，例如树脂材料。
之后，如图2G所示，形成贯穿平坦化层203和栅极绝缘层242的通孔213，以使得漏极222的至少一部分露出。
在某些实施例中，在形成栅极绝缘层242后即可先形成贯穿栅极绝缘层242的第一通孔，在形成平坦化层203后，再形成与第一通孔连通的第二通孔，从而得到贯穿平坦化层203和栅极绝缘层242的通孔213。
之后，如图2H所示，在平坦化层203上形成阳极204。在一些实施例中，在形成阳极204时，可以同时填充通孔213以使得阳极204与漏极222连接。
在一些实现方式中，阳极204的材料可以是氧化铟锡(ITO)。在另一些实现方式中，阳极204可以是由两层ITO和两层ITO之间的Ag组成的叠层。
之后，如图2I所示，可以在图2H所示的结构上形成像素界定层(PDL)205。另外，在一些实施例中，还可以在PDL 205上形成光阻支撑层(图中未示出)。
根据图2A-图2I所示流程可以形成第一背板，下面将第一背板称为第一背板200。
图3A-3I示出了根据本公开一些实现方式的在形成第二背板的不同阶段所形成的结构的截面示意图。
下面结合图3A-3I对形成第二背板的过程进行详细介绍。
首先，如图3A所示，提供第二基板301。
在一些实施例中，第二基板301包括第二基板层311，例如玻璃层。在一些实施例中，第二基板301具有贯穿第二基板层311的多个连接件，多个连接件可以包括第三连接件321和第四连接件331。在某些实施例中，多个连接件还可以包括贯穿第二基板层311的第五连接件351和第六连接件361。多个连接件例如可以是铜等其他金属连接件。在某些实施例中，第二基板301还可以包括在第二基板层311的上下两个表面上、且覆盖多个连接件的绝缘保护层341，用于防止多个连接件氧化，并且可以保护第二基板层311。
在一个或多个实施例中，可以通过上面给出的TGV技术来形成第二基板301。这种情况下，第二基板301也可以称为TGV基板301。
接下来，如图3B所示，在第二基板层311的某一面上的绝缘保护层341上形成有源层312。有源层312例如可以是栅极驱动电路的第二薄膜晶体管的有源层。在某些实施例中，在形成有源层312时可以同时形成其他薄膜晶体管的有源层，例如源极驱动电路的第二薄膜晶体管的有源层312’。
在一些实施例中，可以通过低温多晶硅技术(Low Temperature Poly-silicon，LTPS)形成多晶硅作为有源层312或有源层312’。例如，可以先在绝缘保护层341上形成非晶硅，然后利用准分子激光退火(ELA)等技术将非晶硅晶化成多晶硅。在一些例子中，可以将紫外波段的准分子激光照射到非晶硅的表面。非晶硅在吸收紫外波段的光后，会被快速加热，进而会逐渐被熔融。之后，随着热量的逐渐释放，熔融的硅会逐渐形成多晶硅。
然后，如图3C所示，形成覆盖有源层312的栅极绝缘层322。栅极绝缘层322具有使得第三连接件321的至少一部分露出的开口3221。
在某些实施例中，还可以形成覆盖有源层312’的栅极绝缘层322’，栅极绝缘层322’具有使得第五连接件341的至少一部分露出的开口3221’。在一些实施例中，可以同时形成栅极绝缘层322和栅极绝缘层322’。在另一些实施例中，也可以分别独立地形成栅极绝缘层322和栅极绝缘层322’。
之后，如图3D所示，形成栅极332。这里，栅极332与第三连接件321连接。例如，栅极332的一部分位于栅极绝缘层322上，栅极332的另一部分填充开口3221并与第三连接件321接触。
在某些实施例中，还可以形成栅极332’。这里，栅极332’与第五连接件341连接。例如，栅极332’的一部分位于栅极绝缘层322’上，栅极332’的另一部分填 充开口3221’并与第五连接件341接触。
之后，如图3E所示，形成覆盖栅极332的层间电介质层303，例如硅的氧化物等。在某些实施例中，层间电介质层303还可以覆盖栅极332’(如果有的话)。
之后，如图3F所示，形成贯穿层间电介质层303和栅极绝缘层322的通孔313和通孔323，并形成贯穿层间电介质层303、栅极绝缘层322和绝缘保护层341的通孔333。
在某些实施例中，还可以形成贯穿层间电介质层303和栅极绝缘层322’的通孔313’和通孔323’，并形成贯穿层间电介质层303、栅极绝缘层322’和绝缘保护层341的通孔333’。
在一个或多个实施例中，在形成栅极绝缘层322后即可先形成贯穿栅极绝缘层322的第一通孔和第二通孔，在形成层间电介质层303后，再形成与第一通孔连通的第三通孔以及与第二通孔连通的第四通孔，从而得到通孔313和通孔323。也可以以类似的方式形成通孔313’和通孔323’，在此不再赘述。在一个或多个实施例中，也可以以类似的方式形成通孔333和通孔333’。
之后，如图3G所示，形成连接至有源层312和第四连接件331的源极342、以及连接至有源层312的漏极352。在某些实施例中，还可以形成连接至有源层312’和第六连接件351的源极342’、以及连接至有源层312’的漏极352’。
之后，如图3H所示，在图3G所示的结构上形成平坦化层304，例如树脂材料。平坦化层304具有使得漏极352的至少一部分露出的开口314。在某些实施例中，平坦化层304还具有使得漏极352’的至少一部分露出的开口314’。
之后，如图3I所示，形成填充开口314的接触电极305。在某些实施例中，还可以形成填充开口314’的接触电极305’。接触电极305和接触电极305’的材料例如可以是锡等金属材料。
根据图3A-图3I所示流程可以形成第二背板，下面将第二背板称为第二背板300。在形成图2I所示的第一背板200和图3I所示的第二背板300后，可以将第二背板300与第一基板200背离第一薄膜晶体管202的一面接合，从而得到图4所示的显示背板。
例如，可以在第一基板200背离第一薄膜晶体管202的一面上的绝缘保护层241与第一背板200中的连接件(例如第一连接件221或第二连接件231)对应的位置处形成开口，以露出连接件的至少一部分。然后，将第二背板300中的接触电极(例如接触电极305或接触电极305’)与第一背板200中的连接件对齐。之后，在某一温 度范围内对第一背板200和第二背板300中的至少一个施加一定的压力，使得接触电极(例如接触电极305或接触电极305’)与连接件(例如第一连接件221或第二连接件231)接触，从而键合在一起。这样，即可以将第二背板300与第一基板200背离第一薄膜晶体管202的一面压合。应理解，在压合过程中，接触电极305与第一连接件221互相扩散，从而通过分子间结合力键合在一起。类似地，接触电极305’与第二连接件231互相扩散，从而通过分子间结合力键合在一起。
在一些实施例中，第二背板300中的接触电极(例如，与漏极352接触的接触电极305)的材料可以是Sn-Ag-Cu合金或者In-Sn合金。在这种情况下，可以在160℃至200℃(例如170℃、180℃等)的温度范围内，对第一背板200和第二背板300中的至少一个施加小于100kPa的压力，以将第二背板300与第一基板200背离第一薄膜晶体管202的一面压合。这样的压合方式既不容易导致第一基板201和第二基板301受压破损，也不会由于温度过高对第一薄膜晶体管202和第二薄膜晶体管302(302’)的性能造成不利影响。
图4是根据本公开一个实施例的显示背板的结构示意图。如图4所示，显示背板包括第一背板200和第二背板300。
第一背板200包括第一基板201和位于第一基板201上用于驱动发光单元的第一薄膜晶体管202。应理解，第一背板200还可以包括其他部件，例如覆盖栅极252的平坦化层203、位于平坦化层203上且连接至漏极222的阳极204等。
第二背板300包括第二基板301和至少一个第二薄膜晶体管，例如第二薄膜晶体管302(302’)。第二薄膜晶体管302(302’)位于第二基板301与第一基板201之间。第二背板300与第一基板201背离第一薄膜晶体管202的一面接合，例如粘合或键合。
在一些实施例中，第一薄膜晶体管202的有源层232的材料和第二薄膜晶体管302(302’)的有源层312(312’)的材料不同。例如，第一薄膜晶体管202的有源层232的材料包括氧化物半导体，第二薄膜晶体管302(302’)的有源层312(312’)的材料包括多晶硅。在另一些实施例中，第一薄膜晶体管202的有源层232的材料和第二薄膜晶体管302(302’)的有源层312(312’)的材料相同。
在一些实施例中，第二薄膜晶体管302(302’)为驱动电路的薄膜晶体管。例如，驱动电路可以包括栅极驱动电路和源极驱动电路中的至少一个。在某些实施例中，第二薄膜晶体管302(302’)也可以为其他电路的薄膜晶体管。
这里，虽然图4示出的第二背板300包括栅极驱动电路的第二薄膜晶体管302和源极驱动电路的第二薄膜晶体管302’，但是，应理解，这并非是限制性的。例如，第二背板300可以仅包括某一个驱动电路的多个第二薄膜晶体管中的至少一个。也就是说，对于某一个驱动电路来说，驱动电路的部分第二薄膜晶体管可以设置在第二背板300中，或者，驱动电路的全部第二薄膜晶体管可以设置在第二背板300中。
另外，需要说明的是，图4仅示意性地示出了栅极驱动电路中与第一背板200连接的第二薄膜晶体管302、以及源极驱动电路中与第一背板200连接的第二薄膜晶体管302’，并未示出栅极驱动电路和源极驱动电路中的其他第二薄膜晶体管。
上述实施例中，包括至少一个第二薄膜晶体管的第二背板与包括用于驱动发光单元的第一薄膜晶体管的第一背板上下堆叠地接合在一起。这样的显示背板有助于减小显示面板的边框。
在一些实施例中，第一基板201包括第一基板层211，第一基板201具有贯穿第一基板层211的第一连接件221和第二连接件231中的至少一个。
在一些实现方式中，第一薄膜晶体管202的栅极252经由第一连接件221与至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接，例如与栅极驱动电路的第二薄膜晶体管302的漏极352连接。
在另一些实现方式中，第一薄膜晶体管202的源极212经由第二连接件231与至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接，例如与源极驱动电路的第二薄膜晶体管302’的漏极352’连接。
在又一些实现方式中，第一薄膜晶体管202的栅极252经由第一连接件221与至少一个第二薄膜晶体管中的一个第二薄膜晶体管(例如，栅极驱动电路的第二薄膜晶体管302)的漏极连接，第一薄膜晶体管202的源极212经由第二连接件231与至少一个第二薄膜晶体管中的另一个第二薄膜晶体管(例如，源极驱动电路的第二薄膜晶体管302’)的漏极连接。
上述实施例中，第一薄膜晶体管经由第一基板中的连接件与第二薄膜晶体管连接。这样的显示背板中，无需通过额外的周边引线来连接第二薄膜晶体管与第一薄膜晶体管，有助于进一步减小显示面板的边框。
在一些实施例中，第一基板201还包括位于第一基板层211背离第一薄膜晶体管的一侧的绝缘保护层241，第二背板300还包括位于至少一个第二薄膜晶体管(202或202’)背离第二基板301一侧的平坦化层304。
在一些实现方式中，第一连接件221可以经由贯穿绝缘保护层241和平坦化层304的接触电极305与至少一个第二薄膜晶体管中的一个第二薄膜晶体管302的漏极连接。
在另一些实现方式中，第二连接件221’可以经由贯穿绝缘保护层241和平坦化层304的接触电极305’与至少一个第二薄膜晶体管中的一个第二薄膜晶体管302’的漏极连接。
在又一些实现方式中，第一连接件221可以经由贯穿绝缘保护层241和平坦化层304的一个接触电极305与栅极驱动电路的一个第二薄膜晶体管302的漏极连接，第二连接件221’可以经由贯穿绝缘保护层241和平坦化层304的另一个接触电极305’与源极驱动电路的一个第二薄膜晶体管302’的漏极连接。
在一些实施例中，第二基板300包括第二基板层301，第二基板300具有贯穿第二基板层301的多个连接件，例如第三连接件321、第四连接件331、第五连接件341和第六连接件351等。至少一个第二薄膜晶体管中的一个或多个第二薄膜晶体管经由多个连接件与外接电路连接。应理解，在多个第二薄膜晶体管经由多个连接件与外接电路连接的情况下，每个第二薄膜晶体管均经由多个连接件中的多个与外接电路连接。例如，栅极驱动电路的第二薄膜晶体管经由多个连接件中的一部分连接件与外接电路连接，源极驱动电路的第二薄膜晶体管经由多个连接件中的另一部分连接件与外接电路连接。在一些实施例中，上述外接电路例如可以包括但不限于控制电路、触控电路等。
例如，栅极驱动电路的第二薄膜晶体管302经由第三连接件321和第四连接件331与外接电路连接，源极驱动电路第二薄膜晶体管302’经由第五连接件341和第六连接件351与外接电路连接。在一些例子中，栅极驱动电路的第二薄膜晶体管302的栅极332经由第三连接件321与外接电路连接，栅极驱动电路的第二薄膜晶体管302的源极342经由第四连接件331与外接电路连接。在一些例子中，源极驱动电路的第二薄膜晶体管302’的栅极332’经由第五连接件341与外接电路连接，源极驱动电路的第二薄膜晶体管302’的源极342’经由第六连接件351与外接电路连接。
上述实施例中，可以通过第二基板中的连接件将其他外接电路与第二基板连接，有助于更进一步减小显示面板的边框，例如有助于减小显示面板四周的边框。
需要说明的是，第一基板200和第二基板300中的连接件的位置可以根据实际需求进行设置。以下以第二基板300为例给出连接件的两种设置方式。
图5A示出了根据本公开一个实施例的第二基板中的连接件的位置示意图。图5B 示出了根据本公开另一个实施例的第二基板中的连接件的位置示意图。在图5A和图5B中，圆圈所示的位置为连接件的位置。
如图5A所示，与栅极驱动电路连接的连接件501和与源极驱动电路连接的连接件502可以设置在第二基板层311的周边区域。例如，纵向排列的连接连501为与栅极驱动电路连接的连接件，横向排列的连接连502为与源极驱动电路连接的连接件。
如图5B所示，与栅极驱动电路连接的连接件501和与源极驱动电路连接的连接件502可以设置在第二基板层311的中间区域。例如，横向排列的连接连501为与栅极驱动电路连接的连接件，纵向排列的连接连502为与源极驱动电路连接的连接件。
图6是根据本公开一个实施例的显示面板的结构示意图。
如图6所示，显示面板600可以包括上述任意一个实施例的显示背板500。
图7是根据本公开一个实施例的显示装置的结构示意图。
如图7所示，显示装置700可以包括上述任意一个实施例的显示面板600。在一些实施例中，显示装置例如可以是移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示背板，包括：
    第一背板，包括：
    第一基板，和
    第一薄膜晶体管，位于所述第一基板上，用于驱动发光单元；和
    第二背板，与所述第一基板背离所述第一薄膜晶体管的一面接合，包括：
    第二基板，和
    至少一个第二薄膜晶体管，位于所述第二基板与所述第一基板之间。
  2. 根据权利要求1所述的显示背板，其中，所述第一薄膜晶体管的有源层的材料和所述第二薄膜晶体管的有源层的材料不同。
  3. 根据权利要求2所述的显示背板，其中，所述第一薄膜晶体管的有源层的材料包括氧化物半导体，所述第二薄膜晶体管的有源层的材料包括多晶硅。
  4. 根据权利要求1所述的显示背板，其中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第一连接件；
    所述第一薄膜晶体管的栅极经由所述第一连接件与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
  5. 根据权利要求4所述的显示背板，其中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层；
    其中，所述第一连接件经由贯穿所述绝缘保护层和所述平坦化层的接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
  6. 根据权利要求1所述的显示背板，其中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第二连接件；
    所述第一薄膜晶体管的源极经由所述第二连接件与所述至少一个第二薄膜晶体 管中的一个第二薄膜晶体管的漏极连接。
  7. 根据权利要求6所述的显示背板，其中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层；
    其中，所述第二连接件经由贯穿所述绝缘保护层和所述平坦化层的接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接。
  8. 根据权利要求1所述的显示背板，其中，所述第二基板包括第二基板层，所述第二基板具有贯穿所述第二基板层的多个连接件；
    所述至少一个第二薄膜晶体管中的一个或多个第二薄膜晶体管经由所述多个连接件与外接电路连接。
  9. 根据权利要求8所述的显示背板，其中，所述多个连接件设置在所述第二基板层的周边区域。
  10. 根据权利要求1-9任意一项所述的显示背板，其中，所述至少一个第二薄膜晶体管为驱动电路的薄膜晶体管。
  11. 根据权利要求10所述的显示背板，其中，所述驱动电路包括栅极驱动电路和源极驱动电路中的至少一个。
  12. 根据权利要求1所述的显示背板，其中，所述第一基板包括第一基板层，所述第一基板具有贯穿所述第一基板层的第一连接件和第二连接件；
    所述第一薄膜晶体管的栅极经由所述第一连接件与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极连接，所述第一薄膜晶体管的源极经由所述第二连接件与所述至少一个第二薄膜晶体管中的另一个第二薄膜晶体管的漏极连接。
  13. 根据权利要求12所述的显示背板，其中，所述第一薄膜晶体管的栅极经由所述第一连接件与栅极驱动电路的一个第二薄膜晶体管的漏极连接，所述第一薄膜晶 体管的源极经由所述第二连接件与源极驱动电路的一个第二薄膜晶体管的漏极连接。
  14. 根据权利要求13所述的显示背板，其中，所述第一基板还包括位于所述第一基板层背离所述第一薄膜晶体管一侧的绝缘保护层，所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧的平坦化层；
    其中，所述第一连接件经由贯穿所述绝缘保护层和所述平坦化层的一个接触电极与所述栅极驱动电路的一个第二薄膜晶体管的漏极连接，所述第二连接件经由贯穿所述绝缘保护层和所述平坦化层的另一个接触电极与所述源极驱动电路的一个第二薄膜晶体管的漏极连接。
  15. 一种显示面板，包括：如权利要求1-14任意一项所述的显示背板。
  16. 一种显示装置，包括：如权利要求15所述的显示面板。
  17. 一种显示背板的制造方法，包括：
    形成第一背板，所述形成第一背板包括在第一基板上形成用于驱动发光单元的第一薄膜晶体管；
    形成第二背板，所述形成第二背板包括在第二基板上形成至少一个第二薄膜晶体管；和
    将所述第二背板与所述第一基板背离所述第一薄膜晶体管的一面接合，其中，在所述接合后，所述至少一个第二薄膜晶体管位于所述第二基板与所述第一基板之间。
  18. 根据权利要求17所述的方法，其中，所述第一薄膜晶体管的有源层的材料和所述第二薄膜晶体管的有源层的材料不同。
  19. 根据权利要求17所述的方法，其中，
    所述第一基板包括第一基板层、贯穿所述第一基板层的连接件、以及位于所述第一基板层背离所述第一薄膜晶体管的一侧的绝缘保护层，其中，所述连接件与所述第一薄膜晶体管的栅极和源极中的一个连接；
    所述第二背板还包括位于所述至少一个第二薄膜晶体管背离所述第二基板一侧 的平坦化层和贯穿所述平坦化层的接触电极，其中，所述接触电极与所述至少一个第二薄膜晶体管中的一个第二薄膜晶体管的漏极接触；
    所述将所述第二背板与所述第一基板背离所述第一薄膜晶体管的一面接合包括：
    在所述绝缘保护层与所述连接件对应的位置处形成开口，以露出所述连接件的至少一部分；
    将所述接触电极与所述连接件对齐；
    对所述第一背板和所述第二背板中的至少一个施加压力，以使得所述接触电极与所述连接件接触，从而键合在一起。
  20. 根据权利要求19所述的方法，其中，所述接触电极的材料包括Sn-Ag-Cu合金或者In-Sn合金；
    所述对所述第一背板和所述第二背板中的至少一个施加压力包括：
    在160℃至200℃的温度范围内，对所述第一背板和所述第二背板中的至少一个施加小于100kPa的压力。
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CN107248521A (zh) * 2017-06-19 2017-10-13 深圳市华星光电技术有限公司 Amoled背板结构
CN108831892A (zh) * 2018-06-14 2018-11-16 京东方科技集团股份有限公司 显示背板及其制造方法、显示面板和显示装置

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