WO2019235097A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2019235097A1
WO2019235097A1 PCT/JP2019/017626 JP2019017626W WO2019235097A1 WO 2019235097 A1 WO2019235097 A1 WO 2019235097A1 JP 2019017626 W JP2019017626 W JP 2019017626W WO 2019235097 A1 WO2019235097 A1 WO 2019235097A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
wiring
conductive
conduction
circuit pattern
Prior art date
Application number
PCT/JP2019/017626
Other languages
English (en)
French (fr)
Inventor
誠 磯崎
聖一 ▲高▼橋
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2020523563A priority Critical patent/JP6888742B2/ja
Priority to DE112019000169.8T priority patent/DE112019000169T5/de
Priority to CN201980006085.5A priority patent/CN111418049B/zh
Publication of WO2019235097A1 publication Critical patent/WO2019235097A1/ja
Priority to US16/883,464 priority patent/US11177190B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32155—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the semiconductor device includes, for example, semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Semiconductor Field Effect Transistor).
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Semiconductor Field Effect Transistor
  • Such a semiconductor device is used as, for example, a power conversion device.
  • a semiconductor device is arbitrarily connected by a wiring member using a plurality of IGBT chips and FWD (Free Wheeling Diode) chips. Thereby, the semiconductor device can realize a desired function such as an inverter.
  • Such a semiconductor device is required to have a large capacity. For example, a semiconductor module structure capable of processing a large current is demanded (for example, see Patent Document 1).
  • abnormal overheating in the wiring member which is not a problem with the conventional rated current, may occur.
  • abnormal overheating occurs in the wire connecting the circuit patterns of the ceramic circuit board. If abnormal overheating occurs inside the semiconductor device, the overheating may cause a failure of the semiconductor device. This leads to a decrease in the reliability of the semiconductor device.
  • This invention is made in view of such a point, and it aims at providing the semiconductor device which can suppress generation
  • a first conductive portion having a first conductive region and a first wiring region connected to the first conductive region via a first communication portion, a second conductive region, and the second conductive region.
  • a second conductive portion that communicates with the conduction region via a second communication portion and has a second wiring region that faces the first wiring region and is separated by a predetermined distance; and the first wiring region and the second wiring region; And a wiring member that electrically connects the first communication portion and the second communication portion as viewed from the wiring direction of the wiring member.
  • FIG. (1) which shows the modification of the circuit pattern of the ceramic circuit board of embodiment. It is FIG.
  • FIG. (2) which shows the modification of the circuit pattern of the ceramic circuit board of embodiment. It is FIG. (1) which shows the modification of the circuit pattern of the ceramic circuit board of a reference example. It is FIG. (2) which shows the modification of the circuit pattern of the ceramic circuit board of a reference example.
  • FIG. 1 is a plan view of an example of the semiconductor device of the embodiment
  • FIG. 2 is a cross-sectional view of the example of the semiconductor device of the embodiment. 2 is a cross-sectional view taken along one-dot chain line XX in FIG.
  • the semiconductor device 60 includes ceramic circuit boards 10a and 10b, semiconductor elements 21a, 21b, 21c and 21d provided on the front surfaces of the ceramic circuit boards 10a and 10b, and semiconductor elements. 22a, 22b, 22c, 22d.
  • the ceramic circuit boards 10a and 10b are electrically connected by wires 51a and 51b.
  • the semiconductor device 60 includes a case in which the ceramic circuit boards 10a and 10b are arranged on the heat sink 30 and the heat sink 30 arranged via solder (not shown) and surround the ceramic circuit boards 10a and 10b. 40.
  • the case 40 and the ceramic circuit boards 10a and 10b are electrically connected by wires 52a, 52b and 52c.
  • the semiconductor device 60 a case where the connection between the ceramic circuit boards 10a and 10b and the connection between the ceramic circuit boards 10a and 10b and the case 40 are performed by a plurality of wires 51a, 51b, 52a, 52b, and 52c, respectively, is exemplified. Yes.
  • the semiconductor device 60 is not limited to the plurality of wires 51a, 51b, 52a, 52b, and 52c, and may be any wiring member having conductivity.
  • the wiring member has two or more joint portions that are joined to the ceramic circuit boards 10a and 10b or the case 40 directly or via a joining member such as solder, and the electrical connection therebetween is established. Further, the wiring member has a non-bonded portion that does not contact the ceramic circuit boards 10a and 10b or the case 40 between the bonded portions.
  • the wiring member may be a plate-like lead frame or a ribbon-like ribbon.
  • the semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are switching elements made of silicon or silicon carbide.
  • the switching element is, for example, an IGBT or a power MOSFET.
  • Such semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are controlled, for example, with the input electrode (drain electrode or collector electrode) as the main electrode on the back surface and the main electrode on the front surface.
  • An electrode (gate electrode) and an output electrode (source electrode or emitter electrode) are provided.
  • the semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d include diodes such as SBD (Schottky Barrier Diode) and FWD as necessary.
  • Such semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, 22d have an output electrode (cathode electrode) as a main electrode on the back surface and an input electrode (anode electrode) as a main electrode on the front surface.
  • the semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d may include a RC (Reverse-Conducting) -IGBT that is a single element in which an IGBT and an FWD are combined.
  • the case where only the semiconductor elements 21a, 21b, 21c, 21d, 22a, 22b, 22c, and 22d are included is described as an example.
  • electronic components may be installed as necessary.
  • the electronic component is, for example, a resistor, a thermistor, a capacitor, a surge absorber, or the like.
  • the metal plates 12a and 12b are made of a metal such as aluminum, iron, silver, copper, or an alloy containing at least one of them having excellent thermal conductivity.
  • the circuit patterns 13a, 14a, 15a, and 16a and the circuit patterns 13b, 14b, and 15b are made of metal such as copper or copper alloy having excellent conductivity.
  • the semiconductor elements 21a, 21b, 21c, and 21d and the semiconductor elements 22a, 22b, 22c, and 22d are arranged on the circuit patterns 14a and 13b, respectively.
  • the circuit pattern 16a is electrically connected to the control electrodes of the semiconductor elements 21a, 21b, 21c, and 21d through wires (not shown).
  • the circuit pattern 15b is electrically connected to the control electrodes of the semiconductor elements 22a, 22b, 22c, and 22d via wires (not shown).
  • the circuit pattern 13a is electrically connected to the output electrodes of the semiconductor elements 21a, 21b, 21c, and 21d via wires (reference numerals omitted).
  • the circuit pattern 14b is electrically connected to the output electrodes of the semiconductor elements 22a, 22b, 22c, and 22d through wires (not shown).
  • the numbers and shapes of the circuit patterns 13a, 14a, 15a, and 16a and the circuit patterns 13b, 14b, and 15b are examples, and other numbers and shapes may be used.
  • the thickness of the circuit patterns 13a, 14a, 15a, 16a and the circuit patterns 13b, 14b, 15b is 0.1 mm or more and 1 mm or less. Details of the circuit patterns 13a, 14a, 15a, 16a and the circuit patterns 13b, 14b, 15b will be described later.
  • a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board can be used as the ceramic circuit boards 10a and 10b having such a configuration.
  • the ceramic circuit boards 10a and 10b are formed of the semiconductor elements 21a, 21b, 21c, and 21d and the heat generated in the semiconductor elements 22a, 22b, 22c, and 22d, the circuit pattern 14a and the circuit pattern 13b, the insulating plates 11a and 11b, and the metal plate 12a, It can be made to conduct to the heat sink 30 side through 12b.
  • the heat sink 30 is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of them having excellent thermal conductivity.
  • a material such as nickel may be formed on the surface of the heat sink 30 by plating or the like.
  • nickel there are a nickel-phosphorus alloy, a nickel-boron alloy, and the like.
  • the cooler in this case is made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of them having excellent thermal conductivity.
  • the cooler a fin, a heat sink composed of a plurality of fins, a cooling device by water cooling, or the like can be applied.
  • the heat sink 30 may be integrated with such a cooler. In that case, it is comprised with the alloy containing aluminum, iron, silver, copper excellent in thermal conductivity, or at least one of these.
  • materials such as nickel, on the surface of the heat sink 30 integrated with the cooler by the plating process etc., for example.
  • nickel there are a nickel-phosphorus alloy, a nickel-boron alloy, and the like.
  • the case 40 has a side wall 41 that forms a storage area 44 in a box shape that surrounds the four sides.
  • step portions 42 a and 42 b are formed on the side of the storage region 44 of the opposite side wall portion 41 among the side wall portions 41 that surround the four sides.
  • terminal arrangement portions 43a, 43b, 43c, and 43d are formed at end portions on the opening side of the side wall portion 41 where the step portions 42a and 42b are formed.
  • the case 40 includes an internal terminal portion 45a disposed on the step portion 42a and an external terminal portion 46a disposed on the terminal placement portion 43a.
  • the external connection terminal 46 a is electrically connected to the internal terminal portion 45 a and the side wall portion 41.
  • the case 40 includes an internal terminal portion 45b disposed on the step portion 42a and an external terminal portion 46b disposed on the terminal placement portion 43b.
  • the external connection terminal 46 b is electrically connected within the internal terminal portion 45 b and the side wall portion 41.
  • the case 40 includes an internal terminal portion 45c disposed on the step portion 42b and external terminal portions 46c and 46d disposed on the terminal placement portions 43c and 43d.
  • the external connection terminals 46 c and 46 d are electrically connected to the internal terminal portion 45 c and the side wall portion 41.
  • the internal terminal portion 45a and the circuit pattern 14a are electrically connected by a wire 52a.
  • the internal terminal portion 45b and the circuit pattern 15a are electrically connected by a wire 52c.
  • the internal terminal portion 45c and the circuit pattern 13b are electrically connected by a wire 52b. Accordingly, a positive electrode is connected to the external terminal portion 46a and a negative electrode is connected to the external terminal portion 46b, and outputs are obtained from the external terminal portions 46c and 46d.
  • the side wall 41 of the case 40 includes a control terminal to which a control signal is input. The control terminals are electrically connected to the circuit patterns 16a and 15b, respectively.
  • Such a case 40 is configured by, for example, injection molding using a thermoplastic resin.
  • Examples of such a resin include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.
  • PPS polyphenylene sulfide
  • PBT polybutylene terephthalate
  • PBS polybutylene succinate
  • PA polyamide
  • ABS acrylonitrile butadiene styrene
  • the housing region 44 of the case 40 is filled with a sealing member, and the semiconductor elements 21a, 21b, 21c, 21d and the semiconductor elements 22a, 22b, 22c, 22d in the storage region 44
  • the structures such as the wires 52a, 52b, and 52c and the ceramic circuit boards 10a and 10b are sealed.
  • the sealing member is made of a thermosetting resin such as a maleimide-modified epoxy resin, a maleimide-modified phenol resin, or a maleimide resin.
  • the sealing member may be made of silicone gel.
  • the wires 51a, 51b, 52a, 52b, and 52c (and the wires that are omitted from the reference numerals) used in the semiconductor device 60 include aluminum, copper, or at least one of these having excellent conductivity. It is composed of an alloy or the like. Moreover, it is preferable that these diameters are 100 micrometers or more and 1 mm or less.
  • FIG. 3 is a plan view of an example of the ceramic circuit board according to the embodiment.
  • the ceramic circuit boards 10a and 10b shown in FIG. 3 are included in the semiconductor device 60 shown in FIGS. 1 and 2, and a plan view thereof is shown.
  • the circuit patterns 13a, 14a, 15a, and 16a are arranged on the insulating plate 11a in the ceramic circuit board 10a.
  • the circuit pattern 13a includes a conduction region 13a1 and a wiring region 13a3 that communicates with the conduction region 13a1 via a communication portion 13a2 (shown by a broken line).
  • the conduction region 13a1 is a region that is electrically connected to the semiconductor elements 21a and 21b through wires (not shown) and conducts current to the semiconductor elements 21a and 21b.
  • the wiring region 13a3 is a region to which a wire 51a that conducts current to the circuit pattern 13b is connected.
  • the wiring region 13a3 is wider than the conduction region 13a1, and the wiring region 13a3 extends perpendicularly to the conduction region 13a1.
  • the circuit pattern 15a includes a conduction region 15a1 and a wiring region 15a3 that communicates with the conduction region 15a1 via a communication portion 15a2 (shown by a broken line).
  • the wiring region 15a3 is wider than the conduction region 15a1, and the wiring region 15a3 extends perpendicular to the conduction region 15a1.
  • the circuit pattern 14a includes element arrangement regions 14a1 and 14a2 in which the semiconductor elements 21a, 21b, 21c, and 21d are arranged.
  • the circuit patterns 13b, 14b, and 15b are arranged on the insulating plate 11b in the ceramic circuit board 10b.
  • the circuit pattern 13b includes a conduction region 13b1 and a wiring region 13b3 that communicates with the conduction region 13b1 via a communication portion 13b2 (shown by a broken line) and is opposed to the wiring region 13a3 by a predetermined distance.
  • the conduction region 13b1 is a region in which the semiconductor elements 22a and 22b are arranged and current is conducted to the semiconductor elements 22a and 22b.
  • the wiring region 13b3 is a region to which a wire 51a that conducts current is connected to another circuit pattern 13a.
  • the wiring region 13b3 is wider than the conduction region 13b1, and the wiring region 13b3 extends perpendicularly to the conduction region 13b1. That is, the conduction regions 13a1 and 13b1 extend to the opposite sides with respect to the wiring regions 13a3 and 13b3.
  • the communication portion 13b2 has a cutout portion 13b4 at a side portion thereof where at least the communication portion 13a2 and the conduction region 13b1 overlap when viewed from the wiring direction W1 of the wire 51a. Furthermore, the notch 13b4 is formed so as to be equal to or larger than the width of the communication portion 13a2 when viewed from the wiring direction W1 of the wire 51a from the side opposite to the extending direction of the wiring region 13a3.
  • the wiring direction W1 of the wire 51a indicates a direction composed of two connection points, that is, a connection point of the wire 51a in the ceramic circuit board 10a and a connection point of the wire 51a in the ceramic circuit board 10b.
  • the conduction region 13b1 includes element arrangement regions 13b5 and 13b6 in which the semiconductor elements 22a, 22b, 22c, and 22d are arranged.
  • the circuit pattern 14b includes a conductive region 14b1 and a wiring region 14b3 that communicates with the conductive region 14b1 via a communication portion 14b2 (shown by a broken line) and is opposed to the wiring region 15a3 by a predetermined distance.
  • the wiring region 14b3 is wider than the conduction region 14b1, and the wiring region 14b3 extends at a right angle to the conduction region 14b1. That is, the conduction regions 15a1 and 14b1 extend to the opposite sides with the wiring regions 15a3 and 14b3 interposed therebetween.
  • external connection terminals may be electrically connected to the conductive regions 13a1 and 15a1 of the circuit patterns 13a and 15a of the ceramic circuit board 10a as necessary.
  • external connection terminals may be electrically connected to the conductive regions 13b1 and 14b1 of the circuit patterns 13b and 14b of the ceramic circuit board 10b as necessary.
  • the wiring region 13a3 of the circuit pattern 13a and the wiring region 13b3 of the circuit pattern 13b are connected by a wire 51a (not shown in FIG. 3).
  • the wiring region 15a3 of the circuit pattern 15a and the wiring region 14b3 of the circuit pattern 14b are connected by a wire 51b (not shown in FIG. 3).
  • the communication portion 13a2 of the circuit pattern 13a and the communication portion 13b2 of the circuit pattern 13b are separated (distance D1) as viewed from the wiring direction W1 of the wire 51a.
  • the communication portion 15a2 of the circuit pattern 15a and the communication portion 14b2 of the circuit pattern 14b are separated (distance D2) as viewed from the wiring direction W2 of the wire 51b.
  • the wiring regions 13a3, 15a3, 13b3, and 14b3 are examples in which the wires 51a and 51b that connect the circuit patterns 13a, 13b, 14b, and 15a between the ceramic wiring substrates 10a and 10b are connected. It was.
  • the wiring region may be a region where wires 52a, 52b, and 52c that connect the circuit patterns 14a, 15a, and 13b of the ceramic wiring substrates 10a and 10b and the internal terminal portion 45a of the case 40 are connected.
  • the wires 51a, 51b, 52a, 52b, and 52c may be wiring members, and may be lead frames or ribbons, for example.
  • FIG. 4 is a plan view of a sample ceramic circuit board of a reference example.
  • the same reference numerals are given to the same configurations as the semiconductor device 60.
  • the circuit pattern 113b of the ceramic circuit board 110b includes a conduction region 13b1 and a wiring region 13b3 that communicates with the conduction region 13b1 via a communication portion 113b2 (shown by a broken line). That is, unlike the communication portion 13b2, the communication portion 113b2 is not formed with the cutout portion 13b4.
  • the wiring region 13a3 of the circuit pattern 13a and the wiring region 13b3 of the circuit pattern 113b are electrically connected by a wire 51a.
  • the wiring region 15a3 of the circuit pattern 15a and the wiring region 14b3 of the circuit pattern 14b are electrically connected by a wire 51b.
  • the element arrangement regions 14a1 and 14a2 of the circuit pattern 14a and the conduction region 13a1 of the circuit pattern 13a are electrically connected by wires (reference numerals omitted).
  • the element arrangement regions 13b5 and 13b6 of the circuit pattern 113b and the conduction region 14b1 of the circuit pattern 14b are electrically connected by a wire (reference numeral omitted).
  • a current of 1000 A is input from the circuit patterns 14a and 15a of the ceramic circuit board 10a (regions to which the wires 52a and 52c are connected (FIG. 1)). Then, a current is output from the circuit pattern 113b of the ceramic circuit board 110b (a portion corresponding to a region to which the wire 52b of the circuit pattern 13b in FIG. 1 is connected).
  • the surface temperature distribution in the circuit patterns 13a and 113b and the wire 51a when the current was circulated was analyzed.
  • the current input to the circuit pattern 14a is conducted along the conduction path Ia1 in the circuit pattern 13a and flows into the wire 51a.
  • the current from the wire 51a is conducted along the conduction path Ib1 in the circuit pattern 113b.
  • the current input to the circuit pattern 14b is conducted along the conduction path Ib2 in the circuit pattern 14b and flows into the wire 51b.
  • the current from the wire 51b is conducted through the circuit pattern 15a along the conduction path Ib2.
  • FIG. 5 is a diagram showing the rising temperature distribution on the surface of the main part of the sample of the ceramic circuit board of the reference example.
  • the analysis results of the rising temperatures of the circuit patterns 13a and 113b and the wires 51a to be measured are displayed.
  • the isoline described in FIG. 5 represents the distribution of the rising temperature.
  • the wire 51a is represented by a rectangular shape for the sake of convenience in expressing the distribution of the rising temperature.
  • the highest rising temperature (110 ° C.) was analyzed in the isoline region Ta1 on the side close to the communicating portion 13a2 of the wire 51a (the lower side in FIG. 5). Further, as the distance from the region Ta1 increases, the rising temperature decreases. As described with reference to FIG. 4, the current is conducted in the circuit pattern 13a along the conduction path Ia1. That is, when the current flows from the conduction region 13a1 into the wiring region 13a3 via the communication portion 13a2, the conduction direction turns 90 degrees to conduct the wiring region 13a3 (upward in FIG. 5). For this reason, in the circuit pattern 13a, it is possible that the temperature inside a turning part becomes high.
  • region 13a3 flows out into the wire 51a.
  • the current flowing from the wire 51a is conducted along the conduction path Ib1 in the circuit pattern 113b.
  • the lower side in FIG. 5 is shorter than the upper side. Therefore, the wire 51a has a larger current flow rate on the lower side in FIG. 5 than on the upper side.
  • the conduction region 13b1 of the circuit pattern 113b also has a higher current flow rate and a higher temperature on the lower side in FIG.
  • the circuit patterns 13a and 113b through which the current is conducted are asymmetric, the current conduction paths Ia1 and Ib1 through which the current is conducted are also asymmetric. For this reason, in the wire 51a, the heat generation location is biased.
  • the surface temperature distribution and the like related to the circuit patterns 15a and 14b and the wire 51b will be described later.
  • a predetermined current was actually conducted to such a sample 70 and observed with a thermo viewer. As a result, it was found that the highest temperature of the wire 51a was about 270 ° C., and abnormal overheating occurred. That is, the wire 51a has a larger current flow rate on the lower side in FIG. 5 than on the upper side.
  • the wire 51a is separated from the ceramic circuit boards 10a and 10b except for the joint portions with the wiring regions 13a3 and 13b3, it is difficult to be cooled. Therefore, it is considered that abnormal overheating has occurred in the region Ta1 on the side close to the communication portion 13a2 of the wire 51a.
  • the inventors have found that the abnormal overheating of the wiring member that is the wire 51a is promoted by the variation in the current path length due to the shape of the circuit patterns 13a and 113b. In particular, current concentrates in a short current path portion, and abnormal overheating occurs due to loss due to the resistance of the wiring member.
  • FIG. 6 is a plan view of a sample of the ceramic circuit board of the embodiment.
  • a sample 80 of the ceramic circuit boards 10a and 10b of the semiconductor device 60 shown in FIG. 6 is provided with a circuit pattern 13b instead of the circuit pattern 113b of the sample 70.
  • the circuit pattern 13b of the ceramic circuit board 10b includes a conductive region 13b1 and a wiring region 13b3 communicated via a communication portion 13b2 configured by forming a notch 13b4 in the conductive region 13b1.
  • Other configurations and analysis of the surface temperature distribution are the same as those of the sample 70.
  • the current input to the circuit pattern 14a is conducted along the conduction path Ia1 in the circuit pattern 13a and flows into the wire 51a.
  • the notch part 13b4 is formed in the circuit pattern 13b, the current from the wire 51a passes along the conduction path Ib3 in the order of the wiring area 13b3, the communication part 13b2, and the conduction area 13b1 in the circuit pattern 13b.
  • the current input to the circuit pattern 14b is conducted along the conduction path Ib2 in the circuit pattern 14b and flows into the wire 51b. Then, the current from the wire 51b is conducted along the conduction path Ia2 in the circuit pattern 15a.
  • FIG. 7 is a diagram showing the temperature rise distribution on the surface of the main part of the sample of the ceramic circuit board according to the embodiment.
  • the analysis results of the rising temperatures of the circuit patterns 13a and 13b and the wires 51a to be measured are displayed.
  • the isoline described in FIG. 7 represents the distribution of the rising temperature.
  • the wire 51a is represented by a rectangular shape for the sake of convenience in expressing the temperature rise distribution.
  • an isoline region Ta1 on the side close to the communication portion 13a2 of the wire 51a (lower side in FIG. 7) and a region Tb1 on the side close to the communication portion 13b2 of the wire 51a (upper side in FIG. 7) Were the same temperature and the highest temperature rise (80 ° C.).
  • the temperature decreased as the distance from the regions Ta1 and Tb1 increased.
  • the variation in the rising temperature of the surface was small compared with the case where notch part 13b4 is not formed (sample 70).
  • the communication part 13a2 and the communication part 13b2 are separated from each other when viewed from the wiring direction of the wire 51a. That is, the conduction path Ia1 in the circuit pattern 13a and the conduction path Ib3 in the circuit pattern 13b are point-symmetric (with respect to the center of the wire 51a). For this reason, the variation in the length of the conduction path from the conduction region 13a1 to the conduction region 13b1 via the wire 51a is smaller than that in the case where the notch 13b4 is not formed (sample 70). For this reason, the current flows easily in the wire 51a.
  • the temperature deviation of the wire 51a is suppressed.
  • a predetermined current was actually conducted to such a sample 80 and observed with a thermo viewer.
  • the highest temperature was below 250 ° C., and no abnormal overheating occurred. That is, the inventors suppress the variation in the current path length caused by the shape of the circuit patterns 13a and 13b by separating the communication portion 13a2 and the communication portion 13b2 from the wiring direction of the wire 51a. It has been found that the current in the wiring member which is the wire 51a becomes uniform, and as a result, the occurrence of abnormal overheating can be prevented.
  • the circuit patterns 15a and 14b have not been analyzed for the temperature rise of the surface as described above, but have a point-symmetric shape with respect to the center of the region of the wire 51b, and the communication portion 15a2 and the communication portion 14b2 are formed.
  • the wires 51b are separated from each other when viewed from the wiring direction.
  • the conduction paths Ia2 and Ib2 are symmetrical. That is, even in this case, the variation in the length of the conduction path from the conduction region 14b1 to the conduction region 15a1 via the wire 51b can be reduced. Thereby, it is considered that the temperature deviation of the wire 51b is also suppressed.
  • FIG. 8 is a plan view of another sample of the ceramic circuit board according to the embodiment.
  • a plurality of samples 85 shown in FIG. 8 are formed so that at least two points on the surface of the conduction region 15a1 of the circuit pattern 15a of the sample 80 are electrically connected by the ground wire 53.
  • Other configurations and analysis of the surface temperature distribution are the same as those of the sample 80.
  • the ground wire 53 is formed in the conduction region 15a1 of the circuit pattern 15a is described as an example.
  • the ground wire 53 is made of aluminum, copper, or an alloy containing at least one of them having excellent conductivity.
  • these diameters are 100 micrometers or more and 1 mm or less. It can be formed by a wire bonding apparatus. Such a ground wire 53 is not limited to this case, and may be appropriately formed on the circuit pattern according to the shape and size of the circuit pattern.
  • the rising temperature distribution on the surface is the same as the rising temperature distribution of the sample 80 shown in FIG.
  • the internal resistance of samples 80 and 85 was measured with a tester. Each internal resistance is the total electric resistance excluding the semiconductor elements 21a, 21b, 21c, and 21d and the semiconductor elements 22a, 22b, 22c, and 22d from the internal terminal part 45a to the internal terminal part 45b of the case 40. As a result, the internal resistance of the sample 85 was 82% of the internal resistance of the sample 80 shown in FIG.
  • FIGS. 9 and 10 are diagrams showing modifications of the circuit pattern of the ceramic circuit board according to the embodiment.
  • FIG. 9 shows a case (corresponding to circuit patterns 13a and 13b) in which current conduction paths in a pair of circuit patterns are made symmetric by forming a notch.
  • FIG. 10 shows a case (corresponding to the circuit patterns 15a and 14b) in which current conduction paths of a pair of circuit patterns are symmetric based on the shape.
  • FIG. 9A shows a case where the circuit pattern 13b side is displaced upward in FIG.
  • FIG. 9A shows a case where the circuit pattern 13b side is displaced upward in FIG.
  • FIG. 9A shows a case where the circuit pattern 13b side is displaced upward in FIG.
  • FIG. 9A shows a case where the circuit pattern 13b side is displaced upward in FIG.
  • circuit patterns 23a and 23b are electrically connected by a wire 51a.
  • the circuit pattern 23a includes a conduction region 23a1 and a wiring region 23a3 that communicates with the conduction region 23a1 through the communication portion 23a2 to the central portion.
  • the circuit pattern 23b includes a conductive region 23b1 and a wiring region 23b3 that is connected to the conductive region 23b1 through a pair of communication portions 23b2 that are formed by forming a notch 23b4 in the center.
  • FIG. 9C circuit patterns 23a and 23b are electrically connected by a wire 51a.
  • the circuit pattern 23a includes a conduction region 23a1 and a wiring region 23a3 that communicates with the conduction region 23a1 through the communication portion 23a2 to the central portion.
  • the circuit pattern 23b includes a conductive region 23b1 and a wiring region 23b3 that is connected to the conductive region 23b1 through a pair of communication portions 23b2 that are formed by forming a notch 23
  • FIG. 10A shows a case where the circuit pattern 14b side is displaced upward in FIG.
  • FIG. 10B shows a case where only the conduction region 14b1 of the circuit pattern 14b is displaced upward in FIG.
  • FIG. 10C shows a case where the circuit pattern 14b side is displaced upward in FIG. 10B.
  • the cutout portion 13b4 is formed so that the communication portion 13a2 of the circuit pattern 13a and the communication portion 13b2 of the circuit pattern 13b are in the wiring direction of the wire 51a. Seen away from each other. Also in FIG. 9C, the cutout portion 23b4 is formed so that the communication portion 23a2 of the circuit pattern 23a and the communication portion 23b2 of the circuit pattern 23b are separated from each other when viewed from the wiring direction of the wire 51a. In all of FIG. 10, the communication portion 15a2 of the circuit pattern 15a and the communication portion 14b2 of the circuit pattern 14b are separated from each other when viewed from the wiring direction of the wire 51b.
  • the current conduction paths in the circuit patterns 13a and 15a and the circuit patterns 13b and 14b are point-symmetric with respect to the centers of the wires 51a and 51b. Further, the current conduction paths in the circuit pattern 23a and the circuit pattern 23b are axisymmetric with respect to the wiring direction of the wire 51a. Thereby, the bias of heat generation between the circuit patterns 13a, 23a, 15a and the circuit patterns 13b, 23b, 14b is prevented and the internal resistance is reduced. Therefore, the temperature rise of the wires 51a and 51b is suppressed.
  • FIGS. 11 and 12 are diagrams showing modifications of the circuit pattern of the ceramic circuit board of the reference example.
  • FIG. 11 shows the case where the current conduction paths in the pair of circuit patterns are symmetrized by forming the notches.
  • FIG. 12 shows a case where the current conduction paths of a pair of circuit patterns are symmetrized based on the shape. 11 and 12 show only the circuit pattern of the ceramic circuit board.
  • circuit patterns 80a and 80b are electrically connected by a wire 51a.
  • the circuit pattern 80a includes a conduction region 80a1 and a wiring region 80a3 that communicates with the conduction region 80a1 via a communication unit 80a2.
  • the circuit pattern 80b includes a conductive region 80b1 and a wiring region 80b3 communicated via a communication portion 80b2 configured by forming a notch 80b4 in the conductive region 80b1.
  • the cutout portion 80b4 is shallow, and the communication portion 80a2 of the circuit pattern 80a and the communication portion 80b2 of the circuit pattern 80b overlap with each other as viewed from the wiring direction of the wire 51a.
  • the conduction paths of the circuit patterns 80a and 80b are not symmetric because the communication portion 80a2 and the communication portion 80b2 are overlapped when viewed from the wiring direction of the wire 51a. . For this reason, the heat generation portions of the circuit patterns 80a and 80b are biased, and the temperature of the wire 51a may rise without reducing the internal resistance.
  • circuit patterns 81a and 81b are electrically connected by wires 51b.
  • the circuit pattern 81a includes a conduction region 81a1 and a wiring region 81a3 that communicates with the conduction region 81a1 via a communication portion 81a2.
  • the circuit pattern 81b includes a conduction region 81b1 and a wiring region 81b3 that communicates with the conduction region 81b1 via a communication portion 81b2. Also in this case, the communication portion 81a2 of the circuit pattern 81a and the communication portion 81b2 of the circuit pattern 81b overlap with each other as viewed from the wiring direction of the wire 51b.
  • the conduction paths of the circuit patterns 81a and 81b are not symmetric because the communication portion 81a2 and the communication portion 81b2 have overlapping portions when viewed from the wiring direction of the wire 51b. . For this reason, the heat generation portions of the circuit patterns 81a and 81b are biased, and the temperature of the wire 51b may increase without reducing the internal resistance.
  • circuit patterns 82a and 82b are electrically connected by wires 51b.
  • the circuit pattern 82a includes a conduction region 82a1 and a wiring region 82a3 that communicates with the conduction region 82a1 via a communication portion 82a2.
  • the circuit pattern 82b includes a conduction region 82b1 and a wiring region 82b3 that communicates with the conduction region 82b1 via a communication portion 82b2. Also in this case, the communication portion 82a2 of the circuit pattern 82a and the communication portion 82b2 of the circuit pattern 82b are arranged to face each other when viewed from the wiring direction of the wire 51b.
  • the current is conducted from the conduction region 82a1 to the wiring region 82a3 and flows from the wire 51b to the wiring region 82b3.
  • the temperature above the communication portion 82b2 in the drawing may increase.
  • the heat generation portions of the circuit patterns 82a and 82b are biased, and the temperature of the wire 51b may increase without reducing the internal resistance.
  • the circuit patterns 83a and 83b are electrically connected by the wire 51b.
  • the circuit pattern 83a includes a conduction region 83a1 and a wiring region 83a3 that communicates with the conduction region 83a1 via a communication portion 83a2.
  • the circuit pattern 83b includes a conduction region 83b1 and a wiring region 83b3 that communicates with the conduction region 83b1 via a communication portion 83b2.
  • the communication portion 83a2 of the circuit pattern 83a and the communication portion 83b2 of the circuit pattern 83b are arranged to face each other when viewed from the wiring direction of the wire 51b.
  • the current is conducted from the conduction region 83a1 to the wiring region 83a3 (so as to branch) and flows from the wire 51b to the wiring region 83b3.
  • the temperature at both ends (upper and lower in the drawing) of the communication portion 83b2 may increase.
  • the heat generation portions of the circuit patterns 83a and 83b are biased, and the temperature of the wire 51b may increase without reducing the internal resistance.
  • the semiconductor device 60 has circuit patterns 13a and 15a having conductive regions 13a1 and 15a1 and wiring regions 13a3 and 15a3 connected to the conductive regions 13a1 and 15a1 through the communication portions 13a2 and 15a2. Further, circuit patterns 13b and 14b having conductive regions 13b1 and 14b1 and conductive regions 13b1 and 14b1 are connected to each other through communication portions 13b2 and 14b2 and have wiring regions 13b3 and 14b3 that are spaced apart from each other by a predetermined distance. Have Then, wires 51a and 51b are provided to electrically connect the wiring regions 13a3 and 15a3 and the wiring regions 13b3 and 14b3.
  • the communication portions 13a2 and 15a2 and the communication portions 13b2 and 14b2 are separated from each other when viewed from the wiring direction of the wires 51a and 51b.
  • the conduction path in the circuit patterns 13a and 15a and the conduction path in the circuit patterns 13b and 14b are point-symmetric (with respect to the centers of the wires 51a and 51b).
  • biasing of the electric current of wire 51a, 51b is reduced, the raise of the temperature of wire 51a, 51b is suppressed. Therefore, the semiconductor device 60 can prevent the occurrence of damage or the like due to heat generation, and suppress a decrease in reliability.
  • the conduction paths to the circuit patterns 13a and 13b and the circuit patterns 15a and 14b in the semiconductor device 60 are controlled to suppress an increase in the temperature of the wires 51a and 51b.
  • the circuit patterns are not limited to the circuit patterns 13a and 13b and the circuit patterns 15a and 14b.
  • the circuit patterns 13a and 13b and the circuit patterns 15a and 15a of the present embodiment are connected to the pair of conductive parts. It is possible to control the conduction path as in 14b.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

内部の異常過熱の発生を抑制できる。　導通領域（１３ａ１，１５ａ１）と導通領域（１３ａ１，１５ａ１）に連通部（１３ａ２，１５ａ２）を介して連通した配線領域（１３ａ３，１５ａ３）とを有する回路パターン（１３ａ，１５ａ）を有する。また、導通領域（１３ｂ１，１４ｂ１）と導通領域（１３ｂ１，１４ｂ１）に連通部（１３ｂ２，１４ｂ２）を介して連通し、配線領域（１３ａ３，１５ａ３）と所定の間隔離れて向かい合う配線領域（１３ｂ３，１４ｂ３）とを有する回路パターン（１３ｂ，１４ｂ）を有する。そして、配線領域（１３ａ３，１５ａ３）と配線領域（１３ｂ３，１４ｂ３）とを電気的に接続するワイヤを備えている。この際、連通部（１３ａ２，１５ａ２）と連通部（１３ｂ２，１４ｂ２）とがワイヤの配線方向（Ｗ１，Ｗ２）から見て離間している。

Description

半導体装置
　本発明は、半導体装置に関する。
　半導体装置は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等の半導体素子を含んでいる。このような半導体装置は、例えば、電力変換装置として利用されている。半導体装置は、ＩＧＢＴチップとＦＷＤ（Free Wheeling Diode）チップとを複数用いて、配線部材で任意に接続される。これにより半導体装置はインバータ等の所望の機能を実現することができる。このような、半導体装置においては、大容量化が求められている。例えば、大電流を処理することが可能な半導体モジュール構造が求められている（例えば、特許文献１参照）。
特開平８－７８６２０号公報
　ところで、大容量化として定格電流を増加させると、従来の定格電流では問題とならなかった、配線部材における異常過熱が発生してしまう場合がある。例えば、セラミック回路基板の回路パターン間を接続するワイヤに異常過熱が発生してしまう。半導体装置の内部に異常過熱が生じると、その過熱が半導体装置の故障の原因となるおそれがある。これが、半導体装置の信頼性の低下につながる。
　本発明は、このような点に鑑みてなされたものであり、内部の異常過熱の発生を抑制できる半導体装置を提供することを目的とする。
　本発明の一観点によれば、第１導通領域と前記第１導通領域に第１連通部を介して連通した第１配線領域とを有する第１導電部と、第２導通領域と前記第２導通領域に第２連通部を介して連通し、前記第１配線領域と所定の間隔離れて向かい合う第２配線領域とを有する第２導電部と、前記第１配線領域と前記第２配線領域とを電気的に接続する配線部材とを備え、前記第１連通部と前記第２連通部とが前記配線部材の配線方向から見て離間している、半導体装置が提供される。
　開示の技術によれば、内部の異常過熱の発生を抑制して、信頼性の低下を防止することができる。
　本発明の上記及び他の目的、特徴及び利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
実施の形態の半導体装置の一例の平面図である。 実施の形態の半導体装置の一例の断面図である。 実施の形態のセラミック回路基板の一例の平面図である。 参考例のセラミック回路基板のサンプルの平面図である。 参考例のセラミック回路基板のサンプルの要部の表面の上昇温度分布を示す図である。 実施の形態のセラミック回路基板のサンプルの平面図である。 実施の形態のセラミック回路基板のサンプルの要部の表面の上昇温度分布を示す図である。 実施の形態のセラミック回路基板の別のサンプルの平面図である。 実施の形態のセラミック回路基板の回路パターンの変形例を示す図（その１）である。 実施の形態のセラミック回路基板の回路パターンの変形例を示す図（その２）である。 参考例のセラミック回路基板の回路パターンの変形例を示す図（その１）である。 参考例のセラミック回路基板の回路パターンの変形例を示す図（その２）である。
　以下、図面を参照して、実施の形態について説明する。実施の形態の半導体装置について、図１及び図２を用いて説明する。図１は、実施の形態の半導体装置の一例の平面図であり、図２は、実施の形態の半導体装置の一例の断面図である。なお、図２は、図１の一点鎖線Ｘ－Ｘにおける断面図である。半導体装置６０は、図１及び図２に示されるように、セラミック回路基板１０ａ，１０ｂとセラミック回路基板１０ａ，１０ｂのおもて面に設けられた半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ及び半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄとを有している。なお、セラミック回路基板１０ａ，１０ｂはワイヤ５１ａ，５１ｂにより電気的に接続されている。さらに、半導体装置６０は、このようなセラミック回路基板１０ａ，１０ｂがはんだ（図示を省略）を介して配置された放熱板３０と放熱板３０上に配置され、セラミック回路基板１０ａ，１０ｂを取り囲むケース４０とを有している。なお、ケース４０とセラミック回路基板１０ａ，１０ｂはワイヤ５２ａ，５２ｂ，５２ｃで電気的に接続されている。
　半導体装置６０では、セラミック回路基板１０ａ，１０ｂ間の接続、セラミック回路基板１０ａ，１０ｂとケース４０との接続をそれぞれ複数のワイヤ５１ａ，５１ｂ，５２ａ，５２ｂ，５２ｃにより行っている場合を例示している。半導体装置６０では、複数のワイヤ５１ａ，５１ｂ，５２ａ，５２ｂ，５２ｃに限らず、導電性を有する配線部材であればよい。配線部材は、セラミック回路基板１０ａ，１０ｂ、または、ケース４０に直接、または、はんだ等の接合部材を介して接合される２つ以上の接合箇所を有し、その間が電気的に導通される。また、配線部材は、接合箇所と接合箇所の間に、セラミック回路基板１０ａ，１０ｂ、または、ケース４０と接触しない非接合箇所を有する。また、配線部材は、板状のリードフレームまたは薄帯状のリボンを用いてもよい。
　半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄは、シリコンまたは炭化シリコンから構成されるスイッチング素子である。スイッチング素子は、例えば、ＩＧＢＴ、パワーＭＯＳＦＥＴ等である。このような半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄは、例えば、裏面に主電極として入力電極（ドレイン電極またはコレクタ電極）を、おもて面に、主電極として制御電極（ゲート電極）及び出力電極（ソース電極またはエミッタ電極）をそれぞれ備えている。また、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄは、必要に応じて、ＳＢＤ（Schottky Barrier Diode）、ＦＷＤ等のダイオードを含んでいる。このような半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄは、裏面に主電極として出力電極（カソード電極）を、おもて面に主電極として入力電極（アノード電極）をそれぞれ備えている。また、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄは、ＩＧＢＴとＦＷＤとを組み合わせた単一素子である、ＲＣ（Reverse Conducting）－ＩＧＢＴを含んでもよい。なお、本実施の形態では、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ，２２ａ，２２ｂ，２２ｃ，２２ｄのみを含む場合を例に挙げて説明している。この場合に限らず、必要に応じて、電子部品も設置してもよい。なお、電子部品は、例えば、抵抗、サーミスタ、コンデンサ、サージアブソーバ等である。
　セラミック回路基板１０ａ，１０ｂは、絶縁板１１ａ，１１ｂと絶縁板１１ａ，１１ｂの裏面に形成された金属板１２ａ，１２ｂとを有している。さらに、セラミック回路基板１０ａ，１０ｂは、絶縁板１１ａのおもて面に形成された回路パターン１３ａ，１４ａ，１５ａ，１６ａと絶縁板１１ｂのおもて面に形成された回路パターン１３ｂ，１４ｂ，１５ｂとをそれぞれ有している。絶縁板１１ａ，１１ｂは、熱伝導性に優れた、酸化アルミニウム、窒化アルミニウム、窒化珪素等の高熱伝導性のセラミックスにより構成されている。金属板１２ａ，１２ｂは、熱伝導性に優れたアルミニウム、鉄、銀、銅、または、少なくともこれらの一種を含む合金等の金属により構成されている。回路パターン１３ａ，１４ａ，１５ａ，１６ａ及び回路パターン１３ｂ，１４ｂ，１５ｂは、導電性に優れた銅あるいは銅合金等の金属により構成されている。また、回路パターン１４ａ，１３ｂ上に、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ及び半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄがそれぞれ配置されている。回路パターン１６ａは，ワイヤ（符号省略）を介して半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄの制御電極に電気的に接続されている。回路パターン１５ｂは，ワイヤ（符号省略）を介して半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄの制御電極に電気的にそれぞれ接続されている。また、回路パターン１３ａは、ワイヤ（符号省略）を介して半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄの出力電極に電気的にそれぞれ接続されている。回路パターン１４ｂは、ワイヤ（符号省略）を介して半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄの出力電極に電気的にそれぞれ接続されている。なお、回路パターン１３ａ，１４ａ，１５ａ，１６ａ及び回路パターン１３ｂ，１４ｂ，１５ｂの数及び形状は一例であり、別の枚数及び形状であってもよい。このような回路パターン１３ａ，１４ａ，１５ａ，１６ａ及び回路パターン１３ｂ，１４ｂ，１５ｂの厚さは、０．１ｍｍ以上、１ｍｍ以下である。また、回路パターン１３ａ，１４ａ，１５ａ，１６ａ及び回路パターン１３ｂ，１４ｂ，１５ｂの詳細については後述する。このような構成を有するセラミック回路基板１０ａ，１０ｂとして、例えば、ＤＣＢ（Direct Copper Bonding）基板、ＡＭＢ（Active Metal Brazed）基板を用いることができる。セラミック回路基板１０ａ，１０ｂは、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ及び半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄで発生した熱を回路パターン１４ａ及び回路パターン１３ｂ、絶縁板１１ａ，１１ｂ及び金属板１２ａ，１２ｂを介して、放熱板３０側に伝導させることができる。
　放熱板３０は、熱伝導性に優れた、例えば、アルミニウム、鉄、銀、銅、または、少なくともこれらの一種を含む合金により構成されている。また、耐食性を向上させるために、例えば、ニッケル等の材料をめっき処理等により放熱板３０の表面に形成してもよい。具体的には、ニッケルの他に、ニッケル－リン合金、ニッケル－ボロン合金等がある。なお、この放熱板３０の裏面側に冷却器（図示を省略）をはんだまたは銀ろう等を介して取りつけて放熱性を向上させることも可能である。この場合の冷却器は、例えば、熱伝導性に優れたアルミニウム、鉄、銀、銅、または、少なくともこれらの一種を含む合金等により構成されている。また、冷却器として、フィン、または、複数のフィンから構成されるヒートシンク並びに水冷による冷却装置等を適用することができる。また、放熱板３０は、このような冷却器と一体的に構成されてもよい。その場合は、熱伝導性に優れたアルミニウム、鉄、銀、銅、または、少なくともこれらの一種を含む合金により構成される。そして、耐食性を向上させるために、例えば、ニッケル等の材料をめっき処理等により冷却器と一体化された放熱板３０の表面に形成してもよい。具体的には、ニッケルの他に、ニッケル－リン合金、ニッケル－ボロン合金等がある。
　ケース４０は、四方を囲む箱状を成して、収納領域４４を構成する側壁部４１を有している。また、四方を取り囲む側壁部４１のうち、対向する側壁部４１の収納領域４４側に段差部４２ａ，４２ｂが形成されている。また、段差部４２ａ，４２ｂが形成された側壁部４１の開口側の端部に端子配置部４３ａ，４３ｂ，４３ｃ，４３ｄが形成されている。さらに、ケース４０は、段差部４２ａ上に配置された内部端子部４５ａと端子配置部４３ａ上に配置された外部端子部４６ａとを備えている。外部接続端子４６ａは、内部端子部４５ａと側壁部４１内で電気的に接続されている。ケース４０は、段差部４２ａ上に配置された内部端子部４５ｂと端子配置部４３ｂ上に配置された外部端子部４６ｂとを備えている。外部接続端子４６ｂは、内部端子部４５ｂと側壁部４１内で電気的に接続されている。さらに、ケース４０は、段差部４２ｂ上に配置された内部端子部４５ｃと端子配置部４３ｃ，４３ｄ上に配置された外部端子部４６ｃ，４６ｄとを備えている。外部接続端子４６ｃ，４６ｄは、内部端子部４５ｃと側壁部４１内で電気的に接続されている。また、内部端子部４５ａと回路パターン１４ａとはワイヤ５２ａにより電気的に接続されている。内部端子部４５ｂと回路パターン１５ａとはワイヤ５２ｃにより電気的に接続されている。内部端子部４５ｃと回路パターン１３ｂとはワイヤ５２ｂにより電気的に接続されている。したがって、外部端子部４６ａには正極が、外部端子部４６ｂには負極がそれぞれ接続されて、外部端子部４６ｃ，４６ｄから出力が得られる。なお、ケース４０の側壁部４１には、図示はしていないものの、制御信号が入力される制御端子を備える。当該制御端子から回路パターン１６ａ，１５ｂにそれぞれ電気的に接続されている。このようなケース４０は、例えば、熱可塑性樹脂を用いた射出成形により構成されている。このような樹脂として、ポリフェニレンサルファイド（ＰＰＳ）、ポリブチレンテレフタレート（ＰＢＴ）樹脂、ポリブチレンサクシネート（ＰＢＳ）樹脂、ポリアミド（ＰＡ）樹脂、または、アクリロニトリルブタジエンスチレン（ＡＢＳ）樹脂等がある。
　なお、図示はしていないものの、上記ケース４０の収納領域４４に封止部材を充填して、収納領域４４内の半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ及び半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄとワイヤ５２ａ，５２ｂ，５２ｃとセラミック回路基板１０ａ，１０ｂといった構成が封止されている。封止部材は、例えば、マレイミド変性エポキシ樹脂、マレイミド変性フェノール樹脂、マレイミド樹脂等の熱硬化性樹脂で構成されている。また、封止部材は、シリコーンゲルにより構成されてもよい。また、上記半導体装置６０内で用いられているワイヤ５１ａ，５１ｂ，５２ａ，５２ｂ，５２ｃ（及び符号を省略しているワイヤ）は、導電性に優れたアルミニウム、銅または、少なくともこれらの一種を含む合金等により構成されている。また、これらの径は、１００μｍ以上、１ｍｍ以下であることが好ましい。
　次に、セラミック回路基板１０ａに含まれる回路パターン１３ａ，１４ａ，１５ａ，１６ａ及びセラミック回路基板１０ｂに含まれる回路パターン１３ｂ，１４ｂ，１５ｂについて、図３を用いて説明する。図３は、実施の形態のセラミック回路基板の一例の平面図である。なお、図３に示すセラミック回路基板１０ａ，１０ｂは、図１及び図２に示した半導体装置６０に含まれており、これらの平面図を示している。
　セラミック回路基板１０ａには、既述の通り、回路パターン１３ａ，１４ａ，１５ａ，１６ａが絶縁板１１ａ上に配置されている。特に、回路パターン１３ａは、導通領域１３ａ１と導通領域１３ａ１に（破線で示された）連通部１３ａ２を介して連通した配線領域１３ａ３とを有する。導通領域１３ａ１は、ワイヤ（符号省略）を介して半導体素子２１ａ，２１ｂと電気的に接続され、半導体素子２１ａ，２１ｂと電流を導通させる領域である。配線領域１３ａ３は、回路パターン１３ｂへ電流を導通させるワイヤ５１ａが接続される領域である。回路パターン１３ａは、配線領域１３ａ３が導通領域１３ａ１よりも幅広く、配線領域１３ａ３は、導通領域１３ａ１に対して直角に延伸している。また、回路パターン１５ａは、導通領域１５ａ１と導通領域１５ａ１に（破線で示された）連通部１５ａ２を介して連通した配線領域１５ａ３とを有する。回路パターン１５ａは、配線領域１５ａ３が導通領域１５ａ１よりも幅広く、配線領域１５ａ３は導通領域１５ａ１に対して直角に延伸している。なお、回路パターン１４ａは、半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄが配置される素子配置領域１４ａ１，１４ａ２が含まれている。
　セラミック回路基板１０ｂには、既述の通り、回路パターン１３ｂ，１４ｂ，１５ｂが絶縁板１１ｂ上に配置されている。特に、回路パターン１３ｂは、導通領域１３ｂ１と導通領域１３ｂ１に（破線で示された）連通部１３ｂ２を介して連通した、配線領域１３ａ３と所定の間隔離れて向かい合う配線領域１３ｂ３とを有する。導通領域１３ｂ１は、半導体素子２２ａ，２２ｂが配置され、半導体素子２２ａ，２２ｂと電流を導通させる領域である。配線領域１３ｂ３は、他の回路パターン１３ａと電流を導通させるワイヤ５１ａが接続される領域である。回路パターン１３ｂは、配線領域１３ｂ３が導通領域１３ｂ１よりも幅広く、配線領域１３ｂ３は、導通領域１３ｂ１に対して直角に延伸している。すなわち、導通領域１３ａ１，１３ｂ１は、配線領域１３ａ３，１３ｂ３を挟んで反対側にそれぞれ延伸している。
　また、連通部１３ｂ２は、その側部の、少なくとも、ワイヤ５１ａの配線方向Ｗ１から見て連通部１３ａ２と導通領域１３ｂ１とが重なる部分に切り欠き部１３ｂ４が形成されている。さらには、切り欠き部１３ｂ４は、配線領域１３ａ３の延伸する方向の反対側の側部から、ワイヤ５１ａの配線方向Ｗ１から見て連通部１３ａ２の幅以上となるように形成されている。ここでワイヤ５１ａの配線方向Ｗ１とは、セラミック回路基板１０ａにおけるワイヤ５１ａの接続点と、セラミック回路基板１０ｂにおけるワイヤ５１ａの接続点との２つの接続点からなる方向を指す。複数のワイヤ５１ａにおいて配線方向Ｗ１が異なる場合は、それらの平均的な方向を指す。同様に、セラミック回路基板１０ａ，１０ｂとケース４０とをワイヤ５２ａ，５２ｂで接続する場合も、２つの接続点からなる方向を指す。また、リードフレームやリボン等の配線部材においても、各２つの接続点の平均的な方向を指す。例えば、図３の場合には、連通部１３ａ２，１３ｂ２の幅が等しくなるように、切り欠き部１３ｂ４が形成されている。なお、導通領域１３ｂ１には、半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄが配置される素子配置領域１３ｂ５，１３ｂ６を含んでいる。また、回路パターン１４ｂは、導通領域１４ｂ１と導通領域１４ｂ１に（破線で示された）連通部１４ｂ２を介して連通した、配線領域１５ａ３と所定の間隔離れて向かい合う配線領域１４ｂ３とを有する。回路パターン１４ｂは、配線領域１４ｂ３が導通領域１４ｂ１よりも幅広く、配線領域１４ｂ３は、導通領域１４ｂ１に対して直角に延伸している。すなわち、導通領域１５ａ１，１４ｂ１は、配線領域１５ａ３，１４ｂ３を挟んで反対側にそれぞれ延伸している。
　なお、このようなセラミック回路基板１０ａの回路パターン１３ａ，１５ａの導通領域１３ａ１，１５ａ１には、必要に応じて外部接続端子を電気的に接続してもよい。同様に、セラミック回路基板１０ｂの回路パターン１３ｂ，１４ｂの導通領域１３ｂ１，１４ｂ１にも、必要に応じて外部接続端子を電気的に接続してもよい。
　また、図１で示したように、セラミック回路基板１０ａ，１０ｂ間において、回路パターン１３ａの配線領域１３ａ３と回路パターン１３ｂの配線領域１３ｂ３とがワイヤ５１ａ（図３では図示を省略）で接続される。また、回路パターン１５ａの配線領域１５ａ３と回路パターン１４ｂの配線領域１４ｂ３とがワイヤ５１ｂ（図３では図示を省略）で接続される。この際、回路パターン１３ａの連通部１３ａ２と回路パターン１３ｂの連通部１３ｂ２とがワイヤ５１ａの配線方向Ｗ１から見て（距離Ｄ１）離間している。また、回路パターン１５ａの連通部１５ａ２と回路パターン１４ｂの連通部１４ｂ２とがワイヤ５１ｂの配線方向Ｗ２から見て（距離Ｄ２）離間している。ここでは、配線領域１３ａ３，１５ａ３，１３ｂ３，１４ｂ３は、セラミック配線基板１０ａ，１０ｂの回路パターン間１３ａ，１３ｂ，１４ｂ，１５ａを導通させるワイヤ５１ａ，５１ｂが接続される領域である場合の例を示した。配線領域は、これだけではなく、例えば、セラミック配線基板１０ａ，１０ｂの回路パターン１４ａ，１５ａ，１３ｂとケース４０の内部端子部４５ａとを配線するワイヤ５２ａ，５２ｂ，５２ｃが接続される領域でもよい。また、ワイヤ５１ａ，５１ｂ，５２ａ，５２ｂ，５２ｃは、配線部材であればよく、例えば、リードフレームやリボンであっても構わない。
　このようにワイヤ５１ａ，５１ｂで電気的に接続されたセラミック回路基板１０ａ，１０ｂに導通させた際の表面温度分布の計測を行う。なお、この際の計測対象となるサンプルを複数用意する。まず、以下では、比較対象とする参考例のサンプルについて図４を用いて説明する。図４は、参考例のセラミック回路基板のサンプルの平面図である。なお、図４に示す参考例のサンプル７０は、半導体装置６０と同じ構成には同じ符号を付している。この参考例では、セラミック回路基板１１０ｂの回路パターン１１３ｂは、導通領域１３ｂ１と導通領域１３ｂ１に（破線で示された）連通部１１３ｂ２を介して連通した配線領域１３ｂ３とを有する。すなわち、連通部１１３ｂ２には、連通部１３ｂ２と異なり、切り欠き部１３ｂ４が形成されていない。
　また、回路パターン１３ａの配線領域１３ａ３と回路パターン１１３ｂの配線領域１３ｂ３とがワイヤ５１ａで電気的に接続されている。回路パターン１５ａの配線領域１５ａ３と回路パターン１４ｂの配線領域１４ｂ３とがワイヤ５１ｂで電気的に接続されている。さらに、回路パターン１４ａの素子配置領域１４ａ１，１４ａ２と回路パターン１３ａの導通領域１３ａ１とがワイヤ（符号省略）により電気的に接続されている。また、回路パターン１１３ｂの素子配置領域１３ｂ５，１３ｂ６と回路パターン１４ｂの導通領域１４ｂ１とがワイヤ（符号省略）により電気的に接続されている。
　このような構成を有するサンプル７０において、セラミック回路基板１０ａの回路パターン１４ａ，１５ａ（のワイヤ５２ａ，５２ｃが接続される領域（図１））から１０００Ａの電流を入力する。そして、セラミック回路基板１１０ｂの回路パターン１１３ｂ（図１の回路パターン１３ｂのワイヤ５２ｂが接続される領域に対応する箇所）から電流を出力させる。このようにして電流を循環させた際の回路パターン１３ａ，１１３ｂ及びワイヤ５１ａにおける表面温度分布を解析した。また、このサンプル７０では、回路パターン１４ａに入力された電流は回路パターン１３ａ中では導通経路Ｉａ１に沿って導通してワイヤ５１ａに流入する。そして、ワイヤ５１ａからの電流は回路パターン１１３ｂ中を導通経路Ｉｂ１に沿って導通する。また、回路パターン１４ｂに入力された電流は回路パターン１４ｂ中では導通経路Ｉｂ２に沿って導通してワイヤ５１ｂに流入する。そして、ワイヤ５１ｂからの電流は回路パターン１５ａ中を導通経路Ｉｂ２に沿って導通する。
　次に、このようなサンプル７０に対して導通させた際の回路パターン１３ａ，１１３ｂ及びワイヤ５１ａにおける上昇温度の分布について図５を用いて説明する。なお、上昇温度とは、サンプル７０に対して電流を導通させた際の温度から、電流を導通させない時の温度を差し引いた温度である。図５は、参考例のセラミック回路基板のサンプルの要部の表面の上昇温度分布を示す図である。なお、図５では、計測対象の回路パターン１３ａ，１１３ｂ及びワイヤ５１ａの上昇温度の解析結果を表示している。また、図５中に記載の等値線は上昇温度の分布を表している。また、ワイヤ５１ａについては、上昇温度の分布を表現するための便宜上、矩形状で表している。
　図５の表面温度分布によれば、ワイヤ５１ａの連通部１３ａ２に近い側（図５中下側）の等値線の領域Ｔａ１で最も高い上昇温度（１１０℃）が解析された。また、この領域Ｔａ１から遠ざかるに連れて上昇温度が低下していた。これは、図４で説明したように、電流は回路パターン１３ａ中を導通経路Ｉａ１に沿って導通する。すなわち、電流は導通領域１３ａ１から連通部１３ａ２を介して配線領域１３ａ３に流入する際に導通方向が９０度転回して、配線領域１３ａ３を（図５中上方に）導通する。このため、回路パターン１３ａにおいては、転回部分の内側の温度が高くなることが考えられる。そして、配線領域１３ａ３を導通する電流はワイヤ５１ａに流出する。そして、ワイヤ５１ａから流入された電流は回路パターン１１３ｂ中を導通経路Ｉｂ１に沿って導通する。導通領域１３ａ１からワイヤ５１ａを介して導通領域１３ｂ１までの導通経路は、図５中下側の方が上側より短い。そのため、ワイヤ５１ａは図５中下側の方が上側より電流の流量が多い。また、回路パターン１１３ｂの導通領域１３ｂ１も図５中下側の方が電流の流量が多く、温度が高いことが考えられる。
　このように、電流が導通する回路パターン１３ａ，１１３ｂが非対称であるためにそこを導通する電流の導通経路Ｉａ１，Ｉｂ１も非対称となる。このため、ワイヤ５１ａにおいて発熱箇所が偏ってしまう。なお、回路パターン１５ａ，１４ｂ及びワイヤ５１ｂに関する表面温度分布等については後述する。また、このようなサンプル７０に対して、実際に、所定の電流を導通させてサーモビューアで観察した。その結果、ワイヤ５１ａは、最も高い所の温度が２７０℃程度になり、異常過熱が発生していることがわかった。つまり、ワイヤ５１ａは、図５中下側の方が上側より電流の流量が多い。また、ワイヤ５１ａは、配線領域１３ａ３，１３ｂ３との接合箇所以外、セラミック回路基板１０ａ，１０ｂから離れているため、冷却されにくい。そのため、ワイヤ５１ａの連通部１３ａ２に近い側の領域Ｔａ１において、異常過熱が発生したことが考えられる。以上のように、発明者らは、ワイヤ５１ａである配線部材の異常過熱が、回路パターン１３ａ，１１３ｂの形状に起因する電流経路長のばらつきにより促進されることを見い出した。特に、短い電流経路の部分へ電流が集中し、配線部材の抵抗による損失により、異常過熱が生じる。
　次に、半導体装置６０のセラミック回路基板１０ａ，１０ｂに関するサンプルについて、図６を用いて説明する。図６は、実施の形態のセラミック回路基板のサンプルの平面図である。なお、図６に示す半導体装置６０のセラミック回路基板１０ａ，１０ｂのサンプル８０は、サンプル７０の回路パターン１１３ｂに代わり、回路パターン１３ｂが設けられている。セラミック回路基板１０ｂの回路パターン１３ｂは、導通領域１３ｂ１と導通領域１３ｂ１に切り欠き部１３ｂ４が形成されて構成された連通部１３ｂ２を介して連通した配線領域１３ｂ３とを有する。その他の構成、表面温度分布の解析はサンプル７０の場合と同様である。このようなサンプル８０でも、回路パターン１４ａに入力された電流は回路パターン１３ａ中では導通経路Ｉａ１に沿って導通してワイヤ５１ａに流入する。そして、ワイヤ５１ａからの電流は、回路パターン１３ｂには切り欠き部１３ｂ４が形成されているために、回路パターン１３ｂ中を配線領域１３ｂ３、連通部１３ｂ２、導通領域１３ｂ１の順に導通経路Ｉｂ３に沿って導通する。また、回路パターン１４ｂに入力された電流は回路パターン１４ｂ中では導通経路Ｉｂ２に沿って導通してワイヤ５１ｂに流入する。そして、ワイヤ５１ｂからの電流は回路パターン１５ａ中を導通経路Ｉａ２に沿って導通する。
　次に、このようなサンプル８０に対して導通させた際の回路パターン１３ａ，１３ｂ及びワイヤ５１ａにおける上昇温度の分布について図７を用いて説明する。なお、上昇温度とは、サンプル７０に対して電流を導通させた際の温度から、電流を導通させない時の温度を差し引いた温度である。図７は、実施の形態のセラミック回路基板のサンプルの要部の表面の上昇温度分布を示す図である。なお、図７では、計測対象の回路パターン１３ａ，１３ｂ及びワイヤ５１ａの上昇温度の解析結果を表示している。また、図７中に記載の等値線は上昇温度の分布を表している。また、この場合もワイヤ５１ａについては、上昇温度の分布を表現するための便宜上、矩形状で表している。
　図７によれば、ワイヤ５１ａの連通部１３ａ２に近い側（図７中下側）の等値線の領域Ｔａ１と、ワイヤ５１ａの連通部１３ｂ２に近い側（図７中上側）の領域Ｔｂ１とが同じ温度であり最も高い上昇温度（８０℃）であった。ワイヤ５１ａでは、領域Ｔａ１，Ｔｂ１から遠ざかるに連れて温度が低下していた。そして、表面の上昇温度のばらつきは、切り欠き部１３ｂ４が形成されていない場合（サンプル７０）に比べて、小さかった。
　サンプル８０の回路パターン１３ｂでは、切り欠き部１３ｂ４が形成されて連通部１３ｂ２が構成されるために、連通部１３ａ２と連通部１３ｂ２とがワイヤ５１ａの配線方向から見て離間している。すなわち、回路パターン１３ａ中における導通経路Ｉａ１と、回路パターン１３ｂ中における導通経路Ｉｂ３とが（ワイヤ５１ａの中心に対して）点対称となる。このため、導通領域１３ａ１からワイヤ５１ａを介して導通領域１３ｂ１までの導通経路の長さのばらつきは、切り欠き部１３ｂ４が形成されていない場合（サンプル７０）に比べて、小さくなる。そのため、ワイヤ５１ａにおいて電流は均等に流れやすい。したがって、ワイヤ５１ａの温度の偏りが抑制したと考えられる。また、このようなサンプル８０に対して、実際に、所定の電流を導通させてサーモビューアで観察した。その結果、最も高い所の温度が２５０℃を下回り、異常過熱が発生していないことがわかった。つまり、発明者らは、連通部１３ａ２と連通部１３ｂ２とがワイヤ５１ａの配線方向から見て離間していることで、回路パターン１３ａ，１３ｂの形状に起因する電流経路長のばらつきを抑制し、ワイヤ５１ａである配線部材における電流が均等になり、その結果、異常過熱の発生を防げることを見い出した。
　また、回路パターン１５ａ，１４ｂは、上記のような表面の上昇温度の解析を行っていないものの、ワイヤ５１ｂの領域の中心に対して点対称の形状であり、連通部１５ａ２と連通部１４ｂ２とがワイヤ５１ｂの配線方向から見て離間している。このため、回路パターン１３ａ，１３ｂと同様に、導通経路Ｉａ２，Ｉｂ２が対称となる。すなわち、この場合でも、導通領域１４ｂ１からワイヤ５１ｂを介して導通領域１５ａ１までの導通経路の長さのばらつきが小さくなることが考えられる。これにより、ワイヤ５１ｂの温度の偏りも抑制されていると考えられる。したがって、半導体装置６０のケース４０内の封止に、耐熱温度が２５０℃程度のシリコーンゲルが用いられた場合、セラミック回路基板１０ａ，１０ｂを電気的に接続するワイヤ５１ａ，５１ｂの温度が２５０℃よりも低く抑制される。このため、シリコーンゲルの劣化等が防止されて、半導体装置６０の信頼性の低下を抑制することができる。
　次に、サンプル８０の回路パターン１５ａの導通領域１５ａ１にグランドワイヤ５３を形成したサンプルについて図８を用いて説明する。図８は、実施の形態のセラミック回路基板の別のサンプルの平面図である。なお、図８に示すサンプル８５は、サンプル８０の回路パターン１５ａの導通領域１５ａ１の表面の少なくとも２点間をグランドワイヤ５３で電気的に接続するように複数形成されているものである。その他の構成、表面温度分布の解析はサンプル８０の場合と同様である。なお、サンプル８５では、グランドワイヤ５３を回路パターン１５ａの導通領域１５ａ１に形成している場合を例に挙げて説明している。グランドワイヤ５３は、導電性に優れたアルミニウム、銅または、少なくともこれらの一種を含む合金等により構成されている。また、これらの径は、１００μｍ以上、１ｍｍ以下であることが好ましい。ワイヤーボンディング装置で形成することができる。このようなグランドワイヤ５３は、この場合に限らず、回路パターンの形状、大きさに応じて、回路パターン上に適宜形成してもよい。
　このようなサンプル８５は、サンプル８０と同様の回路パターンであるために、表面の上昇温度分布は、図７に示したサンプル８０の上昇温度分布と同様である。また、サンプル８０，８５の内部抵抗を、テスターにより計測した。なお、それぞれの内部抵抗は、ケース４０の内部端子部４５ａから内部端子部４５ｂまでの半導体素子２１ａ，２１ｂ，２１ｃ，２１ｄ及び半導体素子２２ａ，２２ｂ，２２ｃ，２２ｄを除く電気抵抗の合計である。この結果、サンプル８５の内部抵抗は、図６に示したサンプル８０の内部抵抗の８２％であった。これは、回路パターン１５ａの導通領域１５ａ１にグランドワイヤ５３が形成されることにより、導通領域１５ａ１及びグランドワイヤ５３の導通が可能となり、内部抵抗の低下が実現できたことが考えられる。このように内部抵抗を低減することができるために、サンプル８０の場合よりも、半導体装置６０内の導通による発熱を抑制することができるようになり、半導体装置６０の信頼性の低下をより抑制することができる。
　次に、図６で示したように導通に伴う発熱の偏りを抑制できる回路パターンの変形例について図９及び図１０を用いて説明する。図９及び図１０は、実施の形態のセラミック回路基板の回路パターンの変形例を示す図である。なお、図９は、切り欠き部を形成することで一対の回路パターンにおける電流の導通経路を対称化した場合（回路パターン１３ａ，１３ｂに対応）を示している。図１０は、形状に基づき、一対の回路パターンの電流の導通経路を対称化した場合（回路パターン１５ａ，１４ｂに対応）を示している。また、図９及び図１０でも、半導体装置６０と同じ構成には同じ符号を付している。図９（Ａ）は、図６において、回路パターン１３ｂ側が図中上方に位置ずれした場合である。図９（Ｂ）は、図９（Ａ）においてさらに導通領域１３ｂ１及び連通部１３ｂ２がワイヤ５１ａの配線方向に平行となるような傾斜がつけられている場合である。図９（Ｃ）は、回路パターン２３ａ，２３ｂがワイヤ５１ａにより電気的に接続されている。回路パターン２３ａは、導通領域２３ａ１と導通領域２３ａ１に連通部２３ａ２を介して中央部に連通した配線領域２３ａ３とを有する。回路パターン２３ｂは、導通領域２３ｂ１と導通領域２３ｂ１に切り欠き部２３ｂ４が中央部に形成されて構成された一対の連通部２３ｂ２を介して連通した配線領域２３ｂ３とを有する。また、図１０（Ａ）は、図６において、回路パターン１４ｂ側が図中上方に位置ずれした場合である。図１０（Ｂ）は、図６において、回路パターン１４ｂの導通領域１４ｂ１のみが図中上方に位置ずれした場合である。そして、図１０（Ｃ）は、図１０（Ｂ）において回路パターン１４ｂ側が図中上方に位置ずれした場合である。
　このように、図９（Ａ），（Ｂ）のいずれも、切り欠き部１３ｂ４が形成されることで、回路パターン１３ａの連通部１３ａ２と回路パターン１３ｂの連通部１３ｂ２とがワイヤ５１ａの配線方向から見て離間している。図９（Ｃ）でも、切り欠き部２３ｂ４が形成されることで、回路パターン２３ａの連通部２３ａ２と回路パターン２３ｂの連通部２３ｂ２とがワイヤ５１ａの配線方向から見て離間している。また、図１０のいずれも、回路パターン１５ａの連通部１５ａ２と回路パターン１４ｂの連通部１４ｂ２とがワイヤ５１ｂの配線方向から見て離間している。このため、回路パターン１３ａ，１５ａと回路パターン１３ｂ，１４ｂとにおける電流の導通経路がワイヤ５１ａ，５１ｂの中心に対して点対称となる。また、回路パターン２３ａと回路パターン２３ｂとにおける電流の導通経路がワイヤ５１ａの配線方向に対して線対称となる。これにより、回路パターン１３ａ，２３ａ，１５ａと回路パターン１３ｂ，２３ｂ，１４ｂとの発熱の偏りが防止されると共に内部抵抗が低減する。したがって、ワイヤ５１ａ，５１ｂの温度上昇が抑制される。
　次に、参考例としてのセラミック回路基板の回路パターンの変形例について図１１及び図１２を用いて説明する。図１１及び図１２は、参考例のセラミック回路基板の回路パターンの変形例を示す図である。なお、図１１は、切り欠き部を形成することで一対の回路パターンにおける電流の導通経路を対称化した場合を示している。図１２は、形状に基づき、一対の回路パターンの電流の導通経路を対称化した場合を示している。また、図１１及び図１２ではセラミック回路基板の回路パターンのみを表している。
　図１１では、回路パターン８０ａ，８０ｂがワイヤ５１ａにより電気的に接続されている。回路パターン８０ａは、導通領域８０ａ１と導通領域８０ａ１に連通部８０ａ２を介して連通した配線領域８０ａ３とを有する。回路パターン８０ｂは、導通領域８０ｂ１と導通領域８０ｂ１に切り欠き部８０ｂ４が形成されて構成された連通部８０ｂ２を介して連通した配線領域８０ｂ３とを有する。回路パターン８０ｂでは、切り欠き部８０ｂ４の切り込みが浅く、回路パターン８０ａの連通部８０ａ２と回路パターン８０ｂの連通部８０ｂ２とがワイヤ５１ａの配線方向から見て離間しておらず重なっている。回路パターン８０ａから回路パターン８０ｂに電流を導通させると、連通部８０ａ２と連通部８０ｂ２とがワイヤ５１ａの配線方向から見て重複部分があるために、回路パターン８０ａ，８０ｂの導通経路が対称とならない。このため、回路パターン８０ａ，８０ｂの発熱箇所に偏りが生じ、内部抵抗も低減せずに、ワイヤ５１ａの温度が上昇してしまうおそれがある。
　また、図１２（Ａ）では、回路パターン８１ａ，８１ｂがワイヤ５１ｂにより電気的に接続されている。回路パターン８１ａは、導通領域８１ａ１と導通領域８１ａ１に連通部８１ａ２を介して連通した配線領域８１ａ３とを有する。回路パターン８１ｂは、導通領域８１ｂ１と導通領域８１ｂ１に連通部８１ｂ２を介して連通した配線領域８１ｂ３とを有する。この場合も、回路パターン８１ａの連通部８１ａ２と回路パターン８１ｂの連通部８１ｂ２とがワイヤ５１ｂの配線方向から見て離間しておらず重なっている。回路パターン８１ａから回路パターン８１ｂに電流を導通させると、連通部８１ａ２と連通部８１ｂ２とがワイヤ５１ｂの配線方向から見て重複部分があるために、回路パターン８１ａ，８１ｂの導通経路が対称とならない。このため、回路パターン８１ａ，８１ｂの発熱箇所に偏りが生じ、内部抵抗も低減せずに、ワイヤ５１ｂの温度が上昇してしまうおそれがある。
　また、図１２（Ｂ）では、回路パターン８２ａ，８２ｂがワイヤ５１ｂにより電気的に接続されている。回路パターン８２ａは、導通領域８２ａ１と導通領域８２ａ１に連通部８２ａ２を介して連通した配線領域８２ａ３とを有する。回路パターン８２ｂは、導通領域８２ｂ１と導通領域８２ｂ１に連通部８２ｂ２を介して連通した配線領域８２ｂ３とを有する。この場合も、回路パターン８２ａの連通部８２ａ２と回路パターン８２ｂの連通部８２ｂ２とがワイヤ５１ｂの配線方向から見て対向配置している。例えば、回路パターン８２ａから回路パターン８２ｂに電流を導通させると、電流は導通領域８２ａ１から配線領域８２ａ３に導通して、ワイヤ５１ｂから配線領域８２ｂ３に流入する。この際、連通部８２ｂ２の図中上方の温度が上昇してしまうおそれがある。このように、回路パターン８２ａ，８２ｂの発熱箇所に偏りが生じ、内部抵抗も低減せずに、ワイヤ５１ｂの温度が上昇してしまうおそれがある。
　図１２（Ｃ）でも、回路パターン８３ａ，８３ｂがワイヤ５１ｂにより電気的に接続されている。回路パターン８３ａは、導通領域８３ａ１と導通領域８３ａ１に連通部８３ａ２を介して連通した配線領域８３ａ３とを有する。回路パターン８３ｂは、導通領域８３ｂ１と導通領域８３ｂ１に連通部８３ｂ２を介して連通した配線領域８３ｂ３とを有する。この場合も、回路パターン８３ａの連通部８３ａ２と回路パターン８３ｂの連通部８３ｂ２とがワイヤ５１ｂの配線方向から見て対向配置している。例えば、回路パターン８３ａから回路パターン８３ｂに電流を導通させると、電流は導通領域８３ａ１から配線領域８３ａ３に（分岐するように）導通して、ワイヤ５１ｂから配線領域８３ｂ３に流入する。この際、連通部８３ｂ２の両端（図中上下方）の温度が上昇してしまうおそれがある。このように、回路パターン８３ａ，８３ｂの発熱箇所に偏りが生じ、内部抵抗も低減せずに、ワイヤ５１ｂの温度が上昇してしまうおそれがある。
　上記半導体装置６０は、導通領域１３ａ１，１５ａ１と導通領域１３ａ１，１５ａ１に連通部１３ａ２，１５ａ２を介して連通した配線領域１３ａ３，１５ａ３とを有する回路パターン１３ａ，１５ａを有する。また、導通領域１３ｂ１，１４ｂ１と導通領域１３ｂ１，１４ｂ１に連通部１３ｂ２，１４ｂ２を介して連通し、配線領域１３ａ３，１５ａ３と所定の間隔離れて向かい合う配線領域１３ｂ３，１４ｂ３とを有する回路パターン１３ｂ，１４ｂを有する。そして、配線領域１３ａ３，１５ａ３と配線領域１３ｂ３，１４ｂ３とを電気的に接続するワイヤ５１ａ，５１ｂを備えている。この際、連通部１３ａ２，１５ａ２と連通部１３ｂ２，１４ｂ２とがワイヤ５１ａ，５１ｂの配線方向から見て離間している。これにより、回路パターン１３ａ，１５ａ中における導通経路と、回路パターン１３ｂ，１４ｂ中における導通経路とが（ワイヤ５１ａ，５１ｂの中心に対して）点対称となる。このため、ワイヤ５１ａ，５１ｂの電流の偏りが低減されるため、ワイヤ５１ａ，５１ｂの温度の上昇が抑制される。したがって、半導体装置６０は、発熱に起因する損傷等の発生を防止して、信頼性の低下を抑制することができる。なお、本実施の形態では、半導体装置６０内の回路パターン１３ａ，１３ｂ及び回路パターン１５ａ，１４ｂに対する導通経路を制御して、ワイヤ５１ａ，５１ｂの温度の上昇を抑制している。この回路パターン１３ａ，１３ｂ及び回路パターン１５ａ，１４ｂに限らない。例えば、一対のリードフレームのような導電部を配線部材で電気的に接続するような場合にも、当該一対の導通部に対して、本実施の形態の回路パターン１３ａ，１３ｂ及び回路パターン１５ａ，１４ｂのように導通経路を制御することが可能である。
　上記については単に本発明の原理を示すものである。さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成及び応用例に限定されるものではなく、対応するすべての変形例及び均等物は、添付の請求項及びその均等物による本発明の範囲とみなされる。
　１０ａ，１０ｂ　セラミック回路基板
　１１ａ，１１ｂ　絶縁板
　１２ａ，１２ｂ　金属板
　１３ａ，１４ａ，１５ａ，１６ａ，１３ｂ，１４ｂ，１５ｂ　回路パターン
　１３ａ１，１５ａ１，１３ｂ１，１４ｂ１　導通領域
　１３ａ２，１５ａ２，１３ｂ２，１４ｂ２　連通部
　１３ａ３，１５ａ３，１３ｂ３，１４ｂ３　配線領域
　１３ｂ４　切り欠き部
　１４ａ１，１４ａ２，１３ｂ５，１３ｂ６　素子配置領域
　２１ａ，２２ａ，２１ｂ，２２ｂ，２１ｃ，２２ｃ，２１ｄ，２２ｄ　半導体素子
　３０　放熱板
　４０　ケース
　４１　側壁部
　４２ａ，４２ｂ　段差部
　４３ａ，４３ｂ，４３ｃ，４３ｄ　端子配置部
　４４　収納領域
　４５ａ，４５ｂ，４５ｃ　内部端子部
　４６ａ，４６ｂ，４６ｃ，４６ｄ　外部端子部
　５１ａ，５２ａ，５１ｂ，５２ｂ，５２ｃ　ワイヤ
　５３　グランドワイヤ
　６０　半導体装置
　８０，８５　サンプル

Claims (10)

  1. 　第１導通領域と前記第１導通領域に第１連通部を介して連通した第１配線領域とを有する第１導電部と、
    　第２導通領域と前記第２導通領域に第２連通部を介して連通し、前記第１配線領域と所定の間隔離れて向かい合う第２配線領域とを有する第２導電部と、
    　前記第１配線領域と前記第２配線領域とを電気的に接続する配線部材とを備え、
    　前記第１連通部と前記第２連通部とが前記配線部材の配線方向から見て離間している、
    　半導体装置。
  2. 　前記第１導電部は、前記第１配線領域が前記第１導通領域より幅広く、
    　前記第２導電部は、前記第２配線領域が前記第２導通領域より幅広い、
    　請求項１に記載の半導体装置。
  3. 　前記第１導電部にて、前記第１配線領域は前記第１導通領域に対して直角に延伸し、
    　前記第２導電部にて、前記第２配線領域は前記第２導通領域に対して直角に延伸し、
    　前記第１導通領域と前記第２導通領域とは前記第１配線領域及び前記第２配線領域を挟んで反対側にそれぞれ延伸している、
    　請求項２に記載の半導体装置。
  4. 　前記第１導電部では、前記第１配線領域が前記第１導通領域より幅広く、
    　前記第２導電部では、前記第２連通部は、その側部の、少なくとも、前記配線部材の配線方向から見て前記第１連通部と前記第２導通領域とが重なる部分に切り欠き部が形成されている、
    　請求項１に記載の半導体装置。
  5. 　前記第１導電部では、前記第１配線領域は前記第１導通領域に対して直角に延伸し、
    　前記第２導電部では、前記切り欠き部が、前記第１配線領域の延伸する方向の反対側の側部から、前記配線部材の配線方向から見て前記第１連通部の幅以上となるように形成されている、
    　請求項４に記載の半導体装置。
  6. 　前記第１連通部と前記第２連通部との幅は等しい、
    　請求項１乃至５のいずれかに記載の半導体装置。
  7. 　前記配線部材は、複数のワイヤ、リードフレームまたはリボンである、
    　請求項１乃至６のいずれかに記載の半導体装置。
  8. 　前記第１導通領域及び前記第２導通領域の少なくとも一方に半導体素子が配置されている、
    　請求項１乃至７のいずれかに記載の半導体装置。
  9. 　前記第１導通領域及び前記第２導通領域の少なくとも一方に外部接続端子が電気的に接続されている、
    　請求項１乃至８のいずれかに記載の半導体装置。
  10. 　前記第１導通領域及び前記第２導通領域の少なくとも一方の表面上の少なくとも２点間を電気的に接続する別の配線部材が形成されている、
    　請求項１乃至９のいずれかに記載の半導体装置。
PCT/JP2019/017626 2018-06-06 2019-04-25 半導体装置 WO2019235097A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2020523563A JP6888742B2 (ja) 2018-06-06 2019-04-25 半導体装置
DE112019000169.8T DE112019000169T5 (de) 2018-06-06 2019-04-25 Halbleitereinrichtung
CN201980006085.5A CN111418049B (zh) 2018-06-06 2019-04-25 半导体装置
US16/883,464 US11177190B2 (en) 2018-06-06 2020-05-26 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018108437 2018-06-06
JP2018-108437 2018-06-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/883,464 Continuation US11177190B2 (en) 2018-06-06 2020-05-26 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2019235097A1 true WO2019235097A1 (ja) 2019-12-12

Family

ID=68769999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/017626 WO2019235097A1 (ja) 2018-06-06 2019-04-25 半導体装置

Country Status (5)

Country Link
US (1) US11177190B2 (ja)
JP (1) JP6888742B2 (ja)
CN (1) CN111418049B (ja)
DE (1) DE112019000169T5 (ja)
WO (1) WO2019235097A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3958306A1 (de) * 2020-08-19 2022-02-23 Siemens Aktiengesellschaft Leistungsmodul mit mindestens zwei auf einem substrat kontaktierten leistungshalbleiteranordnungen
WO2023053823A1 (ja) * 2021-09-29 2023-04-06 ローム株式会社 半導体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113707643A (zh) * 2021-08-30 2021-11-26 中国振华集团永光电子有限公司（国营第八七三厂） 一种高集成高可靠igbt功率模块及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249394A (ja) * 2010-05-24 2011-12-08 Mitsubishi Electric Corp 半導体装置
JP2015167233A (ja) * 2015-04-13 2015-09-24 ルネサスエレクトロニクス株式会社 半導体装置
JP2017135392A (ja) * 2009-06-18 2017-08-03 ローム株式会社 半導体装置
JP2017139406A (ja) * 2016-02-05 2017-08-10 富士電機株式会社 半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3228839B2 (ja) 1994-09-07 2001-11-12 株式会社日立製作所 電力用半導体装置
EP0706221B8 (en) * 1994-10-07 2008-09-03 Hitachi, Ltd. Semiconductor device comprising a plurality of semiconductor elements
JP3222341B2 (ja) 1995-01-11 2001-10-29 株式会社日立製作所 半導体モジュール
JP2001094035A (ja) 1999-09-27 2001-04-06 Toshiba Corp 半導体装置
US20120153444A1 (en) 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
JP2013258321A (ja) * 2012-06-13 2013-12-26 Fuji Electric Co Ltd 半導体装置
DE112013003161T5 (de) * 2012-07-19 2015-03-12 Mitsubishi Electric Corporation Leistungs-Halbleitermodul
JP5429413B2 (ja) 2013-01-09 2014-02-26 三菱電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017135392A (ja) * 2009-06-18 2017-08-03 ローム株式会社 半導体装置
JP2011249394A (ja) * 2010-05-24 2011-12-08 Mitsubishi Electric Corp 半導体装置
JP2015167233A (ja) * 2015-04-13 2015-09-24 ルネサスエレクトロニクス株式会社 半導体装置
JP2017139406A (ja) * 2016-02-05 2017-08-10 富士電機株式会社 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3958306A1 (de) * 2020-08-19 2022-02-23 Siemens Aktiengesellschaft Leistungsmodul mit mindestens zwei auf einem substrat kontaktierten leistungshalbleiteranordnungen
US11888407B2 (en) 2020-08-19 2024-01-30 Siemens Aktiengesellschaft Power module having at least two power semiconductor arrangements that are contacted on a substrate
WO2023053823A1 (ja) * 2021-09-29 2023-04-06 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
US11177190B2 (en) 2021-11-16
US20200286807A1 (en) 2020-09-10
JPWO2019235097A1 (ja) 2020-12-17
JP6888742B2 (ja) 2021-06-16
DE112019000169T5 (de) 2020-08-20
CN111418049A (zh) 2020-07-14
CN111418049B (zh) 2023-12-08

Similar Documents

Publication Publication Date Title
CN106952897B (zh) 半导体装置及其制造方法
US9379083B2 (en) Semiconductor device and method for manufacturing semiconductor device
US9159715B2 (en) Miniaturized semiconductor device
WO2019235097A1 (ja) 半導体装置
WO2016084622A1 (ja) 半導体装置
KR102156867B1 (ko) 반도체 장치
US11456244B2 (en) Semiconductor device
JPWO2018179981A1 (ja) 半導体装置
US7479693B2 (en) Arrangement of conductive connectors in a power semiconductor device
WO2018151010A1 (ja) 半導体装置
CN116072624A (zh) 半导体装置
WO2022059251A1 (ja) 半導体装置
JP6668617B2 (ja) サーミスタ搭載装置およびサーミスタ部品
JP2019029410A (ja) 半導体モジュール
CN110911375A (zh) 半导体装置
JP7118205B1 (ja) 半導体装置及びそれを用いた半導体モジュール
JP7413720B2 (ja) 半導体モジュール
JP7278439B1 (ja) 半導体装置及びそれを用いた電力変換装置
KR20150045652A (ko) 파워 모듈
WO2022224935A1 (ja) 半導体装置
US20240120249A1 (en) Semiconductor module
US20230345637A1 (en) Semiconductor device
WO2023017707A1 (ja) 半導体装置
JP7106014B2 (ja) パワーモジュール
JP7159609B2 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19815176

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020523563

Country of ref document: JP

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 19815176

Country of ref document: EP

Kind code of ref document: A1