WO2019205489A1 - 内嵌式触控阵列基板、显示面板及制造方法 - Google Patents

内嵌式触控阵列基板、显示面板及制造方法 Download PDF

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WO2019205489A1
WO2019205489A1 PCT/CN2018/108082 CN2018108082W WO2019205489A1 WO 2019205489 A1 WO2019205489 A1 WO 2019205489A1 CN 2018108082 W CN2018108082 W CN 2018108082W WO 2019205489 A1 WO2019205489 A1 WO 2019205489A1
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layer
trace
patterned
transparent electrode
forming
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French (fr)
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王威
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an in-cell touch array substrate, a display panel, and a manufacturing method.
  • the touch display panel can be divided according to the structure: the touch circuit is covered on the liquid crystal cell (On Cell), the touch circuit is embedded in the liquid crystal cell (In Cell), and the external type.
  • the embedded touch display panel has the advantages of low cost and thin thickness, and is favored by various panel manufacturers, and has evolved into the main development direction of the future touch technology.
  • FIG. 1 it is a cross-sectional development view of a conventional in-cell touch array substrate.
  • In-Cell Touch high-resolution in-cell touch
  • LTPS low-temperature polysilicon
  • the in-cell touch adopts the bottom transparent electrode (BITO) 22 as the touch signal electrode, and is independent.
  • the metal wire is used as a touch signal line, and the touch signal line is usually made of a separate third metal layer (M3) 20.
  • M3 third metal layer
  • the existing in-cell touch array substrate mainly comprises: a substrate 10, a low temperature polysilicon thin film transistor array disposed on the substrate 10, a flat layer 18 disposed on the low temperature polysilicon TFT array, and a first insulation disposed on the planar layer 18.
  • the layer 19 can be used as the third metal layer 20 of the touch signal line, the second insulating layer 21, the bottom transparent electrode 22 as the touch signal electrode, the passivation layer 23, and the top transparent electrode 24 as a pixel electrode;
  • the low temperature polysilicon thin film transistor array mainly includes a light shielding layer 11, a buffer layer 12, a polysilicon layer 13, a gate insulating layer 14, a gate layer 15, an interlayer dielectric layer 16, and a source and drain layer 17.
  • the TFT structure and manufacturing process of the in-cell touch low-temperature polysilicon LCD display panel mainly include:
  • a light shielding layer (LS) 11 a light shielding layer film formation ⁇ photolithography (Photo) ⁇ etching ⁇ stripping, forming a light shielding layer pattern; forming a light shielding layer 11 on the substrate 10, the light shielding layer 11 is generally a metal layer Patterning the light shielding layer 11 by a photomask process to strip the photoresist;
  • P-Si 13 3L film formation ⁇ excimer laser annealing (ELA) ⁇ photolithography ⁇ dry etching ⁇ stripping; a buffer layer 12 such as SiNx/SiOx is formed on the light shielding layer 11, and then a polysilicon layer 13 is formed on the buffer layer 12, and then the polysilicon layer 13 is patterned to strip the photoresist;
  • ELA excimer laser annealing
  • NCD photolithography ⁇ NCD ion implantation (IMP) ⁇ stripping; doping the polysilicon layer 13 to form a channel;
  • NP photolithography ⁇ NP ion implantation ⁇ stripping; doping the polysilicon layer 13 with N-type ions to form source and drain regions on both sides of the NMOS channel;
  • gate insulating layer 14 & gate layer 15 Forming gate insulating layer 14 & gate layer 15 (GI&Gate): gate insulating layer 14 & gate layer 15 film formation ⁇ photolithography ⁇ etching ⁇ lightly doped drain region (LDD) ion implantation; forming gate insulation Layer 14 and gate layer 15, then patterning gate layer 15 and gate insulating layer 14, forming a gate of the TFT and a structure such as a scan line, forming a lightly doped drain region by ion implantation;
  • GDD lightly doped drain region
  • Pp photolithography ⁇ Pp ion implantation ⁇ stripping; P-type ion heavily doping of the polysilicon layer 13 to form source and drain regions on both sides of the PMOS channel;
  • interlayer dielectric layer (ILD) 16 interlayer dielectric layer film formation ⁇ rapid thermal annealing (RTA) ⁇ photolithography ⁇ dry etching ⁇ stripping; forming an interlayer dielectric layer 16 , patterned;
  • RTA rapid thermal annealing
  • SD source/drain layer 17: source/drain layer film formation ⁇ lithography ⁇ dry etching ⁇ peeling; forming a source/drain layer 17, patterning, forming a source/drain and a data line;
  • first insulating layer 19 & the third metal layer 20 (IL1 & M3): first insulating layer & third metal layer forming film ⁇ third metal layer photolithography ⁇ etching ⁇ stripping; forming the first insulating layer 19 and the third The metal layer 20 is patterned with the first insulating layer 19 and the third metal layer 20, and the third metal layer 20 serves as a touch signal line;
  • a second insulating layer (IL2) 21 forming a second insulating layer ⁇ photolithography ⁇ dry etching ⁇ stripping, forming a third metal layer and a bottom transparent electrode (BITO) via; forming a second insulating layer 21, Patterning to form a via between the third metal layer 20 and the bottom transparent electrode 22;
  • bottom transparent electrode 22 bottom transparent electrode film formation ⁇ photolithography ⁇ etching ⁇ stripping; forming a bottom transparent electrode 22, patterned, bottom transparent electrode 22 can be used as a touch signal electrode;
  • PV passivation layer
  • passivation layer film formation ⁇ photolithography ⁇ dry etching ⁇ stripping; forming a passivation layer 23, patterning; in the prior art, the passivation layer 23 is dry etched to form via holes It is necessary to etch through the passivation layer 23 / the second insulating layer 21 / the first insulating layer 19 three-layer film, which has the risk of high undercut;
  • top transparent electrode (TITO) 24 top transparent electrode film formation ⁇ photolithography ⁇ etching ⁇ peeling ⁇ annealing (Anneal); forming a top transparent electrode 24, patterned.
  • an object of the present invention is to provide an in-cell touch array substrate, a display panel, and a manufacturing method thereof, which simplifies the process and reduces the cost.
  • an in-cell touch array substrate including:
  • the low temperature polysilicon thin film transistor array disposed on the substrate, the low temperature polysilicon thin film transistor array comprising a patterned light shielding layer and a patterned source and drain layer;
  • a patterned bottom transparent electrode disposed on the flat layer
  • a patterned passivation layer disposed on the bottom transparent electrode
  • a patterned top transparent electrode disposed on the passivation layer
  • the source and drain layers include a first trace connected to the bottom transparent electrode, the light shielding layer includes a second trace as a touch signal line, and the second trace is connected to the first trace.
  • the low temperature polysilicon thin film transistor array comprises:
  • a patterned light shielding layer disposed on the substrate
  • a patterned buffer layer disposed on the substrate and the light shielding layer
  • a patterned polysilicon layer disposed on the buffer layer
  • a patterned gate insulating layer disposed on the polysilicon layer and the buffer layer;
  • a patterned gate layer disposed on the gate insulating layer
  • a patterned interlayer dielectric layer disposed on the gate layer
  • a patterned source and drain layer disposed on the interlayer dielectric layer.
  • the buffer layer is provided with a contact hole for connecting the second trace to the first trace.
  • the gate insulating layer is provided with a via hole for connecting the second trace to the first trace.
  • the interlayer dielectric layer is provided with a via hole for connecting the second trace to the first trace.
  • the flat layer is provided with a via hole for connecting the bottom transparent electrode to the first trace.
  • the flat layer and the passivation layer are respectively provided with via holes for connecting the top transparent electrode to the source drain layer.
  • the bottom transparent electrode and the top transparent electrode are indium tin oxide electrodes.
  • the present invention also provides a display panel comprising the in-cell touch array substrate according to any of the above.
  • the present invention also provides a method for manufacturing an in-cell touch array substrate, comprising:
  • a top transparent electrode is formed and patterned.
  • the in-cell touch array substrate, the display panel and the manufacturing method of the present invention reduce a mask, reduce film formation by 3 times, simplify the process, and reduce the cost; reduce film formation by 3 times, simplify the structure of the film layer, and avoid the first An insulating layer, a second insulating layer, and a passivation layer are directly contacted with the conductive film, thereby reducing the probability of film breakage due to poor stress matching, and also reducing the passivation layer dry etching and etching passivation.
  • Layer/Second Insulation/First Insulation Three-layer film is at high risk of undercutting.
  • 1 is a cross-sectional view showing a conventional in-cell touch array substrate
  • FIG. 2 is a cross-sectional view showing a preferred embodiment of an in-cell touch panel substrate according to the present invention.
  • the in-cell touch array substrate of the preferred embodiment mainly includes: a substrate 10; a low temperature polysilicon thin film transistor array disposed on the substrate 10, the low temperature polysilicon thin film transistor array including a patterned light shielding layer 11 and a patterned source and drain a patterned planar layer 18 disposed on the low temperature polysilicon thin film transistor array; a patterned bottom transparent electrode 22 disposed on the planar layer 18, which can be used as a touch signal electrode; and disposed on the bottom transparent electrode 22 a patterned passivation layer 23; a patterned top transparent electrode 24 disposed on the passivation layer 23, which can be used as a pixel electrode;
  • the source and drain layer 17 of the low temperature polysilicon thin film transistor array has a first trace 171 for connecting to the bottom transparent electrode 22 in addition to the structure of the source and the drain of the TFT and the data line;
  • the layer 11 metal is formed to form a second trace 111 as a touch signal line in addition to the light shielding; and the second trace 111 is connected to the first trace 171 such that the second trace 111 and the bottom transparent electrode 22 Electrical conduction, one as a touch signal line and one as a touch signal electrode for implementing a touch function.
  • the structure of the low-temperature polysilicon thin film transistor array is not particularly limited, and is only illustrated by way of example in FIG. 2, and may generally include: a patterned light shielding layer 11 disposed on the substrate 10; and disposed on the substrate 10 and the light shielding layer 11. a patterned buffer layer 12; a patterned polysilicon layer 13 disposed on the buffer layer 12; a patterned gate insulating layer 14 disposed on the polysilicon layer 13 and the buffer layer 12; disposed on the gate insulating layer 14.
  • the patterned gate layer 15 , the gate layer 15 can form a TFT gate and a scan line; the patterned interlayer dielectric layer 16 disposed on the gate layer 15 is disposed on the interlayer dielectric layer 16
  • the patterned source and drain layers 17 and the source and drain layers 17 may have a structure such as a TFT source drain and a data line.
  • the bottom transparent electrode 22 is connected to the first trace 171, so that the second trace 111 and the bottom transparent electrode 22 are electrically connected, and the buffer layer 12 can be provided.
  • the gate insulating layer 14 may be provided with a via for the first trace 171 to connect the second trace 111;
  • the interlayer dielectric layer 16 A via may be provided for the first trace 171 to connect the second trace 111;
  • the flat layer 18 may be provided with a via for the bottom transparent electrode 22 to connect the first trace 171.
  • the top transparent electrode 24 serves as a pixel electrode, and the flat layer 18 and the passivation layer 23 are respectively provided with via holes for the TFT structure in which the top transparent electrode 24 is connected to the source and drain layers 17.
  • Both the bottom transparent electrode 22 and the top transparent electrode 24 may be indium tin oxide electrodes.
  • the invention can realize the touch signal line trace design by using the light-shielding layer metal directly under the data line, and only need to add a 3L buffer layer on the basis of slightly modifying the four-layer mask pattern compared with the non-embedded type.
  • a mask can be used. Compared with the existing in-line solution, it can reduce film formation by 3 times and reduce a mask, simplifying the process, reducing the cost, and improving the yield.
  • the present invention further provides a display panel including the in-cell touch array substrate.
  • the present invention also provides a method for manufacturing an in-cell touch array substrate, which can be used to fabricate the in-cell touch array substrate and display panel of the present invention.
  • the light shielding layer 11 is formed into a film ⁇ photolithography ⁇ etching ⁇ peeling to form a touch signal line and a light shielding layer pattern;
  • the light-shielding layer 11 is formed on the substrate 10, the light-shielding layer 11 is patterned by the reticle, and the photoresist is stripped, and the metal of the light-shielding layer 11 is used for shielding, and a second trace 111 as a touch signal line is formed;
  • NCD photolithography ⁇ NCD ion implantation ⁇ stripping
  • NP photolithography ⁇ NP ion implantation ⁇ stripping
  • gate insulating layer 14 & gate layer 15 film formation ⁇ photolithography ⁇ etching ⁇ lightly doped drain region ion implantation;
  • a gate insulating layer 14 and a gate layer 15 Forming a gate insulating layer 14 and a gate layer 15, patterning the gate layer 15 and the gate insulating layer 14, forming a TFT gate and a scan line, and forming a gate insulating layer 14 for connecting the second trace 111 to the first trace a via of line 171;
  • interlayer dielectric layer 16 film formation ⁇ rapid thermal annealing ⁇ photolithography ⁇ dry etching ⁇ stripping;
  • source and drain layer 17 film formation ⁇ photolithography ⁇ dry etching ⁇ stripping;
  • the planarization layer 18 is formed and patterned to form a via for the bottom transparent electrode 22 to connect the first trace 171; the planarization layer 18 also forms a via for the TFT structure of the top transparent electrode 24 to connect the source and drain layers 17. ;
  • bottom transparent electrode 22 film formation ⁇ photolithography ⁇ etching ⁇ peeling;
  • the bottom transparent electrode 22 is formed and patterned, and the bottom transparent electrode 22 can be indium tin oxide, which can be used as a touch signal electrode;
  • passivation layer 23 film formation ⁇ photolithography ⁇ dry etching ⁇ stripping;
  • the passivation layer 23 is formed with via holes for the TFT structure in which the top transparent electrode 24 is connected to the source and drain layers 17;
  • top transparent electrode 24 film formation ⁇ photolithography ⁇ etching ⁇ stripping ⁇ annealing;
  • the top transparent electrode 24 is formed and patterned, and the top transparent electrode 24 may be indium tin oxide, which can be used as a pixel electrode.
  • the invention adopts the light-shielding layer layout touch signal line trace design, does not need the IL1, M3, IL2 three-layer film formation, and does not need the M3, IL2 two masks, only needs to add a mask process after the polysilicon layer is completed.
  • the connection via between the control electrode and the light-shielding touch signal line can simplify the process and reduce the cost.
  • the present invention Compared with the existing manufacturing method of the in-cell touch array substrate, the present invention:
  • the in-cell touch array substrate, the display panel and the manufacturing method of the present invention reduce one photomask (14 mask ⁇ 13 mask), reduce film formation by 3 times, simplify the process, and reduce the cost; reduce film formation by 3 times.
  • the film structure is simplified, and the three layers of non-metal film of the first insulating layer, the second insulating layer and the passivation layer are directly contacted with the conductive film, thereby reducing the film due to poor stress matching.
  • the probability of breaking also reduces the risk of undercutting when the passivation layer is dry etched once to etch through the passivation layer/second insulation layer/first insulation layer three-layer film.

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Abstract

本发明涉及一种内嵌式触控阵列基板、显示面板及制造方法。该内嵌式触控阵列基板包括：基板(10)；设于基板(10)上的低温多晶硅薄膜晶体管阵列包括图案化的遮光层(11)和图案化的源漏极层(17)；设于所述低温多晶硅TFT阵列上的图案化的平坦层(18)；设于平坦层(18)上的图案化的底部透明电极(22)；设于底部透明电极(22)上的图案化的钝化层(23)；设于钝化层(23)上的图案化的顶部透明电极(24)；源漏极层(17)包括与上方底部透明电极(22)相连接的第一走线(171)，所述遮光层(11)包括作为触控信号线的第二走线(111)，所述第二走线(111)与上方的第一走线(171)相连接。本发明减少一道光罩，减少3次成膜，制程简化，成本降低。

Description

内嵌式触控阵列基板、显示面板及制造方法 技术领域
本发明涉及显示技术领域，尤其涉及一种内嵌式触控阵列基板、显示面板及制造方法。
背景技术
触控显示面板根据结构不同可划分为：触控电路覆盖于液晶盒上式(On Cell)，触控电路内嵌在液晶盒内式(In Cell)、以及外挂式。内嵌式触控显示面板具有成本较低、厚度较薄等优点，受到各大面板厂家青睐，已演化为未来触控技术的主要发展方向。
参见图1，其为一种现有内嵌式触控阵列基板的剖面展开示意图。目前高解析度内嵌式触控(In-Cell Touch)已成为低温多晶硅(LTPS)LCD显示面板主流，目前内嵌式触控多采用底部透明电极(BITO)22作为触控信号电极，使用独立金属(Metal)线作为触控(Touch)信号线，触控信号线多采用独立的第三金属层(M3)20制作而成。与非内嵌式(Non In-Cell)相比较，需要增加第一绝缘层19&第三金属层20、第二绝缘层21(IL1&M3、IL2)三次成膜、两道光罩(Mask)制程，制造成本、不良率也随之增加。
现有内嵌式触控阵列基板主要包括：基板10，设于基板10上的低温多晶硅薄膜晶体管阵列，设于低温多晶硅TFT阵列上的平坦层18，以及设于平坦层18上的第一绝缘层19，可作为触控信号线的第三金属层20，第二绝缘层21，可作为触控信号电极的底部透明电极22，钝化层23，以及可作为像素电极的顶部透明电极24；低温多晶硅薄膜晶体管阵列主要包括遮光层11，缓冲层12，多晶硅层13，栅极绝缘层14，栅极层15，层间介质层16，以及源漏极层17。
目前内嵌式触控低温多晶硅LCD显示面板的TFT结构以及制造工艺主要包括：
(1)形成遮光层(LS)11：遮光层成膜→光刻(Photo)→蚀刻→剥离(Strip)，形成遮光层图案；在基板10上形成遮光层11，遮光层11一般为金属层，利用光罩制程图案化遮光层11，剥离光阻；
(2)形成多晶硅层(P-Si)13：3L成膜→准分子激光退火(ELA)→光刻→干蚀刻→剥离；在遮光层11上形成缓冲层12，例如SiNx/SiOx，之后在缓冲层12上形成多晶硅层13，然后图案化多晶硅层13，剥离光阻；
(3)NCD：光刻→NCD离子注入(IMP)→剥离；对多晶硅层13进行沟道掺杂，形成沟道；
(4)NP：光刻→NP离子注入→剥离；对多晶硅层13进行N型离子重掺杂，形成NMOS沟道两侧的源极区和漏极区；
(5)形成栅极绝缘层14&栅极层15(GI&Gate)：栅极绝缘层14&栅极层15成膜→光刻→蚀刻→轻掺杂漏极区(LDD)离子注入；形成栅极绝缘层14和栅极层15，然后图案化栅极层15和栅极绝缘层14，形成TFT的栅极以及扫描线等结构，通过离子注入形成轻掺杂漏极区；
(6)Pp：光刻→Pp离子注入→剥离；对多晶硅层13进行P型离子重掺杂，形成PMOS沟道两侧的源极区和漏极区；
(7)形成层间介质层(ILD)16：层间介质层成膜→快速热退火(RTA)→光刻→干蚀刻→剥离；形成层间介质层16，图案化；
(8)形成源漏极层(SD)17：源漏极层成膜→光刻→干蚀刻→剥离；形成源漏极层17，图案化，形成源极/漏极和数据线等结构；
(9)形成平坦层(PLN)18：平坦层光刻→平坦层灰化(Ash)；形成平坦层18，图案化，灰化去除光阻；
(10)形成第一绝缘层19&第三金属层20(IL1&M3)：第一绝缘层&第三金属层成膜→第三金属层光刻→蚀刻→剥离；形成第一绝缘层19和第三金属层20，图案化第一绝缘层19和第三金属层20，第三金属层20作为触控信号线；
(11)形成第二绝缘层(IL2)21：第二绝缘层成膜→光刻→干蚀刻→剥离，形成第三金属层与底部透明电极(BITO)过孔；形成第二绝缘层21，图案化，形成第三金属层20与底部透明电极22之间的过孔；
(12)形成底部透明电极(BITO)22：底部透明电极成膜→光刻→蚀刻→剥离；形成底部透明电极22，图案化，底部透明电极22可作为触控信号电极；
(13)形成钝化层(PV)23：钝化层成膜→光刻→干蚀刻→剥离；形成钝化层23，图案化；现有技术中，钝化层23干蚀刻形成过孔时，需要一次蚀刻穿钝化层23/第二绝缘层21/第一绝缘层19三层膜，具有底切高发的风险；
(14)形成顶部透明电极(TITO)24：顶部透明电极成膜→光刻→蚀刻→剥离→退火(Anneal)；形成顶部透明电极24，图案化。
共需要14道光罩制程才能完成，工艺复杂、成本较高。
发明内容
因此，本发明的目的在于提供一种内嵌式触控阵列基板、显示面板及制造方法，简化制程、降低成本。
为实现上述目的，本发明提供了一种内嵌式触控阵列基板，包括：
基板；
设于基板上的低温多晶硅薄膜晶体管阵列，所述低温多晶硅薄膜晶体管阵列包括图案化的遮光层和图案化的源漏极层；
设于所述低温多晶硅薄膜晶体管阵列上的图案化的平坦层；
设于平坦层上的图案化的底部透明电极；
设于底部透明电极上的图案化的钝化层；
设于钝化层上的图案化的顶部透明电极；
所述源漏极层包括与底部透明电极相连接的第一走线，所述遮光层包括作为触控信号线的第二走线，所述第二走线与第一走线相连接。
其中，所述低温多晶硅薄膜晶体管阵列包括：
设于基板上的图案化的遮光层；
设于基板和遮光层上的图案化的缓冲层；
设于缓冲层上的图案化的多晶硅层；
设于多晶硅层和缓冲层上的图案化的栅极绝缘层；
设于栅极绝缘层上的图案化的栅极层；
设于栅极层上的图案化的层间介质层；
设于层间介质层上的图案化的源漏极层。
其中，所述缓冲层设有接触孔，以用于第一走线连接第二走线。
其中，所述栅极绝缘层设有过孔，以用于第一走线连接第二走线。
其中，所述层间介质层设有过孔，以用于第一走线连接第二走线。
其中，所述平坦层设有过孔，以用于底部透明电极连接第一走线。
其中，所述平坦层和钝化层分别设有过孔以用于所述顶部透明电极连接源漏极层。
其中，所述底部透明电极和顶部透明电极为氧化铟锡电极。
本发明还提供了一种显示面板，包括上述任一项所述的内嵌式触控阵列基板。
本发明还提供了一种内嵌式触控阵列基板的制造方法，包括：
在基板上形成遮光层，图案化遮光层，形成作为触控信号线的第二走线；
形成缓冲层及多晶硅层，图案化多晶硅层；
图案化缓冲层，形成用于第二走线连接第一走线的接触孔；
对多晶硅层进行沟道掺杂；
对多晶硅层进行N型离子重掺杂；
形成栅极绝缘层和栅极层，图案化栅极层和栅极绝缘层，栅极绝缘层形成用于第二走线连接第一走线的过孔；
对多晶硅层进行P型离子重掺杂；
形成层间介质层并使其图案化，形成用于第二走线连接第一走线的过孔；
形成源漏极层并使其图案化，形成用于与底部透明电极相连接的第一走线；
形成平坦层并使其图案化，形成用于底部透明电极连接第一走线的过孔；
形成底部透明电极，并使其图案化；
形成钝化层，并使其图案化；
形成顶部透明电极，并使其图案化。
综上，本发明的内嵌式触控阵列基板、显示面板及制造方法减少一道光罩，减少3次成膜，制程简化，成本降低；减少3次成膜，膜层结构简化，避免了第一绝缘层、第二绝缘层、钝化层三层非金属膜直接接触导电膜，降低了因应力搭配不佳而导致出现膜破的几率，也降低了钝化层干蚀刻一次蚀刻穿钝化层/第二绝缘层/第一绝缘层三层膜时底切高发的风险。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为一种现有内嵌式触控阵列基板的剖面展开示意图；
图2为本发明内嵌式触控阵列基板一较佳实施例的剖面展开示意图。
具体实施方式
参见图2，其为本发明内嵌式触控阵列基板一较佳实施例的剖面展开示意图。该较佳实施例的内嵌式触控阵列基板，主要包括：基板10；设于基板10上的低温多晶硅薄膜晶体管阵列，低温多晶硅薄膜晶体管阵列包括图案化的遮光层11和图案化的源漏极层17；设于低温多晶硅薄膜晶体管阵列 上的图案化的平坦层18；设于平坦层18上的图案化的底部透明电极22，可用作触控信号电极；设于底部透明电极22上的图案化的钝化层23；设于钝化层23上的图案化的顶部透明电极24，可用作像素电极；
本发明中，低温多晶硅薄膜晶体管阵列的源漏极层17金属除形成TFT的源漏极和数据线等结构外，还形成了用于与底部透明电极22相连接的第一走线171；遮光层11金属除了用于遮光，还形成了作为触控信号线的第二走线111；并且第二走线111与第一走线171相连接，从而使第二走线111与底部透明电极22电性导通，一个作为触控信号线，一个作为触控信号电极，用于实现触控功能。
低温多晶硅薄膜晶体管阵列的结构在此不做特别限制，仅以图2所示作为举例说明，一般可以包括：设于基板10上的图案化的遮光层11；设于基板10和遮光层11上的图案化的缓冲层12；设于缓冲层12上的图案化的多晶硅层13；设于多晶硅层13和缓冲层12上的图案化的栅极绝缘层14；设于栅极绝缘层14上的图案化的栅极层15，栅极层15可以形成TFT栅极及扫描线等结构；设于栅极层15上的图案化的层间介质层16；设于层间介质层16上的图案化的源漏极层17，源漏极层17可以形成TFT源漏极和数据线等结构。
为使第二走线111与第一走线171相连接，底部透明电极22与第一走线171连接，从而使第二走线111与底部透明电极22电性导通，缓冲层12可以设有接触孔，以用于第一走线171连接第二走线111；栅极绝缘层14可以设有过孔，以用于第一走线171连接第二走线111；层间介质层16可以设有过孔，以用于第一走线171连接第二走线111；平坦层18可以设有过孔，以用于底部透明电极22连接第一走线171。
此外，顶部透明电极24作为像素电极，平坦层18和钝化层23分别设有过孔以用于顶部透明电极24连接源漏极层17的TFT结构。底部透明电极22和顶部透明电极24都可以为氧化铟锡电极。
本发明可以通过采用数据(Data)线正下方的遮光层金属实现触控信号线走线设计，与非内嵌式相比只需在四层光罩图案稍作修改的基础上增加3L缓冲层一道光罩即可。与目前已有的内嵌式方案比较，可以减少3次成膜，并减少一道光罩，实现制程简化、成本降低，并有利于良率提高。
根据本发明上述内嵌式触控阵列基板的实施例，本发明还提供了包括上述内嵌式触控阵列基板的显示面板。
本发明还提供了内嵌式触控阵列基板的制造方法，可用于制作本发明的内嵌式触控阵列基板及显示面板。
该内嵌式触控阵列基板的制造方法一较佳实施例主要包括：
(1)形成遮光层11：遮光层11成膜→光刻→蚀刻→剥离，形成触控信号线和遮光层图案；
在基板10上形成遮光层11，利用光罩图案化遮光层11，剥离光阻，遮光层11金属除用于遮光外，还形成作为触控信号线的第二走线111；
(2)形成多晶硅层13：3L成膜→准分子激光退火→光刻→干蚀刻→剥离；
形成缓冲层12及多晶硅层13，图案化多晶硅层13，形成硅岛，剥离光阻；
(3)形成3L缓冲层接触孔(Contact Hole)：光刻→干蚀刻→剥离，形成3L缓冲层12接触孔；
增加一道光罩，图案化缓冲层12，形成用于第二走线111连接第一走线171的接触孔；
(4)NCD：光刻→NCD离子注入→剥离；
对多晶硅层13进行沟道掺杂，例如，可以对NMOS区域进行沟道掺杂，以及对PMOS区域两端进行P型离子轻掺杂处理，以分别形成NMOS沟道和PMOS沟道；
(5)NP：光刻→NP离子注入→剥离；
对多晶硅层13进行N型离子重掺杂；可以形成分别位于NMOS沟道两侧的源极区和漏极区；
(6)形成栅极绝缘层14&栅极层15：栅极绝缘层14&栅极层15成膜→光刻→蚀刻→轻掺杂漏极区离子注入；
形成栅极绝缘层14和栅极层15，图案化栅极层15和栅极绝缘层14，形成TFT栅极和扫描线，栅极绝缘层14形成用于第二走线111连接第一走线171的过孔；
(7)Pp：光刻→Pp离子注入→剥离；
对多晶硅层13进行P型离子重掺杂；可以形成PMOS沟道两侧的源极区和漏极区；
(8)形成层间介质层16：层间介质层16成膜→快速热退火→光刻→干蚀刻→剥离；
形成层间介质层16并使其图案化，形成用于第二走线111连接第一走线171的过孔；
(9)形成源漏极层17：源漏极层17成膜→光刻→干蚀刻→剥离；
形成源漏极层17并使其图案化，除TFT源漏极和数据线外，形成用于 与底部透明电极22相连接的第一走线171；
(10)形成平坦层18：平坦层18光刻→平坦层18灰化；
形成平坦层18并使其图案化，形成用于底部透明电极22连接第一走线171的过孔；平坦层18还形成过孔以用于顶部透明电极24连接源漏极层17的TFT结构；
(11)形成底部透明电极22：底部透明电极22成膜→光刻→蚀刻→剥离；
形成底部透明电极22，并使其图案化，底部透明电极22可以为氧化铟锡，可以用作触控信号电极；
(12)形成钝化层23：钝化层23成膜→光刻→干蚀刻→剥离；
形成钝化层23，并使其图案化；钝化层23形成过孔以用于顶部透明电极24连接源漏极层17的TFT结构；
(13)形成顶部透明电极24：顶部透明电极24成膜→光刻→蚀刻→剥离→退火；
形成顶部透明电极24，并使其图案化，顶部透明电极24可以为氧化铟锡，可以用作像素电极。
本发明采用遮光层布局触控信号线走线设计，无需IL1、M3、IL2三层成膜，也无需M3、IL2两次光罩，只需在多晶硅层完成后，增加一次光罩制程制作触控电极与遮光层触控信号线之间的连接过孔，可以简化制程，降低成本。
相较于现有的内嵌式触控阵列基板的制造方法，本发明：
(一)修改遮光层光罩，在数据线正下方对应区域的遮光层保留作为触控信号线，并增加与上层通过过孔连接结构；
(二)3L多晶硅层剥离光阻后增加一道光罩制程，在3L缓冲层制做出遮光层触控信号线与上层源漏极层连接的过孔；
(三)修改层间介质层光罩，增加遮光层触控信号线与源漏极层连接的层间介质层过孔；
(四)修改源漏极层光罩，增加触控信号线与BITO连接的桥接源漏极层金属；
(五)修改平坦层光罩，增加触控信号线与BITO连接的平坦层过孔。
综上，本发明的内嵌式触控阵列基板、显示面板及制造方法减少一道光罩(14光罩→13光罩)，减少3次成膜，制程简化，成本降低；减少3次成膜(无需IL1、M3、IL2)，膜层结构简化，避免了第一绝缘层、第二绝缘层、钝化层三层非金属膜直接接触导电膜，降低了因应力搭配不佳而 导致出现膜破的几率，也降低了钝化层干蚀刻一次蚀刻穿钝化层/第二绝缘层/第一绝缘层三层膜时底切(UnderCut)高发的风险。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种内嵌式触控阵列基板，包括：
    基板；
    设于基板上的低温多晶硅薄膜晶体管阵列，所述低温多晶硅薄膜晶体管阵列包括图案化的遮光层和图案化的源漏极层；
    设于所述低温多晶硅薄膜晶体管阵列上的图案化的平坦层；
    设于平坦层上的图案化的底部透明电极；
    设于底部透明电极上的图案化的钝化层；
    设于钝化层上的图案化的顶部透明电极；
    所述源漏极层包括与底部透明电极相连接的第一走线，所述遮光层包括作为触控信号线的第二走线，所述第二走线与第一走线相连接。
  2. 如权利要求1所述的内嵌式触控阵列基板，其中，所述低温多晶硅薄膜晶体管阵列包括：
    设于基板上的图案化的遮光层；
    设于基板和遮光层上的图案化的缓冲层；
    设于缓冲层上的图案化的多晶硅层；
    设于多晶硅层和缓冲层上的图案化的栅极绝缘层；
    设于栅极绝缘层上的图案化的栅极层；
    设于栅极层上的图案化的层间介质层；
    设于层间介质层上的图案化的源漏极层。
  3. 如权利要求2所述的内嵌式触控阵列基板，其中，所述缓冲层设有接触孔，以用于第一走线连接第二走线。
  4. 如权利要求2所述的内嵌式触控阵列基板，其中，所述栅极绝缘层设有过孔，以用于第一走线连接第二走线。
  5. 如权利要求2所述的内嵌式触控阵列基板，其中，所述层间介质层设有过孔，以用于第一走线连接第二走线。
  6. 如权利要求1所述的内嵌式触控阵列基板，其中，所述平坦层设有过孔，以用于底部透明电极连接第一走线。
  7. 如权利要求1所述的内嵌式触控阵列基板，其中，所述平坦层和钝化层分别设有过孔以用于所述顶部透明电极连接源漏极层。
  8. 如权利要求1所述的内嵌式触控阵列基板，其中，所述底部透明电极和顶部透明电极为氧化铟锡电极。
  9. 一种显示面板，包括：如权利要求1所述的内嵌式触控阵列基板。
  10. 一种内嵌式触控阵列基板的制造方法，包括：
    在基板上形成遮光层，图案化遮光层，形成作为触控信号线的第二走线；
    形成缓冲层及多晶硅层，图案化多晶硅层；
    图案化缓冲层，形成用于第二走线连接第一走线的接触孔；
    对多晶硅层进行沟道掺杂；
    对多晶硅层进行N型离子重掺杂；
    形成栅极绝缘层和栅极层，图案化栅极层和栅极绝缘层，栅极绝缘层形成用于第二走线连接第一走线的过孔；
    对多晶硅层进行P型离子重掺杂；
    形成层间介质层并使其图案化，形成用于第二走线连接第一走线的过孔；
    形成源漏极层并使其图案化，形成用于与底部透明电极相连接的第一走线；
    形成平坦层并使其图案化，形成用于底部透明电极连接第一走线的过孔；
    形成底部透明电极，并使其图案化；
    形成钝化层，并使其图案化；
    形成顶部透明电极，并使其图案化。
PCT/CN2018/108082 2018-04-28 2018-09-27 内嵌式触控阵列基板、显示面板及制造方法 Ceased WO2019205489A1 (zh)

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