WO2019179062A1 - Procédé de fabrication et d'emballage de support capable d'empêcher un court-circuit provoqué par une soudure d'une puce de circuit à deux surfaces - Google Patents

Procédé de fabrication et d'emballage de support capable d'empêcher un court-circuit provoqué par une soudure d'une puce de circuit à deux surfaces Download PDF

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Publication number
WO2019179062A1
WO2019179062A1 PCT/CN2018/104481 CN2018104481W WO2019179062A1 WO 2019179062 A1 WO2019179062 A1 WO 2019179062A1 CN 2018104481 W CN2018104481 W CN 2018104481W WO 2019179062 A1 WO2019179062 A1 WO 2019179062A1
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WIPO (PCT)
Prior art keywords
wafer
carrier
pad
solder
double
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PCT/CN2018/104481
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English (en)
Chinese (zh)
Inventor
吴现伟
龙华
郭嘉帅
郑瑞
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深圳飞骧科技有限公司
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Publication of WO2019179062A1 publication Critical patent/WO2019179062A1/fr

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Definitions

  • the invention relates to the field of welding, in particular to a method for fabricating and packaging a carrier plate for solving a short circuit of a wafer of a double-sided circuit.
  • the wafer is a carrier used in the production of integrated circuits, and refers to a single crystal silicon wafer, and a compound wafer such as gallium arsenide, silicon carbide, gallium nitride or indium phosphide.
  • wafers are typically fabricated in a single-sided design.
  • the requirements for transistor integration density are becoming higher and higher, and it is becoming more and more challenging.
  • the side-mounted patch is obtained by sucking the wafer and matching it through two vacuum conduit brackets, using the plastic nozzle at the front end of the bracket to contact and adsorbing the surface of the wafer, rotating 90 degrees, and the other bracket sucking the upper side of the wafer, moving to the sticker Above the chip position, the process of mounting the chip on the chip side is completed according to the set falling speed.
  • the non-pad area on the surface of the wafer is usually covered with a layer of oily organic passivation layer, which is lipophilic, which can prevent non-oily substances from climbing and spreading.
  • a layer of oily organic passivation layer which is lipophilic, which can prevent non-oily substances from climbing and spreading.
  • the adjacent pads on the same side of the wafer will be short-circuited by the solder on the bottom side of the wafer, or the circuit pads on both sides of the wafer will be climbed on the bottom side of the wafer by the solder. Climb a short circuit.
  • the invention can effectively solve the short circuit problem between the pads by utilizing the characteristics of the solder composition, the material characteristics of the carrier, the design of the carrier structure, and the application process of the non-conductive rubber material.
  • the non-conductive adhesive in the double-sided circuit side mounting process also effectively improves the bonding force between the wafer and the carrier, further improving the stress damage and reliability of the packaged components.
  • the present invention intends to provide a carrier plate fabrication and packaging method for solving the short-circuit soldering of the double-sided circuit wafer, using the composition characteristics of the solder, the material properties of the carrier, the design of the carrier structure, And the application of non-conductive rubber material packaging technology can effectively solve the short circuit problem between the pads, and further improve the stress damage and reliability of the packaged finished components.
  • the invention provides a carrier plate fabrication and packaging method for solving a short circuit of a double-sided circuit wafer solder, characterized in that the method comprises the following steps:
  • Step S1 designing a double-sided circuit wafer
  • Step S2 designing and fabricating a carrier according to the thickness of the double-sided circuit wafer, the pad distribution, and the spatial arrangement of the package unit;
  • Step S3 applying a non-conductive adhesive on the surface of the carrier green oil corresponding to the wafer;
  • Step S4 coating a conductive paste on the carrier pad corresponding to the wafer pad;
  • Step S5 the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer is first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the corresponding carrier on the bottom of the wafer.
  • Step S6 the carrier board exits the workbench for a period of time
  • step S7 the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
  • the method further includes a step S8, an appearance check to confirm the combination.
  • the method may replace the conductive paste with a solder paste, wherein the steps S3-S7 are replaced by the following steps:
  • the reflow process melts the semi-cured solder paste in the heating zone and the heat preservation zone, and the tin material is effectively passed through the intermetallic wettability and the carrier pad and the die pad. Combined, the tin material is solidified in the cooling zone, and the reflow solder joint is completed;
  • the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
  • the thickness of the wafer is between 200 um and 300 um.
  • step S1 the non-pad region of the double-sided circuit of the wafer is coated with an oily passivation layer, and the bottom of the wafer has no oil-coated passivation layer.
  • step S2 when the carrier is designed and fabricated, the carrier green oil at the wafer pad is fenestrated, and the carrier and the wafer corresponding pad are exposed.
  • step S6 the set time is 3 to 10 minutes.
  • the thickness of the printed steel mesh may be selected from 60 um and 80 um.
  • solder paste comprises tin silver, tin silver copper, tin copper, and is in a semi-cured form.
  • the oven bakes and cures the conductive adhesive or the non-conductive adhesive, and the baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature, and temperature drop for 2 hours.
  • the double-sided conductive adhesive can be short-circuited by the mutual effect of the contact between the wafer and the carrier due to the capillary effect, thereby improving the package yield and reducing the loss;
  • the combination of the wafer and the carrier plate is more stable, effectively preventing the product from falling off the weld of the wafer and the carrier due to internal or external stress, and improving the stress damage and reliability of the packaged component.
  • FIG. 1 is a schematic flow chart of a method for using a conductive paste according to the present invention.
  • FIG. 2 is a schematic flow chart of a method for using a solder paste of the present invention.
  • FIG 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • FIG. 4 is a schematic diagram of the size and spacing of a common die pad.
  • Fig. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer.
  • Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention.
  • Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention.
  • Figure 8 is a plan view of the carrier of the present invention.
  • Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention.
  • Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention.
  • Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention.
  • FIG. 1 is a schematic flow chart of a method for using a conductive paste according to the present invention. The method includes the following steps:
  • step S1 a double-sided circuit wafer is designed, and the thickness of the wafer is between 200 um and 300 um.
  • the thickness of the wafer is preferably ⁇ 200 um, which is limited by the wafer cutting process, and the thickness of the wafer is preferably ⁇ 300 um.
  • the bottleneck of the wafer cutting process will be broadened, and the packaging process will be further strengthened, which will be more suitable for large-area wafer products.
  • the non-pad regions on both sides of the wafer are usually coated with an oil-based passivation layer.
  • the pad region without passivation layer is usually exposed with metallic aluminum or gold.
  • the bottom of the wafer is separated by dicing die. Or the compound substrate is exposed, there is no oily passivation layer applied, and there is no significant lipophilic or oleophobic property.
  • step S2 the carrier board is designed and fabricated according to the thickness of the double-sided circuit wafer, the pad distribution, and the space arrangement of the package unit.
  • FIG. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer.
  • step S3 a "one" or “ten” non-conductive paste is applied on the surface of the carrier green oil corresponding to the wafer.
  • the non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
  • non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
  • Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention.
  • Figure 8 is a plan view of the carrier of the present invention. 6 and FIG. 8 , in one embodiment of the present invention, in order to avoid short circuit of the conductive paste and the pads on both sides, the non-conductive adhesive coated on the surface of the green oil in the middle of the carrier is well insulated. The conductive paste and pads on both sides avoid short circuits. And the wafer and the carrier are combined and cured.
  • Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention.
  • the non-conductive surface of the green oil is applied at a small area in the middle of the carrier pad and the pad. Glue, good isolation of conductive adhesive and pads in adjacent locations, avoiding short circuits. And the wafer and the carrier are combined and cured.
  • Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention.
  • Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention.
  • the non-conductive adhesive coated on the surface of the green oil surface solved by the wafer and the carrier is The transistor circuit and the carrier circuit are well isolated to avoid short circuits. And the wafer and the carrier are combined and cured.
  • step S4 the conductive paste is coated on the carrier pad corresponding to the wafer pad.
  • the conductive adhesive needs to meet the characteristics of low diluent content, high silver powder content and high viscosity. Silver metal oleophobic in the conductive adhesive composition is not easy to conduct to the passivation layer on the surface of the wafer. However, due to the liquid organic lipophilic component such as diluent, the conductive paste will be guided along the exposed surface of the substrate at the bottom of the wafer, resulting in a carrier. The adjacent pads are shorted.
  • FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • the wafer pad and the carrier pad are bonded and bonded by solder, that is, conductive paste.
  • the wafer circuit is designed on both sides.
  • FIG. 4 is a schematic diagram of the size and spacing of the general-purpose wafer pads.
  • the pad pitch is ⁇ 60 um, and the pad length is ⁇ 50 um.
  • Step S5 the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer will be first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the bottom of the wafer.
  • the glue will quickly bond to the wafer pads.
  • FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • the wafer pad corresponds to the position of the carrier pad, and is bonded and bonded by solder, that is, conductive paste.
  • step S6 the carrier board is left out of the table for 3 to 10 minutes, and the process brings the conductive paste into full contact with the wafer pad.
  • step S7 the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
  • the oven bakes and cures the conductive adhesive or non-conductive adhesive.
  • the baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.
  • step S8 the appearance inspection confirms the combination.
  • the method can replace the conductive paste with a solder paste, as shown in FIG. 2, and FIG. 2 is a schematic flow chart of the method for using the solder paste of the present invention. Steps S3-S7 in the above method are replaced by the following steps S31-S71.
  • the thickness of the printed steel mesh may be selected from 60 um and 80 um; and the solder paste is printed on the carrier pad corresponding to the wafer pad.
  • the solder paste includes tin silver, tin silver copper, tin copper, and the like.
  • the solder paste is in a semi-cured form and has a high viscosity.
  • the non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
  • non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
  • Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention.
  • the non-conductive adhesive applied on the surface of the green oil in the middle of the carrier is well insulated. Place the solder paste and pads to avoid short circuits. And the wafer and the carrier are combined and cured.
  • the bottom of the wafer may be in contact with the non-conductive glue first, or may be in contact with the solder paste first.
  • the wafer continues to be pressed down to make the non-conductive glue fill the green oil region corresponding to the bottom of the wafer, and at the same time, the solder paste at the bottom contact position of the wafer collapses, so that the side wiring pads of the wafer are in contact with the solder paste.
  • the solder paste is in contact with the die pad but is not bonded.
  • the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
  • the baking condition of the non-conductive glue is usually 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

L'invention concerne un procédé de fabrication et d'emballage d'un support capable d'empêcher un court-circuit provoqué par une soudure d'une puce de circuit à deux surfaces. Le procédé comprend les étapes suivantes consistant à : concevoir une puce de circuit à deux surfaces (S1); concevoir et fabriquer un support selon une épaisseur des puces de circuit à deux surfaces, agencer des plots de soudure et une disposition spatiale d'unités d'emballage (S2); appliquer un adhésif électriquement non conducteur sur une surface d'un masque de soudure de support à une position correspondant à une puce devant être montée latéralement (S3, S41); appliquer un adhésif électroconducteur sur un plot de soudure de support correspondant à un plot de soudure de puce (S4); monter latéralement et lier des puces de circuit à deux surfaces (S5, S51); retirer le support d'un établi, et laisser reposer le support pendant une certaine période de temps (S6); chauffer et durcir les adhésifs dans un four, de telle sorte que l'adhésif électriquement non conducteur est durci pour améliorer la liaison entre la puce et le support, et l'adhésif électroconducteur est durci entre le plot de soudure de support et le plot de soudure de puce (S7, S71); et inspecter l'apparence pour confirmer les performances de liaison (S8). Le procédé peut résoudre un problème dans lequel, lors du montage latéral d'une puce à deux circuits de surface, le fluage mutuel d'adhésifs conducteurs sur les deux côtés sur une région de contact en raison d'un effet capillaire conduit à un court-circuit, ce qui permet d'améliorer le rendement de l'emballage, et de renforcer la liaison entre la puce et le support.
PCT/CN2018/104481 2018-03-22 2018-09-07 Procédé de fabrication et d'emballage de support capable d'empêcher un court-circuit provoqué par une soudure d'une puce de circuit à deux surfaces WO2019179062A1 (fr)

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CN201810241152.9 2018-03-22
CN201810241152.9A CN108493121B (zh) 2018-03-22 2018-03-22 一种解决双面电路晶元焊料短路的载板制作及封装方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314539A (zh) * 2023-03-31 2023-06-23 广东省旭晟半导体股份有限公司 一种具有增强led可靠性的封装结构及其制备工艺

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493121B (zh) * 2018-03-22 2019-09-20 上海飞骧电子科技有限公司 一种解决双面电路晶元焊料短路的载板制作及封装方法
CN109650323B (zh) * 2018-12-24 2020-11-03 烟台艾睿光电科技有限公司 一种焊料隔离结构以及电子器件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198463A (ja) * 2000-12-26 2002-07-12 Canon Inc チップサイズパッケージおよびその製造方法
CN103311205A (zh) * 2013-05-16 2013-09-18 华天科技（西安）有限公司 一种防止芯片凸点短路的封装件及其制造工艺
CN103545303A (zh) * 2012-07-17 2014-01-29 马维尔国际贸易有限公司 Ic封装体和组装
CN103582302A (zh) * 2012-07-25 2014-02-12 纬创资通股份有限公司 印刷电路板及印刷电路板的制造方法
CN104486907A (zh) * 2014-12-10 2015-04-01 华进半导体封装先导技术研发中心有限公司 高频ipd模块三维集成晶圆级封装结构及封装方法
CN108493121A (zh) * 2018-03-22 2018-09-04 上海飞骧电子科技有限公司 一种解决双面电路晶元焊料短路的载板制作及封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198463A (ja) * 2000-12-26 2002-07-12 Canon Inc チップサイズパッケージおよびその製造方法
CN103545303A (zh) * 2012-07-17 2014-01-29 马维尔国际贸易有限公司 Ic封装体和组装
CN103582302A (zh) * 2012-07-25 2014-02-12 纬创资通股份有限公司 印刷电路板及印刷电路板的制造方法
CN103311205A (zh) * 2013-05-16 2013-09-18 华天科技（西安）有限公司 一种防止芯片凸点短路的封装件及其制造工艺
CN104486907A (zh) * 2014-12-10 2015-04-01 华进半导体封装先导技术研发中心有限公司 高频ipd模块三维集成晶圆级封装结构及封装方法
CN108493121A (zh) * 2018-03-22 2018-09-04 上海飞骧电子科技有限公司 一种解决双面电路晶元焊料短路的载板制作及封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314539A (zh) * 2023-03-31 2023-06-23 广东省旭晟半导体股份有限公司 一种具有增强led可靠性的封装结构及其制备工艺
CN116314539B (zh) * 2023-03-31 2023-11-21 广东省旭晟半导体股份有限公司 一种具有增强led可靠性的封装结构及其制备工艺

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