WO2019179062A1 - Method for manufacturing and packaging carrier capable of preventing short circuit caused by solder of two surface circuit die - Google Patents

Method for manufacturing and packaging carrier capable of preventing short circuit caused by solder of two surface circuit die Download PDF

Info

Publication number
WO2019179062A1
WO2019179062A1 PCT/CN2018/104481 CN2018104481W WO2019179062A1 WO 2019179062 A1 WO2019179062 A1 WO 2019179062A1 CN 2018104481 W CN2018104481 W CN 2018104481W WO 2019179062 A1 WO2019179062 A1 WO 2019179062A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
carrier
pad
solder
double
Prior art date
Application number
PCT/CN2018/104481
Other languages
French (fr)
Chinese (zh)
Inventor
吴现伟
龙华
郭嘉帅
郑瑞
Original Assignee
深圳飞骧科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳飞骧科技有限公司 filed Critical 深圳飞骧科技有限公司
Publication of WO2019179062A1 publication Critical patent/WO2019179062A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3005—Shape
    • H01L2224/30051—Layer connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Definitions

  • the invention relates to the field of welding, in particular to a method for fabricating and packaging a carrier plate for solving a short circuit of a wafer of a double-sided circuit.
  • the wafer is a carrier used in the production of integrated circuits, and refers to a single crystal silicon wafer, and a compound wafer such as gallium arsenide, silicon carbide, gallium nitride or indium phosphide.
  • wafers are typically fabricated in a single-sided design.
  • the requirements for transistor integration density are becoming higher and higher, and it is becoming more and more challenging.
  • the side-mounted patch is obtained by sucking the wafer and matching it through two vacuum conduit brackets, using the plastic nozzle at the front end of the bracket to contact and adsorbing the surface of the wafer, rotating 90 degrees, and the other bracket sucking the upper side of the wafer, moving to the sticker Above the chip position, the process of mounting the chip on the chip side is completed according to the set falling speed.
  • the non-pad area on the surface of the wafer is usually covered with a layer of oily organic passivation layer, which is lipophilic, which can prevent non-oily substances from climbing and spreading.
  • a layer of oily organic passivation layer which is lipophilic, which can prevent non-oily substances from climbing and spreading.
  • the adjacent pads on the same side of the wafer will be short-circuited by the solder on the bottom side of the wafer, or the circuit pads on both sides of the wafer will be climbed on the bottom side of the wafer by the solder. Climb a short circuit.
  • the invention can effectively solve the short circuit problem between the pads by utilizing the characteristics of the solder composition, the material characteristics of the carrier, the design of the carrier structure, and the application process of the non-conductive rubber material.
  • the non-conductive adhesive in the double-sided circuit side mounting process also effectively improves the bonding force between the wafer and the carrier, further improving the stress damage and reliability of the packaged components.
  • the present invention intends to provide a carrier plate fabrication and packaging method for solving the short-circuit soldering of the double-sided circuit wafer, using the composition characteristics of the solder, the material properties of the carrier, the design of the carrier structure, And the application of non-conductive rubber material packaging technology can effectively solve the short circuit problem between the pads, and further improve the stress damage and reliability of the packaged finished components.
  • the invention provides a carrier plate fabrication and packaging method for solving a short circuit of a double-sided circuit wafer solder, characterized in that the method comprises the following steps:
  • Step S1 designing a double-sided circuit wafer
  • Step S2 designing and fabricating a carrier according to the thickness of the double-sided circuit wafer, the pad distribution, and the spatial arrangement of the package unit;
  • Step S3 applying a non-conductive adhesive on the surface of the carrier green oil corresponding to the wafer;
  • Step S4 coating a conductive paste on the carrier pad corresponding to the wafer pad;
  • Step S5 the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer is first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the corresponding carrier on the bottom of the wafer.
  • Step S6 the carrier board exits the workbench for a period of time
  • step S7 the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
  • the method further includes a step S8, an appearance check to confirm the combination.
  • the method may replace the conductive paste with a solder paste, wherein the steps S3-S7 are replaced by the following steps:
  • the reflow process melts the semi-cured solder paste in the heating zone and the heat preservation zone, and the tin material is effectively passed through the intermetallic wettability and the carrier pad and the die pad. Combined, the tin material is solidified in the cooling zone, and the reflow solder joint is completed;
  • the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
  • the thickness of the wafer is between 200 um and 300 um.
  • step S1 the non-pad region of the double-sided circuit of the wafer is coated with an oily passivation layer, and the bottom of the wafer has no oil-coated passivation layer.
  • step S2 when the carrier is designed and fabricated, the carrier green oil at the wafer pad is fenestrated, and the carrier and the wafer corresponding pad are exposed.
  • step S6 the set time is 3 to 10 minutes.
  • the thickness of the printed steel mesh may be selected from 60 um and 80 um.
  • solder paste comprises tin silver, tin silver copper, tin copper, and is in a semi-cured form.
  • the oven bakes and cures the conductive adhesive or the non-conductive adhesive, and the baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature, and temperature drop for 2 hours.
  • the double-sided conductive adhesive can be short-circuited by the mutual effect of the contact between the wafer and the carrier due to the capillary effect, thereby improving the package yield and reducing the loss;
  • the combination of the wafer and the carrier plate is more stable, effectively preventing the product from falling off the weld of the wafer and the carrier due to internal or external stress, and improving the stress damage and reliability of the packaged component.
  • FIG. 1 is a schematic flow chart of a method for using a conductive paste according to the present invention.
  • FIG. 2 is a schematic flow chart of a method for using a solder paste of the present invention.
  • FIG 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • FIG. 4 is a schematic diagram of the size and spacing of a common die pad.
  • Fig. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer.
  • Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention.
  • Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention.
  • Figure 8 is a plan view of the carrier of the present invention.
  • Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention.
  • Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention.
  • Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention.
  • FIG. 1 is a schematic flow chart of a method for using a conductive paste according to the present invention. The method includes the following steps:
  • step S1 a double-sided circuit wafer is designed, and the thickness of the wafer is between 200 um and 300 um.
  • the thickness of the wafer is preferably ⁇ 200 um, which is limited by the wafer cutting process, and the thickness of the wafer is preferably ⁇ 300 um.
  • the bottleneck of the wafer cutting process will be broadened, and the packaging process will be further strengthened, which will be more suitable for large-area wafer products.
  • the non-pad regions on both sides of the wafer are usually coated with an oil-based passivation layer.
  • the pad region without passivation layer is usually exposed with metallic aluminum or gold.
  • the bottom of the wafer is separated by dicing die. Or the compound substrate is exposed, there is no oily passivation layer applied, and there is no significant lipophilic or oleophobic property.
  • step S2 the carrier board is designed and fabricated according to the thickness of the double-sided circuit wafer, the pad distribution, and the space arrangement of the package unit.
  • FIG. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer.
  • step S3 a "one" or “ten” non-conductive paste is applied on the surface of the carrier green oil corresponding to the wafer.
  • the non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
  • non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
  • Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention.
  • Figure 8 is a plan view of the carrier of the present invention. 6 and FIG. 8 , in one embodiment of the present invention, in order to avoid short circuit of the conductive paste and the pads on both sides, the non-conductive adhesive coated on the surface of the green oil in the middle of the carrier is well insulated. The conductive paste and pads on both sides avoid short circuits. And the wafer and the carrier are combined and cured.
  • Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention.
  • the non-conductive surface of the green oil is applied at a small area in the middle of the carrier pad and the pad. Glue, good isolation of conductive adhesive and pads in adjacent locations, avoiding short circuits. And the wafer and the carrier are combined and cured.
  • Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention.
  • Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention.
  • the non-conductive adhesive coated on the surface of the green oil surface solved by the wafer and the carrier is The transistor circuit and the carrier circuit are well isolated to avoid short circuits. And the wafer and the carrier are combined and cured.
  • step S4 the conductive paste is coated on the carrier pad corresponding to the wafer pad.
  • the conductive adhesive needs to meet the characteristics of low diluent content, high silver powder content and high viscosity. Silver metal oleophobic in the conductive adhesive composition is not easy to conduct to the passivation layer on the surface of the wafer. However, due to the liquid organic lipophilic component such as diluent, the conductive paste will be guided along the exposed surface of the substrate at the bottom of the wafer, resulting in a carrier. The adjacent pads are shorted.
  • FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • the wafer pad and the carrier pad are bonded and bonded by solder, that is, conductive paste.
  • the wafer circuit is designed on both sides.
  • FIG. 4 is a schematic diagram of the size and spacing of the general-purpose wafer pads.
  • the pad pitch is ⁇ 60 um, and the pad length is ⁇ 50 um.
  • Step S5 the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer will be first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the bottom of the wafer.
  • the glue will quickly bond to the wafer pads.
  • FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention.
  • the wafer pad corresponds to the position of the carrier pad, and is bonded and bonded by solder, that is, conductive paste.
  • step S6 the carrier board is left out of the table for 3 to 10 minutes, and the process brings the conductive paste into full contact with the wafer pad.
  • step S7 the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
  • the oven bakes and cures the conductive adhesive or non-conductive adhesive.
  • the baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.
  • step S8 the appearance inspection confirms the combination.
  • the method can replace the conductive paste with a solder paste, as shown in FIG. 2, and FIG. 2 is a schematic flow chart of the method for using the solder paste of the present invention. Steps S3-S7 in the above method are replaced by the following steps S31-S71.
  • the thickness of the printed steel mesh may be selected from 60 um and 80 um; and the solder paste is printed on the carrier pad corresponding to the wafer pad.
  • the solder paste includes tin silver, tin silver copper, tin copper, and the like.
  • the solder paste is in a semi-cured form and has a high viscosity.
  • the non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
  • non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
  • Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention.
  • the non-conductive adhesive applied on the surface of the green oil in the middle of the carrier is well insulated. Place the solder paste and pads to avoid short circuits. And the wafer and the carrier are combined and cured.
  • the bottom of the wafer may be in contact with the non-conductive glue first, or may be in contact with the solder paste first.
  • the wafer continues to be pressed down to make the non-conductive glue fill the green oil region corresponding to the bottom of the wafer, and at the same time, the solder paste at the bottom contact position of the wafer collapses, so that the side wiring pads of the wafer are in contact with the solder paste.
  • the solder paste is in contact with the die pad but is not bonded.
  • the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
  • the baking condition of the non-conductive glue is usually 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method for manufacturing and packaging a carrier capable of preventing a short circuit caused by a solder of a two surface circuit die. The method comprises the following steps: designing a two surface circuit die (S1); designing and manufacturing a carrier according to a thickness of the two surface circuit die, arrangement of solder pads and a spatial layout of package units (S2); applying an electrically non-conductive adhesive to a surface of a carrier solder mask at a position corresponding to a die to be side-mounted (S3, S41); applying an electrically conductive adhesive to a carrier solder pad corresponding to a die solder pad (S4); side mounting and bonding the two surface circuit die (S5, S51); removing the carrier from a workbench, and leaving the carrier to stand for a period of time (S6); heating and curing the adhesives in an oven, such that the electrically non-conductive adhesive is cured to enhance bonding between the die and the carrier, and the electrically conductive adhesive is cured between the carrier solder pad and the die solder pad (S7, S71); and inspecting the appearance to confirm bonding performance (S8). The method can solve a problem in which upon side mounting a two surface circuit die, mutual creeping of conductive adhesives at both sides over a contact region due to a capillary effect results in a short circuit, thereby improving a package yield, and reinforcing bonding between the die and the carrier.

Description

一种解决双面电路晶元焊料短路的载板制作及封装方法Carrier plate manufacturing and packaging method for solving short circuit soldering of double-sided circuit 技术领域Technical field
本发明涉及焊接领域，具体涉及一种解决双面电路晶元焊料短路的载板制作及封装方法。The invention relates to the field of welding, in particular to a method for fabricating and packaging a carrier plate for solving a short circuit of a wafer of a double-sided circuit.
背景技术Background technique
晶元，是生产集成电路所用的载体，多指单晶硅圆片，还有砷化镓、碳化硅、氮化镓、磷化铟等化合物圆片。半导体制造工艺中，晶元通常为单面设计制造。但随着各类功能集成的需求越来越多越来越高，对晶体管集成密度要求也越来越高，越来越有挑战性。The wafer is a carrier used in the production of integrated circuits, and refers to a single crystal silicon wafer, and a compound wafer such as gallium arsenide, silicon carbide, gallium nitride or indium phosphide. In semiconductor manufacturing processes, wafers are typically fabricated in a single-sided design. However, as the demand for various types of functional integration increases, the requirements for transistor integration density are becoming higher and higher, and it is becoming more and more challenging.
侧装贴片，是将晶元吸取并通过两个真空导管支架配合，利用支架前端塑料吸嘴接触并吸附晶元表面，旋转90度，另一支架吸嘴吸取晶元上方侧面，移至贴片位置上方，根据设置下降速度，完成芯片侧装贴片的过程。The side-mounted patch is obtained by sucking the wafer and matching it through two vacuum conduit brackets, using the plastic nozzle at the front end of the bracket to contact and adsorbing the surface of the wafer, rotating 90 degrees, and the other bracket sucking the upper side of the wafer, moving to the sticker Above the chip position, the process of mounting the chip on the chip side is completed according to the set falling speed.
晶元表面非焊盘区域通常覆有一层油性有机钝化层，具有亲油性，能够防止非油性物质攀爬扩散，晶元贴装前需分离切割为单颗晶粒，切割道位置会将晶粒四周侧面单晶硅或化合物基底暴露出来，基底不具备亲油或疏油特性，流动性较强流体物质会在其表面攀爬扩散。双面电路晶元侧装过程中会遇到晶元同一侧电路相邻焊盘因焊料在晶元底部侧面基底攀爬短路，或晶元两侧电路焊盘因焊料在晶元底部侧面基底攀爬短路。本发明利用焊料成分特性、载板材料特性、载板结构设计、及封装非导电胶材料工艺运用等，可有效解决焊盘间短路问题。另外，非导电胶在双面电路侧装的封装工艺运用上还有效提升了晶元与载板之间的结合力，进一步提升了封装成品元件的防应力损坏及可靠性等。The non-pad area on the surface of the wafer is usually covered with a layer of oily organic passivation layer, which is lipophilic, which can prevent non-oily substances from climbing and spreading. Before the wafer is mounted, it needs to be separated and cut into single grains, and the position of the cutting channel will be crystal. The single crystal silicon or compound substrate on the side of the particle is exposed, and the substrate does not have lipophilic or oleophobic properties. The fluidity of the fluid material will climb and spread on the surface. During the side-mounted process of the double-sided circuit wafer, the adjacent pads on the same side of the wafer will be short-circuited by the solder on the bottom side of the wafer, or the circuit pads on both sides of the wafer will be climbed on the bottom side of the wafer by the solder. Climb a short circuit. The invention can effectively solve the short circuit problem between the pads by utilizing the characteristics of the solder composition, the material characteristics of the carrier, the design of the carrier structure, and the application process of the non-conductive rubber material. In addition, the non-conductive adhesive in the double-sided circuit side mounting process also effectively improves the bonding force between the wafer and the carrier, further improving the stress damage and reliability of the packaged components.
发明内容Summary of the invention
为了有效解决双面电路晶元焊料短路的问题，本发明拟提供一种解决双面电路晶元焊料短路的载板制作及封装方法，利用焊料成分特性、载板材料特性、载板结构设计、及封装非导电胶材料工艺运用等，可有效解决焊盘间短路问题，并进一步提升了封装成品元件的防应力损坏及可靠性等。In order to effectively solve the problem of short circuit soldering of the double-sided circuit wafer, the present invention intends to provide a carrier plate fabrication and packaging method for solving the short-circuit soldering of the double-sided circuit wafer, using the composition characteristics of the solder, the material properties of the carrier, the design of the carrier structure, And the application of non-conductive rubber material packaging technology can effectively solve the short circuit problem between the pads, and further improve the stress damage and reliability of the packaged finished components.
本发明提供一种解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，该方法包括以下步骤：The invention provides a carrier plate fabrication and packaging method for solving a short circuit of a double-sided circuit wafer solder, characterized in that the method comprises the following steps:
步骤S1，设计双面电路晶元；Step S1, designing a double-sided circuit wafer;
步骤S2，根据双面电路晶元的厚度、焊盘分布及封装单元空间排布，设计并制作载板；Step S2, designing and fabricating a carrier according to the thickness of the double-sided circuit wafer, the pad distribution, and the spatial arrangement of the package unit;
步骤S3，在晶元对应的载板绿油表面位置涂覆非导电胶；Step S3, applying a non-conductive adhesive on the surface of the carrier green oil corresponding to the wafer;
步骤S4，在与晶元焊盘对应的载板焊盘涂覆导电胶；Step S4, coating a conductive paste on the carrier pad corresponding to the wafer pad;
步骤S5，侧装粘贴双面电路晶元，晶元自上向下贴装过程中，晶元底部先与非导电胶接触并向下挤压，使非导电胶充满晶元底部对应的载板绿油区域；晶元继续向下贴装，晶元侧面及侧面焊盘与导电胶接触，使导电胶快速与晶元焊盘结合；Step S5, the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer is first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the corresponding carrier on the bottom of the wafer. The green oil area; the wafer continues to be mounted downward, and the side and side pads of the wafer are in contact with the conductive paste, so that the conductive paste is quickly combined with the wafer pad;
步骤S6，载板退出工作台搁置一段时间；Step S6, the carrier board exits the workbench for a period of time;
步骤S7，烤箱烘烤固化胶体，使非导电胶固化增强晶元与载板结合，使导电胶与载板焊盘及晶元焊盘固化。In step S7, the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
进一步地，所述方法还包括步骤S8，外观检验，确认结合性。Further, the method further includes a step S8, an appearance check to confirm the combination.
进一步地，所述方法可以用锡膏来代替导电胶，其中步骤S3-S7用如下步骤来代替：Further, the method may replace the conductive paste with a solder paste, wherein the steps S3-S7 are replaced by the following steps:
S31、设计制作印刷电路板，根据载板焊锡位置及尺寸，设计并制作相同尺寸印刷钢网；在与晶元焊盘对应的载板焊盘印刷锡膏；S31, designing and manufacturing a printed circuit board, designing and fabricating the same size printed steel mesh according to the position and size of the carrier solder; printing the solder paste on the carrier pad corresponding to the wafer pad;
S41、在晶元对应的载板绿油表面位置涂覆非导电胶；S41, applying a non-conductive adhesive on a surface of the carrier green oil corresponding to the wafer;
S51、侧装粘贴双面电路晶元，晶元自上向下贴装过程中，使非导电胶充满晶元底部对应载板绿油区域，同时使晶元底部接触位置锡膏塌陷，使晶元侧面电路焊盘与锡膏接触，此时，锡膏与晶元焊盘处于接触但未结合状态；S51, side-mounted paste double-sided circuit wafer, the wafer is loaded from the top to the bottom, so that the non-conductive glue fills the green oil area corresponding to the bottom of the wafer, and the solder paste collapses at the bottom contact position of the wafer. The side surface circuit pad is in contact with the solder paste. At this time, the solder paste is in contact with the wafer pad but is not bonded;
S61、回流焊导通固化晶元与载板焊盘，回流焊过程在升温区及保温区使半固化锡膏熔化，锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合，至降温区锡料固化，回流焊接缝焊完成；S61, reflow soldering and curing the crystal cell and the carrier pad, the reflow process melts the semi-cured solder paste in the heating zone and the heat preservation zone, and the tin material is effectively passed through the intermetallic wettability and the carrier pad and the die pad. Combined, the tin material is solidified in the cooling zone, and the reflow solder joint is completed;
S71、烤箱烘烤固化非导电胶，使非导电胶固化，增强晶元与载板结合。S71, the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
进一步地，步骤S1中，所述晶元厚度在200um～300um之间。Further, in step S1, the thickness of the wafer is between 200 um and 300 um.
进一步地，步骤S1中，所述晶元的双面电路的非焊盘区域涂覆油性钝化层，所述晶元的底部无涂覆油性钝化层。Further, in step S1, the non-pad region of the double-sided circuit of the wafer is coated with an oily passivation layer, and the bottom of the wafer has no oil-coated passivation layer.
进一步地，在步骤S2中，设计并制作载板时，将晶元焊盘处的载板绿油做开窗处理，并露出载板与晶元对应焊盘。Further, in step S2, when the carrier is designed and fabricated, the carrier green oil at the wafer pad is fenestrated, and the carrier and the wafer corresponding pad are exposed.
进一步地，步骤S6中，所述搁置时间为3～10分钟。Further, in step S6, the set time is 3 to 10 minutes.
进一步地，在步骤S31中，所述印刷钢网厚度可选择60um、80um。Further, in step S31, the thickness of the printed steel mesh may be selected from 60 um and 80 um.
进一步地，所述锡膏包括锡银、锡银铜、锡铜，呈半固化形式。Further, the solder paste comprises tin silver, tin silver copper, tin copper, and is in a semi-cured form.
进一步地，烤箱烘烤固化导电胶或非导电胶，烘烤条件相同，温度为175度，时间包含升温、恒温、降温共2小时。Further, the oven bakes and cures the conductive adhesive or the non-conductive adhesive, and the baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature, and temperature drop for 2 hours.
本发明取得了以下有益效果：The present invention achieves the following beneficial effects:
解决双面电路晶元侧装时，双侧导电胶因毛细管效应通过晶元与载板接触位置相互爬胶导致的短路问题，从而可提高封装良率，降低不良损失；When solving the side-mounted of the double-sided circuit wafer, the double-sided conductive adhesive can be short-circuited by the mutual effect of the contact between the wafer and the carrier due to the capillary effect, thereby improving the package yield and reducing the loss;
使晶元与载板结合更加稳固，有效防止产品因内部或外部应力造成晶元与载板焊缝脱落，提升了封装成品元件的防应力损坏及可靠性。The combination of the wafer and the carrier plate is more stable, effectively preventing the product from falling off the weld of the wafer and the carrier due to internal or external stress, and improving the stress damage and reliability of the packaged component.
附图说明DRAWINGS
图1是本发明采用导电胶的方法流程示意图。1 is a schematic flow chart of a method for using a conductive paste according to the present invention.
图2是本发明采用锡膏的方法流程示意图。2 is a schematic flow chart of a method for using a solder paste of the present invention.
图3是本发明双面电路晶元侧装示意图。3 is a schematic side view of a double-sided circuit wafer of the present invention.
图4是通用晶元焊盘尺寸及间距示意图。4 is a schematic diagram of the size and spacing of a common die pad.
图5是双面电路晶元侧装之载板焊盘开窗示意图。Fig. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer.
图6是本发明双面电路晶元侧装之涂覆导电胶和涂覆非导电胶剖面图。Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention.
图7是本发明双面电路晶元侧装之印刷锡膏和涂覆非导电胶剖面图。Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention.
图8是本发明载板俯视图。Figure 8 is a plan view of the carrier of the present invention.
图9是本发明双面电路晶元侧装电路剖面图。Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention.
图10是本发明双面电路晶元侧装非电路面载板焊盘剖面图。Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention.
图11是本发明双面电路晶元侧装非电路面非载板焊盘剖面图。Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention.
具体实施方式detailed description
以下结合附图和实施例，对本发明的具体实施方式进行更加详细的说明，以便能够更好地理解本发明的方案及其各个方面的优涂覆。然而，以下描述的具体实施方式和实施例仅是说明的目的，而不是对本发明的限制。The embodiments of the present invention are described in more detail below with reference to the accompanying drawings and embodiments in order to provide a better understanding of the aspects of the invention and the various aspects thereof. However, the specific embodiments and examples described below are illustrative only and not limiting of the invention.
一种解决双面电路晶元焊料短路的载板制作及封装方法，如图1所示，图1是本发明采用导电胶的方法流程示意图。该方法包括以下步骤：A method for fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder is shown in FIG. 1. FIG. 1 is a schematic flow chart of a method for using a conductive paste according to the present invention. The method includes the following steps:
步骤S1，设计双面电路晶元，所述晶元厚度在200um～300um之间。In step S1, a double-sided circuit wafer is designed, and the thickness of the wafer is between 200 um and 300 um.
受限于当前封装侧装吸嘴大小，所述晶元的厚度≥200um最佳，受 限于晶元切割工艺，所述晶元的厚度≤300um最佳。随着技术提升，晶元切割工艺瓶颈或将拓宽，封装工艺也进一步加强，届时将更适合大面积晶元产品。Limited by the current package side-mounted nozzle size, the thickness of the wafer is preferably ≥200 um, which is limited by the wafer cutting process, and the thickness of the wafer is preferably ≤300 um. With the advancement of technology, the bottleneck of the wafer cutting process will be broadened, and the packaging process will be further strengthened, which will be more suitable for large-area wafer products.
晶元两侧表面非焊盘区域通常会涂覆一层油性钝化层，无钝化层的焊盘区域通常是露出金属铝或金成分；晶元底部因分隔划片晶粒使单晶硅或化合物基底暴露，此处没有涂覆油性钝化层，没有明显亲油或疏油特性。The non-pad regions on both sides of the wafer are usually coated with an oil-based passivation layer. The pad region without passivation layer is usually exposed with metallic aluminum or gold. The bottom of the wafer is separated by dicing die. Or the compound substrate is exposed, there is no oily passivation layer applied, and there is no significant lipophilic or oleophobic property.
步骤S2，根据双面电路晶元的厚度、焊盘分布及封装单元空间排布，设计并制作载板。In step S2, the carrier board is designed and fabricated according to the thickness of the double-sided circuit wafer, the pad distribution, and the space arrangement of the package unit.
如图5所示，图5是双面电路晶元侧装之载板焊盘开窗示意图。设计并制作载板时，将晶元焊盘处的载板绿油做开窗处理，并露出载板与晶元对应焊盘。As shown in FIG. 5, FIG. 5 is a schematic view showing the window opening of the carrier pad on the side of the double-sided circuit wafer. When designing and fabricating the carrier, the carrier green oil at the wafer pad is fenestrated, and the carrier and the corresponding pad of the wafer are exposed.
步骤S3，在晶元对应的载板绿油表面位置涂覆“一”字或“十”字非导电胶。In step S3, a "one" or "ten" non-conductive paste is applied on the surface of the carrier green oil corresponding to the wafer.
非导电胶有明显亲油性特征，涂覆胶后非导电胶会因其亲油性及毛细管效应，沿载板表面绿油缓慢扩散。The non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
涂覆非导电胶其作用一，隔离两侧导电胶，避免双面晶元两侧导电胶因毛细管效应沿晶元底部相互爬胶导致短路；涂覆非导电胶其作用二，固定侧装晶元，通过非导电胶将晶元底部与载板表面绿油结合固化。Applying non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
图6是本发明双面电路晶元侧装之涂覆导电胶和涂覆非导电胶剖面图。图8是本发明载板俯视图。由图6和图8可见，本发明的一个实施例，为了避免两侧位置的导电胶及焊盘发生短路，在载板中间大块的绿油表面位置涂覆的非导电胶，良好的隔离了两侧位置的导电胶及焊盘，避免了短路。并且使晶元和载板结合固化。Figure 6 is a cross-sectional view showing the coated conductive paste and the coated non-conductive paste on the side of the double-sided circuit wafer of the present invention. Figure 8 is a plan view of the carrier of the present invention. 6 and FIG. 8 , in one embodiment of the present invention, in order to avoid short circuit of the conductive paste and the pads on both sides, the non-conductive adhesive coated on the surface of the green oil in the middle of the carrier is well insulated. The conductive paste and pads on both sides avoid short circuits. And the wafer and the carrier are combined and cured.
图9是本发明双面电路晶元侧装电路剖面图。由图9可见，本发明的另一个实施例，为了避免相邻位置的导电胶及焊盘发生短路，在载板焊盘与焊盘的中间位置的小区域绿油表面位置涂覆的非导电胶，良好的隔离了相邻位置的导电胶及焊盘，避免了短路。并且使晶元和载板结合 固化。Figure 9 is a cross-sectional view showing a side-mounted circuit of a double-sided circuit wafer of the present invention. As can be seen from FIG. 9, in another embodiment of the present invention, in order to avoid short-circuiting of the conductive paste and the pads at adjacent positions, the non-conductive surface of the green oil is applied at a small area in the middle of the carrier pad and the pad. Glue, good isolation of conductive adhesive and pads in adjacent locations, avoiding short circuits. And the wafer and the carrier are combined and cured.
图10是本发明双面电路晶元侧装非电路面载板焊盘剖面图。图11是本发明双面电路晶元侧装非电路面非载板焊盘剖面图。如图10、图11可见，本发明的另一个实施例，为了避免晶元电路与载板电路之间发生短路，在晶元和载板解决的侧面绿油表面位置涂覆的非导电胶，良好的隔离了晶元电路和载板电路，避免了短路。并且使晶元和载板结合固化。Figure 10 is a cross-sectional view showing the pad of the double-sided circuit wafer side mounted non-circuit surface carrier of the present invention. Figure 11 is a cross-sectional view showing the non-circuit surface non-carrier pad of the double-sided circuit wafer side of the present invention. As shown in FIG. 10 and FIG. 11 , in another embodiment of the present invention, in order to avoid a short circuit between the crystal circuit and the carrier circuit, the non-conductive adhesive coated on the surface of the green oil surface solved by the wafer and the carrier is The transistor circuit and the carrier circuit are well isolated to avoid short circuits. And the wafer and the carrier are combined and cured.
步骤S4，在与晶元焊盘对应的载板焊盘涂覆导电胶。In step S4, the conductive paste is coated on the carrier pad corresponding to the wafer pad.
所述导电胶需满足稀释剂含量低、银粉含量高、粘稠度高的特性。导电胶成分中的银金属疏油，不易导流至晶元表面钝化层，但因含有稀释剂等液态有机亲油性成分，会使导电胶沿晶元底部基底裸露表面导流，导致载板相邻焊盘短路。The conductive adhesive needs to meet the characteristics of low diluent content, high silver powder content and high viscosity. Silver metal oleophobic in the conductive adhesive composition is not easy to conduct to the passivation layer on the surface of the wafer. However, due to the liquid organic lipophilic component such as diluent, the conductive paste will be guided along the exposed surface of the substrate at the bottom of the wafer, resulting in a carrier. The adjacent pads are shorted.
如图3所示，图3是本发明双面电路晶元侧装示意图。晶元焊盘和载板焊盘通过焊料即导电胶进行粘贴结合。晶元电路为双面设计。As shown in FIG. 3, FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention. The wafer pad and the carrier pad are bonded and bonded by solder, that is, conductive paste. The wafer circuit is designed on both sides.
如图4所示，图4是通用晶元焊盘尺寸及间距示意图。所述焊盘间距≥60um，焊盘长度≥50um。As shown in FIG. 4, FIG. 4 is a schematic diagram of the size and spacing of the general-purpose wafer pads. The pad pitch is ≥ 60 um, and the pad length is ≥ 50 um.
步骤S5，侧装粘贴双面电路晶元，晶元自上向下贴装过程中，晶元底部将先与非导电胶接触并向下挤压，使非导电胶充满晶元底部对应的载板绿油区域；晶元继续向下贴装，晶元侧面及侧面焊盘将与导电胶接触，因银金属疏油特性及与晶元焊盘表面金属铝或金的高润湿性，导电胶将快速与晶元焊盘结合。Step S5, the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer will be first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the bottom of the wafer. The green oil area of the plate; the wafer continues to be mounted downward, and the side and side pads of the wafer will be in contact with the conductive paste, which is conductive due to the oleophobic property of the silver metal and the high wettability of the metal aluminum or gold on the surface of the wafer pad. The glue will quickly bond to the wafer pads.
如图3所示，图3是本发明双面电路晶元侧装示意图。晶元焊盘和载板焊盘位置相对应，通过焊料即导电胶进行粘贴结合。As shown in FIG. 3, FIG. 3 is a schematic side view of a double-sided circuit wafer of the present invention. The wafer pad corresponds to the position of the carrier pad, and is bonded and bonded by solder, that is, conductive paste.
步骤S6，载板退出工作台搁置3到10分钟，此过程使导电胶与晶元焊盘充分接触。In step S6, the carrier board is left out of the table for 3 to 10 minutes, and the process brings the conductive paste into full contact with the wafer pad.
步骤S7，烤箱烘烤固化胶体，使非导电胶固化增强晶元与载板结合，使导电胶与载板焊盘及晶元焊盘固化。In step S7, the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
烤箱烘烤固化导电胶或非导电胶，烘烤条件相同，温度为175度，时间包含升温、恒温、降温共2小时。The oven bakes and cures the conductive adhesive or non-conductive adhesive. The baking conditions are the same, the temperature is 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.
步骤S8，外观检验，确认结合性。In step S8, the appearance inspection confirms the combination.
所述方法可以用锡膏来代替导电胶，如图2所示，图2是本发明采用锡膏的方法流程示意图。上述方法中的步骤S3-S7用如下步骤S31-S71来代替。The method can replace the conductive paste with a solder paste, as shown in FIG. 2, and FIG. 2 is a schematic flow chart of the method for using the solder paste of the present invention. Steps S3-S7 in the above method are replaced by the following steps S31-S71.
S31、设计制作印刷电路板，根据载板焊锡位置及尺寸，设计并制作相同尺寸印刷钢网。所述印刷钢网厚度可选择60um、80um；在与晶元焊盘对应的载板焊盘印刷锡膏。所述锡膏包括锡银、锡银铜、锡铜等。所述锡膏呈半固化形式，粘稠度高。S31. Design and manufacture a printed circuit board, and design and manufacture a printed steel mesh of the same size according to the position and size of the soldering of the carrier. The thickness of the printed steel mesh may be selected from 60 um and 80 um; and the solder paste is printed on the carrier pad corresponding to the wafer pad. The solder paste includes tin silver, tin silver copper, tin copper, and the like. The solder paste is in a semi-cured form and has a high viscosity.
S41、在晶元对应的载板绿油表面位置涂覆“一”字或“十”字非导电胶。S41, applying a "one" word or a "ten" word non-conductive glue on the surface of the carrier green oil corresponding to the wafer.
非导电胶有明显亲油性特征，涂覆胶后非导电胶会因其亲油性及毛细管效应，沿载板表面绿油缓慢扩散。The non-conductive glue has obvious lipophilic characteristics. After the glue is applied, the non-conductive glue will slowly diffuse along the surface of the carrier plate due to its lipophilicity and capillary effect.
涂覆非导电胶其作用一，隔离两侧导电胶，避免双面晶元两侧导电胶因毛细管效应沿晶元底部相互爬胶导致短路；涂覆非导电胶其作用二，固定侧装晶元，通过非导电胶将晶元底部与载板表面绿油结合固化。Applying non-conductive glue to its role, isolating the conductive adhesive on both sides, avoiding the short-circuiting of the conductive adhesive on both sides of the double-sided wafer due to the capillary effect along the bottom of the wafer, causing a short circuit; coating the non-conductive adhesive to act as a second, fixing the side-mounted crystal Yuan, the bottom of the wafer is combined with the green oil on the surface of the carrier by a non-conductive glue.
图7是本发明双面电路晶元侧装之印刷锡膏和涂覆非导电胶剖面图。如图7可见，本发明的一个实施例，为了避免两侧位置的锡膏及焊盘发生短路，在载板中间大块的绿油表面位置涂覆的非导电胶，良好的隔离了两侧位置的锡膏及焊盘，避免了短路。并且使晶元和载板结合固化。Figure 7 is a cross-sectional view showing a printed solder paste and a non-conductive paste coated on the side of a double-sided circuit wafer of the present invention. As can be seen from FIG. 7, in one embodiment of the present invention, in order to avoid short circuit of the solder paste and the pads on both sides, the non-conductive adhesive applied on the surface of the green oil in the middle of the carrier is well insulated. Place the solder paste and pads to avoid short circuits. And the wafer and the carrier are combined and cured.
S51、侧装粘贴双面电路晶元，晶元自上向下贴装过程中，因锡膏电路板厚度不同选择，晶元底部将可能先与非导电胶接触，也可能先与锡膏接触，晶元继续向下贴装挤压，使非导电胶充满晶元底部对应载板绿油区域，同时使晶元底部接触位置锡膏塌陷，使晶元侧面线路焊盘与锡膏接触，此时，锡膏与晶元焊盘处于接触但未结合状态。S51, side-mounted paste double-sided circuit die, in the process of wafer top-down mounting, depending on the thickness of the solder paste circuit board, the bottom of the wafer may be in contact with the non-conductive glue first, or may be in contact with the solder paste first. The wafer continues to be pressed down to make the non-conductive glue fill the green oil region corresponding to the bottom of the wafer, and at the same time, the solder paste at the bottom contact position of the wafer collapses, so that the side wiring pads of the wafer are in contact with the solder paste. The solder paste is in contact with the die pad but is not bonded.
S61、回流焊导通固化晶元与载板焊盘，考虑到若先进行烤箱加热固化非导电胶，会导致晶元焊盘及锡膏在烤箱加热过程被氧化，需先进性锡膏的回流焊接流程，回流焊过程在升温区及保温区使半固化锡膏熔化，锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合，至降温区锡料固化，回流焊接缝焊完成。S61, reflow soldering and curing wafer and carrier pad, considering that if the oven is heated and cured, the non-conductive paste will cause the wafer pad and solder paste to be oxidized during the heating process of the oven, requiring advanced solder paste reflow. In the welding process, the reflow soldering process melts the semi-cured solder paste in the heating zone and the holding zone. The tin material is effectively combined with the carrier pad and the die pad by the intermetallic wettability, and the tin material is solidified in the cooling zone, and the reflow solder joint is formed. The welding is completed.
S71、烤箱烘烤固化非导电胶，使非导电胶固化，增强晶元与载板结合，非导电胶烘烤条件通常温度通常为175度，时间包含升温、恒温、降温共2小时。S71, the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier. The baking condition of the non-conductive glue is usually 175 degrees, and the time includes temperature rise, constant temperature and temperature drop for 2 hours.
S8、外观检验，确认结合性。S8. Appearance inspection, confirming the combination.
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本发明而非限制本发明的范围，本领域的普通技术人员应当理解，在不脱离本发明的精神和范围的前提下对本发明进行的修改或者等同替换，均应涵盖在本发明的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。It should be noted that the various embodiments described above with reference to the accompanying drawings are only to illustrate the invention and not to limit the scope of the invention, and those of ordinary skill in the art should understand that without departing from the spirit and scope of the invention Modifications or equivalents to the invention are intended to be included within the scope of the invention. In addition, unless the context indicates otherwise, words in the singular include plural and vice versa. In addition, all or a portion of any embodiment can be used in combination with all or a portion of any other embodiment, unless otherwise stated.

Claims (10)

  1. 一种解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，该方法包括以下步骤：A carrier board fabrication and packaging method for solving a short circuit of a double-sided circuit wafer solder, characterized in that the method comprises the following steps:
    步骤S1，设计双面电路晶元；Step S1, designing a double-sided circuit wafer;
    步骤S2，根据双面电路晶元的厚度、焊盘分布及封装单元空间排布，设计并制作载板；Step S2, designing and fabricating a carrier according to the thickness of the double-sided circuit wafer, the pad distribution, and the spatial arrangement of the package unit;
    步骤S3，在晶元对应的载板绿油表面位置涂覆非导电胶；Step S3, applying a non-conductive adhesive on the surface of the carrier green oil corresponding to the wafer;
    步骤S4，在与晶元焊盘对应的载板焊盘涂覆导电胶；Step S4, coating a conductive paste on the carrier pad corresponding to the wafer pad;
    步骤S5，侧装粘贴双面电路晶元，晶元自上向下贴装过程中，晶元底部先与非导电胶接触并向下挤压，使非导电胶充满晶元底部对应的载板绿油区域；晶元继续向下贴装，晶元侧面及侧面焊盘与导电胶接触，使导电胶快速与晶元焊盘结合；Step S5, the side-mounted paste double-sided circuit wafer, in the process of the wafer from the top to the bottom, the bottom of the wafer is first contacted with the non-conductive glue and pressed downward, so that the non-conductive glue fills the corresponding carrier on the bottom of the wafer. The green oil area; the wafer continues to be mounted downward, and the side and side pads of the wafer are in contact with the conductive paste, so that the conductive paste is quickly combined with the wafer pad;
    步骤S6，载板退出工作台搁置一段时间；Step S6, the carrier board exits the workbench for a period of time;
    步骤S7，烤箱烘烤固化胶体，使非导电胶固化增强晶元与载板结合，使导电胶与载板焊盘及晶元焊盘固化。In step S7, the oven is baked to cure the colloid, so that the non-conductive adhesive cures the crystal unit to bond with the carrier, and the conductive paste and the carrier pad and the wafer pad are cured.
  2. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，所述方法还包括步骤S8，外观检验，确认结合性。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein the method further comprises the step S8, visual inspection, and confirming the bonding property.
  3. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，所述方法可以用锡膏来代替导电胶，其中步骤S3-S7用如下步骤来代替：The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein the method can replace the conductive paste with a solder paste, wherein the steps S3-S7 are replaced by the following steps:
    S31、设计制作印刷电路板，根据载板焊锡位置及尺寸，设计并制作相同尺寸印刷钢网；在与晶元焊盘对应的载板焊盘印刷锡膏；S31, designing and manufacturing a printed circuit board, designing and fabricating the same size printed steel mesh according to the position and size of the carrier solder; printing the solder paste on the carrier pad corresponding to the wafer pad;
    S41、在晶元对应的载板绿油表面位置涂覆非导电胶；S41, applying a non-conductive adhesive on a surface of the carrier green oil corresponding to the wafer;
    S51、侧装粘贴双面电路晶元，晶元自上向下贴装过程中，使非导电胶充满晶元底部对应载板绿油区域，同时使晶元底部接触位置锡膏塌陷，使晶元侧面电路焊盘与锡膏接触，此时，锡膏与晶元焊盘处于接触但未结合状态；S51, side-mounted paste double-sided circuit wafer, the wafer is loaded from the top to the bottom, so that the non-conductive glue fills the green oil area corresponding to the bottom of the wafer, and the solder paste collapses at the bottom contact position of the wafer. The side surface circuit pad is in contact with the solder paste. At this time, the solder paste is in contact with the wafer pad but is not bonded;
    S61、回流焊导通固化晶元与载板焊盘，回流焊过程在升温区及保温区使半固化锡膏熔化，锡料通过金属间润湿性与载板焊盘及晶元焊盘有效结合，至降温区锡料固化，回流焊接缝焊完成；S61, reflow soldering and curing the crystal cell and the carrier pad, the reflow process melts the semi-cured solder paste in the heating zone and the heat preservation zone, and the tin material is effectively passed through the intermetallic wettability and the carrier pad and the die pad. Combined, the tin material is solidified in the cooling zone, and the reflow solder joint is completed;
    S71、烤箱烘烤固化非导电胶，使非导电胶固化，增强晶元与载板结合。S71, the oven bakes and solidifies the non-conductive glue to solidify the non-conductive glue, and enhances the combination of the wafer and the carrier.
  4. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，步骤S1中，所述晶元厚度在200um～300um之间。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein in the step S1, the thickness of the wafer is between 200 um and 300 um.
  5. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，步骤S1中，所述晶元的双面电路的非焊盘区域涂覆油性钝化层，所述晶元的底部无涂覆油性钝化层。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein in step S1, the non-pad region of the double-sided circuit of the wafer is coated with an oil-based passivation layer The bottom of the wafer has no oil-coated passivation layer.
  6. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，在步骤S2中，设计并制作载板时，将晶元焊盘处的载板绿油做开窗处理，并露出载板与晶元对应焊盘。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein in the step S2, when the carrier is designed and fabricated, the carrier green material at the wafer pad is used. Do the windowing process and expose the pads corresponding to the carrier and the wafer.
  7. 根据权利要求1所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，步骤S6中，所述搁置时间为3～10分钟。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1, wherein in the step S6, the leaving time is 3 to 10 minutes.
  8. 根据权利要求3所述的解决双面电路晶元焊料短路的载板制作 及封装方法，其特征在于，在步骤S31中，所述印刷钢网厚度可选择60um、80um。The method of fabricating and packaging a carrier for solving a short-circuit of a double-sided circuit wafer solder according to claim 3, wherein in step S31, the thickness of the printed steel mesh is 60 μm or 80 μm.
  9. 根据权利要求3所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，所述锡膏包括锡银、锡银铜、锡铜，呈半固化形式。The method of fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 3, wherein the solder paste comprises tin silver, tin silver copper, tin copper, and is in a semi-cured form.
  10. 根据权利要求1或3所述的解决双面电路晶元焊料短路的载板制作及封装方法，其特征在于，烤箱烘烤固化导电胶或非导电胶，烘烤条件相同，温度为175度，时间包含升温、恒温、降温共2小时。The method for fabricating and packaging a carrier for solving a short circuit of a double-sided circuit wafer solder according to claim 1 or 3, wherein the oven is baked and cured with a conductive adhesive or a non-conductive adhesive, and the baking condition is the same, and the temperature is 175 degrees. The time includes heating, constant temperature, and cooling for 2 hours.
PCT/CN2018/104481 2018-03-22 2018-09-07 Method for manufacturing and packaging carrier capable of preventing short circuit caused by solder of two surface circuit die WO2019179062A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810241152.9 2018-03-22
CN201810241152.9A CN108493121B (en) 2018-03-22 2018-03-22 A kind of support plate production and packaging method solving double-sided circuit wafer short-circuited with solder

Publications (1)

Publication Number Publication Date
WO2019179062A1 true WO2019179062A1 (en) 2019-09-26

Family

ID=63319310

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/104481 WO2019179062A1 (en) 2018-03-22 2018-09-07 Method for manufacturing and packaging carrier capable of preventing short circuit caused by solder of two surface circuit die

Country Status (2)

Country Link
CN (1) CN108493121B (en)
WO (1) WO2019179062A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314539A (en) * 2023-03-31 2023-06-23 广东省旭晟半导体股份有限公司 Packaging structure with enhanced LED reliability and preparation process thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493121B (en) * 2018-03-22 2019-09-20 上海飞骧电子科技有限公司 A kind of support plate production and packaging method solving double-sided circuit wafer short-circuited with solder
CN109650323B (en) * 2018-12-24 2020-11-03 烟台艾睿光电科技有限公司 Solder isolation structure and electronic device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198463A (en) * 2000-12-26 2002-07-12 Canon Inc Chip size package and its manufacturing method
CN103311205A (en) * 2013-05-16 2013-09-18 华天科技（西安）有限公司 Encapsulating piece for preventing chip salient point from being short-circuited and manufacturing process thereof
CN103545303A (en) * 2012-07-17 2014-01-29 马维尔国际贸易有限公司 IC package and assembly
CN103582302A (en) * 2012-07-25 2014-02-12 纬创资通股份有限公司 Printed circuit board and method for manufacturing printed circuit board
CN104486907A (en) * 2014-12-10 2015-04-01 华进半导体封装先导技术研发中心有限公司 Three-dimensional integrated wafer-level package structure and package method for high-frequency IPD (Integrated Passive Device) module
CN108493121A (en) * 2018-03-22 2018-09-04 上海飞骧电子科技有限公司 It is a kind of solve double-sided circuit wafer short-circuited with solder support plate make and packaging method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002198463A (en) * 2000-12-26 2002-07-12 Canon Inc Chip size package and its manufacturing method
CN103545303A (en) * 2012-07-17 2014-01-29 马维尔国际贸易有限公司 IC package and assembly
CN103582302A (en) * 2012-07-25 2014-02-12 纬创资通股份有限公司 Printed circuit board and method for manufacturing printed circuit board
CN103311205A (en) * 2013-05-16 2013-09-18 华天科技（西安）有限公司 Encapsulating piece for preventing chip salient point from being short-circuited and manufacturing process thereof
CN104486907A (en) * 2014-12-10 2015-04-01 华进半导体封装先导技术研发中心有限公司 Three-dimensional integrated wafer-level package structure and package method for high-frequency IPD (Integrated Passive Device) module
CN108493121A (en) * 2018-03-22 2018-09-04 上海飞骧电子科技有限公司 It is a kind of solve double-sided circuit wafer short-circuited with solder support plate make and packaging method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116314539A (en) * 2023-03-31 2023-06-23 广东省旭晟半导体股份有限公司 Packaging structure with enhanced LED reliability and preparation process thereof
CN116314539B (en) * 2023-03-31 2023-11-21 广东省旭晟半导体股份有限公司 Packaging structure with enhanced LED reliability and preparation process thereof

Also Published As

Publication number Publication date
CN108493121B (en) 2019-09-20
CN108493121A (en) 2018-09-04

Similar Documents

Publication Publication Date Title
TWI241675B (en) Chip carrier for semiconductor chip
US6774497B1 (en) Flip-chip assembly with thin underfill and thick solder mask
US6550666B2 (en) Method for forming a flip chip on leadframe semiconductor package
TWI295500B (en)
TWI485817B (en) Microelectronic packages with enhanced heat dissipation and methods of manufacturing
US8222748B2 (en) Packaged electronic devices having die attach regions with selective thin dielectric layer
WO2019179062A1 (en) Method for manufacturing and packaging carrier capable of preventing short circuit caused by solder of two surface circuit die
JP2023165871A (en) Method for manufacturing electronic component device and electronic component device
US20100105173A1 (en) Method of producing semiconductor device provided with flip-chip mounted semiconductor element
US9508594B2 (en) Fabricating pillar solder bump
US20170053854A1 (en) Packaged Device with Additive Substrate Surface Modification
TWI532133B (en) Lead-free structures in a semiconductor device
US20070269930A1 (en) Methodology to control underfill fillet size, flow-out and bleed in flip chips (FC), chip scale packages (CSP) and ball grid arrays (BGA)
KR101530528B1 (en) Production method for solder transfer base matrerial, solder precoating method, and solder transfer base material
US11742310B2 (en) Method of manufacturing semiconductor device
CN111128912A (en) Packaging structure and preparation method thereof
US8987055B2 (en) Method for packaging low-K chip
US20130277828A1 (en) Methods and Apparatus for bump-on-trace Chip Packaging
US20220122940A1 (en) Semiconductor device assembly with pre-reflowed solder
CN112271170A (en) Packaging substrate, flip chip packaging structure and manufacturing method thereof
TWM500997U (en) LED flip-chip packaging structure
CN101000899A (en) Chip package structure
TWI569386B (en) Structure and method
TWI508243B (en) A package structure and the method to manufacture thereof
JP4246095B2 (en) Semiconductor package mounting structure and semiconductor package mounting method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18910693

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25/01/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18910693

Country of ref document: EP

Kind code of ref document: A1