WO2019176833A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2019176833A1
WO2019176833A1 PCT/JP2019/009605 JP2019009605W WO2019176833A1 WO 2019176833 A1 WO2019176833 A1 WO 2019176833A1 JP 2019009605 W JP2019009605 W JP 2019009605W WO 2019176833 A1 WO2019176833 A1 WO 2019176833A1
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WO
WIPO (PCT)
Prior art keywords
layer
electrode
semiconductor device
protective layer
film
Prior art date
Application number
PCT/JP2019/009605
Other languages
English (en)
Japanese (ja)
Inventor
岡本　浩一郎
宗弘 多田
直樹 伴野
井口　憲幸
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Publication of WO2019176833A1 publication Critical patent/WO2019176833A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

Afin de supprimer l'absorption d'humidité dans une couche à résistance variable incluse dans un élément à résistance variable et de réduire les variations de la tension de consigne, la présente invention concerne un dispositif à semi-conducteur comprenant : une première électrode ; une première couche d'isolation qui est disposée sur la première électrode et qui a au moins une ouverture ; une couche à résistance variable qui est disposée sur la première couche d'isolation et qui est reliée à la première électrode au niveau d'une partie à l'intérieur de l'ouverture ; une seconde électrode disposée sur la couche à résistance variable ; une première couche de protection qui recouvre les surfaces latérales de la couche à résistance variable ; et une seconde couche de protection qui recouvre la première couche de protection.
PCT/JP2019/009605 2018-03-13 2019-03-11 Dispositif à semi-conducteur et son procédé de fabrication WO2019176833A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018044852 2018-03-13
JP2018-044852 2018-03-13

Publications (1)

Publication Number Publication Date
WO2019176833A1 true WO2019176833A1 (fr) 2019-09-19

Family

ID=67908214

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/009605 WO2019176833A1 (fr) 2018-03-13 2019-03-11 Dispositif à semi-conducteur et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2019176833A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021750A (ja) * 2006-07-11 2008-01-31 Matsushita Electric Ind Co Ltd 抵抗変化素子およびその製造方法、ならびにそれを用いた抵抗変化型メモリ
JP2012195530A (ja) * 2011-03-18 2012-10-11 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
WO2014030393A1 (fr) * 2012-08-20 2014-02-27 日本電気株式会社 Élément de changement de résistance, et procédé pour fabriquer un élément de changement de résistance
JP2016192510A (ja) * 2015-03-31 2016-11-10 日本電気株式会社 抵抗変化素子およびその形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021750A (ja) * 2006-07-11 2008-01-31 Matsushita Electric Ind Co Ltd 抵抗変化素子およびその製造方法、ならびにそれを用いた抵抗変化型メモリ
JP2012195530A (ja) * 2011-03-18 2012-10-11 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
WO2014030393A1 (fr) * 2012-08-20 2014-02-27 日本電気株式会社 Élément de changement de résistance, et procédé pour fabriquer un élément de changement de résistance
JP2016192510A (ja) * 2015-03-31 2016-11-10 日本電気株式会社 抵抗変化素子およびその形成方法

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