WO2019176833A1

WO2019176833A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2019176833A1
Application number: PCT/JP2019/009605
Authority: WO
Inventors: 岡本　浩一郎; 宗弘多田; 直樹伴野; 井口　憲幸
Original assignee: 日本電気株式会社
Priority date: 2018-03-13
Filing date: 2019-03-11
Publication date: 2019-09-19

Abstract

In order to suppress moisture absorption in a variable resistance layer included in a variable resistance element and to reduce variations in set voltage, this semiconductor device is provided with: a first electrode; a first insulation layer which is disposed on the first electrode and which has at least one opening; a variable resistance layer which is disposed on the first insulation layer and which is connected to the first electrode at a portion inside the opening; a second electrode disposed on the variable resistance layer; a first protection layer which covers lateral surfaces of the variable resistance layer; and a second protection layer which covers the first protection layer.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device including a resistance change element and a manufacturing method thereof.

Semiconductor devices have been integrated and reduced in power by miniaturization. In particular, silicon devices have been developed at a pace where the integration degree is quadrupled in three years so as to follow the scaling law (Moore's law). Along with this, the gate length of MOSFET (Metal Oxide Semiconductor Semiconductor Field Field Effect Transistor) has become 20 nanometers or less. As a result, the price of the apparatus and mask set used in the lithography process has soared, and the operation and variation of device dimensions have reached physical limits. Therefore, improvement of device performance by an approach different from the conventional scaling law is required.

A device called FPGA (Field Programmable Gate Array) has been developed as an intermediate position between the gate array and the standard cell. In the FPGA, the customer himself can perform an arbitrary circuit configuration on the manufactured chip. In the programmable element included in the FPGA, a variable resistance nonvolatile element (also referred to as a variable resistance element) or the like is interposed in the connection portion of the wiring, so that the customer himself can set the electrical connection of the desired wiring. If FPGA is used, the freedom degree of a circuit can be improved.

Resistance change element is a general term for elements that store information according to a change in resistance state. A resistance change element used in an FPGA has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and changes the resistance state of the resistance change layer by applying a voltage between both electrodes. be able to. For example, as the resistance change element, there are a ReRAM (Resistive Random Access Memory) using a metal oxide as a resistance change layer, a solid electrolyte switch element using a solid electrolyte, and the like. Non-Patent Document 1 and Non-Patent Document 2 disclose a resistance change phenomenon using a chalcogenide compound as a solid electrolyte material.

Patent Document 1 discloses an example of a memory element using a solid electrolyte. The memory element of Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a lower electrode and an upper electrode. When the configuration of the memory element of Patent Document 1 is compared with the configuration of the solid electrolyte switch element described above, the resistance change layer corresponds to a solid electrolyte layer, and the ion source layer corresponds to an electrode that supplies metal ions. The memory element of Patent Document 1 has a configuration in which the upper and lower structures of the above solid electrolyte switch element are reversed.

Patent Document 2 and Patent Document 3 disclose a two-terminal solid electrolyte switch element provided in a copper multilayer wiring structure on a CMOS substrate and a method for manufacturing the same. In the methods of Patent Document 2 and Patent Document 3, a two-terminal type solid electrolyte switch element in which an active electrode is a copper wiring itself exposed by opening a part of an insulating layer in a copper multilayer wiring structure on a CMOS substrate. Is made.

In application of a solid electrolyte switch element to a nonvolatile memory and a nonvolatile switch, it is required to suppress variations in characteristics among a large number of solid electrolyte switch elements. For example, in the voltage (set voltage) necessary for setting the solid electrolyte switch element, the set yield when the program voltage is applied can be improved as the variation between the elements is smaller.

When using a copper electrode as a lower electrode when manufacturing a solid electrolyte switch element, if the surface of the copper electrode is oxidized, the variation in leakage current in the off state increases. When the surface of the copper electrode is oxidized and the variation in leakage current in the off state increases, the dielectric breakdown voltage at the time of reset decreases.

In Non-Patent Document 3, in the stacking of solid electrolyte switch elements, in order to prevent oxidation of the copper surface, the free energy of oxidation is negatively larger than copper between copper as the lower electrode and the solid electrolyte layer. A method of depositing metal as a valve metal is disclosed. According to the method of Non-Patent Document 3, the element can be provided with a buffer structure in which oxidation of copper is suppressed by oxidizing the valve metal.

In Patent Document 3, in the process of manufacturing a solid electrolyte switch element, after the switch element laminated structure is etched, the surface of copper is covered with a protective film such as silicon nitride (SiN) having a high chemical barrier property. Techniques to do this are disclosed.

JP 2011-187925 A International Publication No. 2010/0779816 JP 2011-091317 A

In the manufacturing process of a solid electrolyte switch element in a general copper multilayer wiring layer, the side surfaces of the upper electrode and the solid electrolyte layer are exposed when the laminated structure is etched. At that time, there is a problem that deterioration due to moisture absorption from the exposed side surface to the solid electrolyte layer occurs, and variation in device operation increases.

According to the technique of Patent Document 3, moisture absorption to the resistance change layer can be suppressed by coating the laminated structure with a protective insulating film having a chemically high barrier property such as SiN. However, the technique of Patent Document 3 has a problem that it takes time until the side wall of the resistance change layer is exposed by etching and is covered with the protective insulating film.

An object of the present invention is to provide a semiconductor device in which moisture absorption to a resistance change layer included in a resistance change element is suppressed and variation in set voltage is suppressed in order to solve the above-described problem.

A semiconductor device of one embodiment of the present invention includes a first electrode, a first insulating layer that is disposed on the first electrode and has at least one opening formed thereon, and is disposed on the first insulating layer and has an opening. A variable resistance layer connected to the first electrode in the inside of the unit; a second electrode disposed on the variable resistance layer; a first protective layer covering a side surface of the variable resistance layer; and a first protective layer A second protective layer.

In the semiconductor device manufacturing method of one embodiment of the present invention, the first electrode is formed on the substrate, the first insulating layer is formed on the upper surface of the first electrode, and the opening exposing a part of the upper surface of the first electrode Is formed on the first insulating layer, the buffer layer is formed on the upper surface of the first insulating layer including the inside of the opening, the solid electrolyte layer is formed on the upper surface of the buffer layer, and the second layer is formed on the upper surface of the solid electrolyte layer. The electrode is formed, at least one patterning mask is formed on the upper surface of the upper electrode, and the second electrode, the solid electrolyte layer, and the buffer layer are sequentially etched, and at the same time, the patterning mask, the buffer layer, and the solid electrolyte are etched. The first protective layer is formed on at least the exposed surfaces of the solid electrolyte layer and the buffer layer among the exposed surfaces formed on the layer and the second electrode, and the second protective layer is formed on the surface of the first protective layer.

According to the present invention, it is possible to provide a semiconductor device in which moisture absorption to the variable resistance layer included in the variable resistance element is suppressed and variation in set voltage is suppressed.

It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device concerning a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device of modification 1 concerning a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device of modification 2 concerning a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device of modification 3 concerning a 1st embodiment of the present invention. It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process A1 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process A2 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process A3 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process A4 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process A5 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B1 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B2 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B3 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B4 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B5 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process B6 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process C1 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process C2 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process C3 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view for explaining process C4 included in the manufacturing method of the semiconductor device concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view showing an example of 1 composition of a semiconductor device concerning a 3rd embodiment of the present invention.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, the preferred embodiments described below are technically preferable for carrying out the present invention, but the scope of the invention is not limited to the following. In addition, in all the drawings used for description of the following embodiments, the same reference numerals are given to the same parts unless there is a particular reason. In the following embodiments, repeated description of similar configurations and operations may be omitted. Moreover, in all the drawings used for description of the following embodiments, there are places where hatching is performed to show a cross section, but there are also places where hatching is omitted.

(First embodiment)
First, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view showing a configuration example of the semiconductor device 1 of the present embodiment. As shown in FIG. 1, the semiconductor device 1 includes a lower electrode 11, an upper electrode 12, a resistance change layer 13, an insulating barrier layer 14, a first protective layer 15, and a second protective layer 16. Lower electrode 11, upper electrode 12, and resistance change layer 13 constitute resistance change element 10. The resistance change layer 13 includes a solid electrolyte layer 131 and a buffer layer 132. Further, the first protective layer 15 and the second protective layer 16 are collectively referred to as a protective layer.

The resistance change element 10 is a kind of solid electrolyte switch element, and has a structure in which a solid electrolyte layer (resistance change layer 13) is sandwiched between two electrodes (lower electrode 11 and upper electrode 12). One of the two electrodes (lower electrode 11) is made of a metal that is chemically active and can be easily oxidized and reduced by voltage application. A chemically inert metal material is used for the other (upper electrode 12) of the two electrodes.

The lower electrode 11 (also referred to as a first electrode) is one of the two electrodes of the resistance change element 10. The lower electrode 11 is an active electrode. For example, the lower electrode 11 is preferably composed of a material containing Cu. For example, the lower electrode 11 may also serve as a wiring on the semiconductor substrate. When the lower electrode 11 also serves as a wiring on the semiconductor substrate, the process of manufacturing the resistance change element 10 on the semiconductor substrate can be simplified.

For example, the semiconductor substrate includes a substrate on which a semiconductor element including a MOS (Metal Oxide Semiconductor) transistor and a resistance element, and a semiconductor device in which these semiconductor elements are combined is configured. Further, as the semiconductor substrate, a substrate such as a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, or a liquid crystal manufacturing substrate may be used.

The upper electrode 12 (also referred to as a second electrode) is the other of the two electrodes of the resistance change element 10. The upper electrode 12 is an inert electrode. The upper electrode 12 is provided on the resistance change layer 13.

For example, the upper electrode 12 is preferably made of a material containing at least one of iridium Ir, palladium Pd, platinum Pt, ruthenium Ru, tantalum Ta, and titanium Ti. The upper electrode 12 may be composed of two or more metal layers made of different materials. When the upper electrode 12 is composed of two or more metal layers, the metal layer in contact with the solid electrolyte layer 131 is composed of a metal layer containing at least one of Ir, Pd, Pt, Ru, Ta, and Ti. It is preferable.

The resistance change layer 13 is provided between the lower electrode 11 and the upper electrode 12. The resistance change layer 13 has a structure in which a solid electrolyte layer 131 and a buffer layer 132 are stacked.

The solid electrolyte layer 131 is in contact with the upper electrode 12. The solid electrolyte layer 131 is a material containing at least one of tantalum Ta, nickel Ni, titanium Ti, zirconium Zr, hafnium Hf, silicon Si, aluminum Al, iron Fe, vanadium V, manganese Mn, cobalt Co, and tungsten W. Can be configured. For the solid electrolyte layer 131, a metal oxide film containing these elements, a carbon-doped silicon oxide film (SiOCH film), a chalcogenide film, or a laminated film thereof can be applied. For example, as the solid electrolyte layer 131, a 7-nm-thick SiOCH film can be applied.

The buffer layer 132 is in contact with the lower electrode 11. The buffer layer 132 is preferably made of a material made of an oxide containing at least one of a metal having a negative free energy of oxidation larger than that of Cu or a nonmetal belonging to a Group 14 element. More preferably, the buffer layer 132 is preferably made of an oxide containing at least one of aluminum Al, hafnium Hf, niobium Nb, silicon Si, tantalum Ta, titanium Ti, and zirconium Zr. These oxides can be stably formed without causing an interface reaction with the solid electrolyte layer 131, the lower electrode 11, and the upper electrode 12, and moisture absorption of the solid electrolyte layer 131 can be effectively suppressed. In addition, these oxides have good compatibility with general semiconductor manufacturing processes.

When the resistance change element 10 is in the off state (high resistance state), if the lower electrode 11 is grounded and a negative voltage is applied to the upper electrode 12, the metal atoms constituting the lower electrode 11 are ionized to form the resistance change layer 13. A metal bridge eluting into and having conductivity is formed between the electrodes. When both electrodes are electrically connected by the metal bridge formed in the resistance change layer 13, the resistance change element 10 is turned on (low resistance state). In this way, an operation of changing from an off state to an on state by voltage application is referred to as a set.

On the other hand, when the variable resistance element 10 is in the on state (low resistance state), when the lower electrode 11 is grounded and a positive voltage is applied to the upper electrode 12, the metal bridge that bridges between the two electrodes dissolves and the metal atoms are dissolved. It is pulled back to the lower electrode 11. As a result, both electrodes are electrically insulated, and the variable resistance element 10 changes to an off state (high resistance state). In this manner, an operation of changing from an on state to an off state by applying a positive voltage is referred to as reset. The set and reset are collectively called programming.

As described above, in the solid electrolyte switch element including the resistance change element 10, it is nonvolatile between the on state and the off state and can be repeatedly programmed. By utilizing this characteristic, the solid electrolyte switch element can be applied to a nonvolatile memory or a nonvolatile switch.

The insulating barrier layer 14 (also referred to as a first insulating layer) is formed on the lower electrode 11. At least one opening 140 is formed in a part of the insulating barrier layer 14. The surface of the lower electrode 11 exposed in the opening 140 is in contact with the buffer layer 132 of the resistance change layer 13 through the opening 140. When the surface of the lower electrode 11 exposed at the bottom of the opening 140 is in contact with the buffer layer 132 of the resistance change layer 13 through the opening 140, affinity for a general semiconductor manufacturing process can be improved.

For example, the insulating barrier layer 14 is formed on the upper surface of the Cu wiring. The insulating barrier layer 14 has a function of preventing Cu oxidation and diffusion of Cu into the insulating film, and a function as an etching stopper layer during processing. For example, a silicon carbide film (SiC film), a silicon nitride carbide film (SiCN film), a silicon nitride film (SiN film), a laminated film of these films, or the like is used for the insulating barrier layer 14.

The first protective layer 15 covers at least a part of the side surface of the resistance change layer 13 and the side surface of the upper electrode 12. At least a part of the first protective layer 15 is covered with the second protective layer 16. The first protective layer 15 serves to protect the side portions exposed during the processes of the resistance change layer 13 and the upper electrode 12. For example, the first protective layer 15 covers the entire side of the variable resistance layer 13 and the entire side of the upper electrode 12. For example, the first protective layer 15 covers the entire side of the variable resistance layer 13 and a part of the side of the upper electrode 12. For example, the first protective layer 15 covers a part of the side of the resistance change layer 13 and a part of the side of the upper electrode 12.

The first protective layer 15 is made of a material having higher chemical stability than the material constituting the resistance change layer 13 and the upper electrode 12. Similar to the buffer layer 132, the first protective layer 15 is made of a material made of an oxide containing at least one of a metal having a negative free energy of oxidation larger than that of Cu or a nonmetal belonging to the Group 14 element. It is preferable. More preferably, the first protective layer 15 is preferably made of an oxide containing at least one of Al, Hf, Nb, Si, Ta, Ti, and Zr. These oxides can be stably formed without causing an interface reaction with the solid electrolyte layer 131, the lower electrode 11, and the upper electrode 12, and moisture absorption of the solid electrolyte layer 131 can be effectively suppressed. In addition, these oxides have good compatibility with general semiconductor manufacturing processes.

The first protective layer 15 is preferably made of the same material as the buffer layer 132. With such a material structure, the first protective layer 15 can be formed by being in close contact with the exposed side walls of the solid electrolyte layer 131, the buffer layer 132, and the upper electrode 12 at the same time as the buffer layer 132 is etched. As a result, it is possible to efficiently suppress the processing moisture absorption of the sidewalls of the buffer layer 132, the solid electrolyte layer 131, and the upper electrode 12 that are exposed when the buffer layer 132 is etched. Further, if the first protective layer 15 and the buffer layer 132 are made of the same material, the adhesive property with the upper electrode 12 is ensured while maintaining the operation characteristics as the variable resistance element 10, and the solid electrolyte layer 131. Can be more effectively suppressed.

In addition, one end of the first protective layer 15 is preferably in contact with the side surface of the buffer layer 132. By bringing the first protective layer 15 and the buffer layer 132 into contact with each other and closing the gap between the side surface of the buffer layer 132 and the first protective layer 15, moisture absorption to the solid electrolyte layer 131 can be further reduced.

Further, by forming a double structure in which the second protective layer 16 is deposited on the first protective layer 15, the first protective layer 15 is formed on the sidewalls of the resistance change layer 13 and the upper electrode 12 simultaneously with the element lamination etching process. can do. Therefore, moisture absorption of the resistance change layer 13 and the upper electrode 12 can be suppressed, and variation in the set voltage of the resistance change element 10 due to oxidation of the resistance change layer 13 and the upper electrode 12 can be reduced.

The film thickness of the first protective layer 15 is preferably smaller than the film thickness of the buffer layer 132. If the first protective layer 15 is made thinner than the buffer layer 132, the chemical composition in the film thickness direction is homogenized in the first protective layer 15 formed simultaneously with the etching process of the buffer layer 132. The moisture absorption resistance can be improved.

The second protective layer 16 covers at least a part of the first protective layer 15. As shown in FIG. 1, the second protective layer 16 is preferably configured to cover all of the exposed portion including the side surface and the upper side of the first protective layer 15.

The second protective layer 16 is preferably composed of at least one of SiCN, SiN, and SiC. If these materials are used for the second protective layer 16, the adhesion with the lower insulating barrier layer 14 made of a similar material is improved, and the moisture absorption resistance can be further improved. Moreover, the 2nd protective layer 16 is not limited to being comprised by one layer containing one of these materials, You may be comprised by two or more layers which consist of two or more of these materials.

As described above, the semiconductor device of this embodiment includes the first electrode, the second electrode, the resistance change layer, and the first insulating layer. The first insulating layer is disposed on the first electrode, and at least one opening is formed. The variable resistance layer is disposed on the first insulating layer and connected to the first electrode inside the opening. The second electrode is disposed on the resistance change layer. The side surfaces of the first protective layer and the resistance change layer are covered. The second protective layer covers the first protective layer.

In the semiconductor device of this embodiment, the side surface of the resistance change layer is covered with the first protective layer, and further, the first protective layer is covered with the second protective layer, so that moisture absorption of the resistance change layer to the solid electrolyte layer is suppressed. Is done. As a result, according to the semiconductor device of the present embodiment, variation in element operation due to moisture absorption by the solid electrolyte layer is reduced, and variation in set voltage is suppressed. That is, according to the semiconductor device of the present embodiment, variation in set voltage can be improved while suppressing moisture absorption to the solid electrolyte layer.

For example, the thickness and material of each of the first protective layer and the second protective layer of the present embodiment can be confirmed with various measuring instruments. In addition, the film thickness, material dimensions, constituent elements, and chemical composition of each of the first protective layer and the second protective layer can be analyzed by a transmission electron microscope. Moreover, the film thickness and material of each of the first protective layer and the second protective layer can be analyzed by an analysis method such as energy dispersive X-ray spectroscopy or electron energy loss spectroscopy.

(Modification)
Here, a modification of the semiconductor device 1 of the first embodiment will be described with reference to the drawings. Note that, in the following modification, the same reference numerals are given to the same configurations as those of the semiconductor device 1 of the first embodiment.

[Modification 1]
FIG. 2 is a partial cross-sectional view showing a configuration example of the semiconductor device 1-1 of the first modification. As shown in FIG. 2, the semiconductor device 1-1 includes an interlayer insulating film 17 and a barrier metal 18. In the semiconductor device 1-1 of Modification 1, the opening 140 of the insulating barrier layer 14 includes a first opening region 141 and a second opening region 142. The lower electrode 11 of the semiconductor device 1-1 of Modification 1 is formed inside the interlayer insulating film 17 and has a configuration exposed to part of the opening 140. A plurality of lower electrodes 11 may be configured to be exposed in one opening 140.

The interlayer insulating film 17 is provided below the insulating barrier layer 14. The interlayer insulating film 17 is in contact with the solid electrolyte layer 131 in the second opening region 142 in the opening 140.

The barrier metal 18 is provided between the lower electrode 11 and the interlayer insulating film 17. Barrier metal 18 and lower electrode 11 are in contact with solid electrolyte layer 131 in first opening region 141 in opening 140.

The barrier metal 18 is a conductive film having a barrier property for covering the side and bottom surfaces of the wiring in order to prevent the metal elements constituting the wiring from diffusing into the interlayer insulating film and the lower layer. For example, when the material constituting the wiring is a metal having Cu as a main component, a high melting point metal such as tantalum Ta, a nitride such as tantalum nitride TaN or titanium nitride TiN, or a single nitride carbide such as tungsten carbonitride WCN. A layer film can be used as the barrier metal 18. In addition, a laminated film of these refractory metals, nitrides, and nitrocarbides can be used as a barrier metal. The film of the material mentioned here can be easily processed by dry etching, and has good consistency with the LSI (Large Scale Integration) manufacturing process before Cu is used as a wiring material.

The semiconductor device 1 (FIG. 1) has a structure in which the lower electrode 11 and the buffer layer 132 are in contact with each other over the entire surface of the opening 140. On the other hand, the semiconductor device 1-1 (FIG. 2) has a structure in which the lower electrode 11 and the buffer layer 132 are in contact with each other in part of the opening 140.

[Modification 2]
FIG. 3 is a partial cross-sectional view illustrating a configuration example of the semiconductor device 1-2 according to the second modification. As shown in FIG. 3, in the semiconductor device 1-2 of Modification 2, the first protective layer 15 is covered with the second protective layer 16. In the configuration of Modification 2 (FIG. 3), a part of the upper electrode 12 and the insulating barrier layer 14 is exposed.

In the configuration of Modification 2 (FIG. 3), the end portions of the upper electrode 12, the solid electrolyte layer 131, and the buffer layer 132 are covered with the first protective layer 15, so that an oxidation suppressing effect is obtained. However, in the configuration of the modified example 2 (FIG. 3), the upper electrode 12 and a part of the insulating barrier layer 14 are not covered with the second protective layer 16, so that the oxidation suppressing effect cannot be obtained. Therefore, practically, it is preferable to cover all of the upper electrode 12 and the insulating barrier layer 14 with the second protective layer 16 as in the semiconductor device 1 of the first embodiment (FIG. 1).

[Modification 3]
FIG. 4 is a partial cross-sectional view illustrating a configuration example of the semiconductor device 1-3 according to the third modification. As shown in FIG. 4, in the semiconductor device 1-3 of the third modification, a hard mask layer 19 for processing a resistance change element pattern is formed on the upper surface of the upper electrode 12.

For example, the first protective layer 15 may be in contact with the side surface of the hard mask layer 19. For example, the second protective layer 16 is continuous including the side surfaces of the upper electrode 12 and the resistance change layer 13 covered with the first protective layer 15, the upper surface of the insulating barrier layer 14, and the upper surface and side surfaces of the hard mask layer 19. And may be coated.

The semiconductor devices 1-1 to 3 of Modifications 1 to 3 shown in FIGS. 2 to 4 are configuration examples of the first embodiment together with the semiconductor device 1 of FIG. Therefore, according to the semiconductor devices 1-1 to 3 of Modifications 1 to 3 shown in FIGS. 2 to 4, like the semiconductor device 1 shown in FIG. 1, the set voltage is suppressed while the moisture absorption to the solid electrolyte layer is suppressed. Can be improved.

For example, the first protective layer covers the side surface of the second electrode.

For example, the second protective layer is continuously coated from above the second electrode to the upper surface of the first insulating layer.

For example, the semiconductor device of this embodiment includes a second insulating layer that is disposed below the first insulating layer and in which a wiring trench is formed. The first electrode is embedded in the wiring groove formed in the second insulating layer, and is connected to the resistance change layer at the opening.

For example, the resistance change layer includes a buffer layer disposed from the inside to the periphery of the opening, and a solid electrolyte layer disposed on the buffer layer. For example, one end of the first protective layer is connected to the side surface of the buffer layer. For example, the first protective layer is made of the same material as the buffer layer. For example, the buffer layer and the first protective layer are made of an oxide material containing at least one of a metal element having a negative energy larger than that of the material constituting the first electrode and a non-metal element belonging to Group 14 Is done.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. The semiconductor device of this embodiment has a configuration in which the variable resistance element of the first embodiment is provided inside a multilayer wiring structure formed on a semiconductor substrate. In particular, in the present embodiment, a configuration in which the variable resistance element according to Modification 3 of the first embodiment is provided in the multilayer wiring structure will be described as an example.

FIG. 5 is a partial cross-sectional view showing a configuration example of the semiconductor device 2. As shown in FIG. 5, the semiconductor device 2 is formed on the semiconductor substrate 201.

The semiconductor device 2 includes a lower electrode 21, an upper electrode 22, a resistance change layer 23, a first protective layer 25, and a second protective layer 26. The lower electrode 21, the upper electrode 22, and the resistance change layer 23 constitute the resistance change element 20. The resistance change layer 23 includes a solid electrolyte layer 231 and a buffer layer 232. The upper electrode 22 includes a first upper electrode 221 and a second upper electrode 222.

The semiconductor device 2 includes a first interlayer insulating film 202, a second interlayer insulating film 203, a first cap insulating film 204, a first barrier metal 205, a first insulating barrier film 206, a second hard mask layer 208, and A third hard mask layer 209 is provided. In addition, the semiconductor device 2 includes the first via interlayer insulating film 210, the third interlayer insulating film 211, the second cap insulating film 212, the second barrier metal 213, the via plug 214, the upper wiring 215, and the second insulating barrier film 216. Prepare. Furthermore, an opening 240, a wiring groove 250, a via hole 260, and a wiring groove 270 are formed in the semiconductor device 2. Although the first hard mask layer 207 is formed in the manufacturing process of the semiconductor device 2, it is not shown in FIG. 5 (shown in FIG. 9) because it is removed during the manufacturing.

Here, the correspondence relationship between the configuration of the semiconductor device 2 (FIG. 5) of the present embodiment and the components of the semiconductor device 1-3 (FIG. 4) of Modification 3 according to the first embodiment will be summarized. The lower electrode 21 corresponds to the lower electrode 11. The solid electrolyte layer 231 corresponds to the solid electrolyte layer 131. The buffer layer 232 corresponds to the buffer layer 132. The upper electrode 22 including the first upper electrode 221 and the second upper electrode 222 corresponds to the upper electrode 12. The first insulating barrier film 206 corresponds to the insulating barrier layer 14. The combined structure of the second hard mask layer 208 and the third hard mask layer 209 corresponds to the hard mask layer 19. Each of the first protective layer 25 and the second protective layer 26 corresponds to each of the first protective layer 15 and the second protective layer 16. Unless otherwise specified, the components having the above-described correspondence can be made of the same material.

[Resistance change element]
First, the configuration of the resistance change element 20 will be described. Since the resistance change element 20 can be configured in the same manner as the resistance change element 10 of the first embodiment, the overlapping description may be omitted.

The resistance change element 20 is formed on the first interlayer insulating film 202. The resistance change element 20 includes a lower electrode 21, an upper electrode 22, and a resistance change layer 23.

The lower electrode 21 (also referred to as a first electrode) is one of the two electrodes of the resistance change element 20. The lower electrode 21 is an active electrode. For example, the lower electrode 21 is made of a metal material whose main component is Cu. The lower electrode 21 is included in a first barrier metal 205 formed on the first interlayer insulating film 202. The lower electrode 21 is formed so as to be buried in the wiring trench 250 formed in the second interlayer insulating film 203 and the first cap insulating film 204 through the first barrier metal 205. Further, the lower electrode 21 is in contact with the buffer layer 232 over the entire inside of the opening 240 of the first insulating barrier film 206.

Similar to the lower electrode 11 (FIG. 2) of the first embodiment, the lower electrode 21 is in contact with the buffer layer 232 through the opening 240 provided in the first insulating barrier film 206, and on the semiconductor substrate 201. Also serves as wiring. Therefore, a Cu electrode serving also as a Cu wiring can be applied to the lower electrode 21, and the resistance change element 20 using the Cu electrode can be formed in the multilayer wiring structure on the CMOS substrate. If the lower electrode 21 of the variable resistance element 20 is configured to also serve as a wiring on the semiconductor substrate 201, the process of manufacturing the variable resistance element 20 on the semiconductor substrate 201 can be simplified. With the configuration as shown in FIG. 5, Cu atoms in the lower electrode 21 can be ionized and eluted into the solid electrolyte layer 231.

The upper electrode 22 (also referred to as a second electrode) is the other of the two electrodes of the resistance change element 20. The upper electrode 22 is an inert electrode. The upper electrode 22 is provided on the resistance change layer 23. The upper electrode 22 includes a first upper electrode 221 and a second upper electrode 222.

The first upper electrode 221 is formed on the solid electrolyte layer 231. A second upper electrode 222 is formed on the first upper electrode 221. The first upper electrode 221 is in contact with the solid electrolyte layer 231 and the second upper electrode 222. Further, the side portion of the first upper electrode 221 is in contact with the first protective layer 25. For example, Ru _0.5 Ti _0.5 having a film thickness of 10 nanometers can be applied to the first upper electrode 221.

The second upper electrode 222 is formed on the first upper electrode 221. A second hard mask layer 208 is formed on the second upper electrode 222. The second upper electrode 222 is in contact with the first upper electrode 221 and the second hard mask layer 208. Further, the side portion of the second upper electrode 222 is in contact with the first protective layer 25.

Further, a second barrier metal 213 and a via plug 214 are formed above the second upper electrode 222. The second upper electrode 222 is in contact with the second barrier metal 213 in the opening (via hole 260) formed in the second hard mask layer 208. The second upper electrode 222 is electrically connected to the upper wiring 215 via the second barrier metal 213 and the via plug 214.

The second upper electrode 222 is a conductive film having a barrier property. The second upper electrode 222 is formed in order to prevent the metal contained in the first upper electrode 221 in the immediately lower layer from diffusing into the via plug 214 or the like. For example, Ta having a film thickness of 25 nanometers can be applied to the second upper electrode 222.

The resistance change layer 23 is provided between the lower electrode 21 and the upper electrode 22. In the resistance change layer 23, the solid electrolyte layer 231 and the buffer layer 232 are in contact with each other. The solid electrolyte layer 231 is in contact with the first upper electrode 221. The buffer layer 232 is in contact with the lower electrode 21. Each of the solid electrolyte layer 231 and the buffer layer 232 can be made of the same material as each of the solid electrolyte layer 131 and the buffer layer 132 of the first embodiment.

For example, a SiOCH film having a thickness of 6 nanometers can be applied to the solid electrolyte layer 231. For example, a titanium oxide TiO _y1 film having a thickness of 1.2 nm can be applied to the buffer layer 232. For example, the oxygen composition y1 of the TiO _y1 film applied to the buffer layer 232 is preferably 1.5 or more and 2.0 or less.

[Protective layer]
Next, the first protective layer 25 and the second protective layer 26 included in the semiconductor device 2 will be described.

The first protective layer 25 covers at least a part of the side surface of the resistance change layer 23 and the side surface of the upper electrode 22. In other words, the first protective layer 25 covers the side surfaces of the first upper electrode 221, the second upper electrode 222, the solid electrolyte layer 231, and the buffer layer 232. At least a part of the first protective layer 25 is covered with the second protective layer 26. The first protective layer 25 serves to protect the side portions exposed during the process of the resistance change layer 23 and the upper electrode 22.

For example, the first protective layer 25 covers the entire side of the resistance change layer 23 and the entire side of the upper electrode 22. For example, the first protective layer 25 covers the entire side of the resistance change layer 23 and a part of the side of the upper electrode 22. For example, the first protective layer 25 covers a part of the side of the resistance change layer 23 and a part of the side of the upper electrode 22. Note that one end (the lower end in FIG. 5) of the first protective layer 25 is preferably in contact with the side surface of the buffer layer 232. By bringing the first protective layer 25 and the buffer layer 232 into contact with each other and closing the gap between the side surface of the buffer layer 232 and the first protective layer 25, moisture absorption into the solid electrolyte layer 231 can be further reduced. The 1st protective layer 25 can be comprised with the material similar to the 1st protective layer 15 of 1st Embodiment. However, the covering state of the buffer layer 232, the solid electrolyte layer 231, the first upper electrode 221, and the second upper electrode 222 by the first protective layer 25 is not limited to those described here.

For example, a titanium oxide TiO _y1 film having a thickness of 0.8 nanometer can be applied to the first protective layer 25. For example, the oxygen composition y1 of TiO _y1 is preferably 1.5 or more and 2.0 or less. The first protective layer 25 is preferably composed of a film having the same composition as the buffer layer 232.

The second protective layer 26 collectively covers the surface of the first protective layer 25, the side surfaces of the second hard mask layer 208, the side surfaces and the upper surface of the third hard mask layer 209, and the surface of the first insulating barrier film 206. To do. As shown in FIG. 5, the second protective layer 26 is preferably configured to cover all of the exposed portion including the side surface and the upper side of the first protective layer 25. The second protective layer 26 can be made of the same material as the second protective layer 16 of the first embodiment.

The second protective layer 26 is an insulating film disposed so as not to damage the resistance change element 20 whose side surface is exposed. The second protective layer 26 has a function of preventing the constituent atoms of the variable resistance element 20 from diffusing into the first via interlayer insulating film 210. For example, a SiN film, a SiCN film, or the like can be used for the second protective layer 26.

[Peripheral configuration]
Next, the configuration around the resistance change element 20 will be described.

The semiconductor substrate 201 is a substrate of the semiconductor device 2. A first interlayer insulating film 202 is formed on the semiconductor substrate 201.

The first interlayer insulating film 202 is an insulating film formed on the semiconductor substrate 201. A second interlayer insulating film 203 is formed on the first interlayer insulating film 202. In addition, a first barrier metal 205 including the lower electrode 21 is formed on the first interlayer insulating film 202 via a wiring groove 250 formed in the second interlayer insulating film 203. In the configuration of FIG. 5, the lower part of the first barrier metal 205 is reduced to the upper part of the first interlayer insulating film 202.

The second interlayer insulating film 203 is an insulating film formed on the first interlayer insulating film 202. A first cap insulating film 204 is formed on the second interlayer insulating film 203. A wiring groove 250 is formed in the second interlayer insulating film 203.

The first cap insulating film 204 is an insulating film formed on the second interlayer insulating film 203. A first insulating barrier film 206 is formed on the first cap insulating film 204. A wiring groove 250 is formed in the first cap insulating film 204.

The wiring trench 250 penetrates the second interlayer insulating film 203 and the first cap insulating film 204, and a part of the upper surface of the first interlayer insulating film 202 is a bottom surface. A first barrier metal 205 is formed on the inner surface of the wiring groove 250. The second interlayer insulating film 203 and the first cap insulating film 204 in which the wiring trench 250 is formed are collectively referred to as a second insulating layer.

As with the second upper electrode 222, the first barrier metal 205 is a conductive film having a barrier property. The first barrier metal 205 is used to prevent the metal contained in the lower electrode 21 from diffusing into the first interlayer insulating film 202, the second interlayer insulating film 203, and the first cap insulating film 204. Cover side and bottom. For example, when the lower electrode 21 is made of a metal element whose main component is Cu, the first barrier metal 205 includes a refractory metal such as Ta, TaN, TiN, and WCN, nitrides thereof, or a laminated film thereof. Is preferred.

The first barrier metal 205 is formed on the second interlayer insulating film 203 and the first cap insulating film 204, and covers the inner surface of the wiring trench 250 having a part of the upper surface of the first interlayer insulating film 202 as the bottom surface. A lower electrode 21 is formed inside the first barrier metal 205. On the first barrier metal 205, the variable resistance element 20 and the first insulating barrier film 206 are formed.

The first insulating barrier film 206 is formed on the lower electrode 21, the first cap insulating film 204, and the first barrier metal 205. On the first insulating barrier film 206, the variable resistance element 20, the first protective layer 25, and the second protective layer 26 are formed. At least one opening 240 is formed in a part of the first insulating barrier film 206. In the first insulating barrier film 206, the buffer layer 232 is disposed on the inner surface of the opening 240 and a part of the upper surface including the periphery of the opening 240. A first protective layer 25 is formed on the upper surface of the first insulating barrier film 206 so as to surround the buffer layer 232. Further, the second protective layer 26 is formed on the remaining portion of the upper surface of the first insulating barrier film 206 so as to surround the first protective layer 25. The first insulating barrier film 206 is an insulating film having a function of preventing metal diffusion.

In the opening 240 of the first insulating barrier film 206, the lower electrode 21 and the buffer layer 232 of the resistance change layer 23 are in contact with each other. When the surface of the lower electrode 21 partially exposed at the bottom of the opening 240 is in contact with the buffer layer 232 of the resistance change layer 23 through the opening 240, the affinity for a general semiconductor manufacturing process is improved. it can.

Further, the solid electrolyte layer 231 and the lower electrode 21 are connected through the opening 240 of the first insulating barrier film 206 with the buffer layer 232 interposed therebetween. The lateral width of the lower electrode 21 connected to the solid electrolyte layer 231 with the buffer layer 232 interposed therebetween is preferably larger than the diameter of the opening 240 of the first insulating barrier film 206.

The second hard mask layer 208 is formed on the second upper electrode 222. A third hard mask layer 209 is formed on the second hard mask layer 208. A via hole 260 passes through the second hard mask layer 208. The side portion of the second hard mask layer 208 is covered with the second protective layer 26.

The third hard mask layer 209 is formed on the second hard mask layer 208. A first via interlayer insulating film 210 is formed on the third hard mask layer 209. A via hole 260 passes through the third hard mask layer 209. Side portions and an upper portion of the third hard mask layer 209 are covered with the second protective layer 26.

The third hard mask layer 209 is a film that serves as a hard mask when the second hard mask layer 208 is etched. The second hard mask layer 208 is preferably a different type of film from the third hard mask layer 209. For example, if the second hard mask layer 208 is a SiCN film, a SiO ₂ film different from the SiCN film may be used for the third hard mask layer 209.

The first via interlayer insulating film 210 is an insulating film formed on the second protective layer 26. A third interlayer insulating film 211 is formed on the first via interlayer insulating film 210. A via hole 260 passes through the first via interlayer insulating film 210. In the configuration of FIG. 5, a part of the second barrier metal 213 is reduced above the first via interlayer insulating film 210.

The via hole 260 penetrates the second hard mask layer 208, the third hard mask layer 209, and the first via interlayer insulating film 210, and a part of the upper surface of the second upper electrode 222 is a bottom surface. A second barrier metal 213 that includes the via plug 214 is disposed inside the via hole 260.

The third interlayer insulating film 211 is an insulating film formed on the first via interlayer insulating film 210. A second cap insulating film 212 is formed on the third interlayer insulating film 211. A wiring trench 270 passes through the third interlayer insulating film 211.

The second cap insulating film 212 is an insulating film formed on the third interlayer insulating film 211. A second insulating barrier film 216 is formed on the second cap insulating film 212. A wiring groove 270 passes through the second cap insulating film 212.

The wiring trench 270 penetrates the third interlayer insulating film 211 and the second cap insulating film 212, and a part of the upper surface of the first via interlayer insulating film 210 is a bottom surface. A second barrier metal 213 that encloses the upper wiring 215 is disposed inside the wiring groove 270. In the example of FIG. 5, the wiring groove 270 has a larger opening area than the via hole 260. The via plug 214 disposed inside the via hole 260 and the second barrier metal 213 disposed inside the wiring groove 270 are integrally formed.

The second barrier metal 213 is formed on the inner surfaces of the via hole 260 and the wiring groove 270. An upper wiring 215 is formed inside the second barrier metal 213. A second insulating barrier film 216 is formed on the second barrier metal 213.

The second barrier metal 213 is a conductive film having the same barrier properties as the first barrier metal 205. The second barrier metal 213 covers the side surfaces and the bottom surface of the upper wiring 215 and the via plug 214. The second barrier metal 213 prevents the metal contained in the via plug 214 and the upper wiring 215 from diffusing into the first via interlayer insulating film 210, the third interlayer insulating film 211, and the second cap insulating film 212.

For example, when the via plug 214 and the upper wiring 215 are mainly composed of Cu, the second barrier metal 213 includes a refractory metal such as Ta, TaN, TiN, and WCN, and its nitride, as in the first barrier metal 205. A thing etc. or those laminated films are used. The second barrier metal 213 is preferably made of the same material as the second upper electrode 222 that is a part of the configuration of the resistance change element 20 from the viewpoint of reducing contact resistance. For example, when the second upper electrode 222 is Ta, it is preferable to use Ta for the second barrier metal 213 in contact with the upper portion thereof.

The via plug 214 is included in the second barrier metal 213 disposed inside the via hole 260. That is, the via plug 214 is embedded in the prepared holes formed in the second protective layer 26, the second hard mask layer 208, and the third hard mask layer 209 via the second barrier metal 213. The via plug 214 is formed integrally with the upper wiring 215 disposed inside the wiring groove 270.

The upper wiring 215 is included in the second barrier metal 213 disposed on the inner surface of the wiring groove 270. That is, the upper wiring 215 is a wiring embedded in the wiring groove 270 formed in the third interlayer insulating film 211 and the second cap insulating film 212 via the second barrier metal 213. The upper wiring 215 is formed integrally with the via plug 214 disposed inside the wiring groove 270.

The via plug 214 and the upper wiring 215 are electrically connected to the resistance change element 20 via the second barrier metal 213. For example, a material containing Cu is used for the upper wiring 215 and the via plug 214.

The second insulating barrier film 216 is formed on the second cap insulating film 212, the second barrier metal 213, and the upper wiring 215. The second insulating barrier film 216 is an insulating film having a function of preventing metal diffusion.

As described above, in the present embodiment, as in the first embodiment, the first protective layer and the second protective layer are provided, the side surfaces of the resistance change layer are covered with the first protective layer, and the first protection is further performed. Since the layer is covered with the second protective layer, moisture absorption of the variable resistance layer to the solid electrolyte layer is suppressed. As a result, according to the semiconductor device of the present embodiment, variation in element operation due to moisture absorption by the solid electrolyte layer is reduced, and variation in set voltage is suppressed. That is, according to the semiconductor device of the present embodiment, moisture absorption of the variable resistance layer to the solid electrolyte layer can be suppressed, and variation in set voltage can be reduced.

〔Production method〕
Next, a method for manufacturing the semiconductor device 2 of the present embodiment will be described with reference to the drawings. Note that the manufacturing method of the semiconductor device 2 described below is an example, and the manufacturing method of the semiconductor device 2 is not limited. Moreover, in the manufacturing method of the semiconductor device 2 shown below, some processes may be put together or a specific process may be simplified.

6 to 19 are schematic views for explaining a method for manufacturing the semiconductor device 2. 6 to 19 are partial cross-sectional views of the semiconductor device 2 in the manufacturing process. The manufacturing method of the semiconductor device 2 includes a process A, a process B, and a process C.

[Process A]
First, step A of the method for manufacturing the semiconductor device 2 will be described with reference to FIGS. Step A includes step A1 to step A5. Process A is a process from the formation of the first interlayer insulating film 202 on the semiconductor substrate 201 to the formation of the opening 240 in the first insulating barrier film 206.

First, as shown in FIG. 6, a first interlayer insulating film 202, a second interlayer insulating film 203, and a first cap insulating film 204 are sequentially stacked on a semiconductor substrate 201 (step A1).

The semiconductor substrate 201 may be the substrate itself or a substrate on which a semiconductor element (not shown) is formed on the substrate surface. For example, the first interlayer insulating film 202 can be a 300 nm thick SiO ₂ film. Further, for example, a SiOCH film having a thickness of 150 nm can be used for the second interlayer insulating film 203. For example, the first cap insulating film 204 can be a SiO ₂ film having a thickness of 100 nanometers.

Next, as shown in FIG. 7, a wiring trench 250 is formed in the laminated film of the first cap insulating film 204, the second interlayer insulating film 203, and the first interlayer insulating film 202 by using a lithography method (step A2). .

The lithography method includes a photoresist formation process, a dry etching process, and a resist removal process. The photoresist forming process is a process of forming a resist with a predetermined pattern on the first cap insulating film 204. The dry etching process is a process of performing anisotropic etching on the laminated film using a resist as a mask. The resist removal process is a process of removing the resist after forming the wiring groove 250 by etching.

Next, as shown in FIG. 8, the first barrier metal 205 is formed on the inner surface of the wiring groove 250, and the lower electrode 21 is formed by embedding the metal in the first barrier metal 205 (step A3).

For example, a stacked structure of TaN (film thickness 5 nanometers) / Ta (film thickness 5 nanometers) can be used for the first barrier metal 205. For example, Cu can be used for the lower electrode 21.

Next, as shown in FIG. 9, a first insulating barrier film 206 and a first hard mask layer 207 are sequentially stacked on the lower electrode 21, the first barrier metal 205, and the first cap insulating film 204 (see FIG. 9). Step A4).

For example, as the first insulating barrier film 206, a SiCN film having a thickness of 30 nanometers can be used. Further, the first hard mask layer 207 is preferably made of a material different from that of the first insulating barrier film 206 from the viewpoint of maintaining a high etching selectivity in the dry etching process. For example, the first hard mask layer 207 can be a SiO ₂ film having a deposited film thickness of 40 nanometers.

Next, a photoresist having a predetermined opening pattern is formed on the first insulating barrier film 206, and dry etching is performed to form an opening in the first insulating barrier film 206 (not shown). . For example, the photoresist is removed by O ₂ plasma ashing or the like.

Next, by etching back the first insulating barrier film 206 exposed at the bottom of the opening of the first hard mask layer 207, the opening where a part of the upper surface of the lower electrode 21 is exposed as shown in FIG. 240 is formed (step A5).

For example, the first hard mask layer 207 is etched away during etch back if the film thickness is set to 40 nanometers. After the etch back, the surface of the lower electrode 21 exposed from the opening 240 is cleaned by plasma irradiation using an organic solvent, hydrogen gas, inert gas, or the like.

For example, when the first insulating barrier film 206 is a SiN film or a SiCN film, plasma containing CF ₄ can be used for etch back when the opening 240 of the first insulating barrier film 206 is formed. . When using a plasma containing CF ₄ , set the CF ₄ / Ar gas flow rate to 25/50 sccm (Standard Cubic Centimeter per Minute), the pressure to 0.53 Pascal, the source power to 400 watts, and the substrate bias power to 90 watts. That's fine. When the first insulating barrier film 206 is etched back, the ionicity at the time of etching is improved by reducing the source power or increasing the substrate bias, so that the opening surface of the first insulating barrier film 206 is improved. Can be formed into a tapered shape. Further, the first hard mask layer 207 can be removed by etching back.

This completes the description of the process A of the method for manufacturing the semiconductor device 2.

[Process B]
Secondly, step B of the method for manufacturing the semiconductor device 2 will be described with reference to FIGS. Step B includes Steps B1 to B5. Process B is a process until the resistance change element 20 is formed and the formed resistance change element 20 is covered with the second protective layer.

First, as shown in FIG. 11, a buffer layer 232 is formed on the first insulating barrier film 206 including the inner surface of the opening 240 from which the lower electrode 21 is exposed (step B1).

For example, the buffer layer 232 can be a titanium oxide TiO _y1 film having a thickness of 1.2 nanometers. For example, the oxygen composition y1 of TiO _y1 is preferably 1.5 or more and 2.0 or less. When a titanium oxide TiO _y1 film is used as the buffer layer 232, after titanium Ti is deposited on the first insulating barrier film 206, oxidation treatment is performed by irradiation with a gas containing O ₂ under reduced pressure without being exposed to the atmosphere. Do. Then, by performing vacuum heat treatment at a temperature higher than the film formation temperature under reduced pressure, the buffer layer 232 can be formed as shown in FIG. However, the formation method of the buffer layer 232 mentioned here is an example, and the formation method of the buffer layer 232 is not limited.

For example, the metal layer for forming the buffer layer 232 can be deposited by resistance heating of a metal raw material, an evaporation method using electron beam irradiation or laser irradiation, a direct current (DC) sputtering method, or the like. For example, when the buffer layer 232 is a titanium oxide TiO _y1 film, the buffer is formed by DC sputtering using Ti as a target, sputtering power of 100 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa. Layer 232 can be deposited.

Next, as shown in FIG. 12, the solid electrolyte layer 231, the first upper electrode 221, and the second upper electrode 222 are sequentially stacked on the buffer layer 232 (step B2).

For example, a SiOCH film having a thickness of 6 nm is used for the solid electrolyte layer 231. When a SiOCH film is used for the solid electrolyte layer 231, the solid electrolyte layer 231 is deposited by a plasma CVD (Chemical Vapor Deposition) method, and then an inert gas plasma treatment is performed.

The plasma CVD method is a method of forming a continuous film on a substrate. In the plasma CVD method, a raw material obtained by vaporizing a gas raw material or a liquid raw material is continuously supplied to a reaction chamber under reduced pressure, molecules are excited by plasma energy, and the substrate is subjected to a gas phase reaction or a substrate surface reaction. A continuous film is formed.

When a SiOCH film is used for the solid electrolyte layer 231, the solid electrolyte layer 231 can be formed by a plasma CVD method under the following conditions. As the raw material, liquid SiOCH monomer molecules are used. The substrate temperature is 400 ° C. or lower, the flow rate of helium He is 500 to 2000 sccm, the raw material flow rate is 0.1 to 0.8 g / min, the plasma CVD chamber pressure is 360 to 700 Pascal, and the RF (Radio Frequency) output is 20 to Set to 100 watts. More specifically, the substrate temperature is set to 350 ° C., the He flow rate is set to 1500 sccm, the raw material flow rate is set to 0.75 g / min, the plasma CVD chamber pressure is set to 470 Pascals, and the RF output is set to 50 Watts.

For example, the inert plasma treatment after depositing the solid electrolyte layer 231 uses He as an inert gas, the substrate temperature is 400 ° C. or lower, the He flow rate is 500-1500 sccm, and the plasma chamber pressure is 2.7-3. Set 5 Torr, RF power to 20-200 Watts. More specifically, the substrate temperature is set to 350 ° C., the He flow rate is set to 1000 sccm, the plasma chamber pressure is set to 360 Pascals, and the RF output is set to 50 Watts. If inert plasma processing is used, adhesiveness with the 1st upper electrode 221 formed on the solid electrolyte layer 231 can be improved.

For example, the first upper electrode 221 and the second upper electrode 222 are sequentially formed on the solid electrolyte layer 231 by DC sputtering. For example, the first upper electrode 221 is a ruthenium titanium alloy Ru _0.5 Ti _0.5 having a thickness of 10 nanometers. For example, the second upper electrode 222 is Ta having a film thickness of 25 nanometers. When the first upper electrode 221 is made of Ru or a Ru alloy, the second upper electrode is continuously exposed without being exposed to the atmosphere after the first upper electrode 221 is deposited in order to prevent surface oxidation of the first upper electrode 221. Preferably 222 is deposited.

For example, when forming Ru _0.5 Ti _0.5 as the first upper electrode 221, simultaneous DC sputtering using Ru and Ti as targets may be used. In this case, the substrate temperature is set to room temperature, the Ru sputtering output is set to 120 watts, the Ti sputtering output is set to 150 watts, the Ar flow rate is set to 20 sccm, and the pressure is set to 0.5 Pa. Further, when forming Ta with a thickness of 25 nanometers as the second upper electrode 222, DC sputtering using Ta as a target may be used. In that case, the substrate temperature is set to room temperature, the sputtering output is set to 300 watts, the Ar flow rate is set to 25 sccm, and the pressure is set to 0.5 Pascal.

The lower electrode 21, the buffer layer 232, the solid electrolyte layer 231, the first upper electrode 221, and the second upper electrode 222 constitute a stacked body that becomes the resistance change element 20.

Next, as shown in FIG. 13, the second hard mask layer 208 and the third hard mask layer 209 are sequentially stacked on the second upper electrode 222 (step B3).

For example, the second hard mask layer 208 is preferably made of the same material as the first insulating barrier film 206 from the viewpoint of adhesion. For example, a SiCN film having a thickness of 30 nanometers is used for the second hard mask layer 208. For example, as the third hard mask layer 209, a SiO ₂ film having a thickness of 100 nanometers is used.

For example, the second hard mask layer 208 and the third hard mask layer 209 can be formed using a plasma CVD method. The film formation temperature may be selected in the range of 200 ° C. to 400 ° C. More specifically, the film forming temperature is preferably set to 350 ° C.

Next, after forming a photoresist having a processing pattern of the resistance change element 20 on the third hard mask layer 209, the third hard mask layer 209 is dry-etched until the second hard mask layer 208 is exposed (the figure is shown). (Omitted). The photoresist is removed by an O ₂ plasma ashing process.

Next, as shown in FIG. 14, the second hard mask layer 208, the second upper electrode 222, the first upper electrode 221, the solid electrolyte layer 231 and the buffer layer 232 are successively formed using the third hard mask layer 209 as a mask. Dry etching is performed (step B4).

For example, the dry etching of the third hard mask layer 209 is preferably stopped on the upper surface or inside the second hard mask layer 208. In this case, since the variable resistance element 20 is covered with the second hard mask layer 208, it is not exposed to O ₂ plasma. Further, since the first upper electrode 221 containing Ru is not exposed to O ₂ plasma, the occurrence of side etching on the first upper electrode 221 can be suppressed. For example, a parallel plate type dry etching apparatus can be used for dry etching of the third hard mask layer 209.

Further, the etching of the second hard mask layer 208, the second upper electrode 222, the first upper electrode 221, the solid electrolyte layer 231, and the buffer layer 232 is also performed collectively using a parallel plate type dry etcher. Can do.

For example, when SiCN is used for the second hard mask layer 208, the flow rate of CF ₄ / Ar gas is 25/50 sccm, the pressure is 0.53 Pascal, the source output is 400 watts, and the substrate bias output is 90 watts. .

For example, when Ta is used for the second upper electrode 222, the substrate temperature is set to 90 ° C., the chlorine Cl ₂ gas flow rate is set to 50 sccm, the pressure is set to 0.53 Pascal, the source output is set to 400 watts, and the substrate bias output is set to 60 watts. That's fine.

For example, when Ru _0.5 Ti _0.5 is used for the first upper electrode 221, the substrate temperature is set to room temperature, the flow rate of O ₂ / Cl ₂ gas is 160/30 sccm, the pressure is 0.53 Pascal, and the source output is 300 to 600. What is necessary is just to set watt and a substrate bias output to 100-300W.

For example, when SiOCH is used for the solid electrolyte layer 231, the same conditions may be set as when Ru _0.5 Ti _0.5 is used for the first upper electrode 221. In that case, the solid electrolyte layer 231 can be etched together with the first upper electrode 221.

For example, when TiO _y1 is used for the buffer layer 232, the same conditions as those for the first upper electrode 221 may be set in the same manner as the solid electrolyte layer 231 when Ru _0.5 Ti _0.5 is used for the first upper electrode 221. In that case, the buffer layer 232 can be etched together with the first upper electrode 221 and the solid electrolyte layer 231.

Next, as shown in FIG. 15, the first protective layer 25 is formed on the side surfaces of the second upper electrode 222, the first upper electrode 221, the solid electrolyte layer 231, and the buffer layer 232 (step B5).

For example, when a titanium oxide TiO _y1 film is used for the first protective layer 25, titanium Ti is deposited on the side surfaces of the second upper electrode 222, the first upper electrode 221, the solid electrolyte layer 231, and the buffer layer 232, and then under reduced pressure. The oxidation treatment is performed by irradiation with a gas containing O ₂ without being exposed to the atmosphere. Then, by performing vacuum heat treatment at a temperature higher than the film formation temperature under reduced pressure, the buffer layer 232 can be formed as shown in FIG. However, the formation method of the buffer layer 232 mentioned here is an example, and the formation method of the buffer layer 232 is not limited.

For example, if the first protective layer 25 is made of the same material as the buffer layer 232, the buffer layer 232 is etched, and at the same time, the exposed solid electrolyte layer 231, buffer layer 232, second upper electrode 222, first upper electrode 221 are etched. The first protective layer 25 can be formed in close contact with the side surfaces of the first protective layer 25. In the case where the first protective layer 25 is etched simultaneously with the buffer layer 232, the second electrolyte electrode 231 is etched on the side surfaces of the second upper electrode 222, the first upper electrode 221, and the solid electrolyte layer 231 after etching the solid electrolyte layer 231 in Step B 4. One protective layer 25 may be formed.

Next, as shown in FIG. 16, the second protective layer 26 is formed on the top and side surfaces of the third hard mask layer 209, the second hard mask layer 208, the first protective layer 25, and the first insulating barrier film 206. (Step B6).

The second protective layer 26 is preferably made of the same material as the first insulating barrier film 206 and the second hard mask layer 208. For example, a SiCN film having a thickness of 30 nanometers is used for the second protective layer 26.

For example, when a SiCN film is used for the second protective layer 26, the second protective layer 26 can be formed by using plasma CVD method with tetramethylsilane and ammonia as source gases and a substrate temperature of 200 ° C. If the first insulating barrier film 206, the second protective layer 26, and the second hard mask layer 208 are made of the same material (for example, a SiCN film), the periphery of the resistance change element 20 can be integrated and protected. Interfacial adhesion can be improved. As a result, hygroscopicity, water resistance and oxygen desorption resistance can be improved, and the yield and reliability of the device can be improved.

This completes the description of the process B of the method for manufacturing the semiconductor device 2.

[Process C]
Third, step C of the method for manufacturing the semiconductor device 2 will be described with reference to FIGS. Step C includes steps C1 to C4. Step C forms a via hole 260 and a wiring groove 270 in a laminated structure in which the first via interlayer insulating film 210, the third interlayer insulating film 211, and the second cap insulating film 212 are formed on the second protective layer 26. It is a process until.

First, as shown in FIG. 17, a first via interlayer insulating film 210 is deposited on the upper surface and side surfaces of the second protective layer 26 (step C1).

For example, the first via interlayer insulating film 210 is deposited on the upper surface and side surfaces of the second protective layer 26 using a plasma CVD method. For example, the first via interlayer insulating film 210 may be a SiO ₂ film having a thickness of 210 nanometers. The deposited first via interlayer insulating film 210 is planarized using a CMP method (Chemical Mechanical Polishing).

The CMP method is a method of flattening the unevenness of the wafer surface that occurs during the multilayer wiring formation process by contacting the polishing surface with a polishing pad that is rotated while flowing a polishing liquid on the wafer surface for polishing. The CMP method is used not only for polishing and planarizing an interlayer insulating film, but also for forming a buried wiring called a damascene wiring. When copper Cu is used as the wiring material, Cu is formed on the insulating film in which the groove is formed in advance, and then the Cu embedded in the groove is left by CMP, and excess Cu on the insulating film is polished and removed. Thus, a damascene wiring in which Cu is embedded in the groove can be formed.

For example, when a SiO ₂ film having a thickness of 210 nanometers is planarized as the first via interlayer insulating film 210, if about 100 nanometers are scraped from the top surface of the first via interlayer insulating film 210, about 110 nanometers are obtained. The first via interlayer insulating film 210 can be formed. In the case where a SiO ₂ film is used as the first via interlayer insulating film 210, CMP can be performed using colloidal silica or ceria-based slurry.

Next, as shown in FIG. 18, a third interlayer insulating film 211 and a second cap insulating film 212 are sequentially deposited on the planarized upper surface of the first via interlayer insulating film 210 (step C2).

For example, a material different from that of the first via interlayer insulating film 210 is used for the third interlayer insulating film 211 in order to use the first via interlayer insulating film 210 in contact with the lower surface as an etching stopper layer. For example, as the third interlayer insulating film 211, a SiOCH film having a thickness of 150 nanometers is used. The third interlayer insulating film 211 and the second cap insulating film 212 can be deposited using a plasma CVD method.

Next, as shown in FIG. 19, a via hole 260 extending from the second cap insulating film 212 to the upper surface of the second upper electrode 222 is formed (step C3).

For example, the via hole 260 is formed using a via first method which is a kind of dual damascene method. First, a photoresist having a pattern of via holes 260 is formed on the second cap insulating film 212. Next, via holes 260 penetrating through the second cap insulating film 212, the third interlayer insulating film 211, the first via interlayer insulating film 210, the second protective layer 26, and the third hard mask layer 209 are formed by dry etching. To do. Thereafter, the photoresist is removed by performing plasma ashing including H ₂ gas and organic peeling.

For example, after forming the via hole 260, an antireflection film may be embedded on the via hole 260. By embedding an antireflection film on the via hole 260, the bottom of the via hole 260 can be prevented from being scraped when the wiring groove 270 is formed by dry etching.

Next, as shown in FIG. 20, a wiring groove 270 extending from the second cap insulating film 212 to the upper surface of the first via interlayer insulating film 210 is formed (step C4).

For example, the wiring trench 270 is formed by using the via first method, similarly to the via hole 260. First, a photoresist having a pattern of the wiring trench 270 is formed on the second cap insulating film 212. Next, a wiring groove 270 is formed in the second cap insulating film 212 and the third interlayer insulating film 211 by dry etching. Thereafter, the photoresist is removed by performing plasma ashing including H ₂ gas and organic peeling.

This completes the description of the process C of the method for manufacturing the semiconductor device 2. The drawings are omitted for the following steps.

After forming the via hole 260 and the wiring groove 270 in Step C, the upper surface of the second upper electrode 222 is exposed from the via hole 260 by etching the second hard mask layer 208 remaining at the bottom of the via hole 260.

Thereafter, the second barrier metal 213 is formed on the inner surfaces of the via hole 260 and the wiring groove 270, and the upper wiring 215 and the via plug 214 are simultaneously formed therein. For example, Ta having a thickness of 10 nanometers can be used for the second barrier metal 213. For the upper wiring 215 and the via plug 214, a metal containing Cu can be used.

For example, the upper wiring can be formed by the same process as the lower electrode 21. At this time, the diameter of the bottom surface of the via plug 214 is preferably smaller than the diameter of the opening of the first insulating barrier film 206. For example, the diameter of the bottom surface of the via plug 214 can be set to 60 nanometers, and the diameter of the opening of the first insulating barrier film 206 can be set to 100 nanometers.

For example, if the second barrier metal 213 and the second upper electrode 222 are made of the same material, the contact resistance between the via plug 214 and the second upper electrode 222 is reduced, and the resistance of the resistance change element 10 in the on state is reduced. Can be reduced. As a result, the element performance of the resistance change element 20 can be improved.

Thereafter, the second insulating barrier film 216 is deposited on the upper surface of the second cap insulating film 212 including the upper wiring 215, whereby the semiconductor device 2 of FIG. 5 can be manufactured. For example, a 50 nanometer SiCN film) can be used for the second insulating barrier film 216.

This completes the description of the method for manufacturing the semiconductor device 2. In addition, the manufacturing method of the semiconductor device 2 described above is an example, and a plurality of processes may be integrated into one, unnecessary processes may be deleted, processes may be replaced, or new processes may be added. .

As described above, when manufacturing the semiconductor device of this embodiment, first, the first electrode is formed on the substrate. Next, a first insulating layer is formed on the upper surface of the first electrode, and an opening exposing a part of the upper surface of the first electrode is formed in the first insulating layer. Next, a buffer layer is formed on the upper surface of the first insulating layer including the inside of the opening, a solid electrolyte layer is formed on the upper surface of the buffer layer, and a second electrode is formed on the upper surface of the solid electrolyte layer. Next, at least one patterning mask is formed on the upper surface of the second electrode, and the second electrode, the solid electrolyte layer, and the buffer layer are sequentially etched. At the same time, the first protective layer is formed on at least the exposed surfaces of the solid electrolyte layer and the buffer layer among the exposed surfaces formed on the patterning mask, the buffer layer, the solid electrolyte layer, and the second electrode by etching. Then, a second protective layer is formed on the surface of the first protective layer.

(Third embodiment)
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. The semiconductor device of this embodiment includes a three-terminal variable resistance element including two variable resistance elements in which two lower electrodes are configured with respect to one upper electrode.

FIG. 21 is a partial cross-sectional view showing a configuration example of the semiconductor device 3. As shown in FIG. 21, the semiconductor device 3 is formed on the semiconductor substrate 301.

As shown in FIG. 21, the semiconductor device 3 includes a first lower electrode 31a, a second lower electrode 31b, an upper electrode 32, a resistance change layer 33, a first protective layer 35, and a second protective layer 36. The first lower electrode 31a, the upper electrode 32, and the resistance change layer 33 constitute a first resistance change element 30a. The second lower electrode 31b, the upper electrode 32, and the resistance change layer 33 constitute a second resistance change element 30b. The resistance change layer 33 includes a solid electrolyte layer 331 and a buffer layer 332. The upper electrode 32 includes a first upper electrode 321 and a second upper electrode 322.

In addition, the semiconductor device 3 includes a first interlayer insulating film 302, a second interlayer insulating film 303, a first cap insulating film 304, a first barrier metal 305a, a third barrier metal 305b, a first insulating barrier film 306, a second A hard mask layer 308 and a third hard mask layer 309 are provided. The semiconductor device 3 includes a first via interlayer insulating film 310, a third interlayer insulating film 311, a second cap insulating film 312, a second barrier metal 313, a via plug 314, an upper wiring 315, and a second insulating barrier film 316. Prepare.

Here, the correspondence between the constituent elements of the semiconductor device 2 of the second embodiment and the constituent elements of the semiconductor device 3 of the present embodiment is shown.

The first lower electrode 31 a and the second lower electrode 31 b correspond to the lower electrode 21. The upper electrode 32, the resistance change layer 33, the first protective layer 35, and the second protective layer 36 correspond to the upper electrode 22, the resistance change layer 23, the first protective layer 25, and the second protective layer 26, respectively. To do. The resistance change element 30 corresponds to the resistance change element 20. Each of the solid electrolyte layer 331 and the buffer layer 332 corresponds to each of the solid electrolyte layer 231 and the buffer layer 232. Each of the first upper electrode 321 and the second upper electrode 322 corresponds to each of the first upper electrode 221 and the second upper electrode 222. The first interlayer insulating film 302, the second interlayer insulating film 303, and the first cap insulating film 304 correspond to the first interlayer insulating film 202, the second interlayer insulating film 203, and the first cap insulating film 204, respectively. To do. The first barrier metal 305 a and the third barrier metal 305 b correspond to the first barrier metal 205. The first insulating barrier film 306, the second hard mask layer 308, and the third hard mask layer 309 are respectively the first insulating barrier film 206, the second hard mask layer 208, and the third hard mask layer 209. Corresponding to The first via interlayer insulating film 310, the third interlayer insulating film 311, and the second cap insulating film 312 are respectively the first via interlayer insulating film 210, the third interlayer insulating film 211, and the second cap insulating film 212. Corresponding to The second barrier metal 313, the via plug 314, the upper wiring 315, and the second insulating barrier film 316 correspond to the second barrier metal 213, the via plug 214, the upper wiring 215, and the second insulating barrier film 216, respectively. To do.

Hereinafter, differences (resistance change elements) from the semiconductor device 2 of the second embodiment will be mainly described.

[Resistance change element]
Here, the configuration of the first variable resistance element 30a and the second variable resistance element 30b will be described. Since the first variable resistance element 30a and the second variable resistance element 30b can be configured in the same manner as the variable resistance element 20 of the second embodiment, overlapping description may be omitted.

The first resistance change element 30 a and the second resistance change element 30 b are formed on the first interlayer insulating film 302. The first resistance change element 30 a includes a first lower electrode 31 a, an upper electrode 32, and a resistance change layer 33. The second resistance change element 30 b is configured by the second lower electrode 31 b, the upper electrode 32, and the resistance change layer 33.

The semiconductor device 3 includes a first barrier metal 305a and a third barrier metal 305b. The first barrier metal 305a and the third barrier metal 305b are electrically insulated via the second interlayer insulating film 303 and the first cap insulating film 304.

The first lower electrode 31a (also referred to as a first electrode) is one of the two electrodes of the first resistance change element 30a. The first lower electrode 31a is an active electrode. For example, the first lower electrode 31a is made of a metal material whose main component is Cu. The first lower electrode 31 a is included in a first barrier metal 305 a formed on the first interlayer insulating film 302. The first lower electrode 31a is formed so as to be buried in the wiring trench formed in the second interlayer insulating film 303 and the first cap insulating film 304 via the first barrier metal 305a.

The second lower electrode 31b (also referred to as a third electrode) is one of the two electrodes of the second resistance change element 30b. The second lower electrode 31b is an active electrode. For example, the second lower electrode 31b is made of a metal material whose main component is Cu. The second lower electrode 31 b is included in a third barrier metal 305 b formed on the first interlayer insulating film 302. The second lower electrode 31b is formed so as to be embedded in the wiring trench formed in the second interlayer insulating film 303 and the first cap insulating film 304 via the third barrier metal 305b.

The first lower electrode 31a is in contact with the buffer layer 332 at a part inside the opening of the first insulating barrier film 306 (first region 340a). On the other hand, the second lower electrode 31b is in contact with the buffer layer 332 in a part (second region 340b) inside the opening of the first insulating barrier film 306.

The first lower electrode 31a is in contact with the buffer layer 332 in the first region 340a of the opening provided in the first insulating barrier film 306, and also serves as a wiring on the semiconductor substrate 301. Similarly, the second lower electrode 31 b is in contact with the buffer layer 332 in the second region 340 b of the opening provided in the first insulating barrier film 306 and also serves as a wiring on the semiconductor substrate 301. Therefore, a Cu electrode serving as a Cu wiring can be applied to the first lower electrode 31a and the second lower electrode 31b, and the first resistance change element 30a and the second resistance change using the Cu electrode in the multilayer wiring structure on the CMOS substrate. The element 30b can be formed. When the first lower electrode 31a and the second lower electrode 31b also serve as wiring on the semiconductor substrate 201, the process of manufacturing the first resistance change element 30a and the second resistance change element 30b on the semiconductor substrate 301 can be simplified. . With the configuration as shown in FIG. 21, Cu atoms in the first lower electrode 31 a and the second lower electrode 31 b can be ionized and eluted into the solid electrolyte layer 331.

As shown in FIG. 21, the first resistance change element 30a and the second resistance change element 30b constitute a three-terminal resistance change switch that shares the upper electrode 32 and the resistance change layer 33 and uses the upper electrode 32 as a shared node. To do.

The resistance state of the first variable resistance element 30a depends on the voltage applied to the wiring connected to the first lower electrode 31a and the voltage applied to the wiring connected to the upper electrode 32 via the upper wiring 315. Change. The resistance state of the second variable resistance element 30b depends on the voltage applied to the wiring connected to the second lower electrode 31b and the voltage applied to the wiring connected to the upper electrode 32 via the upper wiring 315. The resistance state changes. That is, the resistance states of the first variable resistance element 30a and the second variable resistance element 30b that constitute the three-terminal variable resistance switch can be controlled independently of each other.

As shown in FIG. 21, in the three-terminal variable resistance element including the first variable resistance element 30a and the second variable resistance element 30b, the first lower electrode 31a and the second lower electrode 31b are provided as the lower electrodes. A part of the upper surface of the first lower electrode 31a is in contact with the buffer layer 332 in the first region 340a. A part of the upper surface of the second lower electrode 31b is in contact with the buffer layer 332 in the second region 340b. Part of the upper surface of each of the first lower electrode 31a and the second lower electrode 31b is separated from each other through the first cap insulating film 304 in the opening formed in the first insulating barrier film 306.

For example, when both the first lower electrode 31a and the second lower electrode 31b are made of a material containing Cu, the same structure as that of the lower electrode 21 of the semiconductor device 2 shown in FIG. Therefore, the first lower electrode 31 a and the second lower electrode 31 b can be formed by the same method as the lower electrode 21. If the first lower electrode 31a is the first electrode and the second lower electrode 31b is the third electrode, the first electrode and the third electrode are formed in the same layer, which is different from the first electrode and the third electrode. A second electrode can be formed on the layer.

As described above, in the semiconductor device of this embodiment, the two insulating trenches are formed in the second insulating layer. The first electrode is embedded in one of the two wiring grooves formed in the second insulating layer. A third electrode is embedded in the other of the two wiring grooves formed in the second insulating layer. The first electrode and the third electrode are spaced apart from each other across the second insulating layer in the opening, and are connected to the buffer layer.

In the present embodiment, the first protective layer and the second protective layer are provided, the side surface of the variable resistance layer is covered with the first protective layer, and the first protective layer is further covered with the second protective layer. Moisture absorption into the solid electrolyte layer is suppressed. As a result, according to the semiconductor device of the present embodiment, variation in element operation due to moisture absorption by the solid electrolyte layer is reduced, and variation in set voltage is suppressed. That is, according to the present embodiment, it is possible to provide a semiconductor device including a three-terminal variable resistance element in which moisture absorption of the variable resistance layer to the solid electrolyte layer is suppressed and variation in set voltage is reduced.

In each of the above embodiments, a semiconductor device having a CMOS circuit has been described, and an example in which a solid electrolyte switch element is formed in a multilayer wiring structure on a semiconductor substrate has been described. The semiconductor device of each embodiment can also be applied to semiconductor products having memory circuits such as DRAM, SRAM (Static RAM), flash memory, FeRAM (Ferro-Electric RAM), capacitor, and bipolar transistor. The semiconductor device of each embodiment can also be applied to a semiconductor product having a logic circuit such as a microprocessor. In addition, the semiconductor device of each embodiment can be applied to a metal wiring forming process of a board or package on which these semiconductor products are mounted. The technology of each embodiment can also be applied to a wiring formation process for connecting a semiconductor device to an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro-Electro-Mechanical Systems), or the like.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2018-044852 filed on Mar. 13, 2018, the entire disclosure of which is incorporated herein.

1, 2, 3 Semiconductor device 10

Resistance change element

11, 21

Lower electrode

12, 22, 32

Upper electrode

13, 23, 33 Resistance change layer 14 Insulating

barrier layer

15, 25, 35 First

protective layer

16, 26, 36 Second protective layer 17 Interlayer insulating film 18 Barrier metal 19 Hard mask layer 30a First resistance change element 30b Second resistance change element 31a First lower electrode 31b Second

lower electrode

131, 231, 331

Solid electrolyte layer

132, 232, 332

Buffer layer

201, 301

Semiconductor substrate

202, 302 First

interlayer insulating film

203, 303 Second

interlayer insulating film

204, 304 First cap insulating film 205

First barrier metal

206, 306 First insulating barrier film 207 First

hard mask Layer

208, 308 Second

hard mask layer

209, 309 Third

hard Disc layer

210, 310 First via

interlayer insulation film

211, 311 Third

interlayer insulation film

212, 312 Second

cap insulation film

213, 313

Second barrier metal

214, 314 Via

plug

215, 315

Upper wiring

216, 316 Second

insulation Barrier films

221 and 321 First

upper electrode

222 and 322 Second upper electrode 305a First barrier metal 305b Third barrier metal

Claims

A first electrode;
A first insulating layer disposed on the first electrode and having at least one opening formed therein;
A variable resistance layer disposed on the first insulating layer and connected to the first electrode inside the opening;
A second electrode disposed on the variable resistance layer;
A first protective layer covering a side surface of the variable resistance layer;
A semiconductor device comprising: a second protective layer that covers the first protective layer.
The first protective layer includes
The semiconductor device according to claim 1, wherein a side surface of the second electrode is covered.
The second protective layer is
The semiconductor device according to claim 1, wherein the semiconductor device is continuously covered from above the second electrode to an upper surface of the first insulating layer.
A second insulating layer disposed under the first insulating layer and having a wiring groove formed thereon;
The first electrode is
4. The semiconductor device according to claim 1, embedded in the wiring groove formed in the second insulating layer, and connected to the resistance change layer in the opening. 5.
The resistance change layer includes:
A buffer layer disposed from the inside to the periphery of the opening,
The semiconductor device according to claim 4, further comprising: a solid electrolyte layer disposed on the buffer layer.
The semiconductor device according to claim 5, wherein one end of the first protective layer is connected to a side surface of the buffer layer.
The first protective layer includes
The semiconductor device according to claim 5, comprising the same material as the buffer layer.
The buffer layer and the first protective layer are:
8. The semiconductor device according to claim 7, wherein the semiconductor device is formed of an oxide material containing at least one of a metal element having a negative energy larger than that of the material forming the first electrode and a nonmetal element belonging to Group 14. .
Two wiring grooves are formed in the second insulating layer,
The first electrode is embedded in one of the two wiring grooves formed in the second insulating layer;
A third electrode embedded in the other of the two wiring grooves formed in the second insulating layer;
The first electrode and the third electrode are:
The semiconductor device according to claim 5, wherein the opening is spaced apart with the second insulating layer interposed therebetween and connected to the buffer layer.
Forming a first electrode on the substrate;
Forming a first insulating layer on the upper surface of the first electrode;
Forming an opening in the first insulating layer to expose a portion of the upper surface of the first electrode;
Forming a buffer layer on the upper surface of the first insulating layer, including the inside of the opening,
Forming a solid electrolyte layer on the upper surface of the buffer layer;
Forming a second electrode on the upper surface of the solid electrolyte layer;
Forming at least one patterning mask on the upper surface of the second electrode;
Etching the second electrode, the solid electrolyte layer, and the buffer layer in order, and simultaneously exposing the exposed surface formed on the patterning mask, the buffer layer, the solid electrolyte layer, and the second electrode by etching. Forming a first protective layer on at least the exposed surfaces of the solid electrolyte layer and the buffer layer,
A method of manufacturing a semiconductor device, wherein a second protective layer is formed on a surface of the first protective layer.