JP2009065019A - Wiring structure, memory element and its fabrication method, and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure including a vertical connection layer of minute and flat surface, and having a configuration which selects a material suitable for a recording material in the lower electrode of a memory element having an ionization layer. <P>SOLUTION: A vertical connection layer 14 is formed in the trench 13 of a first insulating layer 1. The vertical connection layer 14 consists of a columnar proximal portion 14A buried in the trench 13, a columnar upper portion 14B having a cross sectional area smaller than that of the proximal portion 14A, and a frustoconical intermediate portion 14C. The front surface of a second insulating layer 15 and the front surface at the upper portion 14B of the vertical connection layer 14 form a common flat surface. The vertical connection layer 14 also serves as a lower electrode, and a storage layer 16 and an upper electrode 17 are laminated in this order on an insulating layer 12 and the upper portion 14B of the vertical connection layer 14. The upper portion 14B of the vertical connection layer 14 may have a minute and flat surface, while the proximal portion 14A may have a large diameter. There is no risk of occurrence of air gap thereby, and flatness of the front surface is assured. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a miniaturized wiring structure for a memory element, a memory element including the wiring structure, a method for manufacturing the memory element, and a memory device.

  In information devices such as computers, DRAM (Dynamic Random Access Memory), FeRAM (Ferroelectric Random Access Memory, ferroelectric memory) as nonvolatile memory, etc. are used. With the reduction in size, it has become difficult to ensure characteristics as a memory element. Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.

This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes. In this memory element, when a voltage is applied between two electrodes by including a metal contained in the ionic conductor in one of the two electrodes, the metal contained in the electrode is contained in the ionic conductor. By diffusing as ions, the electrical characteristics such as the resistance value or capacitance of the ionic conductor change. For example, Patent Document 1 and Non-Patent Document 1 describe a configuration of a memory device using this characteristic. In particular, Patent Document 1 proposes a configuration in which the ionic conductor is made of a solid solution of chalcogenite and metal. ing. Specifically, it is made of a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes contains Ag, Cu, Zn.
Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104)

By the way, when such elements are miniaturized and multilayered, a wiring structure is indispensable in an electric circuit. Conventionally, such a wiring structure is formed by the following method. That is, first, wiring-shaped grooves are formed in silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ), which is an insulating material, and further, when connecting upper and lower wirings in a multilayer structure, A hole to be a wiring structure (plug) in the direction is formed. Then, a conductive material such as aluminum (Al), copper (Cu), or tungsten (W) is deposited on the entire wafer surface including the groove or hole by a technique such as CVD (Chemical Vapor Deposition) or plating. Then, using a method such as CMP (Chemical Mechanical Polish), the conductive material other than the groove or hole is polished and removed, and the vertical wiring portion is flattened and the roughness is improved.

  FIG. 7 shows a conventional multilayer wiring structure formed by such a method. In this wiring structure, the insulating layer 102 is laminated on the lower wiring layer 101. A groove 102A reaching the wiring layer 101 is provided in the insulating layer 102, and a vertical connection layer (plug) 104 is embedded in the groove 102A with a barrier metal layer 103 therebetween. An upper wiring layer 105 is formed on the vertical connection layer 104 and the insulating layer 102. The memory element as described above is formed by laminating a memory layer and an upper electrode layer (not shown) in this order on the vertical connection layer 104 and the wiring layer 105 as a lower electrode.

  By the way, in the memory element having the structure in which the recording element is directly arranged on the upper surface of the vertical wiring (plug) in this way, the lower electrode material affects the memory characteristics. Therefore, the vertical connection layer 104 corresponding to the lower electrode and the wiring For the material of the layer 105, a process or structure capable of selecting any material according to the recording material is desired. However, in the conventional method, the material used for the vertical connection layer 104 in particular from the viewpoint of electrical characteristics such as low specific resistivity and the ease of depositing the material in the wiring groove or hole in the production process, It is limited to Al, W, Cu, etc. as described above, and it is difficult to use an arbitrary material.

  In addition, the memory element is often formed by a laminated structure of ultrathin films, and it is desired that the surface serving as a base, that is, the surface of the wiring layer 105 is flat. However, as the aspect ratio increases with miniaturization, the embedding material in the groove 102A is likely to adhere to the wall surface, and the upper surface is blocked. As a result, voids 106 are likely to be generated inside the vertical connection layer 104. . The gap 106 is also exposed on the surface of the vertical connection layer 104 as shown in FIG. Then, due to the influence of the gap 106, a recess 105A and a hole are formed on the surface of the wiring layer 105. Therefore, conventionally, there has been a problem that it is difficult to ideally form a thin film laminated structure of a recording material. It is considered that the problem due to the generation of the void 106 will become more prominent as the miniaturization progresses.

  The present invention has been made in view of such problems, and a first object thereof is a material having a vertical connection layer having a fine and flat surface and suitable as a recording material as a lower electrode of the above storage element. It is an object to provide a wiring structure having a configuration capable of selecting a memory element, a memory element and a memory device provided with the wiring structure.

  A second object of the present invention is to provide a method for manufacturing a memory element that can easily produce a memory element having the above wiring structure.

  The wiring structure of the present invention is a wiring structure for forming a memory element, and includes a wiring layer, a first insulating layer formed on the wiring layer and having a groove reaching the wiring layer, and at least part of the wiring structure is in the groove. It has a buried columnar base and a columnar upper portion having a smaller cross-sectional area than the base, and a vertical connection layer serving as one electrode of the memory element, and a surface of the upper portion of the vertical connection layer that covers the first insulating layer And a second insulating layer forming a common flat surface.

  Further, the memory element of the present invention has a laminated structure including a memory layer including an ionized layer and the other electrode on the vertical connection layer (lower electrode) of the wiring structure of the present invention.

  Furthermore, the memory device of the present invention has one electrode provided in the wiring structure, a memory layer including an ionization layer, and the other electrode in this order, and a plurality of information that stores information by changing electrical characteristics of the memory layer. A storage element and pulse applying means for selectively applying a voltage or current pulse to a plurality of storage elements are provided, and the wiring structure of the present invention is provided as a wiring structure.

  The method for manufacturing a memory element of the present invention includes a step of forming a first insulating layer on a wiring layer, forming a groove reaching the wiring layer in the first insulating layer, and electrically connecting the wiring layer in the groove. Forming a connected base portion, forming a columnar upper portion on the base portion having a cross-sectional area smaller than that of the base portion and forming a vertical connection layer that forms one electrode of the memory element together with the base portion; Forming a second insulating layer on the layer, and performing a planarization treatment so that a surface of the second insulating layer forms a common flat surface with the upper surface; and on the vertical connection layer and the second insulating layer Forming a memory layer including an ionization layer and the other electrode in this order.

  According to the wiring structure, the memory element, the manufacturing method thereof, and the memory device of the present invention, the upper portion of the vertical connection layer is finely processed, and the upper surface forms a common flat surface with the adjacent first insulating layer. As a result, the base portion can be of any size with a large diameter, that is, the aspect ratio can be reduced, so that there is no risk of voids occurring in the manufacturing process, and flatness in the fine upper portion can be ensured. And a memory element made of an ultrathin film can be stably formed thereon.

  In addition, as a method for forming (depositing) the vertical wiring layer, various methods such as a sputtering method can be used without being limited to the conventional CVD method and plating method, and the memory element including the ionized layer can be used. It is possible to select a material suitable for the recording material as the lower electrode, thereby improving the characteristics of the memory element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a cross-sectional configuration of a memory element having a wiring structure according to the first embodiment of the present invention. In this wiring structure, a first insulating layer 12 made of, for example, SiO2 is formed on a wiring layer 11 made of, for example, Al or Cu, and a columnar, for example, cylindrical groove reaching the wiring layer 11 is formed in the first insulating layer 12. 13 is provided. A longitudinal connection layer (plug) 14 is formed in the groove 13.

  The vertical connection layer 14 includes, for example, a columnar base portion 14A embedded in the groove 13, a columnar upper portion 14B having a smaller cross-sectional area than the base portion 14A, and a space between the base portion 14A and the upper portion 14B. It is comprised by the intermediate part 14C of the truncated cone shape to connect. The first insulating layer 12 is covered with a second insulating layer 15, and the surface of the second insulating layer 15 and the surface of the upper portion 14 </ b> B of the vertical connection layer 14 form a common flat surface. The vertical connection layer 14 also serves as the lower electrode of the memory element 1, and the memory layer 16 and the upper electrode 17 are stacked in this order on the vertical connection layer 14 and the second insulating layer 15. That is, the vertical connection layer (lower electrode) 14, the memory layer 16, and the upper electrode 17 constitute the memory element 1.

  The vertical connection layer (lower electrode) 14 constituting the memory element 1 has a wiring material used in a semiconductor process, such as W (tungsten), WN (tungsten nitride), Cu (copper), Al (aluminum), Mo ( Molybdenum), Ta (tantalum), silicide, and the like can be used.

  The memory layer 16 includes a high resistance layer 16A and an ionization layer 16B that are stacked in this order from the longitudinal connection layer 14 side. The ionized layer 16B contains Cu (copper) and Zr (zirconium) as a metal element (which can be ionized) together with an ion conductive material. Examples of the ion conductive material include S (sulfur), Se (selenium), and Te (tellurium) (chalcogenide element), and these elements may be used alone or in combination of two or more.

  As the high resistance layer 16A, any material can be used as long as it is an insulator or a semiconductor that is stable even if it is in contact with the ionized layer 16B made of Cu-chalcogenide, but preferably a rare earth element such as Gd (gadolinium), An oxide or nitride containing at least one of Al, Mg (magnesium), Ta, Si (silicon), and Cu is preferable.

  The upper electrode 17 is made of the same semiconductor wiring material as that of the lower electrode.

  In the memory element 1 of the present embodiment, when a predetermined voltage pulse or current pulse is applied from a power source (pulse applying means) (not shown) through the vertical connection layer (lower electrode) 14 and the upper electrode 17 through the wiring structure, The electrical characteristics of the storage layer 16, for example, the resistance value changes, whereby information is stored, erased, and further read. The storage device of the present invention can be configured by arranging a large number of such storage elements 1, for example, in a matrix.

  Next, with reference to FIG. 2 and FIG. 3, the manufacturing method of the memory element 1 provided with the said wiring structure is demonstrated.

  First, as shown in FIG. 2A, on the wiring layer 11 made of Al or Cu, for example, silicon oxide (SiO2) or silicon nitride is formed by, for example, CVD (Chemical Vapor Deposition). A first insulating layer 12 made of (SiN) is formed. Subsequently, using the resist layer (not shown) as a mask, the wiring layer 11 is exposed by, for example, RIE (Reactive Ion Etching) method, IM (Ion Milling) method, wet etching method, or the like. The first insulating layer 12 is selectively removed until a cylindrical groove 13 having a diameter of, for example, 300 nmφ is formed. Then, for example, tungsten (W) is buried in the groove 13 by, for example, a CVD method, a plating method, or a sputtering method to form a layer 18 serving as a vertical connection layer.

  Subsequently, a first resist layer 19 made of, for example, a photoresist for an exposure apparatus using ultraviolet rays or an EB (Electron Beam) resist for electron beam drawing using an electron beam is formed on the layer 18. Then, it is patterned into a fine shape, for example, a cylindrical shape with a diameter of 50 nmφ.

  Subsequently, as shown in FIG. 2B, using the patterned first resist layer 19 as a mask, the first insulating layer 12 and a part of the vertical connection layer 14 are removed by the IM method. As a result, the upper portion of the layer 18 is processed into a fine cylindrical shape to which the surface (shape) where the mask is in contact with the layer 18 is transferred to become the upper portion 14B of the vertical connection layer 14 and the base portion 14A. A frustoconical intermediate portion 14C is formed. The RIE method can also be used as the processing method here.

  When performing the ion milling process, the sample (wafer) is rotated so that ions are incident on the object from a 360 ° direction in a certain time. At this time, the ion incident angle is oblique, specifically, a constant angle in the range of 30 ° to 75 ° when the ion incident angle is zero in the direction perpendicular to the wafer surface.

Incidentally, when the ion incident angle is set to 50 °, from the observation result by AFM (Atomic Force Microscope), the height of the finely processed upper portion 14B of the longitudinal connection layer 14 is about 30 nm, for example. I understood. Further, a step of about 60 nm was generated between the upper portion 14B of the vertical connection layer 14 and the first insulating layer 12. This is because the etching rate of the material (SiO ₂ ) of the first insulating layer 12 is higher than the wiring material (for example, W) of the vertical connection layer 14.

Next, as shown in FIG. 2C, a second insulating layer made of, for example, SiO ₂ , SiN, Al ₂ O ₃ or the like so as to cover the first insulating layer 12 and the longitudinal connection layer 14 by, eg, CVD. 15 is formed. The film thickness of the second insulating layer 15 is set such that the step amount between the upper part 14B of the vertical connection layer 14 and the first insulating film 12 is a lower limit, and no upper limit is provided. For example, when the amount of the step is 60 nm, the thickness of the second insulating layer 15 is set to 60 nm or more.

  Next, as shown in FIG. 3A, a second layer made of, for example, a photoresist or an EB resist is formed on the second insulating layer 15 (wafer surface) by a spin coating method using a coating apparatus such as a spin coater. A resist layer 20 is formed. Here, as a resist material used for the second resist layer 20, it is possible to cover even a very narrow region of the uneven surface without gaps, and selection of a viscosity that has a thickness enough to completely cover the uneven step amount. It can be easily performed, the surface of the resist has no irregularities, and it is easy to form (apply) a smooth shape, and the etching rate balance between the insulating material of the second insulating layer 15 and the resist material of the second resist layer 20 is equal. Alternatively, it is desirable that the resist material has an etching rate higher than that of the insulating material.

  Next, as shown in FIG. 3B, the upper surface 14B of the vertical connection layer 14 and the surface of the second insulating layer 15 are planarized by a resist etch back method. In the present embodiment, the second resist layer 20 formed on the second insulating layer 15 is removed by the IM method. This ion milling process is performed until the resist is completely removed in the convex portion where the resist is applied to the thickest. At this time, the concavo-convex shape on the second insulating layer 15 is flattened by etching the insulating material portion on the vertical connection layer 14 simultaneously with the second resist layer 20.

  When the etching rates of the resist material of the second resist layer 20 and the insulating material of the second insulating layer 15 are the same, the surface of the second insulating layer 15 is removed when the resist in the thickest portion of the resist layer 20 is used up. Becomes a flat state. On the other hand, when the insulating material of the second insulating layer 15 is lower than the resist of the second resist layer 20 with respect to the etching rate, a reduction amount of the step corresponding to the ratio can be obtained. For example, when the etching rate is resist material> insulating material and the ratio is 2: 1, when the remaining film of the second resist layer 20 becomes zero, the second insulating layer 15 and the second resist layer 20 The step amount is ½ of the initial value. In this case, by repeating the steps such as resist application and removal in the same manner as described above, the amount of the step can be reduced according to the number and the ratio. Note that it is possible to grasp the remaining amount of the resist and calculate the amount of variation in the step by checking the etching rates of the resist material and the insulating material in advance.

  Further, the angle dependency of the etching rate by the ion milling process differs depending on the material to be etched. Although the etching rate of each material used for the second insulating layer 15 and the second resist layer 20 has upper and lower limits, by using this angle-dependent characteristic, an angle or a ratio at which the etching rate is equivalent between different materials can be set. Can be selected.

  Next, the surface of the flattened second insulating layer 15 is further thinned uniformly by continuing the same etching process, and an exposed surface of the upper portion 14B of the vertical connection layer 14 is obtained. At this time, by matching the etching rate of the insulating material of the second insulating layer 15 and the wiring material of the upper portion 14B of the vertical connection layer 14 in accordance with conditions such as the material and the etching angle, the second insulating layer 15 and the vertical connection layer As a result, there is no unevenness at the boundary portion of the upper portion 14B of 14 and a flat surface can be formed. Incidentally, in the observation result by AFM, the unevenness at the boundary portion between the second insulating layer 15 and the upper portion 14B of the vertical connection layer 14 could be suppressed to about 1 nm.

  Subsequently, as shown in FIG. 1, a high resistance layer 16A made of, for example, a Gd oxide film is formed. For example, after forming a metal Gd film with a film thickness of, for example, 1 nm using a Gd target, the film is oxidized by oxygen plasma. Next, an ionization layer 16B, for example, a CuTeSiZr film is formed by DC magnetron sputtering. Finally, for example, a W film is formed as the upper electrode 17. In this manner, the memory element 1 having the wiring structure of the present embodiment can be formed.

  As described above, in the present embodiment, the large-diameter vertical connection layer 14 is formed in advance and the upper portion of the vertical connection layer 14 is processed. Therefore, the upper portion 14B can be formed finely and flatly. Therefore, the memory element 1 made of an extremely thin film can be stably formed thereon. Further, since the base portion 14A has a large-diameter columnar shape, that is, the aspect ratio can be reduced, there is no possibility of generating voids as described in the prior art, and flatness in the fine upper portion 14B is ensured. be able to.

  Further, in the present embodiment, the method of forming (depositing) the wiring material of the vertical connection layer 14 is not limited to the CVD method or the plating method used in a general semiconductor process, but a sputtering method, A wide variety of methods can be used, and any material suitable for the material of the memory layer 16 can be selected in the selection of the material, which improves the characteristics of the memory element 1.

  Furthermore, in this embodiment, since the planarization process by resist etch back (FIGS. 3A and 3B) is performed, even when an arbitrary material is used for the vertical connection layer 14, It is possible to avoid the formation of a recess or the like between the peripheral insulating material and a flattening process with high control accuracy. As a result, the thickness of the thin film becomes uniform at the boundary between the steps, and it becomes possible to form a material in an ultrathin film region of several nanometers, and to form a thin insulating film in the same manner as between the stacked layers. Further, since there is no need to combine many elemental technologies as in the smoothing technology by the CMP method, the manufacturing process is simplified.

  Next, a second embodiment of the present invention will be described with reference to FIGS. Note that the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, a fine connection portion having a small diameter is formed by processing the upper portion 14B of the vertical connection layer 14, but in this embodiment, as shown in FIG. The upper portion 24B of the connection layer 24 is formed in a separate process from the base portion 24A.

  Specifically, a first insulating layer 22 is laminated on the wiring layer 21, and a cylindrical groove 23 reaching the wiring layer 21 is formed inside the first insulating layer 22. A base 24A of the vertical connection layer 24 is embedded in the groove 23, and a cylindrical upper portion 24B having a smaller diameter than the base 24A is formed on the base 24A. A vertical connection layer 24 is constituted by the base portion 24A and the upper portion 24B. The first insulating layer 22 is covered with a second insulating layer 25, and the surface of the second insulating layer 25 forms a common flat surface with the surface of the upper portion 24B.

  The vertical connection layer 24 also serves as the lower electrode of the memory element 2, and the memory layer 16 and the upper electrode 17 are stacked in this order on the upper portion 24 </ b> B of the vertical connection layer 24. As described above, the vertical connection layer (lower electrode) 24, the memory layer 16, and the upper electrode 17 constitute the memory element 2.

Next, a method for manufacturing the memory element 2 having the above wiring structure will be described with reference to FIGS. First, as shown in FIG. 5A, a first insulating layer 22 made of, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN) is formed on the wiring layer 21 made of Al or Cu by, for example, a CVD method. Form. Subsequently, by using the resist layer (not shown) as a mask, the first insulating layer 22 is selectively removed by, for example, the RIE method, the IM method, the wet etching method, or the like until the wiring layer 21 is exposed, for example, the diameter. A cylindrical groove 23 of 300 nmφ is formed. Then, for example, tungsten (W) is buried in the groove 23 by, for example, a CVD method, a plating method, or a sputtering method to form the base portion 24A of the vertical connection layer 24.

  Subsequently, a wiring material layer 26 is formed on the entire surface of the first insulating layer 22 and the base 24A. As a film forming method, besides the CVD method and the plating method, a method such as a sputtering method can be easily used, and the material is not limited to Al, W, Cu, and any material can be used. it can.

  Subsequently, a pattern of a first resist layer 27 made of, for example, a photoresist or an EB resist is selectively formed in a region corresponding to the base 24A on the wiring material layer 26. The shape of the first resist layer 27 at this time is such that the shape of the surface in contact with the wiring material layer 26 is a cylindrical shape having a small diameter, for example, a diameter of 50 nmφ.

  Subsequently, as shown in FIG. 5B, using the first resist layer 27 as a mask, a part of the wiring material layer 26 and the first insulating layer 22 is selectively removed by the IM method, and the vertical connection layer 24 is removed. Forming an upper portion 24B of the. As a result, the vertical connection layer 24 including the finely processed upper portion 24B is formed on the base portion 24A.

Next, as shown in FIG. 5C, the second insulating layer 25 made of, for example, SiO ₂ , SiN, Al ₂ O ₃ so as to cover the first insulating layer 22 and the longitudinal connection layer 24 by, eg, CVD. Form. The film thickness of the second insulating layer 25 is, for example, about 90 nm or more when the step difference between the vertical connection layer 24 and the first insulating layer 22 is 90 nm at the maximum.

  Next, as shown in FIGS. 6A and 6B, a second resist layer 28 made of, for example, a photoresist or an EB resist is formed on the wafer surface by, for example, a spin coating method, and the first embodiment ( A flattening process similar to that in FIGS. 3A and 3B is performed.

  Subsequently, as shown in FIG. 4, the high resistance layer 16 </ b> A, the ionization layer 16 </ b> B, and the upper electrode 17 are sequentially formed on the upper portion 24 </ b> B of the vertical connection layer 24 and the second insulating layer 25 to form the memory element 2. To do.

  As described above, in this embodiment, the base 24A and the upper portion 24B of the vertical connection layer 24 are separated, and the upper portion 24B is formed on the entire surface of the base material 24A and the first insulating layer 22 after the wiring material layer 26 is formed. Since the wiring material layer 26 is formed by selectively removing it, the method of forming the wiring material layer 26 (upper part 24B) is not limited to the CVD method or the plating method. This method can also be used. Further, the wiring material is not limited to Al, W, Cu or the like, and any material can be used. Thereby, in the memory structure in which the longitudinal connection layer 24 is the lower electrode of the recording element 2, the lower electrode material can be easily selected for the recording material for the purpose of improving the memory characteristics.

  Other effects are the same as those of the first embodiment. In the method of the present embodiment, the size of the upper portion 24B can be arbitrarily set according to the size of the memory element, and can be, for example, equal to or larger than the base portion 24A. is there.

  Although the present invention has been described above by the embodiments, the present invention is not limited to the above embodiments and can be variously modified. For example, other materials, film thicknesses, film forming methods, etc. are selected in each layer. You may make it do.

It is sectional drawing showing the memory element provided with the wiring structure which concerns on the 1st Embodiment of this invention. It is sectional drawing showing the manufacturing method of the said memory element for every process. FIG. 3 is a diagram illustrating a process following FIG. 2. It is sectional drawing showing the memory element provided with the wiring structure which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing the manufacturing method of the said memory element for every process. It is a figure showing the process of following FIG. It is sectional drawing showing the conventional wiring structure.

Explanation of symbols

11, 21 ... wiring layer, 12, 22 ... first insulating layer, 13, 23 ... groove, 14, 24 ... longitudinal connection layer (lower electrode), 14A, 24A ... base, 14C ... intermediate part, 14B, 24B ... upper part , 15, 25 ... second insulating layer, 16 ... memory layer, 17 ... upper electrode, 18 ... layer serving as a vertical connection layer.

Claims (8)

A wiring structure for forming a memory element,
A wiring layer;
A first insulating layer formed on the wiring layer and having a groove reaching the wiring layer;
A columnar base portion at least partially embedded in the groove, and a columnar upper portion having a smaller cross-sectional area than the base portion, and a vertical connection layer serving as one electrode of the memory element;
A second insulating layer covering the first insulating layer and forming a common flat surface with the upper surface of the vertical connection layer;
A wiring structure characterized by comprising: A storage element having a wiring structure,
The wiring structure is
A wiring layer;
A first insulating layer formed on the wiring layer and having a groove reaching the wiring layer;
A columnar base portion at least partially embedded in the groove, and a columnar upper portion having a smaller cross-sectional area than the base portion, and a vertical connection layer serving as one electrode of the memory element;
A second insulating layer covering the first insulating layer and forming a common flat surface with the upper surface of the vertical connection layer;
A memory element having a laminated structure including a memory layer including an ionization layer and the other electrode on the vertical connection layer and the second insulating layer. The vertical connection layer includes a columnar base portion at least partially embedded in the groove, a columnar upper portion having a smaller cross-sectional area than the base portion, and a truncated cone shape connecting between the base portion and the upper portion. The memory element according to claim 2, comprising: an intermediate portion. The memory element according to claim 2, wherein the vertical connection layer includes a columnar base portion embedded in the groove and a columnar upper portion having a smaller cross-sectional area than the base portion. A plurality of storage elements each having one electrode provided in the wiring structure, a storage layer including an ionization layer, and the other electrode in this order, and storing information by a change in electrical characteristics of the storage layer, and the plurality of storages A storage device comprising pulse applying means for selectively applying a voltage or current pulse to the element,
The wiring structure is
A wiring layer;
A first insulating layer formed on the wiring layer and having a groove reaching the wiring layer;
A columnar base portion at least partially embedded in the groove, and a columnar upper portion having a smaller cross-sectional area than the base portion, and a vertical connection layer serving as one electrode of the memory element;
A second insulating layer covering the first insulating layer and forming a common flat surface with the upper surface of the vertical connection layer;
And a storage device. A method of manufacturing a memory element having a wiring structure,
Forming a first insulating layer on the wiring layer, and forming a groove reaching the wiring layer in the first insulating layer;
A base portion electrically connected to the wiring layer is formed in the groove, and a vertical connection is formed on the base portion so that a cross-sectional area is smaller than the base portion and serves as one electrode of the memory element together with the base portion. Forming a columnar upper portion constituting the layer;
Forming a second insulating layer on the first insulating layer, and performing a planarization process so that a surface of the second insulating layer forms a flat surface common to the upper surface;
Forming a memory layer including an ionization layer and the other electrode in this order on the vertical connection layer and the second insulating layer. After embedding a conductive material in the groove,
Forming a layer to be the vertical connection layer by performing a planarization process, and then forming a first resist layer having a cross section having a smaller cross-sectional area than the layer on the layer to be the vertical connection layer;
Forming the upper and middle portions of the vertical connection layer and forming the base of the vertical connection layer by selectively removing the layer using the first resist layer as a mask;
Forming a second resist layer on the entire surface of the second insulating layer after forming a second insulating layer on the vertical connection layer and the first insulating layer;
The method according to claim 6, further comprising: performing a planarization process using the second resist layer and the second insulating layer to expose an upper surface of the vertical connection layer. Method. After embedding a conductive material in the groove,
Forming a wiring material layer on the base and the first insulating layer after performing a planarization process to form the base of the vertical connection layer; and
Forming a first resist layer having a cross section with a smaller cross-sectional area than the base at a position corresponding to the base on the wiring material layer;
Forming the upper portion of the vertical connection layer by selectively removing the wiring material layer using the first resist layer as a mask;
Forming a second resist layer on the entire surface of the second insulating layer after forming a second insulating layer on the vertical connection layer and the first insulating layer;
The method according to claim 6, further comprising: performing a planarization process using the second resist layer and the second insulating layer to expose an upper surface of the vertical connection layer. Method.

Images