JP2016192510A - Resistance change element and formation method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change element having reduced leak current in the OFF state and improved breakdown voltage at the time of reset.SOLUTION: A variable-resistance element includes: a first electrode 1; a second electrode 2; and a resistance change layer 3 provided between the first electrode and second electrode. The resistance change layer 3 is composed of: a buffer layer 4 in contact with the first electrode 1; and a solid electrolyte layer 5 in contact with the second electrode 2. The first electrode 1 has a structure including copper; and ionizes the copper when voltage is applied between the first electrode and second electrode, and injects the ionized copper into the buffer layer and solid electrolyte layer. The buffer layer 4 is made from oxide of valve metal having oxidation free energy negatively larger than that of copper; and has a structure in which a first metal oxide layer 6 and second metal oxide layer 7 are provided in this order from the side closer to the first electrode, where the second metal oxide layer 7 is a passive layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a resistance change element and a method for forming the same.

Semiconductor devices (particularly silicon devices) have been developed at a pace of three years, with the integration and low power consumption of the devices being advanced by miniaturization (scaling law: Moore's law). In recent years, the gate length of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has become 20 nm or less, so far due to soaring lithography process (apparatus price and mask set price), and physical limits of device dimensions (operation limits and dispersion limits). There is a need to improve device performance with an approach different from the scaling law.
Examples of the functional element formed inside the copper multilayer wiring structure on the semiconductor device include a resistance variable nonvolatile element (hereinafter referred to as “resistance variable element”) and a capacitor (capacitance element).
Examples of capacitors embedded on a logic LSI (Large Scale Integration) include an embedded DRAM (Dynamic Random Access Memory) and a decoupling capacitor. By mounting these capacitors on the copper wiring, it is possible to increase the capacity and area of the capacitor.
A device called FPGA (Field Programmable Gate Array) has been developed as an intermediate position between the gate array and the standard cell. This makes it possible for the customer himself to perform an arbitrary circuit configuration after manufacturing the chip. As the programmable element, a resistance change element or the like is interposed in the wiring connection portion, so that the customer himself can arbitrarily connect the wiring. By using such a semiconductor device, the degree of freedom of the circuit can be improved.

A resistance change element is a generic term for elements that store information by changing a resistance state, and has a three-layer structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode, and a voltage is applied between the two electrodes. This utilizes the phenomenon that the resistance change of the resistance change layer occurs. Examples of the resistance change element include ReRAM (Resistive RAM) using a metal oxide as a resistance change layer, and a solid electrolyte switch element using a solid electrolyte.
Several studies on solid electrolyte switch elements have been reported since the latter half of the 1990s, and resistance change phenomena due to various solid electrolyte materials have been confirmed. For example, Non-Patent Document 1 and Non-Patent Document 2 report a resistance change phenomenon using a chalcogenide compound.
The structure and switching operation of the solid electrolyte switch element will be briefly described below.

The solid electrolyte switch element has a structure in which a solid electrolyte layer is sandwiched between two electrodes (a lower electrode and an upper electrode). Here, one of the two electrodes is chemically active, a metal that can be easily oxidized and reduced by voltage application is used, and a chemically inactive metal material is used for the other electrode. .
Next, the operation of the solid electrolyte switch element will be described. Here, as an example, a chemically active electrode is used as the lower electrode.
For example, in a solid electrolyte switch element in an off state (high resistance state), when the lower electrode (chemically active electrode) is grounded and a negative voltage is applied to the upper electrode (chemically inactive electrode), Metal atoms constituting the electrode are ionized and eluted into the solid electrolyte layer, and conductive metal bridges are formed. When both electrodes are electrically connected by the metal bridge formed in the solid electrolyte, the switch is turned on (low resistance state). The operation of changing from the off state to the on state by applying this voltage is called a set.
On the other hand, in the ON state, when the lower electrode is grounded again and a positive voltage is applied to the upper electrode, the metal bridge dissolves, the metal atoms are pulled back to the lower electrode, and both electrodes are electrically insulated. The switch changes to the high resistance OFF state. The operation of changing from the on state to the off state by applying a positive voltage is called reset, and the set and reset are collectively called programming.
As described above, the solid electrolyte switch element is nonvolatile between the on state and the off state, and can be repeatedly programmed. By utilizing this characteristic, it can be applied to a nonvolatile memory or a nonvolatile switch. .

  An example of a memory element using a solid electrolyte is disclosed in Patent Document 1. The memory element disclosed in Patent Document 1 has a configuration in which a memory layer in which a resistance change layer and an ion source layer are stacked is provided between a lower electrode and an upper electrode. When the configuration of the memory element is compared with the configuration of the solid electrolyte switch element, the resistance change layer corresponds to a solid electrolyte layer, and the ion source layer corresponds to an electrode that supplies metal ions. The memory element disclosed in Patent Document 1 has a configuration in which the upper and lower structures of the above solid electrolyte switch element are reversed.

  In application of the solid electrolyte switch element to a nonvolatile memory and a nonvolatile switch, it is preferable that the OFF state has a lower leakage current, that is, a higher resistance. Therefore, in order to increase the resistance in the OFF state, generally, a higher positive voltage is applied during the reset operation. However, when a high reset voltage higher than a certain voltage is applied, dielectric breakdown occurs in the solid electrolyte layer, and the resistance change does not show any more while transitioning to a lower resistance state than the normal ON state. This voltage is called a dielectric breakdown voltage. Therefore, a high reset voltage can be applied and a higher resistance OFF state can be obtained by designing and manufacturing the element so that the dielectric breakdown voltage becomes high.

A method of forming these inside the copper multilayer wiring on the semiconductor device is known. For example, Patent Document 2 and Patent Document 3 disclose a two-terminal solid electrolyte switch element provided in a copper multilayer wiring structure on a CMOS substrate and a method for manufacturing the same. In Patent Document 2 and Patent Document 3, an active electrode for supplying metal ions into a solid electrolyte is formed by exposing a copper wiring itself exposed by opening a part of an insulating layer in a copper multilayer wiring structure on a CMOS substrate. To produce a two-terminal solid electrolyte switch element.
In manufacturing a solid electrolyte switch element, when a copper electrode is used as the lower electrode, if the surface of the copper electrode is oxidized, variation in leakage current in the off state increases. Furthermore, the breakdown voltage at the time of reset is reduced. A method for solving this problem is disclosed in Non-Patent Document 3. In Non-Patent Document 3, in the stacking of solid electrolyte switch elements, a metal having a negative oxidation free energy larger than that of copper is used as valve metal to prevent oxidation of the copper surface between the lower electrode copper and the solid electrolyte layer. It is proposed that the element be provided with a buffer structure that suppresses copper oxidation by oxidizing the valve metal.

JP 2011-187925 A JP 2011-091317 A International Publication No. 2010/0779816

M. N. Kozicki, et al. , "Information storage using nanoscale electrodeposition of metal in solid electorates", Superstratics and Microstructures, Vol. 34, p. 459-465, 2003 R. Waser, et al. , "Nanoionics-based reactive switching memories", Nature Materials, Vol. 6, p. 833-840, 2007 M.M. Tada, et al. , "Improved ON-State Reliability of Atom Switching Using Electrodes", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 10, p. 3534-3540, 2013

  In the resistance change element disclosed in Non-Patent Document 3, the valve metal works favorably in order to suppress oxidation of the surface of the copper electrode. When the inventors conducted a detailed study including variations relating to device characteristics using a large-scale variable resistance element array, a portion of the valve metal constituting the buffer layer remained as a metal component without being oxidized. It was observed that an increase in leakage current occurred. On the other hand, in order to solve the problem, it was found that when the valve metal was completely oxidized, the surface of the copper electrode was oxidized and the dielectric breakdown voltage at the time of resetting decreased.

  The present invention has been made in order to solve the above-described problems of the technology, and provides a resistance change element and a method of forming the same that reduce a leakage current in an off state and improve a breakdown voltage at reset. The purpose is to provide.

In order to achieve the above object, a variable resistance element according to the present invention is a variable resistance element having a first electrode, a second electrode, and a variable resistance layer provided between the first electrode and the second electrode. ,
The variable resistance layer includes a buffer layer in contact with the first electrode and a solid electrolyte layer in contact with the second electrode.
The first electrode is configured to include copper, and when a voltage is applied between the first electrode and the second electrode, copper is ionized and injected into the buffer layer and the solid electrolyte layer,
The buffer layer is made of a valve metal oxide having a negative oxidation free energy larger than that of copper, and a first metal oxide layer and a second metal oxide layer are provided in order from the side closer to the first electrode. Configuration,
The second metal oxide layer is a passive layer.

Moreover, the method of forming the resistance change element of the present invention includes:
Forming a first electrode containing copper on the substrate;
Forming an insulating barrier film having an opening exposing a part of the upper surface of the first electrode on the first electrode;
A first metal layer that is a film containing a first metal and a second metal layer that is a film containing a second metal are sequentially deposited on the insulating barrier film including the opening,
After depositing the second metal layer, the first metal layer and the second metal layer are oxidized without being exposed to the atmosphere to form a first metal oxide layer and a second metal oxide layer,
After the oxidation treatment, heat treatment is performed under reduced pressure at a temperature higher than the deposition temperature of the second metal layer, to convert the second metal oxide layer into a passive layer,
A solid electrolyte layer and a second electrode are sequentially formed on the second metal oxide layer.

  According to the present invention, it is possible to reduce the leakage current in the off state and improve the dielectric breakdown voltage at the time of reset.

It is a fragmentary sectional view showing an example of 1 composition of a resistance change element of a 1st embodiment. It is a fragmentary sectional view showing an example of 1 composition of a resistance change element of a 2nd embodiment. It is the fragmentary sectional view which showed typically the structure by which the resistance change element of 3rd Embodiment was provided in the inside of the multilayer wiring structure on a semiconductor substrate. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a fragmentary sectional view for demonstrating the manufacturing method for providing the inside of the multilayer wiring structure on a semiconductor substrate about the resistance change element of 3rd Embodiment. It is a table | surface which shows the off-leakage current measurement result at the time of 1V application about the resistance change element of Example 1, and a comparative example. It is a table | surface which shows the dielectric breakdown voltage measurement result at the time of reset about the resistance change element of Example 1, and a comparative example. It is the fragmentary sectional view which showed typically the structure by which the 3 terminal type resistance change element of Example 3 was provided in the inside of the multilayer wiring structure on a semiconductor substrate.

Before describing embodiments of the present invention in detail, the meanings of terms used in the specification will be described.
The semiconductor substrate includes a substrate on which a semiconductor element including a MOS transistor and a resistance element and a semiconductor device in which these semiconductor elements are combined are configured. The semiconductor substrate also includes a substrate such as a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, or a liquid crystal manufacturing substrate.
The plasma CVD (Chemical Vapor Deposition) method is, for example, a gas material or a liquid material vaporized continuously supplied to a reaction chamber under reduced pressure, and the molecules are excited by plasma energy to cause a gas phase reaction. Alternatively, a continuous film is formed on the substrate by a substrate surface reaction or the like.
The CMP (Chemical Mechanical Polishing) method is a method of flattening the unevenness of the wafer surface that occurs during the multilayer wiring formation process by bringing the polishing liquid into contact with a rotating polishing pad while flowing the polishing liquid over the wafer surface and polishing it. . The CMP method is used not only for polishing and planarizing an interlayer insulating film, but also for forming a buried wiring called a damascene wiring. A method of forming damascene wiring will be briefly described in the case of using copper (Cu) as a wiring material. Cu is formed on the insulating film in which the groove is formed in advance. Thereafter, by the CMP method, the Cu buried in the trench is left, and excess Cu on the insulating film is polished and removed. In this way, a damascene wiring in which Cu is embedded in the groove is formed.

The barrier metal refers to a conductive film having a barrier property that covers the side and bottom surfaces of the wiring in order to prevent the metal elements constituting the wiring from diffusing into the interlayer insulating film or the lower layer. For example, when the material constituting the wiring is a metal mainly composed of Cu, a refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), or the like A nitride or the like or a laminated film thereof is used as a barrier metal. These films are easy to process by dry etching and have good consistency with the LSI manufacturing process before Cu is used as a wiring material.
The barrier insulating film is formed on the upper surface of the Cu wiring and has a function of preventing Cu oxidation and diffusion of Cu into the insulating film and a role as an etching stopper layer during processing. For example, a SiC film, a SiCN film, a SiN film, or a laminated film thereof is used as the barrier insulating film.
Hereinafter, a variable resistance element and a manufacturing method thereof according to preferred embodiments of the present invention will be described in detail with reference to the drawings. However, although each embodiment will be described in a technically preferable form for carrying out the present invention, the scope of the invention is not limited to the embodiment described below.

(First embodiment)
The configuration of the variable resistance element according to the first embodiment of the present invention will be described.
FIG. 1 is a partial cross-sectional view showing a configuration example of the variable resistance element according to the first embodiment.
The resistance change element of the present embodiment includes a first electrode 1, a second electrode 2, and a resistance change layer 3 provided between the first electrode 1 and the second electrode 2. The resistance change layer 3 includes a buffer layer 4 and a solid electrolyte layer 5. The first electrode 1 is in contact with the buffer layer 4, and the second electrode 2 is in contact with the solid electrolyte layer 5. The first electrode 1 contains Cu, and when voltage is applied between the first electrode 1 and the second electrode 2, the first electrode 1 serves to ionize copper and inject it into the buffer layer 4 and the solid electrolyte layer 5. The buffer layer 4 is made of a valve metal oxide having a negative oxidation free energy larger than that of Cu. The buffer layer 4 has a configuration in which a first metal oxide layer 6 and a second metal oxide layer 7 are laminated in order from at least the side closer to the first electrode 1. The second metal oxide layer 7 is a passive layer.
Here, the valve metal is a metal material that forms a film of an oxide layer on the surface by a general anodizing treatment, and refers to a material that increases chemical resistance as compared with the case where there is no oxide film. A passive layer is an oxide layer in which atoms formed in the vicinity of a surface of a metal material are closely bonded by, for example, exposing the surface to the atmosphere or performing a specific chemical treatment. It is. The passive layer has a function of increasing the chemical resistance of the metal material by preventing diffusion of oxygen atoms from other adjacent oxide layers into the metal material.
In the resistance change element of the present embodiment, the second metal oxide layer 7 which is a passive layer controls the degree of oxidation of the lower first metal oxide layer 6, and the lower layer Cu is the main component. The surface oxidation of the first electrode 1 is reduced. Therefore, the breakdown voltage at reset can be improved.
Further, even if a layer made of a metal component that did not constitute the first metal oxide layer 6 remains unoxidized, the metal is alloyed with Cu of the first electrode 1 mainly composed of the underlying Cu. Diffuses into the electrode. Therefore, no metal remains between the first electrode 1 and the first metal oxide layer 6, and the leakage current in the off state can be reduced.
The configuration shown in FIG. 1 will be described in detail below.

The second metal oxide layer 7 is preferably made of an oxide containing at least one of aluminum (Al), niobium (Nb), and tantalum (Ta). By configuring the second metal oxide layer 7 as this configuration, it can function as a passive layer by an appropriate surface oxidation treatment, and the first metal oxide layer 6 can be configured with a sufficient degree of oxidation. And the oxidation of the 1st electrode 1 containing Cu can be suppressed. As a result, the breakdown voltage at reset can be improved.
The second metal oxide layer 7 is made of an oxide containing at least one of Al, Nb, and Ta. When the main component of the second metal oxide layer 7 is an oxide of Al, when the chemical composition is expressed as AlOx1 using the oxygen composition x1, x1 satisfies 1.3 ≦ x1 ≦ 1.5. Is preferred. In this chemical composition, AlOx1 functions as a passive layer and can suppress oxidation of the first electrode 1 containing Cu in the lower layer.
Further, when the second metal oxide layer 7 is an oxide of Nb as a main component, the chemical composition is expressed as NbOx2 using the oxygen composition x2, and x2 satisfies 1.8 ≦ x2 ≦ 2.5. It is preferable to satisfy. In this chemical composition, the NbOx2 functions as a passive layer as in the case of AlOx1, and the oxidation of the first electrode 1 containing the underlying Cu can be suppressed. Further, when the second metal oxide layer 7 is an oxide of Ta as a main component, when the chemical composition is represented by TaOx3 using the oxygen composition x3, x3 satisfies 1.8 ≦ x3 ≦ 2.5. It is preferable to satisfy. In this chemical composition, TaOx3 functions as a passive layer as in the case of AlOx1 or NbOx2, and the oxidation of the first electrode 1 containing Cu in the lower layer can be suppressed.
In addition, when x1 in AlOx1 is 1.5, when x2 in NbOx2 is 2.5, or when x3 in TaOx3 is 2.5, all become oxides having a stoichiometric composition. An oxide having a larger oxygen composition x1, x2, and x3 cannot be formed.
The second metal oxide layer 7 is not limited to containing any one of Al, Nb, and Ta, and may be an oxide containing two or more of these metal elements. .

The first metal oxide layer 6 is preferably composed of an oxide containing at least one of titanium (Ti), zirconium (Zr), and hafnium (Hf). By making the first metal oxide layer 6 have this configuration, it is possible to suppress an increase in programming voltage while reducing leakage current. Further, in the elementary metal layer that becomes the first metal oxide layer 6, the unoxidized metal component is alloyed with Cu of the lower first electrode 1 and diffused into the electrode, and functions as a suitable alloyed layer. To do.
The first metal oxide layer 6 is composed of an oxide containing at least one of Ti, Zr, and Hf. When the first metal oxide layer 6 is an oxide of Ti, the chemical composition is expressed as TiOy1 using the oxygen composition y1, and y1 satisfies 1.5 ≦ y1 ≦ 2.0. Is preferred. When the first metal oxide layer 6 is an oxide of Zr as a main component, the chemical composition is expressed as ZrOy2 using the oxygen composition y2, and y2 satisfies 1.5 ≦ y2 ≦ 2.0. Is preferred. Further, when the first metal oxide layer 6 is an oxide whose main component is Hf, when the chemical composition is expressed by HfOy3 using the oxygen composition y3, y3 satisfies 1.5 ≦ y3 ≦ 2.0. It is preferable to satisfy. With any one of these configurations, the leakage current can be more effectively reduced, and variations in characteristics between elements can be reduced.
In addition, when y1 in TiOy1 is 2.0, y2 in ZrOy2 is 2.0, or y3 in HfOy3 is 2.0, all become oxides having a stoichiometric composition. An oxide having a larger oxygen composition y1, y2 and y3 cannot be formed.

It is preferable that the surface of the first electrode 1 in contact with the first metal oxide layer 6 is provided with an alloy containing a metal contained in the first metal oxide layer 6 and Cu. With this configuration, the metal bridge formed in the resistance change layer 3 in the on state is composed of an alloy containing the metal contained in the first metal oxide layer 6 and Cu, as in the case of the alloy. The retention characteristics can be improved.
Moreover, it is preferable that the film thickness of the 1st metal for forming the 1st metal oxide layer 6 is 0.7 nm or less. The film thickness of the second metal for forming the second electrode oxide layer 7 is preferably 0.5 nm or less. By setting it as such a film thickness structure, a 1st metal and a 2nd metal can be oxidized, and the 1st metal oxide layer 6 and the 2nd metal oxide layer 7 can be formed, respectively. With such a film thickness configuration, the first metal can be alloyed with Cu and diffused into the electrode without leaving the unoxidized second metal.
The solid electrolyte layer 5 includes a metal oxide film containing at least one of Ta, Ni, Ti, Zr, Hf, Si, Al, Fe, V, Mn, Co, and W, a SiOCH film, or a chalcogenide film, or These laminated films can be used. For example, a 6 nm thick SiOCH film is used as the solid electrolyte layer 5.
For the second electrode 2, a metal or metal nitride containing at least one of Pt, Ir, Ru, Ta, RuTa, RuTi, TiN, TaN, HfN, and ZrN, or a laminated film thereof can be used. It is. For example, RuTa is used as the second electrode 2.

According to the variable resistance element of this embodiment, it is possible to reduce the leakage current in the off state and improve the dielectric breakdown voltage at the time of reset.
Each of the first metal oxide layer 6 and the second metal oxide layer 7 is composed of the film thickness and material described in the present embodiment, and the first electrode is in contact with the first metal oxide layer 6. It can be confirmed with various measuring instruments that the surface of 1 is an alloy containing a metal contained in the first metal oxide layer 6 and Cu. For example, the above-described configuration can be confirmed by examining its constituent elements and chemical composition by transmission electron microscope (TEM) observation, energy dispersive X-ray spectroscopy, and electron energy loss spectroscopy.
The method for forming a variable resistance element according to this embodiment will be described in detail in the third embodiment, and the description thereof will be omitted in this embodiment.

(Second Embodiment)
The second embodiment of the present invention has a configuration in which a third metal oxide layer is provided between the second metal oxide layer 7 and the solid electrolyte layer 5 described in the first embodiment.
The configuration of the variable resistance element according to the second embodiment will be described. FIG. 2 is a partial cross-sectional view showing a configuration example of the variable resistance element according to the second embodiment.
As shown in FIG. 2, the variable resistance element according to the present embodiment is the same as the variable resistance element shown in FIG. 1 except that a third metal oxide layer 8 is provided between the second metal oxide layer 7 and the solid electrolyte layer 5. It has been. The third metal oxide layer 8 contains the same metal element as the first metal oxide layer 6.
In addition, the third metal oxide layer 8 is not limited to the configuration containing the same metal element as the first metal oxide layer 6, and at least one of Ti, Zr, and Hf is the same as the first metal oxide layer 6. It may be an oxide containing two. When the third metal oxide layer 8 is an oxide of Ti as a main component, the chemical composition is expressed as TiOy1 using the oxygen composition y1, and y1 is an oxide that satisfies 1.5 ≦ y1 ≦ 2.0. It may be a thing. When the third metal oxide layer 8 is an oxide of Zr as a main component, when the chemical composition is expressed by ZrOy2 using the oxygen composition y2, y2 is an oxide that satisfies 1.5 ≦ y2 ≦ 2.0. It may be a thing. Further, when the third metal oxide layer 8 is an oxide whose main component is Hf, when the chemical composition is expressed by HfOy3 using the oxygen composition y3, y3 satisfies 1.5 ≦ y3 ≦ 2.0. The oxide which fills may be sufficient.

With the configuration of the resistance change element in the present embodiment, the barrier property against oxygen diffusion of the second metal oxide layer 7 serving as a passive layer can be more easily controlled by the third metal oxide layer 8.
As with the first embodiment, the film thickness and material of the configuration in the present embodiment can also be examined with a measuring instrument. In addition to the film thickness and material related to the first metal oxide layer 6 and the second metal oxide layer 7 and the alloy containing the metal and Cu contained in the first metal oxide layer 6, the third metal oxide layer 8 This configuration can be examined with various measuring instruments. For example, the above-described configuration can be confirmed by examining its constituent elements and chemical composition by transmission electron microscope (TEM) observation, energy dispersive X-ray spectroscopy, and electron energy loss spectroscopy.

(Third embodiment)
The third embodiment of the present invention has a configuration in which the variable resistance element described in the first embodiment is provided inside a multilayer wiring structure formed on a semiconductor substrate. As will be described later, in the variable resistance element of this embodiment, the first electrode is a Cu electrode that also serves as a Cu wiring.
A configuration of the variable resistance element according to the third embodiment will be described.
FIG. 3 is a partial cross-sectional view schematically showing a configuration in which the variable resistance element according to the third embodiment is provided inside a multilayer wiring structure on a semiconductor substrate.
As shown in FIG. 3, a resistance change element 126 is provided on the semiconductor substrate 101 via the first interlayer insulating film 102. The variable resistance element 126 of the present embodiment includes a lower wiring 106, a first metal oxide layer 121, a second metal oxide layer 122, a solid electrolyte layer 123, a first upper electrode 124, and a second upper electrode. 125.
As an example, the configuration described in the first embodiment may be applied to the lower wiring 106, the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, and the first upper electrode 124. Is possible. The lower wiring 106 corresponds to the first electrode 1 shown in FIG. The first metal oxide layer 121 corresponds to the first metal oxide layer 6, and the second metal oxide layer 122 corresponds to the second metal oxide layer 7. The solid electrolyte layer 123 corresponds to the solid electrolyte layer 5, and the first upper electrode 124 corresponds to the second electrode 2. Since these configurations are the same as those described in the first embodiment, detailed description thereof is omitted in this embodiment.
Also in the present embodiment, by providing the first metal oxide layer 121, it is possible to more effectively reduce the leakage current and reduce the inter-element characteristic variation. In the present embodiment, the first metal oxide layer 121 is, for example, TiOy1 in which an oxygen composition y1 having a thickness of 0.5 nm satisfies 1.5 ≦ y1 ≦ 2.0.
In addition, the second metal oxide layer 127 functions as a passive layer, and the oxidation of the lower lower wiring 106 containing Cu in the lower layer can be suppressed. In the present embodiment, the second metal oxide layer 122 is, for example, AlOx1 in which the 0.3 nm-thickness oxygen composition x1 satisfies 1.3 ≦ x1 ≦ 1.5.

The solid electrolyte layer 123 is a SiOCH film having a thickness of 6 nm, for example. The first upper electrode 124 is, for example, Ru _0.5 Ti _0.5 with a film thickness of 10 nm.
The second upper electrode 125 is a conductive film having a barrier property, and is formed to prevent the metal contained in the first upper electrode 124 in contact with the lower portion from diffusing into the via plug 144 or the like. For example, Ta with a film thickness of 25 nm.
As shown in FIG. 3, the second hard mask film 128 and the third hard mask film 129 are formed on the stacked body of the first upper electrode 124 and the second upper electrode 125 in the variable resistance element 126. Side surfaces of the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, the second upper electrode 125, the second hard mask film 128, and the third hard mask film 129; The upper surface of the first barrier insulating film 107 is covered with a protective insulating film 130.
The lower wiring 106 is a wiring embedded in the wiring trench formed in the second interlayer insulating film 103 and the first cap insulating film 104 via the first barrier metal 105. The lower wiring 106 is made of a metal material containing Cu as a main component, and is used as a lower electrode corresponding to the first electrode 1 in the first embodiment. With this configuration, the lower wiring 106 can have a function of ionizing Cu atoms in the lower wiring 106 and eluting them into the solid electrolyte layer 123. Furthermore, by forming the lower wiring 106 with a Cu material structure, a metal component that has not been formed in the first metal oxide layer 121 while being unoxidized can be alloyed with Cu and diffused into the lower wiring 106. For example, when Cu is used for the lower wiring 106 and the main component constituting the first metal oxide layer 121 is an oxide made of Ti, the interface between the lower wiring 106 and the first metal oxide layer 121 is An alloying layer mainly composed of Cu and Ti is formed.

The solid electrolyte layer 123 and the lower wiring 106 are connected at the opening of the first barrier insulating film 107 via the first metal oxide layer 121 and the second metal oxide layer 122. At this time, the width of the lower wiring 106 connected to the solid electrolyte layer 123 through the metal oxide layer is preferably larger than the diameter of the opening of the barrier insulating film 107.
The first barrier metal 105 is a conductive film having a barrier property similar to that of the second upper electrode 125. The first barrier metal 105 is formed on the lower wiring 106 in order to prevent the metal contained in the lower wiring 106 from diffusing into the first interlayer insulating film 102, the second interlayer insulating film 103, the first cap insulating film 104, and the like. The side and bottom are covered. For example, when the lower wiring 106 is made of a metal element whose main component is Cu, the first barrier metal 105 includes a refractory metal such as Ta, TaN, TiN, and WCN, nitrides thereof, or a laminated film thereof. Is used.
The upper wiring 145 is a wiring embedded in a wiring groove formed in the third interlayer insulating film 141 and the second cap insulating film 142 via the second barrier metal 143. The upper wiring 145 is integrated with the via plug 144. The via plug 144 is embedded in a prepared hole formed in the protective insulating film 130, the third hard mask film 129, and the second hard mask film 128 via the second barrier metal 143. The via plug 144 is electrically connected to the resistance change element 126 via the second barrier metal 143. For example, Cu is used for the upper wiring 145 and the via plug 144.

The second barrier metal 143 is a conductive film having the same barrier properties as the first barrier metal 105. The second barrier metal 143 is formed on the upper wiring 145 and the via plug 144 to prevent the metal contained in the upper wiring 145 and the via plug 144 from diffusing into the first via interlayer insulating film 140, the third interlayer insulating film 141, and the second cap insulating film 142. The side surfaces and bottom surfaces of the wiring 145 and the via plug 144 are covered. In the second barrier metal 143, for example, when the upper wiring 145 and the via plug 144 are made of a metal element containing Cu as a main component, like the first barrier metal 105, Ta, TaN, TiN, WCN, etc. A refractory metal, a nitride thereof, or a laminated film thereof is used.
The second barrier metal 143 is preferably made of the same material as the second upper electrode 125 which is a part of the configuration of the variable resistance element 126 from the viewpoint of reducing contact resistance. For example, when the second upper electrode 125 is Ta, it is preferable to use Ta for the second barrier metal 143 in contact with the upper portion thereof.
The third hard mask film 129 is a film that serves as a hard mask when the second hard mask film 128 is etched. The second hard mask film 128 is preferably a different type of film from the third hard mask film 129. For example, if the second hard mask film 128 is a SiCN film, a SiO 2 film is used as the third hard mask film 129. It is possible to use.
The protective insulating film 130 is an insulating film having a function of preventing diffusion of constituent atoms from the variable resistance element 126 to the first via interlayer insulating film 140 without damaging the variable resistance element 126 whose side surface is exposed. As the protective insulating film 130, for example, a SiN film, a SiCN film, or the like can be used. The first barrier insulating film 107 and the second barrier insulating film 146 are insulating films having a function of preventing metal diffusion.

  In the present embodiment, as shown in FIG. 3, the lower wiring 106 corresponding to the first electrode 1 and the first metal oxide layer 121 are in contact with each other through the opening provided in the first barrier insulating film 107. Become. With this configuration, a Cu electrode serving also as a Cu wiring can be used as the first electrode 1, and a resistance change element using a Cu electrode can be formed in the multilayer wiring structure on the CMOS substrate. Since the lower electrode of the variable resistance element also functions as a Cu wiring, the manufacturing process can be simplified.

Next, the manufacturing method of the variable resistance element according to the present embodiment will be described in the case of the configuration shown in FIG.
4 to 13 are partial cross-sectional views for explaining a manufacturing method for providing the variable resistance element according to the third embodiment inside the multilayer wiring structure on the semiconductor substrate.
First, a first interlayer insulating film 102, a second interlayer insulating film 103, and a first cap insulating film 104 are sequentially formed on the semiconductor substrate 101. The semiconductor substrate 101 here may be the semiconductor substrate itself or a substrate on which a semiconductor element (not shown) is formed on the surface of the substrate. For example, the first interlayer insulating film 102 is a 300 nm thick SiO 2 film, the second interlayer insulating film 103 is a 150 nm thick SiOCH film, and the first cap insulating film 104 is a 100 nm thick SiO 2 film.
Subsequently, a wiring trench is formed in the laminated film of the first cap insulating film 104, the second interlayer insulating film 103, and the first interlayer insulating film 102 by using a lithography method. This lithography method includes a photoresist forming process for forming a resist with a predetermined pattern on the first cap insulating film 104, a dry etching process for performing anisotropic etching on the laminated film using the resist as a mask, and an etching process. And a process of removing the resist after forming the wiring trench.
Thereafter, a metal is embedded in the wiring trench via the first barrier metal 105 to form the lower wiring 106. The laminated structure of the first barrier metal 105 is, for example, TaN (film thickness 5 nm) / Ta (film thickness 5 nm). The material of the lower wiring 106 is, for example, Cu.

Subsequently, a first barrier insulating film 107 is formed on the first cap insulating film 104 including the lower wiring 106. The first barrier insulating film 107 is, for example, a SiCN film having a film thickness of 30 nm. Next, as shown in FIG. 4, a first hard mask film 108 is formed on the first barrier insulating film 107. The first hard mask film 108 is preferably made of a material different from that of the first barrier insulating film 107 from the viewpoint of maintaining a high etching selectivity in the dry etching process. Here, for example, a SiO 2 film is used as the first hard mask film 108. The deposited film thickness of the first hard mask film 108 is, for example, a SiO 2 film having a film thickness of 40 nm.
Subsequently, a photoresist having a predetermined opening pattern is formed on the first hard mask film 108 and dry etching is performed to form openings in the first hard mask film 108. The photoresist is removed by O2 plasma ashing or the like. Then, the first barrier insulating film 107 exposed at the bottom of the opening of the first hard mask film 108 is etched back, so that an opening exposing a part of the upper surface of the lower wiring 106 is formed in the first barrier insulating film 107. Form. The first hard mask film 108 is removed by etching during this etch back by setting the film thickness to 40 nm. After this etch-back, as shown in FIG. 5, the surface of the lower wiring 106 exposed at the bottom of the opening is cleaned by plasma irradiation using an organic solvent or a gas containing H ₂ or an inert gas.
Step A1 is performed until the structure shown in the order of FIGS. 4 to 5 is formed.

In step A1, the etch back when forming the opening of the first barrier insulating film 107 can be performed by using plasma containing CF ₄ when the first barrier insulating film 107 is a SiN film or a SiCN film. It is. The conditions are, for example, the conditions of CF ₄ / Ar gas flow rate = 25/50 sccm, pressure 0.53 Pa, source power 400 W, and substrate bias power 90 W. By reducing the source power or increasing the substrate bias, the ionicity at the time of etching can be improved, and the side wall of the first barrier insulating film 107 can be tapered. Further, the first hard mask film 108 can be removed by etching by this etch back.

Next, as shown in FIG. 6, the first metal layer 161 for forming the first metal oxide layer 121 on the first barrier insulating film 107 including the opening from which the lower wiring 106 is exposed, and the first A second metal layer 162 for forming the two metal oxide layer 122 is deposited in this order. The first metal layer 161 includes at least one of Ti, Zr, and Hf. The second metal layer 162 includes at least one of Al, Nb, and Ta. As an example, the first metal layer 161 is Ti with a thickness of 0.5 nm, and the second metal layer is Al with a thickness of 0.2 nm.
After the first metal layer 161 and the second metal layer 162 are deposited, the first metal layer 161 and the second metal layer 162 are oxidized by irradiation with a gas containing O 2 without exposure to the atmosphere under reduced pressure. Process. Subsequently, a vacuum heat treatment is performed under reduced pressure at a temperature higher than the film formation temperature, whereby the first metal oxide layer 121 and the second metal oxide layer 122 are formed simultaneously as shown in FIG.
Step A2 is the process until the structure shown in the order of FIGS.

In Step A2, the first metal layer 161 and the second metal layer 162 can be deposited by vapor deposition using resistance heating, electron beam irradiation, laser irradiation, or the like of a metal raw material, DC sputtering, or the like. As an example, when the first metal layer 161 is Ti, DC sputtering is used, using Ti as a target, sputtering power of 100 W, substrate temperature at room temperature, Ar flow rate of 20 sccm, and pressure of 0.5 Pa. A first metal layer 161 can be deposited. Further, when the second metal layer 162 is Al, a DC sputtering method is used, using Al as a target, a sputtering power of 150 W, a substrate temperature of room temperature, an Ar flow rate of 20 sccm, and a pressure of 0.5 Pa. A second metal layer 162 can be deposited.
In Step A2, the first metal oxide layer 121 formed by the oxidation of the first metal layer 161 and the second metal layer are performed by performing the oxidation treatment by the gas irradiation including O 2 without being exposed to the atmosphere. The degree of oxidation of the second metal oxide layer 122 formed by the oxidation of 162 can be accurately controlled. As an example, when the first metal layer 161 is Ti with a thickness of 0.5 nm and the second metal layer 162 is Al with a thickness of 0.2 nm, the substrate temperature is room temperature, the O 2 flow rate is 10 sccm, and the pressure The first metal oxide layer 121 made of an oxide of Ti and the second metal oxide layer 122 made of an oxide of Al can be formed by O 2 gas irradiation of 0.5 Pa and an irradiation time of 60 seconds.
Further, in step A2, for example, the heat treatment after the oxidation treatment described above includes, as an example, the first metal layer 161 made of Ti with a thickness of 0.5 nm and the second metal layer made of Al with a thickness of 0.2 nm. In some cases, it is preferable that the substrate temperature be 400 ° C. or lower under conditions of N 2 and O 2 flow rates of 10/10 sccm, a pressure of 900 Pa, and a processing time of 30 seconds. By this heat treatment, the metal component in the first metal layer 161 remaining unreacted in the above oxidation treatment can be removed by alloying diffusion on the surface of the lower electrode 106 made of Cu. Further, the vacuum means a state where the atmospheric pressure in the chamber is as low as possible, and is at least a lower pressure than the above-described oxidation treatment. The thickness of the first metal oxide layer 121 is preferably 1.0 nm or less, and the thickness of the second electrode oxide layer 122 is preferably 0.8 nm or less.

Next, the solid electrolyte layer 123 is deposited on the formed second metal oxide layer 122. For the solid electrolyte layer 123, for example, a SiOCH film having a thickness of 6 nm is used. In this case, the solid electrolyte layer 123 is deposited by a plasma CVD method, and then an inert gas plasma process is performed.
Subsequently, the first upper electrode 124 and the second upper electrode 125 are formed in this order on the solid electrolyte layer 123 by DC sputtering. The lower wiring 106, the first metal oxide layer 121, the second metal oxide layer 122, the solid electrolyte layer 123, the first upper electrode 124, and the second upper electrode 125 constitute a stacked body that becomes the resistance change element 126. The first upper electrode 124 is, for example, Ru0.5Ti0.5 having a thickness of 10 nm. The second upper electrode 125 is, for example, Ta with a film thickness of 25 nm. When the first upper electrode 124 is made of Ru or Ru alloy, the second upper electrode 125 is continuously exposed without being exposed to the atmosphere after the first upper electrode 124 is deposited in order to prevent surface oxidation of the first upper electrode 124. Is preferably deposited.
Subsequently, as shown in FIG. 8, the second hard mask film 128 and the third hard mask film 129 are stacked in this order on the second upper electrode 125. The second hard mask film 128 is preferably made of the same material as the first barrier insulating film 107 from the viewpoint of adhesion, and is, for example, a SiCN film having a thickness of 30 nm. The third hard mask film 129 is, for example, a SiO 2 film having a thickness of 100 nm.
The process from the structure shown in FIG. 7 to the structure shown in FIG. 8 is defined as step A3.

  In step A3, when a SiOCH film is used for the solid electrolyte layer 123, the solid electrolyte layer 123 is formed under the following conditions by the plasma CVD method. Liquid SiOCH monomer molecules are used as the raw material, the substrate temperature is 400 ° C. or less, the He flow rate is 500 to 2000 sccm, the raw material flow rate is 0.1 to 0.8 g / min, the plasma CVD chamber pressure is 360 to 700 Pa, and the RF power is 20 to 100 W. By setting each, the solid electrolyte layer 123 can be deposited. Specifically, the solid electrolyte layer 123 can be deposited under conditions of a substrate temperature of 350 ° C., a He flow rate of 1500 sccm, a raw material flow rate of 0.75 g / min, a plasma CVD chamber pressure of 470 Pa, and an RF power of 50 W. In addition, the inert plasma treatment after the deposition of the solid electrolyte layer 123 uses He as an inert gas, the substrate temperature is set to 400 ° C. or less, the He flow rate is 500 to 1500 sccm, the plasma chamber pressure is 2.7 to 3.5 Torr, and the RF power. This can be done by setting each of 20 to 200 W. Specifically, it can be performed under the conditions of a substrate temperature of 350 ° C., a He flow rate of 1000 sccm, a plasma chamber pressure of 360 Pa, an RF power of 50 W, and a processing time of 30 seconds. By this inert plasma treatment, the adhesion with the first upper electrode 124 to be deposited next can be improved.

In Step A3, for example, when Ru _0.5 Ti _0.5 is used, the first upper electrode 124 has Ru sputtering power 120 W, Ti sputtering power 150 W, and substrate temperature by simultaneous DC sputtering using Ru and Ti as targets. The deposition can be performed at room temperature by using an Ar flow rate of 20 sccm and a pressure of 0.5 Pa. When the second upper electrode 125 is Ta having a film thickness of 25 nm, DC sputtering is performed using Ta as a target, sputtering power of 300 W, substrate temperature at room temperature, Ar flow rate of 25 sccm, and pressure of 0.5 Pa. Can be deposited respectively.
In Step A3, both the second hard mask film 128 and the third hard mask film 129 can be formed by using a general plasma CVD method in the technical field of semiconductor manufacturing. The film forming temperature can be selected in the range of 200 ° C to 400 ° C. Here, the film formation temperature was 350 ° C.

Next, after forming a photoresist having a processing pattern of the resistance change element 126 on the third hard mask film 129, the third hard mask film 129 is dry-etched until the second hard mask film 128 appears. continue. After removing the photoresist by the O 2 plasma ashing process, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide, using the third hard mask film 129 as a mask. The physical layer 122 and the first metal oxide layer 121 are continuously dry etched. FIG. 9 shows the state after the etching.
The process from the structure shown in FIG. 8 to the structure shown in FIG. 9 is defined as step A4.

In step A4, the dry etching of the third hard mask film 129 is preferably stopped on the upper surface or inside the second hard mask film 128. In this case, since the variable resistance element 126 is covered with the second hard mask film 128, it is not exposed to the O 2 plasma. Further, since the first upper electrode 124 containing Ru is not exposed to O 2 plasma, the occurrence of side etching on the first upper electrode 124 can be suppressed. The third hard mask film 129 can be dry etched using a general parallel plate type dry etching apparatus.
In step A4, each etching of the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide layer 121 is performed. Also, it can be performed collectively using a parallel plate type dry etcher.
Etching of the second hard mask film 128 (for example, SiCN) can be performed under the conditions of a gas flow rate of CF 4 / Ar = 25/50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 90 W.

In Step A4, the etching of the second upper electrode 125 (for example, Ta) is performed under the conditions of a substrate temperature of 90 ° C., a Cl 2 gas flow rate = 50 sccm, a pressure of 0.53 Pa, a source power of 400 W, and a substrate bias power of 60 W. Can do.
Etching of the first upper electrode 124 (eg, Ru0.5Ti0.5) is performed at a substrate temperature of room temperature, an O2 / Cl2 gas flow rate = 160/30 sccm, a pressure of 0.53 Pa, a source power of 300 to 600 W, and a substrate bias power. It can carry out on the conditions of 100-300W.
The solid electrolyte layer 123 (for example, SiOCH) can be etched under the same conditions as the etching of the first upper electrode 124 when Ru _0.5 Ti _0.5 is used for the first upper electrode 124. Therefore, etching can be performed together with the first upper electrode 124.
Further, the second metal oxide layer 122 (for example, AlOx1 in which the 0.3 nm-thickness oxygen composition x1 satisfies 1.3 ≦ x1 ≦ 1.5) and the first metal oxide layer 121 (for example, the thickness of 0 Similarly to the solid electrolyte layer 123 in the case where Ru _0.5 Ti _0.5 is used for the first upper electrode 124, the etching of TiOy1) in which the oxygen composition y1 of _0.5 nm satisfies 1.5 ≦ y1 ≦ 2.0 is also performed in the first The etching can be performed under the same conditions as the etching of the upper electrode 124. Therefore, etching can be performed together with the first upper electrode 124 and the solid electrolyte layer 123.
In Step A4, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide are formed under the above-described conditions. After each etching of the layer 121, the remaining thickness of the third hard mask film 129 can be 50 nm.

Next, the third hard mask film 129, the second hard mask film 128, the second upper electrode 125, the first upper electrode 124, the solid electrolyte layer 123, the second metal oxide layer 122, and the first metal oxide layer 121. In addition, a protective insulating film 130 is deposited on the upper portion and side wall portion of the laminated structure including the first barrier insulating film 107. The protective insulating film 130 is preferably made of the same material as the first barrier insulating film 107 and the second hard mask film 128, and is, for example, a SiCN film having a thickness of 30 nm.
Subsequently, as shown in FIG. 10, a first via interlayer insulating film 140 is deposited on the protective insulating film 130 using a plasma CVD method. The first via interlayer insulating film 140 is, for example, a SiO 2 film having a thickness of 210 nm. Next, the first via interlayer insulating film 140 is planarized using a CMP method. After the planarization, as shown in FIG. 11, a third interlayer insulating film 141 and a second cap insulating film 142 are deposited in this order on the first via interlayer insulating film 140. The third interlayer insulating film 141 is made of a material different from that of the first via interlayer insulating film 140 in order to use the first via interlayer insulating film 140 that is in contact with the lower portion during the etching process as an etching stopper layer. The third interlayer insulating film 141 is a SiOCH film having a thickness of 150 nm, for example.
The process from the structure shown in FIG. 9 to the structure shown in FIG. 11 is defined as step A5.

In Step A5, when using a SiCN film, for example, the protective insulating film 130 can be formed by plasma CVD using tetramethylsilane and ammonia as source gases and a substrate temperature of 200 ° C. By forming this protective insulating film 130, the first barrier insulating film 107, the protective insulating film 130, and the second hard mask film 128 are SiCN films made of the same material, and the periphery of the resistance change element 126 is integrated to protect the interface. Thus, the moisture absorption, water resistance and oxygen desorption resistance can be improved, and the yield and reliability of the device can be improved.
Further, in step A5, in the planarization of the first via interlayer insulating film 140, about 100 nm can be removed from the top surface of the first via interlayer insulating film 140, and the remaining film can be made about 110 nm. At this time, the CMP for the first via interlayer insulating film 140 can be polished using a general colloidal silica or ceria-based slurry.
In step A5, the third interlayer insulating film 141 and the second cap insulating film 142 can be deposited using a general plasma CVD method.

Next, the upper wiring 145 and the via plug 144 shown in FIG. 3 are formed by using a dual damascene via first method.
In the via first method, first, a photoresist having the pattern of the via hole 147 for the via plug 144 shown in FIG. 3 is formed on the second cap insulating film 142. Subsequently, the via plug shown in FIG. 3 penetrating through the second cap insulating film 142, the third interlayer insulating film 141, the first via interlayer film 140, the protective insulating film 130, and the third hard mask film 129 by dry etching. A via hole 147 for 144 is formed. Then, as shown in FIG. 12, the photoresist is removed by performing plasma ashing including H 2 gas and organic peeling.
Subsequently, after forming a photoresist having the pattern of the wiring groove 148 for the upper wiring 145 shown in FIG. 3 on the second cap insulating film 142, the second cap insulating film 142 and the third interlayer insulation are formed by dry etching. A wiring groove 148 for the upper wiring 145 shown in FIG. Thereafter, as shown in FIG. 13, the photoresist is removed by performing plasma ashing including H 2 gas and organic peeling.
The process from the structure shown in FIG. 11 to the structure shown in FIG. 13 is defined as step A6.
In step A6, after forming the via hole 147, an ARC (Anti-Reflection Coating; antireflection film) or the like is buried on the via hole, thereby preventing the bottom via hole from being penetrated at the time of forming the wiring groove 148 by dry etching. can do.

Next, the second upper electrode 125 is exposed from the via hole 147 by etching the second hard mask film 128 at the bottom of the via hole 147. Thereafter, an upper wiring 145 (for example, Cu) and a via plug 144 (for example, Cu) are simultaneously formed in the wiring trench 148 and the via hole 147 through a second barrier metal 143 (for example, Ta having a thickness of 10 nm). Thereafter, a second barrier insulating film 146 (for example, a 50 nm SiCN film) is deposited on the second cap insulating film 142 including the upper wiring 145, thereby forming the structure shown in FIG.
The process from the structure shown in FIG. 13 to the structure shown in FIG. 3 is defined as step A7.
In step A7, the formation of the upper wiring 145 can use the same process as the formation of the lower wiring 106 in the lower layer. At this time, the bottom diameter of the via plug 144 is preferably made smaller than the opening diameter of the first barrier insulating film 107. In the present embodiment, for example, the diameter of the bottom of the via plug 144 is 60 nm, and the diameter of the opening of the first barrier insulating film 107 is 100 nm.
In step A7, the second barrier metal 143 and the second upper electrode 125 are made of the same material, thereby reducing the contact resistance between the via plug 144 and the second upper electrode 125, and the variable resistance element 126 in the on state. Resistance can be reduced. As a result, device performance can be improved.

  Next, examples of the variable resistance element described above will be described.

In this example, elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 were produced for the variable resistance element 126 of the third embodiment, and the characteristics of these elements were evaluated.
In this example, nine types of variable resistance elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122 were manufactured using the variable resistance element 126 of the third embodiment as a basic structure. Specifically, the combination of the first metal oxide layer 121 and the second metal oxide layer 122 formed on the lower wiring 106 containing Cu as a main component is TiOy1 / AlOx1, TiOy1 / NbOx2, TiOy1 / TaOx3, ZrOy2. There are nine types: / AlOx1, ZrOy2 / NbOx2, ZrOy2 / TaOx3, HfOy3 / AlOx1, HfOy3 / NbOx2, and HfOy3 / TaOx3.
The film thickness of the first metal layer for forming the first metal oxide 121 was 0.5 nm, and the film thickness of the second metal layer for forming the second metal oxide 122 was 0.2 nm. The solid electrolyte layer is a 6 nm thick SiOCH film.
In addition, a resistance change element serving as a comparative example for comparing characteristics with the resistance change element of this example was prepared. In the resistance change element of the comparative example, the metal oxide provided in the buffer layer is made of the first metal oxide layer 121 (TiOy1, ZrOy2, and HfOy3) and the second metal oxide layer 122 (AlOx1, NbOx2, and TaOx3) Among these, it was set as the structure which has only any one, and the film thickness was 0.7 nm.

Next, the results of evaluating the leakage current and the breakdown voltage of the variable resistance element of this example and the variable resistance element of the comparative example will be described.
FIG. 14 is a table showing measurement results of off-leakage current when 1 V is applied for the variable resistance element of this example and the comparative example. The unit of the numerical values shown in FIG. 14 is ampere (A).
As shown in FIG. 14, in the variable resistance element of this example, in any combination of the first metal oxide layer 121 and the second metal oxide layer 122, only the first metal oxide layer 121 is used as a comparative example. In comparison, a reduction in off-leakage current was observed.
FIG. 15 is a table showing the breakdown voltage measurement results at reset for the variable resistance element of this example and the comparative example. The unit of the numerical values shown in FIG. 15 is volts (V).
As shown in FIG. 15, the breakdown voltage at reset is also improved in the resistance change element of this example compared to the comparative example in which only the first metal oxide layer 121 or the second metal oxide layer 122 is used. I found out that

In this example, the structure of the second embodiment is applied to the variable resistance element 126 shown in FIG. 3 to produce elements having different combinations of the first metal oxide layer 121 and the second metal oxide layer 122. The characteristics of these elements were evaluated.
In this example, the variable resistance element 126 of the third embodiment is used as a basic structure, and the first metal oxide layer 6, the second metal oxide layer 7, and the third metal oxide layer 8 shown in FIG. Seven types of variable resistance elements having different values were produced. Specifically, the combination of the first metal oxide layer 6, the second metal oxide layer 7 and the third metal oxide layer 8 formed on the lower wiring mainly composed of Cu is TiOy1 / AlOx1 / TiOy4, TiOy1 / NbOx2 / TiOy4, TiOy1 / TaOx3 / TiOy4, ZrOy2 / AlOx1 / ZrOy5, ZrOy2 / NbOx2, ZrOy2 / TaOx3 / ZrOy5, HfOy3 / AlOx1 / HfOy6. y4, y5 and y6 are the oxygen compositions in the oxides of Ti, Zr and Hf constituting the third metal oxide layer 8, respectively.
A metal layer having a thickness of 0.2 nm was continuously deposited on the second metal layer 7 as the third metal oxide layer 8. The variable resistance element of the present embodiment is the same as the variable resistance element 126 shown in FIG. 3 except that the third variable metal oxide layer 8 is provided.

Next, the measurement result about the characteristic of the resistance change element of a present Example is demonstrated.
Among the seven types of resistance change elements of the present example, in any of the stacked bodies, the result is similar to the result described in Example 1 compared to the resistance change element of the comparative example having only the first metal oxide layer. Reduction of off-leakage and improvement of dielectric breakdown voltage were confirmed.
Specifically, the off-leakage current was ⁷ × 10 ⁻⁷ A as shown in FIG. 14 in the case of the comparative example having only the first metal oxide layer (TiOy1). On the other hand, in the variable resistance element of the present embodiment, for example, when the combination of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer is TiOy1 / AlOx1 / TiOy4, Reduced to 4 × 10 ⁻⁸ A.
The dielectric breakdown voltage is 3.5 V as shown in FIG. 15 in the case of the comparative example having only the first metal oxide layer (TiOy1). On the other hand, in the variable resistance element of the present example, for example, when a laminated body of TiOy1 / AlOx1 / TiOy4 was used, the dielectric breakdown voltage increased to 4.5V. This is considered to be because the oxygen barrier property by the passive formation of the second metal oxide layer in contact with the lower part is controlled by the insertion of the third metal oxide layer.

This example has a configuration in which a three-terminal variable resistance element is provided in a multilayer wiring structure on a semiconductor substrate based on the variable resistance element of the third embodiment and the manufacturing method thereof.
The configuration of the three-terminal variable resistance element according to this embodiment will be described. In this example, a configuration different from the third embodiment will be mainly described, and a detailed description of a configuration similar to the third embodiment will be omitted.
FIG. 16 is a partial cross-sectional view schematically showing a configuration in which the three-terminal variable resistance element of this example is provided in the multilayer wiring structure on the semiconductor substrate.
As shown in FIG. 16, in the three-terminal variable resistance element 224, a first lower wiring 206a and a second lower wiring 206b are provided as lower electrodes. Then, the upper surfaces of the first lower wiring 206a and the second lower wiring 206b that are separated from each other with the first gap insulating film 104 interposed therebetween are partially exposed in one opening formed in the first barrier insulating film 107. doing. The exposed portions of the upper surfaces of the lower wiring 206a and the second lower wiring 206b are in contact with the upper first metal oxide 121 through the opening together with the upper surface of the first gap insulating film 104.
Further, when both the first lower wiring 206a and the second lower wiring 206b are made of, for example, Cu, it is possible to have the same configuration as the lower wiring 106 having the configuration shown in FIG. It can be formed by the method described in the third embodiment.

  In the variable resistance element of this embodiment, if the first lower wiring 206a is the first electrode and the second lower wiring 206b is the third electrode, the first electrode and the third electrode are provided in the same layer, and the second electrode Is a configuration provided in a layer different from the first electrode and the third electrode.

Next, a method for manufacturing the three-terminal variable resistance element according to this embodiment will be described. In this example, processing different from that of the third embodiment will be mainly described, and detailed description of processing similar to that of the third embodiment will be omitted.
In this embodiment, when the opening is formed in the first hard mask film 107 by dry etching, the surface of the first cap insulating film 104 sandwiched between the first lower wiring 206a and the second lower wiring 206b is dry etched. This causes film loss. Therefore, after the opening is formed, the first metal layer 161 to be the first metal oxide 121 and the first metal oxide 121 are formed on the opening including the surfaces of the first lower wiring 206a and the second lower wiring 206b by the DC sputtering method. A second metal layer 162 to be a two metal oxide layer 122 was continuously deposited in this order. In this example, Zr having a thickness of 0.5 nm was selected as the first metal layer 161, and Al having a thickness of 0.2 nm was selected as the second metal layer 162. Thereafter, ZrOy2 as the first metal oxide layer 121 and the second metal oxide layer are irradiated by O2 gas irradiation at an O2 flow rate of 10 sccm, a pressure of 0.5 Pa, and an irradiation time of 60 seconds at room temperature without exposure to the atmosphere. An AlOx1 of 122 was formed. Subsequently, heat treatment was performed at a substrate temperature of 400 ° C. or lower under the conditions of N 2 and O 2 flow rates of 10/10 sccm, pressure of 900 Pa, and treatment time of 30 seconds. By this process, the Zr metal component remaining unreacted between the first lower wiring 206a and the second lower wiring 206b and ZrOy2 which is the first metal oxide layer 121 is converted into the first lower wiring 206a made of Cu and The second lower wiring 206b was removed by alloying and diffusion on the surface.
Next, the solid electrolyte layer 123 was deposited on the second metal oxide layer 122. With respect to the steps after the deposition of the solid electrolyte layer 123, by using the same formation method as that of the resistance change element described in the third embodiment, as shown in FIG. 16, a three-terminal resistance change type is formed in the multilayer wiring structure. An element 224 can be formed.

In the formation of the three-terminal variable resistance element 224 formed as described above, as in Example 1, the off-leakage is reduced as compared with the three-terminal variable resistance element of the comparative example having only the first metal oxide layer 121, and Improvement of dielectric breakdown voltage was confirmed.
Specifically, the off-leakage current is 5 × 10 ⁻⁷ A in the case of only the first metal oxide layer ZrOy2, whereas ZrOy2 that becomes the first metal oxide layer 121 in this example, and in three-terminal variable resistance element 224 with AlOx1 serving as the second metal oxide layer 122 it was confirmed that it has sufficiently reduced and 8x10 ^-8 a.
In addition, the dielectric breakdown voltage was 3.6 V when only the first metal oxide layer ZrOy 2 was used, but increased to 4.3 V in the three-terminal resistance change element 224 of the present example. In this embodiment, as an example, the three-terminal variable resistance element 224 using ZrOy2 as the first metal oxide layer 121 and AlOx1 as the second metal oxide layer 122 has been described. The combination configuration shown in the first embodiment is not limited thereto.
From the above results, it was found that the resistance change element and the manufacturing method thereof according to the present invention also reduce the off-leakage current and improve the breakdown voltage at reset even in the three-terminal resistance change element.

The variable resistance element of the present embodiment may have the following configuration.
(Appendix 1)
A first electrode;
A second electrode provided in a different layer from the first electrode;
A third electrode provided in the same layer as the first electrode;
A variable resistance layer provided between the first electrode, the third electrode, and the second electrode;
The variable resistance layer includes a buffer layer in contact with the first electrode and the third electrode, and a solid electrolyte layer in contact with the second electrode.
The first electrode and the third electrode include copper, and when a voltage is applied between the first electrode, the third electrode, and the second electrode, copper is ionized to form the buffer layer and the Injected into the solid electrolyte layer,
The buffer layer is made of a valve metal oxide having a negative oxidation free energy larger than that of copper, and the first metal oxide layer and the second metal oxide are arranged in order from the closer to the first electrode and the third electrode. A layer is provided,
The resistance change element, wherein the second metal oxide layer is a passive layer.

Moreover, the following method may be sufficient as the manufacturing method of the resistance change element of this embodiment.
(Appendix 2)
Forming a first electrode containing copper on the substrate;
Forming an insulating barrier film having an opening exposing a part of the upper surface of the first electrode on the first electrode;
A first metal layer that is a film containing a first metal and a second metal layer that is a film containing a second metal are sequentially deposited on the insulating barrier film including the opening,
After depositing the second metal layer, the first metal layer and the second metal layer are oxidized without being exposed to the atmosphere to form a first metal oxide layer and a second metal oxide layer,
After the oxidation treatment, under reduced pressure, a vacuum heat treatment is performed at a temperature higher than the deposition temperature of the second metal layer to convert the second metal oxide layer into a passive layer,
A method of forming a resistance change element, comprising sequentially forming a solid electrolyte layer and a second electrode on the second metal oxide layer.

(Appendix 3)
In the method of forming a resistance change element according to attachment 2,
The variable resistance element forming method, wherein the first metal layer has a thickness of 0.7 nm or less, and the second metal layer has a thickness of 0.5 nm or less.

  As mentioned above, although this invention was demonstrated based on embodiment and an Example, these embodiment and an Example are only for demonstrating invention by an example, Comprising: It does not mean limiting. A person skilled in the art naturally thinks of various modifications and improvements based on the above description, and it is understood that these are also included in the scope of the present invention.

  In the above embodiments and examples, as a background of the present invention, a semiconductor device having a CMOS circuit, which is a field of application of the present invention, will be described in detail, and a solid electrolyte switch element mounted in a multilayer wiring structure on a semiconductor substrate is formed. However, the present invention is not limited thereto. The present invention relates to, for example, a semiconductor product having a memory circuit such as a DRAM, SRAM (Static RAM), flash memory, FRAM (registered trademark) (Ferro-Electric RAM), capacitor, bipolar transistor, etc., and a logic circuit such as a microprocessor. The present invention can also be applied to a metal wiring forming process of a semiconductor product having the above or a board or package on which these are simultaneously mounted. The present invention can also be applied to a wiring formation process for connecting a semiconductor device to an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, a MEMS (Micro-Electro-Mechanical Systems), or the like.

DESCRIPTION OF SYMBOLS 1 1st electrode 2 2nd electrode 3 Resistance change layer 4 Buffer layer 5 Solid electrolyte layer 6 1st metal oxide layer 7 2nd metal oxide layer 8 3rd metal oxide layer 106 Lower wiring 107 1st barrier insulating film 121 First metal oxide layer 122 Second metal oxide layer 123 Solid electrolyte layer 124 First upper electrode 125 Second upper electrode 126 Resistance change element 161 First metal layer 162 Second metal layer 206a First lower wiring 206b First 2 lower wiring 224 3 terminal type resistance change element

Claims (10)

A resistance change element having a first electrode, a second electrode, and a resistance change layer provided between the first electrode and the second electrode,
The variable resistance layer includes a buffer layer in contact with the first electrode and a solid electrolyte layer in contact with the second electrode.
The first electrode is configured to include copper, and when a voltage is applied between the first electrode and the second electrode, copper is ionized and injected into the buffer layer and the solid electrolyte layer,
The buffer layer is made of a valve metal oxide having a negative oxidation free energy larger than that of copper, and a first metal oxide layer and a second metal oxide layer are provided in order from the side closer to the first electrode. Configuration,
The resistance change element, wherein the second metal oxide layer is a passive layer. The resistance change element according to claim 1,
The resistance change element, wherein the second metal oxide layer is made of an oxide containing at least one of Al, Nb, and Ta. The resistance change element according to claim 2,
The second metal oxide layer includes at least one of AlOx1, NbOx2, and TaOx3, x1 satisfies 1.3 ≦ x1 ≦ 1.5, x2 satisfies 1.8 ≦ x2 ≦ 2.5, and x3 is A variable resistance element satisfying 1.8 ≦ x3 ≦ 2.5. The resistance change element according to claim 3,
The resistance change element, wherein the first metal oxide layer is made of an oxide containing at least one of Ti, Zr, and Hf. The resistance change element according to claim 4,
The first metal oxide layer includes at least one of TiOy1, ZrOy2, and HfOy3, y1 satisfies 1.5 ≦ y1 ≦ 2.0, y2 satisfies 1.5 ≦ y2 ≦ 2.0, and y3 Is a resistance change element satisfying 1.5 ≦ y3 ≦ 2.0. The resistance change element according to any one of claims 1 to 5,
The resistance change element, wherein an alloy including a metal and copper contained in the first metal oxide layer is provided on a surface where the first electrode is in contact with the first metal oxide layer. The resistance change element according to any one of claims 1 to 6,
A third metal oxide layer is further provided between the second metal oxide layer and the solid electrolyte layer;
The resistance change element, wherein the first metal oxide layer and the third metal oxide layer contain the same metal element. The resistance change element according to any one of claims 1 to 7,
An insulating barrier film having an opening is further provided between the first electrode and the first metal oxide layer;
The first electrode is a copper electrode that also serves as a copper wiring, and is in contact with the first metal oxide layer through the opening. The resistance change element according to any one of claims 1 to 8,
The resistance change element, wherein the first metal oxide layer has a thickness of 1.0 nm or less, and the second metal oxide layer has a thickness of 0.8 nm or less. Forming a first electrode containing copper on the substrate;
Forming an insulating barrier film having an opening exposing a part of the upper surface of the first electrode on the first electrode;
A first metal layer that is a film containing a first metal and a second metal layer that is a film containing a second metal are sequentially deposited on the insulating barrier film including the opening,
After depositing the second metal layer, the first metal layer and the second metal layer are oxidized without being exposed to the atmosphere to form a first metal oxide layer and a second metal oxide layer,
After the oxidation treatment, heat treatment is performed under reduced pressure at a temperature higher than the deposition temperature of the second metal layer, to convert the second metal oxide layer into a passive layer,
A method of forming a resistance change element, comprising sequentially forming a solid electrolyte layer and a second electrode on the second metal oxide layer.