WO2019140993A1 - 信息表示方法、多进制计算电路及电子系统 - Google Patents

信息表示方法、多进制计算电路及电子系统 Download PDF

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Publication number
WO2019140993A1
WO2019140993A1 PCT/CN2018/115258 CN2018115258W WO2019140993A1 WO 2019140993 A1 WO2019140993 A1 WO 2019140993A1 CN 2018115258 W CN2018115258 W CN 2018115258W WO 2019140993 A1 WO2019140993 A1 WO 2019140993A1
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signal
information
threshold
ary
value
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PCT/CN2018/115258
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English (en)
French (fr)
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修黎明
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京东方科技集团股份有限公司
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Priority to EP18882266.2A priority Critical patent/EP3742418B1/en
Priority to US16/465,283 priority patent/US11184020B2/en
Publication of WO2019140993A1 publication Critical patent/WO2019140993A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00—Electric signal transmission systems
    • G08C19/02—Electric signal transmission systems in which the signal transmitted is magnitude of current or voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00—Electric signal transmission systems
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00—Electric signal transmission systems
    • G08C19/16—Electric signal transmission systems in which transmission is by pulses
    • G08C19/18—Electric signal transmission systems in which transmission is by pulses using a variable number of pulses in a train
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/22—Conversion to or from representation by sinusoidal signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching

Definitions

  • Embodiments of the present disclosure relate to an information display method, a multi-digit calculation circuit, and an electronic system.
  • the characteristics of the fourth industrial revolution include information, interconnection, and intelligence.
  • the fourth industrial revolution is aimed at achieving the interconnection of all things and the intelligence of life. Interconnection and intelligence are all built around information.
  • information for the Internet, it is defined as information (for example, the Internet refers to the interconnection of information, not direct contact between machines).
  • intelligence the intelligent control of everything is achieved through information manipulation.
  • Information in the traditional sense refers to speech, words, peak fire, sign language, semaphores, drum sounds, and so on.
  • information refers to the data stream that flows in the electronic world. In the electronic age, data-streamed electronic information has new temporal and spatial characteristics, which can be transmitted in real time over long distances, and can be saved and restored without loss.
  • An embodiment of the present disclosure provides an information representation method of an electronic system, including: acquiring a rate of change of a signal; and using the rate of change of the signal to represent the information.
  • the information is represented as a change rate bit, and the value range of the change rate bit includes N types of change rate states, where N is a positive integer and N>1.
  • the value of the information is equal to the value of the change rate bit, and represents one of the N rate change states.
  • the value of the change rate bit is an N-digit number.
  • the value of the change rate bit is the number of times the signal passes through the threshold within a fixed time window.
  • the signal is a voltage signal
  • the threshold is a threshold voltage
  • the information indicating the rate of change of the signal includes: using the voltage signal in the The number of times the threshold voltage is crossed within a fixed time window to represent the value of the information.
  • the threshold voltage has a selected voltage value.
  • the signal is a current signal
  • the threshold is a threshold current
  • using the rate of change of the signal to represent information includes: using the current signal in the The number of times the threshold current is passed through the fixed time window to represent the value of the information.
  • the threshold current has a selected current value.
  • the value of the change rate bit is the number of times the signal enters the threshold range within a fixed time window, the number of times of leaving the threshold range, or the number of times and the time of entering the threshold range One of the sum of the threshold ranges.
  • the signal is a voltage signal
  • the threshold range is a threshold voltage range
  • the change rate of the signal is used to represent information, including: using the voltage signal The number of times the threshold voltage range is entered and/or exited within the fixed time window to represent the value of the information.
  • the signal is a current signal
  • the threshold range is a threshold current range
  • using the rate of change of the signal to represent information includes: using the current signal in The number of times the threshold current range is entered and/or exited within the fixed time window to represent the value of the information.
  • the rate of change of the signal indicates the speed at which the signal changes within a fixed time window.
  • the rate of change of the signal is associated with a flip speed of a transistor in the electronic system.
  • An embodiment of the present disclosure further provides a multi-ary calculation circuit, including:
  • a first mode conversion circuit configured to: receive an input signal, the amplitude of the input signal is used to represent the first information; and convert the input signal to a first multi-ary signal, the first multi-ary a rate of change of the signal is used to represent the first information;
  • a multi-ary logic operation circuit configured to: receive the first multi-ary signal from the first standard conversion circuit; and perform a multi-ary logical operation according to the first multi-ary signal, and output a a binary signal as a result of the multi-ary logical operation, the rate of change of the second multi-ary signal being used to represent the second information;
  • a second mode conversion circuit configured to: receive the second multi-ary signal from the multi-ary logic operation circuit; and convert the second multi-ary signal into an output signal, the output signal The amplitude is used to represent the second information.
  • the input signal and the output signal are both binary data signals.
  • the first information includes input information of the multi-digit calculation circuit
  • the second information includes output information of the multi-digit calculation circuit.
  • the first information and the second information are both represented as change rate bits, and the range of the change rate bits includes N change rates.
  • N is a positive integer and N>1.
  • the value of the first information and the value of the second information are respectively a first value and a second value of the change rate bit
  • the first value of the rate of change bit represents one of the N rate of change states
  • the second value of the rate of change bit also represents one of the N rate of change states.
  • the first value of the change rate bit is an N-digit number
  • the second value of the change rate bit is also an N-ary number
  • the first value of the change rate bit is the number of times the first multi-digit signal crosses a threshold within a fixed time window
  • the second value of the bit is the number of times the second multi-ary signal crosses the threshold within the fixed time window.
  • the first multi-signal signal and the second multi-ary signal are respectively a first voltage signal and a second voltage signal
  • the threshold is a threshold voltage
  • the value of the first information is the number of times the first voltage signal passes the threshold voltage in the fixed time window
  • the value of the second information is the second voltage signal at the fixed time a number of times the threshold voltage is passed through the window
  • the first multi-signal signal and the second multi-signal signal are respectively a first current signal and a second current signal, the threshold being a threshold current
  • the The value of an information is the number of times the first current signal passes the threshold current in the fixed time window
  • the value of the second information is the second current signal passing through the fixed time window The number of times the threshold current.
  • the first value of the change rate bit is the number of times the first multi-digit signal enters the threshold range within a fixed time window, leaving the threshold. One of the number of times or the sum of the number of times entering the threshold range and the number of times the threshold range is left; and the second value of the rate of change bit is the second time of the second multi-ary signal at the fixed time window One of the number of times the threshold range is entered, the number of times the threshold range is left, or the number of times the threshold range is entered and the number of times the threshold range is entered.
  • the first multi-signal signal and the second multi-ary signal are respectively a first voltage signal and a second voltage signal
  • the threshold range a threshold voltage range
  • the value of the first information being the number of times the first voltage signal enters the threshold voltage range within the fixed time window, the number of times away from the threshold voltage range, or entering the threshold voltage range One of the number of times and the number of times of leaving the threshold voltage range
  • the value of the second information being the number of times the second voltage signal enters the threshold voltage range within the fixed time window, leaving the One of a threshold voltage range or a sum of a number of times of entering the threshold voltage range and a number of times of leaving the threshold voltage range
  • the first multi-signal signal and the second multi-digit signal are respectively a first current signal and a second current signal
  • the threshold range is a threshold current range
  • the value of the first information is the first current signal within the fixed time window One of a number of times of entering the threshold current range
  • An embodiment of the present disclosure further provides an electronic system, including the multi-digit computing circuit of any of the above.
  • an electronic system provided by an embodiment of the present disclosure further includes: one or more data input modes configured to provide the input signal; and one or more data acceptance modes configured to receive the output signal.
  • FIG. 1 is a flowchart of an information representation method according to an embodiment of the present disclosure
  • 2A is a schematic block diagram of an electronic system including a binary computing circuit
  • 2B is a schematic block diagram of an electronic system including a multi-ary computing circuit according to an embodiment of the present disclosure
  • FIG. 3A shows an example of using the amount of charge amount (ie, amplitude) to represent information
  • FIG. 3B illustrates an example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure
  • FIG. 3C illustrates another example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure
  • FIG. 3D illustrates yet another example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure.
  • Moore's Law refers to the phenomenon that when the price is constant, the number of components that can be accommodated on an integrated circuit chip is doubled every 18-24 months.
  • Moore's Law contains both spatial and temporal factors.
  • the spatial factor of Moore's Law indicates that the semiconductor process is progressively reduced by the gradual reduction of the minimum line width.
  • the line width becomes small, the speed at which the transistor is turned over becomes faster, so that the event occurs faster in the electronic world, and the efficiency of expressing information becomes higher. This is manifested as a generation-by-generation improvement in the operating frequency of electronic devices.
  • the embodiment of the present disclosure utilizes the flipping speed of a transistor to express information. For example, within a fixed time window, the information can be represented using the number of times the voltage waveform crosses the threshold.
  • the information representation method and the multi-digit calculation circuit provided by the embodiments of the present disclosure are compatible with the development trend of the semiconductor process.
  • the amplitude of the signal representing the information can be greatly reduced, which contributes to greatly reducing power consumption. Due to the use of multi-ary, a rate-of-change bit will likely contain multiple states, making it possible to perform operations directly in multiple digits in a computer, greatly increasing the computational efficiency of the computer.
  • FIG. 1 is a flowchart of an information representation method according to an embodiment of the present disclosure. As shown in FIG. 1, an embodiment of the present disclosure provides an information representation method 100 of an electronic system.
  • the information representation method 100 includes, but is not limited to:
  • Step S102 acquiring a switching rate of the signal
  • Step S104 using the rate of change of the signal to represent the information.
  • the information is represented as a switching-rate bit, the range of values of the rate-of-change bits includes N rate-of-change states, N being a positive integer and N>1.
  • the value of the information is equal to the value of the rate of change bit and represents one of the N rate of change states.
  • the value of the rate of change bit is an N-digit number.
  • the information may be represented as a multi-value switching rate bit, for example, an N-ary change rate bit.
  • the value range of the N-ary change rate bit includes 0, 1, 2...N-1 (or 1, 2...N-1, N) for a total of N values or states, and the value of the information at a certain time may be Is one of the N values or N states.
  • the value of the rate of change bit is the number of times the signal crosses a threshold within a fixed time window.
  • the length of the fixed time window may be determined in advance according to the data processing capability of the electronic system, or determined by the user, and the disclosure is not limited herein.
  • the signal is a voltage signal and the threshold is a threshold voltage; using the rate of change of the signal to represent information in step S104 includes: using the voltage signal to pass the threshold voltage within the fixed time window The number of times to represent the value of the information.
  • the threshold voltage has a selected voltage value, for example, 0.5V or other predetermined voltage value.
  • FIG. 3B illustrates an example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure
  • FIG. 3C illustrates another example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure.
  • the number of times the voltage signal passes through the threshold voltage is 8, and therefore, the value of the information is 8; in the second time window W2, the number of times the voltage signal passes through the threshold voltage is 4. Therefore, the value of the information is 4.
  • Both the first time window W1 and the second time window W2 have equal lengths of time.
  • the number of times the voltage signal passes through the threshold voltage is 8, 0, 16, and 2, respectively, and therefore, the values of the information in each time window W are 8, 0, and 16, respectively. And 2.
  • the signal is a current signal
  • the threshold is a threshold current
  • using the rate of change of the signal to represent information in step S104 comprising: using the current signal to pass the threshold within the fixed time window The number of currents to represent the value of the information.
  • the threshold current has a selected current value, for example, 0.1 uA or other current value.
  • the value of the rate of change bit is the sum of the number of times the signal enters the threshold range within a fixed time window, the number of times the threshold range is left, or the number of times the threshold range is entered and the number of times the threshold range is left. one of the.
  • the signal is a voltage signal
  • the threshold range is a threshold voltage range
  • using the rate of change of the signal to represent information in step S104 includes: using the voltage signal to enter and/or within the fixed time window Or the number of times the threshold voltage range is left to represent the value of the information.
  • the value of the information is equal to the number of times the voltage signal enters the threshold voltage range within the fixed time window, or is equal to the number of times the voltage signal leaves the threshold voltage range within the fixed time window, Or equal to the sum of the number of times the voltage signal enters the threshold voltage range within the fixed time window and the number of times away from the threshold voltage range.
  • FIG. 3D illustrates yet another example of using the multi-ary rate of change to represent information provided by an embodiment of the present disclosure.
  • the number of times the voltage signal enters the threshold voltage range is 8, and therefore, the value of the information is 8; in the second time window W2, the number of times the voltage signal enters the threshold voltage range is 4. Therefore, the value of the information is 4.
  • Both the first time window W1 and the second time window W2 have equal lengths of time.
  • the number of times the voltage signal leaves the threshold voltage range is 8 and 4, respectively, and thus the values of the information are 8 and 4, respectively.
  • FIG. 3D in conjunction with FIG.
  • the signal is a current signal
  • the threshold range is a threshold current range
  • using the rate of change of the signal to represent information in step S104 comprising: using the current signal to enter the fixed time window
  • the number of times the threshold current range and/or the number of times away from the threshold current range are indicative of the value of the information.
  • the value of the information is equal to the number of times the current signal enters the threshold current range within the fixed time window, or is equal to the number of times the current signal leaves the threshold current range within the fixed time window, Or equal to the sum of the number of times the current signal enters the threshold current range within the fixed time window and the number of times the threshold current range is removed.
  • the rate of change of the signal represents the rate at which the signal changes over a fixed time window.
  • the waveform change speed of the signal in the first time window W1 is greater than the waveform change speed in the second time window W2, that is, the rate of change of the signal in the first time window W1 is greater than in the second time window W2.
  • the rate of change of the signal is associated with the rate of inversion of the transistor in the electronic system. The faster the transistor flips, the faster the signal changes.
  • Fig. 3A shows an example of using the amount of charge amount (i.e., amplitude) to represent information.
  • the amount of charge is used to represent information, and one bit can only represent two states "1" or "0".
  • a large amount of charge ie, a high voltage
  • a small amount of charge ie, a low voltage
  • the magnitude of the voltage (or current) of the signal is no longer the focus of attention. Therefore, with the advancement of the process, the reduction in power supply voltage will not be the main cause of information fidelity.
  • the information representation method provided by the embodiment of the present disclosure is consistent with the development trend of the semiconductor process: the smaller the line width, the faster the transistor flips, and the more effective the information representation method provided by the embodiment of the present disclosure.
  • the information representation method provided by the embodiment of the present disclosure has, but is not limited to, the following advantages.
  • the amplitude of the signal representing the information here can be greatly reduced, helping to greatly reduce power consumption.
  • the amplitude of the voltage signal needs to reach the power supply voltage VDD and the ground voltage VSS in order to distinguish between the high level and the low level.
  • the amplitude of the voltage signal does not need to reach the power supply voltage VDD and the ground voltage VSS (because it is only necessary to determine whether the voltage signal crosses the threshold voltage or the threshold voltage range), which helps Reduce power consumption.
  • the second advantage is multi-ary.
  • one bit can only represent two states.
  • a change rate bit may possibly include multiple states, so that it is possible to directly perform operations in a multi-ary number in a computer, which greatly improves the computational efficiency of the computer.
  • FIG. 2A is a schematic block diagram of an electronic system including a binary computing circuit 200.
  • the electronic system includes an input circuit group 203, a binary calculation circuit 200, and an output circuit group 209.
  • Input circuit group 203 includes one or more data input modes.
  • the sensor circuit 204, the pre-stage input circuit 206, and the data processing chip 208 are three specific examples of data input methods.
  • Each data input circuit provides an input signal 218 to binary computing circuit 200.
  • the amplitude of the input signal 218 is used to represent the first information.
  • the first information is input information.
  • the amplitude of the input signal 218 carries input information.
  • the input signal 218 is a binary signal, and the magnitudes of the used amplitudes represent information "1" and "0", respectively (as shown in FIG. 3A, the high voltage amplitude represents the value of the information "1" and the value of the low voltage amplitude represents the information". 0”).
  • sensor circuit 204 includes an infrared sensor, a temperature sensor, a voice sensor, or any other type of sensor.
  • the pre-stage input circuitry 206 can include, but is not limited to, an image acquisition device (eg, a camera), a sound collection device (eg, a microphone), or other circuitry that inputs data.
  • Data processing chip 208 may include, for example, a chip for processing data, such as filters, analog to digital converters, amplifiers, and the like.
  • the binary logic operational circuit 200 is configured to: receive input signals from respective data input circuits; and perform binary logic operations in accordance with the input signals and use the results of the binary logic operations as output signals 220.
  • the amplitude of the output signal 220 is used to represent the second information.
  • the second information is output information.
  • the amplitude of the output signal 220 carries the output information.
  • the output signal 220 is a binary signal, and the magnitudes of the used amplitudes represent information "1" and "0", respectively.
  • Output circuit group 209 includes one or more data acceptance modes.
  • the display 210, the actuator circuit 212, the subsequent stage receiving circuit 214, and the data receiving chip 216 are specific examples of four different data receiving modes.
  • Each data accepting mode receives the output signal 220 from the binary computing circuit 200 and performs a corresponding operation.
  • display 210 can be an LCD display, an OLED display, or other type of display.
  • the actuator circuit 212 can include a drive motor, such as a motor, or other actuating device.
  • the post-acceptance circuitry 214 can include a sound card, graphics card, or other circuitry for receiving data.
  • the data accepting chip 216 can be, for example, a buffer, a register, or other circuit for receiving data.
  • the pre-stage input circuit 206, the binary logic operation circuit 200 and the post-stage acceptance circuit 214 can be integrated in the same chip, the pre-stage input circuit 206 is the pre-stage circuit of the binary logic operation circuit 200, and the post-stage acceptance circuit 214 is the binary logic operation. The latter stage of the circuit 200.
  • the embodiment of the present disclosure further provides a multi-ary calculation circuit 250, including:
  • a first mode conversion circuit 254 configured to receive an input signal 218, the amplitude of the input signal 218 being used to represent the first information; and converting the input signal 218 to a first multi-ary signal 260, The rate of change of the first multi-ary signal 260 is used to represent the first information;
  • the multi-ary logical operation circuit 252 is configured to: receive the first multi-ary signal 260 from the first standard conversion circuit 254; and perform multi-ary logical operation according to the first multi-ary signal 260 And outputting a second multi-ary signal 262 as a result of the multi-ary logical operation, the rate of change of the second multi-ary signal 262 being used to represent the second information;
  • a second system conversion circuit 256 configured to: receive the second multi-ary signal 262 from the multi-ary logic operation circuit 252; and convert the second multi-ary signal 262 into an output signal 220, The amplitude of the output signal 220 is used to represent the second information.
  • the first system conversion circuit 254, the multi-ary logic operation circuit 252, and the second system conversion circuit 256 may be dedicated circuits, and may be designed as separate chips or integrated in the same chip, respectively.
  • the first system conversion circuit 254, the multi-ary logic operation circuit 252, and the second system conversion circuit 256 may be implemented using a transistor or implemented using an FPGA (or ASIC), which is not limited herein.
  • the input signal 218 and the output signal 220 are both binary data signals.
  • the first information includes input information of the multi-ary calculation circuit 250
  • the second information includes output information of the multi-ary calculation circuit 250.
  • the first information and the second information are both represented as change rate bits, and the value range of the change rate bits includes N change rate states, N being a positive integer and N>1.
  • the value of the first information and the value of the second information are respectively a first value and a second value of the rate of change bit
  • the first value of the rate of change bit represents the N rate of change state
  • the second value of the rate of change bit also represents one of the N rate of change states.
  • the state represented by the first value of the change rate bit and the state represented by the second value of the change rate bit may be the same or different, and the disclosure does not limit this.
  • the first value of the rate-of-change bit is an N-ary number
  • the second value of the rate-of-change bit is also an N-ary number
  • the first value of the change rate bit is a number of times the first multi-ary signal crosses a threshold within a fixed time window
  • the second value of the change rate bit is the second multiple The number of times the hex signal passes through the threshold within the fixed time window
  • the first multi-signal signal and the second multi-ary signal are respectively a first voltage signal and a second voltage signal
  • the threshold is a threshold voltage
  • the value of the first information is the first voltage signal The number of times the threshold voltage is passed through the fixed time window, the value of the second information being the number of times the second voltage signal passes the threshold voltage within the fixed time window.
  • the first multi-signal signal and the second multi-ary signal are respectively a first current signal and a second current signal
  • the threshold is a threshold current
  • the value of the first information is the The number of times a current signal passes through the threshold current during the fixed time window
  • the value of the second information is the number of times the second current signal passes the threshold current within the fixed time window.
  • the first value of the rate of change bit is the number of times the first plurality of signals enters the threshold range within a fixed time window, the number of times the threshold range is left, or the number of times and the range of entering the threshold range One of the sum of the threshold ranges.
  • the second value of the change rate bit is the sum of the number of times the second multi-ary signal enters the threshold range within the fixed time window, the number of times of leaving the threshold range, or the number of times the threshold range is entered and the number of times the threshold range is left. one of the.
  • the first multi-signal signal and the second multi-ary signal are respectively a first voltage signal and a second voltage signal
  • the threshold range is a threshold voltage range.
  • the value of the first information is a sum of a number of times the first voltage signal enters a threshold voltage range within the fixed time window, a number of times of leaving the threshold voltage range, or a number of times of entering the threshold voltage range and a number of times of leaving the threshold voltage range one of the.
  • the value of the second information is a sum of a number of times the second voltage signal enters the threshold voltage range within the fixed time window, a number of times of leaving the threshold voltage range, or a number of times of entering the threshold voltage range and a number of times of leaving the threshold voltage range one of the.
  • the first multi-signal signal and the second multi-ary signal are respectively a first current signal and a second current signal
  • the threshold range is a threshold current range.
  • the value of the first information is a sum of a number of times the first current signal enters a threshold current range within the fixed time window, a number of times of leaving the threshold current range, or a number of times of entering the threshold current range and a number of times of leaving the threshold current range one of the.
  • the value of the second information is the sum of the number of times the second current signal enters the threshold current range within the fixed time window, the number of times the threshold current range is left, or the number of times the threshold current range is entered and the number of times the threshold current range is left. one of the.
  • the description of the multi-ary calculation circuit 250 can also refer to the related description in the embodiment of the above-mentioned information representation method 100, and the repeated description is not repeated herein.
  • an embodiment of the present disclosure further provides an electronic system 299, including the multi-ary computing circuit 250 described in any of the above.
  • the electronic system 299 further includes one or more data input modes configured to provide the input signal 218, and one or more data acceptance modes configured to receive the output signal 220.
  • the electronic system 299 includes an input circuit group 203 and an output circuit group 209.
  • Input circuit group 203 includes one or more data input modes.
  • sensor circuit 204, pre-stage input circuit 206, and data processing chip 208 are three specific examples of data input methods.
  • the display 210, the actuator circuit 212, the subsequent stage receiving circuit 214, and the data receiving chip 216 are specific examples of four different data receiving modes. The similarities between FIG. 2A and FIG. 2B are not repeated here.
  • the pre-stage input circuit 206, the multi-ary calculation circuit 250, and the post-stage acceptance circuit 214 may be integrated in the same chip, the pre-stage input circuit 206 is the previous stage circuit of the multi-ary calculation circuit 250, and the subsequent stage acceptance circuit 214 The latter stage circuit of the circuit 250 is calculated in multiple numbers.
  • each data signal is a binary data signal, and its calculation efficiency is low.
  • the input signal 218 is a binary data signal, which is converted into a first multi-ary signal 260 by the first standard conversion circuit 254; the multi-ary logic operation circuit 252 directly multiplies the first multi-ary signal 260.
  • the logic operates and outputs a second multi-ary signal 262, which converts the second multi-ary signal 262 into an output signal 220 of binary data and provides it to each data receiving circuit.
  • the first-order conversion from binary data to multi-ary data and the second-standard conversion from multi-ary data to binary data, the multi-ary calculation circuit provided by the embodiment of the present disclosure can directly perform operations using multiple numbers, not only Greatly improve the computing efficiency of the computer, and can also be compatible with the existing data input methods and data receiving methods.
  • the multi-ary calculation circuit 250 (including the first system conversion circuit 254, the multi-ary logic operation circuit 252, the second system conversion circuit 256) can be implemented using dedicated hardware (for example, dedicated chip, integration) Circuit, etc.).
  • the multi-ary calculation circuit 250 may also be implemented by a combination of software or software and hardware.
  • the multi-ary calculation circuit 250 can be a circuit board or a combination of a plurality of circuit boards.
  • the one or a combination of the plurality of boards may include: (1) one or more processors; (2) one or more non-transitory computer readable memories coupled to the processor; and (3) A firmware executable by the processor that is stored in the memory.
  • the processor can process the data signals and can include various computing structures, such as a Complex Instruction Set Computer (CISC) architecture, a Structured Reduced Instruction Set Computer (RISC) architecture, or a structure that implements a combination of multiple instruction sets.
  • the processor can also be a microprocessor, such as an X86 processor or an ARM processor, or can be a digital processor (DSP) or the like.
  • the processor can control other components in the electronic system to perform the desired functions.
  • the memory can hold instructions and/or data executed by the processor.
  • the memory can include one or more computer program products, which can include various forms of computer readable storage media, such as volatile memory and/or nonvolatile memory.
  • the volatile memory may include, for example, a random access memory (RAM) and/or a cache or the like.
  • the nonvolatile memory may include, for example, a read only memory (ROM), a hard disk, a flash memory, or the like.
  • One or more computer program instructions can be stored on the computer readable storage medium, and the processor can execute the program instructions to implement the information representations provided by the embodiments of the present disclosure and/or other desired functions.
  • Various applications and various data may also be stored in the computer readable storage medium, such as various data used and/or generated by the application, and the like.
  • the embodiment of the present disclosure further provides a computer readable storage medium having stored thereon computer instructions that, when executed by a processor, implement the operations of the information representation method 100 illustrated in FIG.
  • the above memory is one of a computer readable storage medium.
  • the amplitude of the signal representing the information can be greatly reduced, which contributes to greatly reducing power consumption. Due to the use of multi-ary, a rate-of-change bit will likely contain multiple states, making it possible to perform operations directly in multiple digits in a computer, greatly increasing the computational efficiency of the computer.

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Abstract

一种信息表示方法、多进制计算电路和电子系统。该信息表示方法(100)包括：获取信号的变化率（S102）；以及使用该信号的变化率来表示信息（S104）。

Description

信息表示方法、多进制计算电路及电子系统
本申请要求于2018年01月17日递交的中国专利申请第201810044849.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种信息表示方法、多进制计算电路及电子系统。
背景技术
第四次产业革命的特征包括信息(information)、互联、智能，第四次产业革命是为了达到万物互联和生活智能化的目的。互联与智能都是围绕信息展开的。对互联而言，它的定义对象是信息(例如，互联网是指信息的互相联结，而非机器间的直接接触)。对智能而言，万物的智能化控制是通过信息来操作实现的。传统意义上的信息是指语音、文字、峰火、手语、旗语、鼓声等。在第四次产业革命中，信息指的是在电子世界中流动的数据流(data stream)。在电子时代，数据流化的电子信息具有新的时空特征，既可以被远距离实时传输，还可以被无损耗地保存和恢复。
发明内容
本公开一实施例提供一种电子系统的信息表示方法，包括：获取信号的变化率；以及使用所述信号的变化率来表示信息。
例如，在本公开一实施例提供的信息表示方法中，所述信息被表示为变化率比特，所述变化率比特的取值范围包括N种变化率状态，N为正整数且N>1。
例如，在本公开一实施例提供的信息表示方法中，所述信息的值等于所述变化率比特的值，且代表所述N种变化率状态中的一种。
例如，在本公开一实施例提供的信息表示方法中，所述变化率比特的值为一个N进制数字。
例如，在本公开一实施例提供的信息表示方法中，所述变化率比特的值为所述信号在固定时间窗口内穿过阈值的次数。
例如，在本公开一实施例提供的信息表示方法中，所述信号为电压信号， 所述阈值为阈值电压；使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定时间窗口内穿过所述阈值电压的次数来表示所述信息的值。
例如，在本公开一实施例提供的信息表示方法中，所述阈值电压具有选定的电压值。
例如，在本公开一实施例提供的信息表示方法中，所述信号为电流信号，所述阈值为阈值电流；使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内穿过所述阈值电流的次数来表示所述信息的值。
例如，在本公开一实施例提供的信息表示方法中，所述阈值电流具有选定的电流值。
例如，在本公开一实施例提供的信息表示方法中，所述变化率比特的值为所述信号在固定时间窗口内进入阈值范围的次数、离开阈值范围的次数或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。
例如，在本公开一实施例提供的信息表示方法中，所述信号为电压信号，所述阈值范围为阈值电压范围；使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定时间窗口内进入和/或离开所述阈值电压范围的次数来表示所述信息的值。
例如，在本公开一实施例提供的信息表示方法中，所述信号为电流信号，所述阈值范围为阈值电流范围；使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内进入和/或离开所述阈值电流范围的次数来表示所述信息的值。
例如，在本公开一实施例提供的信息表示方法中，所述信号的变化率表示所述信号在固定时间窗口内变化的速度。
例如，在本公开一实施例提供的信息表示方法中，所述信号的变化率与所述电子系统中晶体管的翻转速度相关联。
本公开一实施例还提供一种多进制计算电路，包括：
第一制式转换电路，被配置为：接收输入信号，所述输入信号的幅度被用来表示第一信息；以及将所述输入信号转换为第一多进制信号，所述第一多进制信号的变化率被用来表示所述第一信息；
多进制逻辑操作电路，被配置为：接收来自所述第一制式转换电路的所述第一多进制信号；以及根据所述第一多进制信号进行多进制逻辑操作，并输出第二多进制信号作为所述多进制逻辑操作的结果，所述第二多进制信号的变化 率被用来表示第二信息；以及
第二制式转换电路，被配置为：接收来自所述多进制逻辑操作电路的所述第二多进制信号；以及将所述第二多进制信号转换为输出信号，所述输出信号的幅度被用来表示所述第二信息。
例如，在本公开一实施例提供的多进制计算电路中，所述输入信号和所述输出信号均为二进制数据信号。
例如，在本公开一实施例提供的多进制计算电路中，所述第一信息包括所述多进制计算电路的输入信息，所述第二信息包括所述多进制计算电路的输出信息。
例如，在本公开一实施例提供的多进制计算电路中，所述第一信息和所述第二信息均被表示为变化率比特，所述变化率比特的取值范围包括N种变化率状态，N为正整数且N>1。
例如，在本公开一实施例提供的多进制计算电路中，所述第一信息的值和所述第二信息的值分别为所述变化率比特的第一数值和第二数值，所述变化率比特的第一数值代表所述N种变化率状态中的一种状态，所述变化率比特的第二数值也代表所述N种变化率状态中的一种状态。
例如，在本公开一实施例提供的多进制计算电路中，所述变化率比特的第一数值为一个N进制数字，所述变化率比特的第二数值也为一个N进制数字。
例如，在本公开一实施例提供的多进制计算电路中，所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内穿过阈值的次数，所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内穿过所述阈值的次数。
例如，在本公开一实施例提供的多进制计算电路中，所述第一多进制信号和第二多进制信号分别为第一电压信号和第二电压信号，所述阈值为阈值电压，所述第一信息的值为所述第一电压信号在所述固定时间窗口内穿过所述阈值电压的次数，所述第二信息的值为所述第二电压信号在所述固定时间窗口内穿过所述阈值电压的次数；或者，所述第一多进制信号和第二多进制信号分别为第一电流信号和第二电流信号，所述阈值为阈值电流，所述第一信息的值为所述第一电流信号在所述固定时间窗口内穿过所述阈值电流的次数，所述第二信息的值为所述第二电流信号在所述固定时间窗口内穿过所述阈值电流的次数。
例如，在本公开一实施例提供的多进制计算电路中，所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内进入阈值范围的次数、离开所述阈值范围的次数或者进入所述阈值范围的次数和离开所述阈值范围的次数之和中的一个；以及所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内进入阈值范围的次数、离开阈值范围的次数或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。
例如，在本公开一实施例提供的多进制计算电路中，所述第一多进制信号和所述第二多进制信号分别为第一电压信号和第二电压信号，所述阈值范围为阈值电压范围，所述第一信息的值为所述第一电压信号在所述固定时间窗口内进入所述阈值电压范围的次数、离开所述阈值电压范围的次数或者进入所述阈值电压范围的次数和离开所述阈值电压范围的次数之和中的一个，所述第二信息的值为所述第二电压信号在所述固定时间窗口内进入所述阈值电压范围的次数、离开所述阈值电压范围的次数或者进入所述阈值电压范围的次数和离开所述阈值电压范围的次数之和中的一个；或者，所述第一多进制信号和所述第二多进制信号分别为第一电流信号和第二电流信号，所述阈值范围为阈值电流范围，所述第一信息的值为所述第一电流信号在所述固定时间窗口内进入所述阈值电流范围的次数、离开所述阈值电流范围的次数或者进入所述阈值电流范围的次数和离开所述阈值电流范围的次数之和中的一个，所述第二信息的值为所述第二电流信号在所述固定时间窗口内进入所述阈值电流范围的次数、离开所述阈值电流范围的次数或者进入所述阈值电流范围的次数和离开所述阈值电流范围的次数之和中的一个。
本公开一实施例还提供一种电子系统，包括上述任一项所述多进制计算电路。
例如，本公开一实施例提供的电子系统还包括：一或多个数据输入方式，被配置为提供所述输入信号；以及一或多个数据接受方式，被配置为接收所述输出信号。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，而非对本公开的限制，对于本领域普通技术人员来讲，在不付 出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种信息表示方法的流程图；
图2A为一种包括二进制计算电路的电子系统示意性框图；
图2B为本公开实施例提供的一种包括多进制计算电路的电子系统示意性框图；
图3A示出了一个使用电荷量的数量(即幅度)来表示信息的例子；
图3B示出了本公开实施例提供的一个使用多进制变化率来表示信息的例子；
图3C示出了本公开实施例提供的另一个使用多进制变化率来表示信息的例子；
图3D示出了本公开实施例提供的又一个使用多进制变化率来表示信息的例子。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，以下举实施例对本公开作进一步详细说明。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
摩尔定律指的是这样一个现象：当价格不变时，一个集成电路芯片上可容纳的元器件数目约每隔18-24个月便会增加一倍。摩尔定律包含着空间因素和时间因素。例如，摩尔定律的空间因素表示：半导体制程是以最小线宽的逐步缩小为世代递进标志的。当线宽变小时，晶体管翻转的速度变快，从而在电子世界内事件发生的速度变快，表达信息的效率变高。这表现为电子器件工作频率的逐代提高。
随着硅片上电路密度的增加，电路的复杂性将呈指数增长。同时，晶体管数目的平方律增加导致制造上的差错率将呈指数增长。这使得彻底的芯片测试几乎成为不可能。当芯片上线条宽度达到纳米数量级时，线条宽度相当于只有几个分子的大小。这种情况下材料的物理和化学性能会发生质的变化，致使器件不能正常工作。从芯片的运行上看，也存在两大问题。第一个问题是功耗急剧增加，大型复杂芯片的功耗有可能达到上百瓦。当晶体管的线宽缩小时，虽然其开关速度越来越快，但其开关性能变得越来越差，在“关”的状态下还有可 观的电流存在，即漏电现象。鳍式晶体管结构虽然能在一定程度上改善这个状况，但也有其潜力极限。第二个问题是由高功耗所带来的高温度。高温度将会导致芯片中的电路无法正常工作。功耗和温度这两个问题在电路集成度不断提高的趋势下会变的越来越严峻。这些事实表明，继续以缩小线宽为标志的空间方向挖掘摩尔定律已无很大潜力。
在集成电路发展的过程中，不论是模拟电路技术还是数字电路技术，信息一直是用电荷的数量(电压幅度的高和低)来表达的。在这种表达方式中，信息的保真度至少受两个因素的影响。第一个因素是电源电压的幅值。第二个因素是背景噪声。在半导体技术发展的过程中，在缩小线宽增加速度的同时，为降低功耗，电源电压一直在逐代降低。但是背景噪声的水平一直没有降低。因此，用电压幅度来表示信息需要解决越来越多的困难。但在另一个方面，晶体管线宽缩小的直接效果是晶体管的翻转速度变快。基于上述半导体工艺的发展趋势，本公开实施例利用晶体管的翻转速度来表达信息。例如，在固定时间窗口内，可以使用电压波形穿过阈值的次数来表示信息。
本公开实施例提供的信息表示方法以及多进制计算电路与半导体工艺的发展趋势相契合的。半导体线宽越变小，晶体管翻转的速度越快，本公开实施例提供的信息表示方法以及多进制计算电路越有效。因此，本公开实施例提供的信息表示方法、多进制计算电路以及电子系统能够有效地降低功耗，同时还能提高计算效率。
在本公开实施例提供的信息表示方法、多进制计算电路和电子系统中，表示信息的信号的幅度可以大幅度地减小，有助于极大地降低功耗。由于采用多进制，一个变化率比特将有可能包含多种状态，使得在计算机中直接用多进制进行运算成为可能，极大地提高计算机的计算效率。
图1为本公开实施例提供的一种信息表示方法的流程图。如图1所示，本公开实施例提供一种电子系统的信息表示(information representation)方法100。该信息表示方法100包括，但不限于：
步骤S102，获取信号的变化率(switching rate)；以及
步骤S104，使用所述信号的变化率来表示信息。
在传统的系统中，最基本的信息单位是比特(bit)。在一个时钟周期，一个比特只能处于高或低两种状态中的一种。在本公开的一些实施例中，所述信息被表示为变化率比特(switching-rate bit)，所述变化率比特的取值范围包括 N种变化率状态，N为正整数且N>1。所述信息的值等于所述变化率比特的值，且代表所述N种变化率状态中的一种。所述变化率比特的值为N进制数字。例如，所述信息可以被表示为多进制变化率比特(multi-value switching-rate bit)，例如，N进制变化率比特。该N进制变化率比特的取值范围包括0,1,2…N-1(或1,2…N-1，N)共N个数值或状态，而在某一时刻的信息的值可以为该N个数值或N个状态中的一个。
例如，在一些实施例中，所述变化率比特的值为所述信号在固定时间窗口内穿过阈值的次数。该固定时间窗口的长度可以预先根据电子系统的数据处理能力确定，或者由用户确定，本公开在此不作限定。
例如，所述信号为电压信号，所述阈值为阈值电压；步骤S104中使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定时间窗口内穿过所述阈值电压的次数来表示所述信息的值。所述阈值电压具有选定的电压值，例如，0.5V或其他预先确定的电压数值。
图3B示出了本公开实施例提供的一个使用多进制变化率来表示信息的例子；图3C示出了本公开实施例提供的另一个使用多进制变化率来表示信息的例子。
例如，结合图3B，在第一时间窗口W1，电压信号穿过阈值电压的次数为8，因此，所述信息的值为8；在第二时间窗口W2，电压信号穿过阈值电压的次数为4，因此，所述信息的值为4。第一时间窗口W1和第二时间窗口W2均具有相等的时间长度。又例如，结合图3C，在各时间窗口W，电压信号穿过阈值电压的次数分别为8、0、16和2，因此，在各时间窗口W所述信息的值分别为8、0、16和2。
又例如，所述信号为电流信号，所述阈值为阈值电流；步骤S104中使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内穿过所述阈值电流的次数来表示所述信息的值。所述阈值电流具有选定的电流值，例如，0.1uA或其他电流数值。
例如，在一些实施例中，所述变化率比特的值为所述信号在固定时间窗口内进入阈值范围的次数、离开阈值范围的次数、或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。
例如，所述信号为电压信号，所述阈值范围为阈值电压范围；在步骤S104中使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定时 间窗口内进入和/或离开所述阈值电压范围的次数来表示所述信息的值。例如，所述信息的值等于所述电压信号在所述固定时间窗口内进入所述阈值电压范围的次数，或者等于所述电压信号在所述固定时间窗口内离开所述阈值电压范围的次数，或者等于所述电压信号在所述固定时间窗口内进入所述阈值电压范围的次数和离开所述阈值电压范围的次数之和。
图3D示出了本公开实施例提供的又一个使用多进制变化率来表示信息的例子。例如，结合图3D，在第一时间窗口W1，电压信号进入阈值电压范围的次数为8，因此，所述信息的值为8；在第二时间窗口W2，电压信号进入阈值电压范围的次数为4，因此，所述信息的值为4。第一时间窗口W1和第二时间窗口W2均具有相等的时间长度。或者，结合图3D，在第一时间窗口W1和第二时间窗口W2，电压信号离开阈值电压范围的次数分别为8和4，因此，所述信息的值分别为8和4。或者，结合图3D，在第一时间窗口W1和第二时间窗口W2，同时计算电压信号进入阈值电压范围的次数和离开阈值电压范围的次数之和，则所述信息的值分别为8+8＝16和4+4＝8。
又例如，所述信号为电流信号，所述阈值范围为阈值电流范围；在步骤S104中使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内进入所述阈值电流范围的次数和/或离开所述阈值电流范围的次数来表示所述信息的值。例如，所述信息的值等于所述电流信号在所述固定时间窗口内进入所述阈值电流范围的次数，或者等于所述电流信号在所述固定时间窗口内离开所述阈值电流范围的次数，或者等于所述电流信号在所述固定时间窗口内进入所述阈值电流范围的次数和离开所述阈值电流范围的次数之和。
例如，所述信号的变化率表示所述信号在固定时间窗口内变化的速度。结合图3B，所述信号在第一时间窗口W1的波形变化速度大于在第二时间窗口W2的波形变化速度，即，所述信号在第一时间窗口W1的变化率大于在第二时间窗口W2的变化率。例如，所述信号的变化率与所述电子系统中晶体管的翻转速度相关联。晶体管的翻转速度越快，信号的变化速度越快。
图3A示出了一个使用电荷量的数量(即幅度)来表示信息的例子。在二进制全振幅数字电路中，如图3A所示，使用电荷的数量来表示信息，一个比特只能表示两个状态“1”或“0”。例如，电荷多(即高电压)表示“1”，电荷少(即低电压)表示“0”。而在本公开实施例提供的信息表示方法中，信号的电压(或电流)的幅度不再是关注的焦点。因此，伴随工艺的进步，电源电 压的降低将不会是影响信息保真度的主要原因。本公开实施例提供的信息表示方法与半导体工艺的发展趋势相吻合：线宽越小，则晶体管翻转的速度越快，本公开实施例提供的信息表示方法越有效。
本公开实施例提供的信息表示方法具有，但不限于，以下的优点。第一，与传统的数字电路不同，这里的表示信息的信号的幅度可以大幅度地减小，有助于极大地降低功耗。如图3A所示，在二进制全振幅数字电路中，由于使用电荷的数量来表示信息，电压信号的幅度需要达到电源电压VDD和地线电压VSS，以便区分高电平和低电平。而在本公开实施例中，结合图3B-3D，电压信号的幅度不需要达到电源电压VDD和地线电压VSS(因为只需判断电压信号是否穿过阈值电压或阈值电压范围)，有助于降低功耗。第二个优势是多进制。在传统的数字电路中，一个比特只能表示两个状态。而在本公开实施例中，一个变化率比特将有可能包含多种状态，使得在计算机中直接用多进制进行运算成为可能，极大地提高计算机的计算效率。
图2A为一种包括二进制计算电路200的电子系统的示意性框图。该电子系统包括输入电路组203、二进制计算电路200和输出电路组209。
输入电路组203包括一或多个数据输入方式。例如，如图2A所示，传感器电路204、前级输入电路206和数据处理芯片208为数据输入方式的三个具体示例。各数据输入电路给二进制计算电路200提供输入信号218。所述输入信号218的幅度被用来表示第一信息。第一信息为输入信息。例如，所述输入信号218的幅度携带着输入信息。又例如，输入信号218为二进制信号，使用幅度的高低分别表示信息“1”和“0”(如图3A所示，高电压幅度表示信息的值“1”和低电压幅度表示信息的值“0”)。
例如，传感器电路204包括红外传感器、温度传感器、声控传感器或其他任何类型的传感器。前级输入电路206可以包括，但不限于，图像采集设备(例如摄像头)、声音采集设备(例如麦克风)或其他输入数据的电路。数据处理芯片208可以包括，例如，滤波器、模数转换器、放大器等用于处理数据的芯片。
二进制逻辑操作电路200被配置为：接收来自各数据输入电路的输入信号；以及根据所述输入信号进行二进制逻辑操作，并将所述二进制逻辑操作的结果作为输出信号220。所述输出信号220的幅度被用来表示第二信息。第二信息为输出信息。例如，所述输出信号220的幅度携带着输出信息。又例如，输出 信号220为二进制信号，使用幅度的高低分别表示信息“1”和“0”。
输出电路组209包括一或多个数据接受方式。例如，显示器210、致动器电路212、后级接受电路214、数据接受芯片216为四个不同的数据接受方式的具体例子。各数据接受方式接收来自二进制计算电路200的输出信号220，并进行相应的操作。
例如，显示器210可以为LCD显示器、OLED显示器或其他类型的显示器。致动器电路212可以包括驱动电机，例如马达，或其他致动设备。后级接受电路214可以包括声卡、显卡或其他用于接收数据的电路。数据接受芯片216例如可以为缓存器、寄存器或其他用于接收数据的电路。
前级输入电路206、二进制逻辑操作电路200和后级接受电路214可以集成于同一芯片中，前级输入电路206为二进制逻辑操作电路200的前一级电路，后级接受电路214为二进制逻辑操作电路200的后一级电路。
如图2B所示，本公开实施例还提供一种多进制计算电路250，包括：
第一制式转换电路254，被配置为：接收输入信号218，所述输入信号218的幅度被用来表示第一信息；以及将所述输入信号218转换为第一多进制信号260，所述第一多进制信号260的变化率被用来表示所述第一信息；
多进制逻辑操作电路252，被配置为：接收来自所述第一制式转换电路254的所述第一多进制信号260；以及根据所述第一多进制信号260进行多进制逻辑操作，并输出第二多进制信号262作为所述多进制逻辑操作的结果，所述第二多进制信号262的变化率被用来表示第二信息；以及
第二制式转换电路256，被配置为：接收来自所述多进制逻辑操作电路252的所述第二多进制信号262；以及将所述第二多进制信号262转换为输出信号220，所述输出信号220的幅度被用来表示所述第二信息。
例如，第一制式转换电路254、多进制逻辑操作电路252和第二制式转换电路256可以为专用的电路，且可以分别设计为独立的芯片或集成于同一芯片中。例如，第一制式转换电路254、多进制逻辑操作电路252和第二制式转换电路256可以使用晶体管实现或使用FPGA(或ASIC)实现，本公开在此不作限定。
例如，所述输入信号218和所述输出信号220均为二进制数据信号。
例如，所述第一信息包括所述多进制计算电路250的输入信息，所述第二信息包括所述多进制计算电路250的输出信息。
例如，所述第一信息和所述第二信息均被表示为变化率比特，所述变化率比特的取值范围包括N种变化率状态，N为正整数且N>1。
例如，所述第一信息的值和所述第二信息的值分别为所述变化率比特的第一数值和第二数值，所述变化率比特的第一数值代表所述N种变化率状态中的一种状态，所述变化率比特的第二数值也代表所述N种变化率状态中的一种状态。例如，所述变化率比特的第一数值所表示的状态和所述变化率比特的第二数值所表示的状态可以相同，也可以不相同，本公开对此不作限制。
例如，所述变化率比特的第一数值为一个N进制数字，所述变化率比特的第二数值也为一个N进制数字。
在一些实施例中，所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内穿过阈值的次数，所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内穿过所述阈值的次数。
例如，所述第一多进制信号和第二多进制信号分别为第一电压信号和第二电压信号，所述阈值为阈值电压，所述第一信息的值为所述第一电压信号在所述固定时间窗口内穿过所述阈值电压的次数，所述第二信息的值为所述第二电压信号在所述固定时间窗口内穿过所述阈值电压的次数。
或者，又例如，所述第一多进制信号和第二多进制信号分别为第一电流信号和第二电流信号，所述阈值为阈值电流，所述第一信息的值为所述第一电流信号在所述固定时间窗口内穿过所述阈值电流的次数，所述第二信息的值为所述第二电流信号在所述固定时间窗口内穿过所述阈值电流的次数。
例如，在一些实施例中，所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内进入阈值范围的次数、离开阈值范围的次数或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内进入阈值范围的次数、离开阈值范围的次数或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。
例如，所述第一多进制信号和所述第二多进制信号分别为第一电压信号和第二电压信号，所述阈值范围为阈值电压范围。所述第一信息的值为所述第一电压信号在所述固定时间窗口内进入阈值电压范围的次数、离开阈值电压范围的次数或者进入阈值电压范围的次数和离开阈值电压范围的次数之和中的一个。所述第二信息的值为所述第二电压信号在所述固定时间窗口内进入阈值电压范围的次数、离开阈值电压范围的次数或者进入阈值电压范围的次数和离开 阈值电压范围的次数之和中的一个。
或者，又例如，所述第一多进制信号和所述第二多进制信号分别为第一电流信号和第二电流信号，所述阈值范围为阈值电流范围。所述第一信息的值为所述第一电流信号在所述固定时间窗口内进入阈值电流范围的次数、离开阈值电流范围的次数或者进入阈值电流范围的次数和离开阈值电流范围的次数之和中的一个。所述第二信息的值为所述第二电流信号在所述固定时间窗口内进入阈值电流范围的次数、离开阈值电流范围的次数或者进入阈值电流范围的次数和离开阈值电流范围的次数之和中的一个。
对多进制计算电路250的描述还可以参照上述的信息表示方法100的实施例中的相关说明，重复之处在此不再赘述。
例如，如图2B所示，本公开实施例还提供一种电子系统299，包括上述任一项所述的多进制计算电路250。
例如，所述电子系统299还包括：一或多个数据输入方式，被配置为提供所述输入信号218；以及一或多个数据接受方式，被配置为接收所述输出信号220。
例如，所述电子系统299包括输入电路组203和输出电路组209。输入电路组203包括一或多个数据输入方式。例如，传感器电路204、前级输入电路206和数据处理芯片208为数据输入方式的三个具体示例。显示器210、致动器电路212、后级接受电路214，数据接受芯片216为四个不同的数据接受方式的具体例子。图2A和图2B的相似之处在此不再重复。
例如，前级输入电路206、多进制计算电路250和后级接受电路214可以集成于同一芯片中，前级输入电路206为多进制计算电路250的前一级电路，后级接受电路214为多进制计算电路250的后一级电路。
对电子系统的描述可以参照上述的信息表示方法100的实施例和多进制计算电路250的实施例中的相关说明，重复之处在此不再赘述。
比较图2A和图2B可知，在图2A中，在数据的处理和操作过程中，各数据信号均为二进制数据信号，其计算效率较低。而在图2B中，输入信号218为二进制数据信号，经过第一制式转换电路254转换为第一多进制信号260；多进制逻辑操作电路252对第一多进制信号260直接进行多进制逻辑操作并输出第二多进制信号262，第二制式转换电路256将第二多进制信号262转换为二进制数据的输出信号220，并提供到各数据接受电路。通过从二进制数据到 多进制数据的第一制式转换和从多进制数据到二进制数据的第二制式转换，本公开实施例提供的多进制计算电路可以直接使用多进制进行运算，不仅极大地提高计算机的计算效率，还可以与现有的各数据输入方式和各数据接受方式相兼容。
在本公开实施例中，多进制计算电路250(包括第一制式转换电路254、多进制逻辑操作电路252、第二制式转换电路256)可以使用专用硬件来实现(例如，专用芯片、集成电路等)。
当然，多进制计算电路250(包括第一制式转换电路254、多进制逻辑操作电路252、第二制式转换电路256)的部分或全部功能也可以使用软件或软件硬件结合的方式来实现。本公开对此不作限定。例如，多进制计算电路250可以为一个电路板或多个电路板的组合。该一个电路板或多个电路板的组合可以包括：(1)一个或多个处理器；(2)与处理器相连接的一个或多个非暂时的计算机可读的存储器；以及(3)处理器可执行的存储在存储器中的固件。
处理器可以处理数据信号，可以包括各种计算结构，例如复杂指令集计算机(CISC)结构、结构精简指令集计算机(RISC)结构或者一种实行多种指令集组合的结构。在一些实施例中，处理器也可以是微处理器，例如X86处理器或ARM处理器，或者可以是数字处理器(DSP)等。处理器可以控制电子系统中的其它部件以执行期望的功能。
存储器可以保存处理器执行的指令和/或数据。例如，存储器可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。所述易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。所述非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在所述计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器可以运行所述程序指令，以实现本公开实施例提供的信息表示以及/或者其它期望的功能。在所述计算机可读存储介质中还可以存储各种应用程序和各种数据，例如所述应用程序使用和/或产生的各种数据等。
本公开实施例还提供一种计算机可读存储介质，其上存储有计算机指令，所述计算机指令被处理器执行时实现图1所示的信息表示方法100的操作。例如，上述存储器为计算机可读存储介质的一种。
综上所述，在本公开实施例提供的信息表示方法、多进制计算电路和电子 系统中，表示信息的信号的幅度可以大幅度地减小，有助于极大地降低功耗。由于采用多进制，一个变化率比特将有可能包含多种状态，使得在计算机中直接用多进制进行运算成为可能，极大地提高计算机的计算效率。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
以上所述，仅为公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种电子系统的信息表示方法，包括：
    获取信号的变化率；以及
    使用所述信号的变化率来表示信息。
  2. 根据权利要求1所述的信息表示方法，其中，所述信息被表示为变化率比特，所述变化率比特的取值范围包括N种变化率状态，N为正整数且N>1。
  3. 根据权利要求2所述的信息表示方法，其中，所述信息的值等于所述变化率比特的值，且代表所述N种变化率状态中的一种。
  4. 根据权利要求3所述的信息表示方法，其中，所述变化率比特的值为一个N进制数字。
  5. 根据权利要求3或4所述的信息表示方法，其中，所述变化率比特的值为所述信号在固定时间窗口内穿过阈值的次数。
  6. 根据权利要求5所述的信息表示方法，其中，所述信号为电压信号，所述阈值为阈值电压，
    使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定时间窗口内穿过所述阈值电压的次数来表示所述信息的值。
  7. 根据权利要求6所述的信息表示方法，其中，所述阈值电压具有选定的电压值。
  8. 根据权利要求5所述的信息表示方法，其中，所述信号为电流信号，所述阈值为阈值电流，
    使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内穿过所述阈值电流的次数来表示所述信息的值。
  9. 根据权利要求8所述的信息表示方法，其中，所述阈值电流具有选定的电流值。
  10. 根据权利要求3或4所述的信息表示方法，其中，所述变化率比特的值为所述信号在固定时间窗口内进入阈值范围的次数、离开阈值范围的次数或者进入阈值范围的次数和离开阈值范围的次数之和中的一个。
  11. 根据权利要求10所述的信息表示方法，其中，所述信号为电压信号，所述阈值范围为阈值电压范围，
    使用所述信号的变化率来表示信息，包括：使用所述电压信号在所述固定 时间窗口内进入和/或离开所述阈值电压范围的次数来表示所述信息的值。
  12. 根据权利要求10所述的信息表示方法，其中，所述信号为电流信号，所述阈值范围为阈值电流范围，
    使用所述信号的变化率来表示信息，包括：使用所述电流信号在所述固定时间窗口内进入和/或离开所述阈值电流范围的次数来表示所述信息的值。
  13. 根据权利要求1-12任一项所述的信息表示方法，其中，所述信号的变化率表示所述信号在固定时间窗口内变化的速度。
  14. 根据权利要求13所述的信息表示方法，其中，所述信号的变化率与所述电子系统中晶体管的翻转速度相关联。
  15. 一种多进制计算电路，包括：
    第一制式转换电路，被配置为：
    接收输入信号，所述输入信号的幅度被用来表示第一信息；以及
    将所述输入信号转换为第一多进制信号，所述第一多进制信号的变化率被用来表示所述第一信息；
    多进制逻辑操作电路，被配置为：
    接收来自所述第一制式转换电路的所述第一多进制信号；以及
    根据所述第一多进制信号进行多进制逻辑操作，并输出第二多进制信号作为所述多进制逻辑操作的结果，所述第二多进制信号的变化率被用来表示第二信息；以及
    第二制式转换电路，被配置为：
    接收来自所述多进制逻辑操作电路的所述第二多进制信号；以及
    将所述第二多进制信号转换为输出信号，所述输出信号的幅度被用来表示所述第二信息。
  16. 根据权利要求15所述的多进制计算电路，其中，所述输入信号和所述输出信号均为二进制数据信号。
  17. 根据权利要求15或16所述的多进制计算电路，其中，所述第一信息包括所述多进制计算电路的输入信息，所述第二信息包括所述多进制计算电路的输出信息。
  18. 根据权利要求15-17任一项所述的多进制计算电路，其中，所述第一信息和所述第二信息均被表示为变化率比特，所述变化率比特的取值范围包括N种变化率状态，N为正整数且N>1。
  19. 根据权利要求15-18任一项所述的多进制计算电路，其中，所述第一信息的值和所述第二信息的值分别为所述变化率比特的第一数值和第二数值，所述变化率比特的第一数值代表所述N种变化率状态中的一种状态，所述变化率比特的第二数值也代表所述N种变化率状态中的一种状态。
  20. 根据权利要求19所述的多进制计算电路，其中，所述变化率比特的第一数值为一个N进制数字，所述变化率比特的第二数值也为一个N进制数字。
  21. 根据权利要求19或20所述的多进制计算电路，其中，所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内穿过阈值的次数，所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内穿过所述阈值的次数。
  22. 根据权利要求21所述的多进制计算电路，其中，
    所述第一多进制信号和第二多进制信号分别为第一电压信号和第二电压信号，所述阈值为阈值电压，所述第一信息的值为所述第一电压信号在所述固定时间窗口内穿过所述阈值电压的次数，所述第二信息的值为所述第二电压信号在所述固定时间窗口内穿过所述阈值电压的次数；或者
    所述第一多进制信号和第二多进制信号分别为第一电流信号和第二电流信号，所述阈值为阈值电流，所述第一信息的值为所述第一电流信号在所述固定时间窗口内穿过所述阈值电流的次数，所述第二信息的值为所述第二电流信号在所述固定时间窗口内穿过所述阈值电流的次数。
  23. 根据权利要求19或20所述的多进制计算电路，其中，
    所述变化率比特的第一数值为所述第一多进制信号在固定时间窗口内进入阈值范围的次数、离开所述阈值范围的次数或者进入所述阈值范围的次数和离开所述阈值范围的次数之和中的一个；以及
    所述变化率比特的第二数值为所述第二多进制信号在所述固定时间窗口内进入所述阈值范围的次数、离开所述阈值范围的次数或者进入所述阈值范围的次数和离开所述阈值范围的次数之和中的一个。
  24. 根据权利要求23所述的多进制计算电路，其中，
    所述第一多进制信号和所述第二多进制信号分别为第一电压信号和第二电压信号，所述阈值范围为阈值电压范围，
    所述第一信息的值为所述第一电压信号在所述固定时间窗口内进入所述阈值电压范围的次数、离开所述阈值电压范围的次数或者进入所述阈值电压范 围的次数和离开所述阈值电压范围的次数之和中的一个，
    所述第二信息的值为所述第二电压信号在所述固定时间窗口内进入所述阈值电压范围的次数、离开所述阈值电压范围的次数或者进入所述阈值电压范围的次数和离开所述阈值电压范围的次数之和中的一个；或者
    所述第一多进制信号和所述第二多进制信号分别为第一电流信号和第二电流信号，所述阈值范围为阈值电流范围，
    所述第一信息的值为所述第一电流信号在所述固定时间窗口内进入所述阈值电流范围的次数、离开所述阈值电流范围的次数或者进入所述阈值电流范围的次数和离开所述阈值电流范围的次数之和中的一个，
    所述第二信息的值为所述第二电流信号在所述固定时间窗口内进入所述阈值电流范围的次数、离开所述阈值电流范围的次数或者进入所述阈值电流范围的次数和离开所述阈值电流范围的次数之和中的一个。
  25. 一种电子系统，包括根据权利要求15-24任一项所述的多进制计算电路。
  26. 根据权利要求25所述的电子系统，还包括：
    一或多个数据输入方式，被配置为提供所述输入信号；以及
    一或多个数据接受方式，被配置为接收所述输出信号。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002046499A1 (en) * 2000-12-05 2002-06-13 Zakrytoe Aktsionernoe Obshestvo 'toxsoft' Method and control unit for operation of aluminum reduction cell
CN205753473U (zh) * 2015-04-13 2016-11-30 半导体元件工业有限责任公司 在电子设备中节能的系统和电子设备
US9659721B1 (en) * 2014-05-06 2017-05-23 Google Inc. Circuit breakers with integrated safety, control, monitoring, and protection features
CN107176038A (zh) * 2016-03-10 2017-09-19 福特全球技术公司 用于检测电池单元衰退事件的电路和方法

Family Cites Families (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2997602A (en) * 1958-03-28 1961-08-22 Honeywell Regulator Co Electronic binary counter circuitry
US3629590A (en) * 1965-01-27 1971-12-21 Versitron Inc Photoelectric relay using optical couples
US3723982A (en) * 1967-11-24 1973-03-27 Gen Dynamics Corp System for transmission, storage and/or multiplexing of information
US4103234A (en) * 1967-11-24 1978-07-25 General Dynamics Corp. System for transmission storage and/or multiplexing of information
US3646531A (en) * 1969-10-10 1972-02-29 Core Memories Inc Magnetic core signal discrimination method
US3653036A (en) * 1969-11-14 1972-03-28 Gen Dynamics Corp Information handling system especially for magnetic recording and reproducing of digital data
US3629823A (en) * 1969-11-14 1971-12-21 Gen Dynamics Corp Information-handling system having error correction capabilities
US3623078A (en) * 1969-11-14 1971-11-23 Gen Dynamics Corp Information handling system especially for magnetic recording and reproducing of digital data
US3618044A (en) * 1969-11-14 1971-11-02 Gen Dynamics Corp Information-handling system especially for magnetic recording and reproducing of digital data
US3618043A (en) * 1969-11-14 1971-11-02 Gen Dynamics Corp Information-handling system especially for magnetic recording and reproducing of digital data
US3641506A (en) * 1969-11-14 1972-02-08 Gen Dynamics Corp Information handling system especially for magnetic recording and reproducing of digital data
US3813560A (en) * 1970-04-30 1974-05-28 Hughes Aircraft Co Current mode switch for high speed digital-to-analog conversion
US3940567A (en) * 1973-12-05 1976-02-24 Nissan Motor Co., Ltd. Multiplex transmission system on-off signal
US4092553A (en) * 1976-02-26 1978-05-30 International Business Machines Corporation Josephson logic circuit powering arrangement
US4379990A (en) * 1980-05-22 1983-04-12 Motorola Inc. Fault detection and diagnostic system for automotive battery charging systems
US4348629A (en) * 1980-05-22 1982-09-07 Motorola, Inc. Stator fault detector for automotive alternator battery charging systems
US4314193A (en) * 1980-05-22 1982-02-02 Motorola, Inc. Field coil fault detector for automotive alternator battery charging systems
US4315204A (en) * 1980-05-22 1982-02-09 Motorola, Inc. Ripple detector for automotive alternator battery charging systems
US4533993A (en) * 1981-08-18 1985-08-06 National Research Development Corp. Multiple processing cell digital data processor
EP0160010B1 (de) * 1983-10-11 1987-12-16 Hölter, Heinz, Dipl.-Ing. Vorrichtung zur reinigung von mit schadstoffen belasteter luft
US4620258A (en) * 1984-03-30 1986-10-28 General Electric Company Circuit for self-commutated turn-off of latched devices, such as of the insulated-gate transistor/rectifier type
US4631428A (en) * 1984-10-26 1986-12-23 International Business Machines Corporation Communication interface connecting binary logic unit through a trinary logic transmission channel
US4947063A (en) * 1987-10-09 1990-08-07 Western Digital Corporation Method and apparatus for reducing transient noise in integrated circuits
US4849659A (en) * 1987-12-15 1989-07-18 North American Philips Corporation, Signetics Division Emitter-coupled logic circuit with three-state capability
JPH0226077A (ja) * 1988-07-15 1990-01-29 Fujitsu Ltd 半導体機能素子
CA2015809A1 (en) * 1989-05-04 1990-11-04 Richard W. Sieber Broadband switch using deactivated crosspoints for establishing switching paths
US5319453A (en) * 1989-06-22 1994-06-07 Airtrax Method and apparatus for video signal encoding, decoding and monitoring
US5051611A (en) * 1989-12-20 1991-09-24 Quadic Systems, Inc. Power-up circuit with hysteresis for an output buffer
US5283479A (en) * 1991-04-30 1994-02-01 Microunity Systems Engineering, Inc. BiCMOS logic gate having plural linearly operated load FETs
US5144157A (en) * 1991-09-23 1992-09-01 Raytheon Company Pin diode driver circuit for radar system
US5512883A (en) 1992-11-03 1996-04-30 Lane, Jr.; William E. Method and device for monitoring the operation of a motor
JPH08147144A (ja) * 1994-11-17 1996-06-07 Yamaha Corp ディジタル回路
US5568064A (en) * 1995-01-23 1996-10-22 International Business Machines Corporation Bidirectional transmission line driver/receiver
DE69625714T2 (de) * 1996-10-10 2004-05-13 Chartec Laboratories A/S Digital gesteuertes schaltnetzteil zum laden von wiederaufladbaren batterien
US5764667A (en) * 1996-12-09 1998-06-09 Hewlett-Packard Company Current steering circuit
US6037827A (en) * 1997-06-27 2000-03-14 United Memories, Inc. Noise isolation circuit
GB9800440D0 (en) * 1998-01-10 1998-03-04 Wood John Digital reflection internet
US6229336B1 (en) * 1998-05-21 2001-05-08 Lattice Semiconductor Corporation Programmable integrated circuit device with slew control and skew control
US6255847B1 (en) * 1998-05-21 2001-07-03 Lattice Semiconductor Corporation Programmable logic device
US6617892B2 (en) * 1998-09-18 2003-09-09 Intel Corporation Single ended interconnect systems
US6169389B1 (en) * 1999-04-05 2001-01-02 Marconi Communications, Inc. Pumped capacitive storage system
US6348817B2 (en) * 1999-05-10 2002-02-19 Jinghui Lu Complementary current mode driver for high speed data communications
GB2366678B (en) * 2000-09-09 2004-04-21 Ibm Optical amplitude demodulator
US9077315B2 (en) * 2003-06-25 2015-07-07 John W. Bogdan Inverse signal transformation
DE502004001715D1 (de) * 2003-08-27 2006-11-23 Fraunhofer Ges Forschung Schaltregler
WO2005022735A1 (de) * 2003-08-27 2005-03-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Steuerungsvorrichtung zum steuern eines ladeschalters in einem schaltregler und verfahren zum steuern eines ladeschalters
EP1658676B1 (de) * 2003-08-27 2007-01-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Schaltung und verfahren zum verarbeiten einer speisespannung mit spannungsspitzen
US7397690B2 (en) * 2004-06-01 2008-07-08 Temarylogic Llc Multi-valued digital information retaining elements and memory devices
JP4118245B2 (ja) * 2004-03-30 2008-07-16 株式会社東芝 画像送信装置、画像受信装置および画像伝送システム
US7304883B2 (en) * 2004-06-09 2007-12-04 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US7983113B2 (en) 2005-03-29 2011-07-19 Baker Hughes Incorporated Method and apparatus for downlink communication using dynamic threshold values for detecting transmitted signals
FR2912014B1 (fr) * 2007-01-31 2011-05-13 St Microelectronics Sa Generateur d'impulsions ultra large bande dote d'une fonction integree d'emulation numerique de filtrage, et procede de transmission.
KR101292574B1 (ko) * 2007-10-08 2013-08-16 삼성전자주식회사 멀티 비트 프로그래밍 장치 및 방법
US8120389B2 (en) * 2008-08-05 2012-02-21 Texas Instruments Incorporated Digital to frequency synthesis using flying-adder with dithered command input
US9749169B2 (en) * 2009-01-10 2017-08-29 John W. Bogdan Data recovery with inverse transformation
US9769003B2 (en) * 2011-12-12 2017-09-19 John W. Bogdan Direct synthesis of OFDM receiver clock
JP5177276B2 (ja) * 2009-02-23 2013-04-03 日本電気株式会社 適応変調方法、無線通信システムおよび無線装置
JP5430484B2 (ja) * 2010-04-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体記憶装置、及びその制御方法
CN102043603A (zh) * 2010-12-13 2011-05-04 山东科技大学 电磁信号转换成三进制数的方法
CN102413086B (zh) * 2011-11-08 2013-11-20 哈尔滨工程大学 三进制调频键控调制方法
US8963618B2 (en) * 2013-05-14 2015-02-24 Ferfics Limited Radio frequency switch with improved switching time
JP6507378B2 (ja) * 2014-05-09 2019-05-08 パナソニックＩｐマネジメント株式会社 整流回路および、これを備えた非接触給電装置
US10454495B2 (en) * 2014-09-18 2019-10-22 Intel Corporation Apparatus and method for mapping binary to ternary and its reverse
US9698845B2 (en) * 2014-11-06 2017-07-04 GM Global Technology Operations LLC High oversampling ratio dynamic element matching scheme for high dynamic range digital to RF data conversion for radio communication systems
WO2016073934A1 (en) * 2014-11-06 2016-05-12 GM Global Technology Operations LLC Optimized data converter design using mixed semiconductor technology for flexible radio communication systems
CN104954026A (zh) * 2015-07-15 2015-09-30 江苏图码信息科技有限公司 多进制数的几何编码表示
CN105119690B (zh) * 2015-07-20 2018-08-07 北方民族大学 一种基于n进制进行数字信号传输的方法
US9621173B1 (en) * 2015-11-19 2017-04-11 Liming Xiu Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same
US10333058B2 (en) * 2016-03-17 2019-06-25 Cornell University Nanosecond-timescale low-error switching of 3-terminal magnetic tunnel junction circuits through dynamic in-plane-field assisted spin-hall effect
CN105739944B (zh) * 2016-03-21 2019-01-04 华中科技大学 一种基于忆阻器的多进制加法运算电路
CN108270437B (zh) * 2017-01-04 2023-04-14 京东方科技集团股份有限公司 数控振荡器和基于数控振荡器的全数字锁频环和锁相环
CN108270441B (zh) * 2017-01-04 2021-12-28 京东方科技集团股份有限公司 频率可调的频率源和相关的系统、方法和电子设备
CN106876334B (zh) * 2017-03-10 2019-11-29 京东方科技集团股份有限公司 阵列基板的制造方法及阵列基板
CN108668399B (zh) * 2017-03-29 2020-06-23 京东方科技集团股份有限公司 信号生成电路及信号生成方法、发光装置驱动电路及显示装置
US10686458B1 (en) * 2017-08-01 2020-06-16 Liming Xiu Method and apparatus for improving frequency source frequency accuracy and frequency stability
GB2567227A (en) * 2017-10-06 2019-04-10 Heyday Integrated Circuits Galvanically isolated gate drive circuit with power transfer
US10509926B2 (en) * 2017-11-01 2019-12-17 Samsung Electronics Co., Ltd. Ternary encoding magnetic stripe data transmitter, system, and method
CN108598131B (zh) * 2018-05-23 2021-01-29 京东方科技集团股份有限公司 发光基板及其制作方法、发光装置及其制作方法
EP3907890A4 (en) * 2019-01-02 2022-08-17 BOE Technology Group Co., Ltd. FREQUENCY ADJUSTMENT DEVICE AND ASSOCIATED FREQUENCY ADJUSTMENT METHOD, AND ELECTRONIC DEVICE

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002046499A1 (en) * 2000-12-05 2002-06-13 Zakrytoe Aktsionernoe Obshestvo 'toxsoft' Method and control unit for operation of aluminum reduction cell
US9659721B1 (en) * 2014-05-06 2017-05-23 Google Inc. Circuit breakers with integrated safety, control, monitoring, and protection features
CN205753473U (zh) * 2015-04-13 2016-11-30 半导体元件工业有限责任公司 在电子设备中节能的系统和电子设备
CN107176038A (zh) * 2016-03-10 2017-09-19 福特全球技术公司 用于检测电池单元衰退事件的电路和方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3742418A4 *

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