WO2019140989A1 - 半导体设备 - Google Patents

半导体设备 Download PDF

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Publication number
WO2019140989A1
WO2019140989A1 PCT/CN2018/114600 CN2018114600W WO2019140989A1 WO 2019140989 A1 WO2019140989 A1 WO 2019140989A1 CN 2018114600 W CN2018114600 W CN 2018114600W WO 2019140989 A1 WO2019140989 A1 WO 2019140989A1
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Prior art keywords
film layer
chamber
capacitor
semiconductor device
vapor deposition
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PCT/CN2018/114600
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English (en)
French (fr)
Inventor
赵雷超
李春雷
纪红
秦海丰
张芳
兰云峰
王勇飞
王洪彪
文莉辉
张鹤南
王宽冒
郑金果
杨玉杰
Original Assignee
北京北方华创微电子装备有限公司
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Priority claimed from CN201810043867.3A external-priority patent/CN108461417A/zh
Priority claimed from CN201820074885.3U external-priority patent/CN207818535U/zh
Application filed by 北京北方华创微电子装备有限公司 filed Critical 北京北方华创微电子装备有限公司
Priority to SG11202006652PA priority Critical patent/SG11202006652PA/en
Publication of WO2019140989A1 publication Critical patent/WO2019140989A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere

Definitions

  • the invention belongs to the technical field of semiconductor processing equipment, and in particular relates to a semiconductor device.
  • micro-capacitors are generally referred to as microcapacitors.
  • Microcapacitors typically include planar capacitors and trench capacitors, Figure 1a shows a planar capacitor; Figure 1b shows a trench. As can be seen from FIGS. 1a and 1b, both the planar capacitance and the trench capacitance are mainly composed of the upper electrode 10, the lower electrode 20, and the dielectric layer 30 between the upper electrode 10 and the lower electrode 20. 1c is a schematic structural diagram of a trench capacitor. As shown in FIG.
  • the upper electrode 10 of the trench capacitor includes a W film layer and a TiN film layer which are sequentially stacked in a direction close to the lower electrode 20; the lower electrode 20 The TiN film layer, the W film layer, and the TiN film layer are sequentially stacked in a direction close to the upper electrode 10; the dielectric layer 30 is an Al 2 O 3 film layer.
  • the trench capacitor shown in FIG. 1c is prepared by: CVD TiN ⁇ CVD W ⁇ CVD TiN ⁇ ALD Al 2 O 3 ⁇ CVD TiN ⁇ CVD W, wherein CVD TiN and CVD W refer to chemical vapor deposition (Chemical Vapor)
  • CVD TiN and CVD W refer to chemical vapor deposition (Chemical Vapor)
  • CVD Al 2 O 3 refers to the preparation of Al 2 O 3 film layer by Atomic Layer Deposition (ALD) process. Need to be carried out in the ALD chamber.
  • CVD W, CVD TiN and ALD Al 2 O 3 are all independent devices on the market and cannot be integrated into the same transmission platform. This has the following problems:
  • the substrate needs to be transferred to a separate device corresponding to the next process. Since the substrate transfer between two separate devices exposes the substrate to the air, the substrate is exposed to air five times throughout the preparation process of the trench capacitor, which inevitably contaminates the surface of the deposited film. .
  • the electrode deposited by the CVD process has a large resistivity, which affects the capacitance performance.
  • the present invention aims to at least solve one of the technical problems existing in the prior art, and proposes a semiconductor device which can not only prevent the substrate from being exposed to the air during transmission, but also can improve the performance of the prepared capacitor and reduce the device. cost.
  • the present invention provides a semiconductor device comprising: a physical vapor deposition chamber, an atomic layer deposition chamber, and a transport platform;
  • the physical vapor deposition chamber is used to prepare an upper electrode and a lower electrode of the capacitor
  • the atomic layer deposition chamber is used to prepare a dielectric layer of the capacitor
  • the transport platform is coupled to the physical vapor deposition chamber and the atomic layer deposition chamber, respectively, for transporting a substrate.
  • a degassing chamber is used for degassing and annealing the substrate; and the degassing chamber is connected to the transport platform.
  • a pre-cleaning chamber for removing impurities on the surface of the substrate; the pre-cleaning chamber being connected to the transport platform.
  • the number of the physical vapor deposition chambers is plural, and the plurality of physical vapor deposition chambers are respectively used to deposit a film of a plurality of materials.
  • the upper electrode and the lower electrode of the capacitor each include at least one W film layer and at least one TiN film layer; the number of the physical vapor deposition chambers is two; and the two physical vapor deposition chambers The chambers are used to deposit a W film layer and a TiN film layer, respectively.
  • the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode;
  • the lower electrode includes a W film layer and a TiN film layer which are sequentially stacked in a direction close to the upper electrode.
  • the upper electrode of the capacitor includes a W film layer and a TiN film layer sequentially stacked in a direction close to the lower electrode;
  • the lower electrode includes a TiN film layer, a W film layer, and a TiN film layer which are sequentially stacked in a direction close to the upper electrode;
  • the dielectric layer is an Al 2 O 3 film.
  • the dielectric layer comprises an Al 2 O 3 film layer; the atomic layer deposition chamber is used for depositing an Al 2 O 3 film.
  • the capacitor is a planar capacitor.
  • the capacitor is a trench capacitor.
  • the semiconductor device provided by the invention adopts a physical vapor deposition chamber to prepare an upper electrode and a lower electrode of a capacitor, which is better in compactness and lower resistivity than chemical vapor deposition, thereby improving the upper surface.
  • the semiconductor device provided by the present invention integrates the physical vapor deposition chamber and the atomic layer deposition chamber with the same transport platform to form a single cluster device system. This not only reduces the cost of the equipment, but also prevents the substrate from being exposed to the air during transport, thereby avoiding contamination of the surface of the film.
  • Figure 1a is a schematic structural view of a planar capacitor
  • Figure 1b is a schematic structural view of a trench capacitor
  • Figure 1c is a schematic structural view of a specific trench capacitor
  • FIG. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
  • FIG. 3a is a schematic structural diagram of a planar capacitor according to an embodiment of the present invention.
  • 3b is a schematic structural view of a trench capacitor according to an embodiment of the present invention.
  • Figure 4 is a schematic structural view of a typical magnetron sputtering chamber
  • Figure 5 is a schematic structural view of a degassing chamber
  • Figure 6 is a schematic view of a structure of a pre-cleaning chamber.
  • a semiconductor device provided by an embodiment of the present invention can be used to prepare a capacitor.
  • 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
  • the semiconductor device includes: a physical vapor deposition (PVD) chamber 40, and an atomic layer deposition (Atomic Layer Deposition, Hereinafter referred to as ALD) chamber 50 and transport platform 60.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • transport platform 60 is connected to the PVD chamber 40 and the ALD chamber 50, respectively, for transporting the substrate .
  • the transport platform 60 mainly includes a transfer chamber and a loading/unloading station, wherein the transfer chamber is a vacuum chamber, and a robot is disposed in the transfer chamber.
  • the PVD chamber 40 and the ALD chamber 50 surround and are in communication with the transfer chamber to form a cluster device system.
  • the substrate After loading the substrate to the loading station of the transfer platform 60, the substrate is taken out of the loading table by the robot, and the substrate is transferred to the PVD chamber 40 and the ALD chamber 50 in a process sequence, after completion of the preparation of the capacitor, The processed substrate is transferred to the unloading station.
  • the semiconductor device provided by the embodiment of the invention uses the PVD chamber to prepare the upper electrode and the lower electrode of the capacitor, which is better than the chemical vapor deposition, and the formed film has better compactness and lower resistivity, thereby improving the upper surface.
  • the number of PVD chambers is multiple, and the plurality of PVD chambers are respectively used to deposit thin films of various materials.
  • a single cluster device system can perform thin film deposition of multiple materials without using multiple independent devices, thereby reducing equipment cost while avoiding substrate exposure to air during transport.
  • the capacitor can be a planar capacitor or a trench capacitor.
  • the upper and lower electrodes of the capacitor may each include at least one W film layer and at least one TiN film layer.
  • the number of PVD chambers may be two; two PVD chambers are used to deposit the W film layer and the TiN film layer, respectively.
  • the dielectric layer comprises an Al 2 O 3 film layer; the ALD chamber is used to deposit an Al 2 O 3 film.
  • FIG. 3a shows a planar capacitor
  • FIG. 3b shows a trench capacitor, both of which include an upper electrode 10, a lower electrode 20, and a dielectric layer 30 therebetween.
  • the upper electrode 10 includes a W film layer and a TiN film layer which are sequentially stacked in a direction close to the lower electrode 20
  • the lower electrode 20 includes a W film layer and a TiN film layer which are sequentially stacked in a direction close to the upper electrode 10
  • the dielectric layer 30 is Al 2 O 3 film layer.
  • PVD W ⁇ PVD TiN ⁇ ALD Al 2 O 3 ⁇ PVD TiN ⁇ PVD W refer to the preparation of TiN film layer and W film layer by physical vapor deposition process, respectively, in two PVD chambers.
  • ALD Al 2 O 3 refers to the preparation of an Al 2 O 3 film layer by an atomic layer deposition process, which needs to be performed in an ALD chamber.
  • the upper electrode and the lower electrode of the capacitor may also adopt other structures.
  • the upper electrode 10 of the capacitor includes a W film layer which is sequentially stacked in a direction close to the lower electrode 20.
  • the TiN film layer; the lower electrode 20 includes a TiN film layer, a W film layer, and a TiN film layer which are sequentially stacked in a direction close to the upper electrode 10.
  • the number of layers and the type of material used for the upper and lower electrodes of the capacitor can be specifically set as needed.
  • the number of PVD chambers and the number of ALD chambers should correspond to the sum of the types of film materials used for the upper and lower electrodes.
  • the PVD chamber is a magnetron sputtering chamber.
  • 4 is a schematic structural view of a typical magnetron sputtering chamber.
  • the magnetron sputtering chamber includes a cavity 8, a process kit, and the like, wherein a susceptor 9 is disposed inside the cavity 8.
  • a target 3 is disposed on the top of the cavity 8.
  • the process kit includes a shield 2, a shadow ring 11 and a deposition ring 14, wherein the shield 2 surrounds the side wall of the cavity 8 for protecting the side walls of the cavity 8.
  • the deposition ring 14 is disposed around the edge region of the susceptor 9, and the shielding ring 11 is disposed on the shield 2 and the deposition ring 14 for shielding the gap therebetween to prevent plasma from entering below the susceptor 15.
  • a magnetron 6 is disposed above the target 3, and the magnetron 6 is rotated about the central axis by the motor 5.
  • a cooling chamber 7 for holding deionized water for cooling the target is disposed above the target 3; the magnetron 6 is located in the cooling chamber 7.
  • a vacuum system 13 is provided at the bottom of the chamber 8 for evacuating the chamber.
  • the semiconductor device provided by the embodiment of the present invention further includes a degas chamber 70 for degassing and annealing the substrate. Also, the degassing chamber 70 is coupled to the transfer platform 60 and forms a cluster device system with the other chambers.
  • FIG. 5 is a schematic structural view of a degassing chamber.
  • the degassing chamber 70 includes a cavity in which a quartz window 71 is disposed, and the quartz window 71 isolates the chamber.
  • a vacuum chamber 72 and an atmospheric chamber 73 wherein a base 74 for carrying the substrate 76 is disposed within the vacuum chamber 72; and a heater wire assembly 75 is disposed within the base 74 for uniform heating of the substrate 76 The role.
  • a heating bulb 77 is disposed in the atmospheric chamber 73, and the heating bulb 77 radiates heat to the substrate 76 through the quartz window 71.
  • the heating bulb 77 is mounted on the mounting plate 79 through the bulb base 78, and a reflecting plate 792 is superposed on the surface of the mounting plate 79 facing the heating bulb 77, and the lower surface of the reflecting plate 792 is smoothed to enable It is good to reflect the heat from the heating bulb 77 toward the direction of the quartz window 71, so that the heating efficiency can be improved.
  • a cooling water pipe 791 is further provided on the mounting plate 79. Used to cool the reflector 792.
  • a shield 793 is disposed around the inner side of the side wall of the chamber, and a cooling water line 794 is disposed in the shield 793 for cooling the side wall of the chamber to avoid overheating of the side wall of the chamber.
  • the heating wire assembly 75 can uniformly heat the substrate 76, rapid and uniform heating can be performed on the substrate 76.
  • the semiconductor device provided by the embodiment of the present invention further includes a pre-cleaning (PreClean) chamber 80 for removing impurities on the surface of the substrate.
  • the pre-cleaning chamber 80 is coupled to the transfer platform 60 and forms a cluster device system with the other chambers.
  • FIG. 6 is a schematic structural view of a pre-cleaning chamber.
  • the pre-cleaning chamber 80 includes a chamber cover 801, an insulating chamber wall 802, an annular metal part 803, and the like, and is provided therein for The base 804 carrying the substrate; and a solenoid coil 805 is wound around the outside of the insulating chamber wall 802, and a shield cover 806 is disposed around the solenoid coil 805 for avoiding the generation of the solenoid coil 805
  • the magnetic induction line radiates to the outside.
  • the solenoid coil 805 is connected to the first RF power source 807 through a matching device, and the first RF power source 807 is used to apply RF power to the solenoid coil 805 to ionize the gas in the chamber to generate plasma;
  • the RF power source 808 is coupled to the susceptor 804 via a matching device for biasing the substrate to attract the plasma to bombard the substrate to remove impurities from the surface of the wafer and to pretreat the surface of the wafer.
  • the typical PVD chamber, the degassing chamber 70 and the pre-cleaning chamber 80 are commonly used in FIGS. 4-6, but the present invention is not limited thereto, and in practical applications, Other configurations of PVD chambers, degassing chambers 70, and pre-cleaning chambers 80 may be employed.
  • the ALD chamber employs a chamber structure commonly used in the prior art and will not be described in detail herein.

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Abstract

一种半导体设备，包括：物理气相沉积腔室（40）、原子层沉积腔室（50）和传输平台（60）；物理气相沉积腔室（40）用于制备电容的上电极（10）和下电极（20）；原子层沉积腔室（50）用于制备电容的电介质层（30）；传输平台（60）分别与物理气相沉积腔室（40）和原子层沉积腔室（50）连接，用于传输基片。半导体设备不仅可以避免基片在传输过程中暴露在空气中，而且可以提高制备出的电容的性能，降低设备成本。

Description

半导体设备 技术领域
本发明属于半导体加工设备技术领域，具体涉及一种半导体设备。
背景技术
电容器作为电路中最基本的元件之一，对整个电子设备起着至关重要的作用。随着半导体技术的发展，薄膜沉积技术使电子元器件进入纳米级工艺制程，成为了电容器走向微型化、集成化的主要手段，一般将制备成的微型化的电容器称为微型电容。
微型电容一般包括平面电容和沟槽电容，图1a示出了一种平面电容；图1b示出了一种沟槽。由图1a和图1b可知，平面电容和沟槽电容均主要由上电极10、下电极20以及位于上电极10和下电极20之间的电介质层30组成。图1c为沟槽电容的一种具体的结构示意图，如图1c所示，该沟槽电容的上电极10包括朝靠近下电极20的方向依次层叠的W膜层和TiN膜层；下电极20包括朝靠近上电极10的方向依次层叠的TiN膜层、W膜层和TiN膜层；电介质层30为Al 2O 3膜层。
图1c示出的沟槽电容的制备方法为：CVD TiN→CVD W→CVD TiN→ALD Al 2O 3→CVD TiN→CVD W，其中，CVD TiN和CVD W是指采用化学气相沉积(Chemical Vapor Deposition，以下简称CVD)工艺制备TiN膜层和W膜层，需要在CVD腔室中进行；ALD Al 2O 3是指采用原子层沉积(Atomic Layer Deposition，ALD)工艺制备Al 2O 3膜层，需要在ALD腔室中进行。
目前，市场上CVD W、CVD TiN以及ALD Al 2O 3均为独立设备，无法集成到同一传输平台，这会存在以下问题：
其一，采用CVD和ALD多个独立设备制备电容，成本较高。
其二，在每个独立设备完成一工艺之后，需要将基片传递至下一工艺对应的独立设备。由于两个独立设备之间的基片传递会使基片暴露在空气中，上述沟槽电容的整个制备流程中基片会暴露在空气中五次，这不可避免地对沉积薄膜的表面造成污染。
其三，采用CVD工艺沉积获得的电极的电阻率较大，从而影响电容性能。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种半导体设备，不仅可以避免基片在传输过程中暴露在空气中，而且可以提高制备出的电容的性能，降低设备成本。
为解决上述问题之一，本发明提供了一种半导体设备，包括：物理气相沉积腔室、原子层沉积腔室和传输平台；
所述物理气相沉积腔室用于制备电容的上电极和下电极；
所述原子层沉积腔室用于制备所述电容的电介质层；
所述传输平台分别与所述物理气相沉积腔室和所述原子层沉积腔室连接，用于传输基片。
可选的，还包括去气腔室，所述去气腔室用于对基片进行除气和退火；所述去气腔室与所述传输平台连接。
可选的，还包括预清洗腔室，所述预清洗腔室用于去除基片表面上的杂质；所述预清洗腔室与所述传输平台连接。
可选的，所述物理气相沉积腔室的数量为多个，多个所述物理气相沉积腔室分别用于沉积多种材料的薄膜。
可选的，所述电容的上电极和下电极均包括至少一层W膜层和至少一 层TiN膜层；所述物理气相沉积腔室的数量为两个；两个所述物理气相沉积腔室分别用于沉积W膜层和TiN膜层。
可选的，所述电容的上电极包括朝靠近所述下电极的方向依次层叠的W膜层和TiN膜层；
所述下电极包括朝靠近所述上电极的方向依次层叠的W膜层和TiN膜层。
可选的，所述电容的上电极包括朝靠近所述下电极的方向依次层叠的W膜层和TiN膜层；
所述下电极包括朝靠近所述上电极的方向依次层叠的TiN膜层、W膜层和TiN膜层；
所述电介质层为Al 2O 3薄膜。
可选的，所述电介质层包括Al 2O 3膜层；所述原子层沉积腔室用于沉积Al 2O 3薄膜。
可选的，所述电容为平面电容。
可选的，所述电容为沟槽电容。
本发明具有以下有益效果：
本发明提供的半导体设备，其采用物理气相沉积腔室制备电容的上电极和下电极，这与采用化学气相沉积相比，形成的薄膜致密性更好，且电阻率较低，从而可以提高上电板和下电极的金属电极性能，进而提高电容的性能；同时，本发明提供的半导体设备将物理气相沉积腔室和原子层沉积腔室与同一传输平台集成在一起，构成单一集簇设备系统，这不仅降低了设备成本，而且可以避免基片在传输过程中暴露在空气中，从而可以避免薄膜表面被污染。
附图说明
图1a为平面电容的结构示意图；
图1b为沟槽电容的结构示意图；
图1c为一种具体的沟槽电容的结构示意图；
图2为本发明实施例提供的半导体设备的结构简图；
图3a为本发明实施例中平面电容的结构示意图；
图3b为本发明实施例中沟槽电容的结构示意图；
图4为典型的磁控溅射腔室的结构简图；
图5为去气腔室的一种结构示意图；
图6为预清洗腔室的一种结构示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图来对本发明提供的半导体设备行详细描述。
实施例1
本发明实施例提供的半导体设备，其可以用于制备电容。图2为本发明实施例提供的半导体设备的结构简图，请参阅图2，该半导体设备包括：物理气相沉积(Physical Vapor Deposition，以下简称PVD)腔室40、原子层沉积(Atomic Layer Deposition，以下简称ALD)腔室50和传输平台60。其中，PVD腔室40用于制备电容的上电极和下电极；ALD腔室50用于制备电容的电介质层；传输平台60分别与PVD腔室40和ALD腔室50连接，用于传输基片。具体地，传输平台60主要包括传输腔室和装/卸载台，其中，传输腔室为真空腔室，且在该传输腔室中设置有机械手。PVD腔室40和ALD腔室50围绕在传输腔室的周围，且与该传输腔室连通，从而构成一集簇设备系统。
在将基片装载至传输平台60的装载台之后，由机械手自装载台取出基 片，并将基片按工艺顺序传输至PVD腔室40和ALD腔室50，在完成电容的制备之后，再将加工完成的基片传出至卸载台。
本发明实施例提供的半导体设备，其采用PVD腔室制备电容的上电极和下电极，这与采用化学气相沉积相比，形成的薄膜致密性更好，且电阻率较低，从而可以提高上电板和下电极的金属电极性能，进而提高电容的性能；同时，本发明提供的半导体设备将PVD腔室和ALD腔室与同一传输平台集成在一起，构成单一集簇设备系统，这不仅降低了设备成本，而且可以避免基片在传输过程中暴露在空气中，从而可以避免薄膜表面被污染。
可选的，PVD腔室的数量为多个，多个PVD腔室分别用于沉积多种材料的薄膜。这样，单个集簇设备系统即可完成多种材料的薄膜沉积，而无需使用多个独立设备，从而可以降低设备成本，同时避免基片在传输过程中暴露在空气中。
例如，电容可以为平面电容或者沟槽电容。并且，电容的上电极和下电极可以均包括至少一层W膜层和至少一层TiN膜层。在这种情况下，PVD腔室的数量可以为两个；两个PVD腔室分别用于沉积W膜层和TiN膜层。可选的，电介质层包括Al 2O 3膜层；ALD腔室用于沉积Al 2O 3薄膜。
在本实施例中，图3a示出了一种平面电容，图3b示出了一种沟槽电容，这两种电容均包括上电极10、下电极20及位于二者之间的电介质层30。其中，上电极10包括朝靠近下电极20的方向依次层叠的W膜层和TiN膜层；下电极20包括朝靠近上电极10的方向依次层叠的W膜层和TiN膜层；电介质层30为Al 2O 3膜层。
上述两种电容的制备方法为：PVD W→PVD TiN→ALD Al 2O 3→PVD TiN→PVD W。其中，PVD TiN和PVD W是指采用物理气相沉积工艺制备TiN膜层和W膜层，分别在两个PVD腔室进行。ALD Al 2O 3是指采用原子层沉积工艺制备Al 2O 3膜层，需要在ALD腔室进行。
需要说明的是，在实际应用中，电容的上电极和下电极还可以采用其他结构，例如，如图1c所示，电容的上电极10包括朝靠近下电极20的方向依次层叠的W膜层和TiN膜层；下电极20包括朝靠近上电极10的方向依次层叠的TiN膜层、W膜层和TiN膜层。当然，电容的上电极和下电极所采用的膜层数量和材料种类可以根据需要具体设置。并且，PVD腔室的数量和ALD腔室的数量应根据上电极和下电极所采用的膜层材料种类之和相对应。
可选的，PVD腔室为磁控溅射腔室。图4为典型的磁控溅射腔室的结构简图，如图4所示，磁控溅射腔室包括腔体8、工艺套件等，其中，在腔体8的内部设置有基座9，用于承载基片；在腔体8的顶部设置有靶材3。工艺套件包括屏蔽件2、遮蔽环11以及沉积环14，其中，屏蔽件2环绕在腔体8的侧壁内侧，用于保护腔体8的侧壁。沉积环14环绕设置在基座9的边缘区域，遮蔽环11设置在屏蔽件2和沉积环14上，用于遮挡二者之间的间隙，以避免等离子体进入基座15的下方。此外，在靶材3上方还设置有磁控管6，该磁控管6在电机5的驱动下绕中心轴旋转。并且，在靶材3上方还设置有用于盛放去离子水的冷却腔7，用于冷却靶材；磁控管6位于该冷却腔7中。另外，在腔体8的底部还设置有真空系统13，用于将腔室抽真空。
如图2所示，本发明实施例提供的半导体设备还包括去气(Degas)腔室70，该去气腔室70用于对基片进行除气和退火。并且，去气腔室70与传输平台60连接，与其他腔室构成一集簇设备系统。
具体地，图5为去气腔室的一种结构示意图，请参阅图5，该去气腔室70包括腔体，在该腔体中设置有石英窗71，石英窗71将腔室隔离形成真空腔72和大气腔73，其中，在真空腔72内设置有用于承载基片76的基座74；并且在基座74内设置有加热丝组件75，用于对基片76起到均匀加热的作用。在大气腔73内设置有加热灯泡77，该加热灯泡77透过石英窗71向基片76辐射热量。加热灯泡77通过灯泡基座78安装在安装板79上，并且，在安 装板79的朝向加热灯泡77的表面上叠置有反射板792，该反射板792的下表面经过光滑处理，以能够更好地将将来自加热灯泡77的热量朝向石英窗71的方向反射，从而可以提高加热效率。此外，在安装板79上还设置有冷却水管路791。用于冷却反射板792。在腔室侧壁的内侧环绕设置有屏蔽件793，且在屏蔽件793内设置有冷却水管路794，用于冷却腔室侧壁，以避免腔室侧壁过热。
通过同时利用加热灯泡77和加热丝组件75加热基片76，不仅可以提高加热效率，而且由于加热丝组件75能够均匀地加热基片76，因此，可以对基片76完成快速均匀加热。
如图2所示，本发明实施例提供的半导体设备还包括预清洗(PreClean)腔室80，该预清洗腔室80用于去除基片表面上的杂质。并且，预清洗腔室80与传输平台60连接，与其他腔室构成一集簇设备系统。
具体地，图6为预清洗腔室的一种结构示意图，请参阅图6，预清洗腔室80包括腔室盖801、绝缘腔室壁802及环形金属零件803等，在其内设置有用于承载基片的基座804；并且，在绝缘腔室壁802的外侧缠绕有螺线管线圈805，且在螺线管线圈805的周围设置有屏蔽罩806，用于避免螺线管线圈805产生的磁感线向外界辐射。此外，螺线管线圈805通过匹配器与第一射频电源807相连，第一射频电源807用于将射频功率施加至螺线管线圈805上，以使腔室内气体离化产生等离子体；第二射频电源808通过匹配器与基座804相连，用于使基片产生负偏压，吸引等离子体轰击基片，以去除晶片表面的杂质，对晶片表面进行预处理。
需要说明的是，图4-图6分别给出了目前常用的典型的PVD腔室、去气腔室70和预清洗腔室80，但本发明并不局限于此，在实际应用中，还可以采用其他结构的PVD腔室、去气腔室70和预清洗腔室80。另外，ALD腔室采用现有技术中常用的腔室结构，在此不再详述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种半导体设备，其特征在于，包括：物理气相沉积腔室、原子层沉积腔室和传输平台；
    所述物理气相沉积腔室用于制备电容的上电极和下电极；
    所述原子层沉积腔室用于制备所述电容的电介质层；
    所述传输平台分别与所述物理气相沉积腔室和所述原子层沉积腔室连接，用于传输基片。
  2. 根据权利要求1所述的半导体设备，其特征在于，还包括去气腔室，所述去气腔室用于对基片进行除气和退火；所述去气腔室与所述传输平台连接。
  3. 根据权利要求1所述的半导体设备，其特征在于，还包括预清洗腔室，所述预清洗腔室用于去除基片表面上的杂质；所述预清洗腔室与所述传输平台连接。
  4. 根据权利要求1所述的半导体设备，其特征在于，所述物理气相沉积腔室的数量为多个，多个所述物理气相沉积腔室分别用于沉积多种材料的薄膜。
  5. 根据权利要求4所述的半导体设备，其特征在于，所述电容的上电极和下电极均包括至少一层W膜层和至少一层TiN膜层；所述物理气相沉积腔室的数量为两个；两个所述物理气相沉积腔室分别用于沉积W膜层和TiN膜层。
  6. 根据权利要求5所述的半导体设备，其特征在于，所述电容的上电 极包括朝靠近所述下电极的方向依次层叠的W膜层和TiN膜层；
    所述下电极包括朝靠近所述上电极的方向依次层叠的W膜层和TiN膜层。
  7. 根据权利要求5所述的半导体设备，其特征在于，所述电容的上电极包括朝靠近所述下电极的方向依次层叠的W膜层和TiN膜层；
    所述下电极包括朝靠近所述上电极的方向依次层叠的TiN膜层、W膜层和TiN膜层；
    所述电介质层为Al 2O 3薄膜。
  8. 根据权利要求1-7任意一项所述的半导体设备，其特征在于，所述电介质层包括Al 2O 3膜层；所述原子层沉积腔室用于沉积Al 2O 3薄膜。
  9. 根据权利要求1所述的半导体设备，其特征在于，所述电容为平面电容。
  10. 根据权利要求1所述的半导体设备，其特征在于，所述电容为沟槽电容。
PCT/CN2018/114600 2018-01-17 2018-11-08 半导体设备 WO2019140989A1 (zh)

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