WO2019128554A1 - 一种半导体器件的制造方法和集成半导体器件 - Google Patents

一种半导体器件的制造方法和集成半导体器件 Download PDF

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WO2019128554A1
WO2019128554A1 PCT/CN2018/116633 CN2018116633W WO2019128554A1 WO 2019128554 A1 WO2019128554 A1 WO 2019128554A1 CN 2018116633 W CN2018116633 W CN 2018116633W WO 2019128554 A1 WO2019128554 A1 WO 2019128554A1
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region
doping type
forming
source
dielectric
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PCT/CN2018/116633
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English (en)
French (fr)
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程诗康
顾炎
张森
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无锡华润上华科技有限公司
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Priority to KR1020207019554A priority Critical patent/KR102363129B1/ko
Priority to JP2020535534A priority patent/JP7083026B2/ja
Priority to US16/768,563 priority patent/US11257720B2/en
Publication of WO2019128554A1 publication Critical patent/WO2019128554A1/zh

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    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a method of fabricating a semiconductor device and an integrated semiconductor device.
  • VDMOS Vertical double-diffused metal oxide field effect devices
  • VDMOS include enhanced and depletion modes, which have the advantages of good off-characteristics and low power consumption, and are widely used in LED drivers and power adapters.
  • most of the existing different types of VDMOS devices are individually packaged, which brings disadvantages such as an increase in process cost and an excessive chip area.
  • a semiconductor device and a method of fabricating the same are provided in accordance with various embodiments of the present application.
  • a method of fabricating a semiconductor device comprising at least:
  • a semiconductor substrate forming a first doping type epitaxial layer having a first region, a second region, and a third region on a front surface of the semiconductor substrate, the third region being located in the first region and the first Between the two regions, at least one trench in the first doping type epitaxial layer is formed in the third region;
  • the dielectric island including a first dielectric island, a second dielectric island, and a third dielectric island, wherein the first medium An island portion covers a region between two adjacent second doping type deep wells in the first region, partially covering two adjacent second doping type deep wells in the second region a region between the first dielectric island and the adjacent two of the second doping type deep wells, the second dielectric island portion covering a portion located in the first region a partial region in the second doping type deep well partially covering a partial region of the second doping type deep well in the second region, the second dielectric island in the first region a second doping type deep well on the side and a second doping type deep well on both sides of the second dielectric island in the second region are regions in which a source region of the first doping type is to be formed, the third a dielectric island covering the trench;
  • first doping type channel Forming a first doping type channel on the epitaxial layers on both sides of the first dielectric island in the first region, the first doping type channel extending into the first region to be formed a region of the first doping type source region;
  • first doping type and the second doping type are opposite.
  • An integrated semiconductor device comprising a semiconductor device fabricated by the method as described above.
  • FIG. 1A-1G are schematic structural views of a semiconductor device formed in a method of fabricating a semiconductor device according to the present application.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present application.
  • the present application provides a method of fabricating a semiconductor device and an integrated semiconductor device.
  • the manufacturing method of the semiconductor device of the present application and the semiconductor device are exemplified by taking the manufacturing process of the VDMOS semiconductor device as an example. It should be understood that the description of the manufacturing process of the VDMOS semiconductor device in this embodiment is merely exemplary. Any method of fabricating a semiconductor device that integrates a depletion device and an enhancement device is suitable for use in the present application.
  • FIG. 1A-1G and FIG. 2 a method for fabricating a semiconductor device according to the present application is exemplarily described.
  • FIGS. 1A-1G are formed in a method of fabricating a semiconductor device according to an embodiment of the present application.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present application.
  • step S1 is performed: providing a semiconductor substrate, forming a first doping type epitaxial layer having a first region, a second region, and a third region on a front surface of the semiconductor substrate, the third region Located between the first region and the second region, a trench in the first doping type epitaxial layer is formed in the third region.
  • a semiconductor substrate 100 is provided, and specifically, may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/
  • the V compound semiconductor further includes a multilayer structure composed of these semiconductors, or the like, or is silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), and silicon-on-insulator (on-silicon). SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate is of a first doping type.
  • the first doping type and the second doping type generally refer to P-type or N-type, for example, the first doping type is P-type, low-doped P-type, and highly doped P+ type.
  • One of the second doping types is one of an N-type, a low-doped N-type, and a highly doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, highly doped N+ type
  • the second doping type is P-type, low-doped P-type, and highly doped P+ type one of them.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate having a doping concentration of 1 ⁇ 10 14 /cm 3 to 2 ⁇ 10 14 /cm. 3 .
  • a first doping type epitaxial layer is formed on a front surface of the first doping type semiconductor substrate.
  • a first doping type epitaxial layer 101 is formed on the first doping type semiconductor substrate 100, and the first doping type epitaxial layer 101 includes a first region 1, a second region 2, and a first Three zones 3, the third zone 3 being formed between the first zone 1 and the second zone 2.
  • the first region 1 is intended to form a depletion type semiconductor device
  • the second region 2 is intended to form an enhancement type semiconductor device
  • the depletion type semiconductor device and the enhancement type are to be formed in the third region
  • the isolation structure of the semiconductor device is intended to form a depletion type semiconductor device.
  • the method of forming the first doping type epitaxial layer 101 includes any method known to those skilled in the art such as ion doping vapor phase epitaxy.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer. Layer, the N- epitaxial layer.
  • the thickness and resistivity of the first doping type epitaxial layer 101 may affect the withstand voltage capability of the device. The thicker the first doping type epitaxial layer 101, the higher the resistivity, and the higher the withstand voltage capability of the device. In the present embodiment, when the VDMOS semiconductor device is formed to have a withstand voltage requirement of 650 V, the first doping type epitaxial layer 101 has a thickness of 45 ⁇ m to 65 ⁇ m and a specific resistance of 15 ⁇ cm to 25 ⁇ cm.
  • At least one trench 102 is formed in the third region 3 of the first doping type epitaxial layer 101. At least one trench 102 located in the third region 3 is disposed in the first doping type epitaxial layer 101, thereby forming an isolation structure disposed by the trench 102, on both sides of the trench.
  • the current path that may be formed between the depletion device and the enhancement device is blocked, and the depletion device and the enhancement device are isolated.
  • the depth of the trench may be smaller than the thickness of the epitaxial layer of the first doping type, or may be equal to or greater than the thickness of the epitaxial layer of the first doping type, and each of them can have an isolation effect.
  • the number of the grooves affects the isolation effect, and the more the number of grooves, the better the isolation effect.
  • the present application adopts a trench to provide an isolation structure, which effectively reduces the area of the isolation structure compared to the isolation structure provided by the deep well, thereby saving chip area.
  • the depth of the trench is greater than or equal to the thickness of the first doping type epitaxial layer, that is, the trench penetrates the first doping type epitaxial layer.
  • a trench 102 penetrates the first doping type epitaxial layer 101 and extends into the semiconductor substrate 100, thereby forming a complete barrier located in the epitaxial layer on both sides of the trench.
  • the steps of forming the isolation structure will be further described.
  • the method of forming the trench 102 includes first forming a patterned mask layer on the first doping type epitaxial layer, the patterned mask layer exposing a position where the trench is to be formed And etching the first doping type epitaxial layer with the patterned mask layer as a mask, and the trench is penetrated by the first doping type by means of end point detection, over etching, or the like Epitaxial layer; Finally, the patterned mask layer is removed. It is to be understood that the steps of forming the trenches are merely exemplary and any method of forming the trenches is suitable for use in the present application.
  • the groove has a width of 0.5 ⁇ m to 2 ⁇ m.
  • the width of the trench is set to 0.5 ⁇ m to 2 ⁇ m, so that the thermal oxidation process can be used to fill the trench while forming the dielectric island during the subsequent trench filling process, reducing the number of process steps while forming a dense filling material.
  • the depth of the trench is determined according to the thickness of the first doping type epitaxial layer.
  • the shape of the groove may be a rectangle, a square, a trapezoid, or an inverted trapezoid, which is not limited thereto.
  • the bottom of the groove may be a circular arc shape, a conical shape or the like.
  • the groove is trapezoidal, and the inclination of the sidewall of the groove may range from 45° to 90°. It should be understood that the dimensions, topography, angles and the like of the trenches given in this embodiment are merely exemplary, and any trenches located in the first epitaxial layer are suitable for the present application.
  • step S2 is performed to form at least two second doping type deep wells in the first region and the second region, respectively.
  • FIG. 1B a schematic structural view of a semiconductor device in which at least two second doping type deep wells are respectively formed in the first region and the second region is illustrated.
  • a method of forming the second doping type deep well includes: forming a patterned mask layer on the first doping type epitaxial layer, the patterned mask layer exposing the pseudo-forming second doping A region of a deep well type; performing a second doping type well region ion implantation, forming a second doping type deep well on the first doping type epitaxial layer; removing the patterned mask layer.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • the second doping type deep well is a P well
  • the ions doped by the second doping type well region are boron ions
  • the injected energy ranges from 50 KeV to 200 Kev
  • the implantation dose range It is 5.0E13/cm 2 to 5.0E14/cm 2 .
  • a step of performing a second doping type deep well annealing is further included.
  • the first annealing has a temperature ranging from 1100 ° C to 1200 ° C and a time ranging from 60 min to 300 min.
  • step S3 is performed: filling the trench and forming a dielectric island on the first doping type epitaxial layer, the dielectric island including a first dielectric island, a second dielectric island, and a a three-medium island, wherein the first dielectric island portion covers an area between two adjacent second doping type deep wells in the first region, partially covering an adjacent portion in the second region a region between two of the second doping type deep wells, and the first dielectric island is not in contact with the two adjacent second doping type deep wells, the second dielectric island Partially covering a partial region of the second doping type deep well in the first region, partially covering a partial region of the second doping type deep well in the second region, the first a second doping type deep well on both sides of the second dielectric island in the region and a second doping type deep well on both sides of the second dielectric island in the second region are intended to form a first doping An area of the type source region, the third dielectric island covering the trench.
  • FIG. 1C a schematic structural view of a semiconductor device after filling the trench and forming a dielectric island on the first doped epitaxial layer is illustrated.
  • the trench 102 is filled, and a plurality of dielectric islands 104 are formed on the first doping type epitaxial layer 101.
  • the dielectric island 104 includes a first dielectric island 1041, a second dielectric island 1042, and a third dielectric island 1043.
  • the first dielectric island 1041 is located above a region between adjacent two second doping type deep wells 1031 in the first region 1 and adjacent two adjacent second portions in the second region 2 Above the region between the doping type deep wells 1032, and in the first region 1, the first dielectric islands 1041 are not in contact with the adjacent two second doping type deep wells 1031, The first dielectric island 1041 in the second region 2 is not in contact with the adjacent two second doping type deep wells 1032; the second dielectric island 1042 is located in the second region 1 in the first region 1 On the hetero-type deep well 1031 and the second doping type deep well 1032 in the second region 2, the second doping type deep well includes a region 110a covered by the second dielectric island, and the region 110a is located to be formed Between the first doping type source regions, that is, the second doping type deep well region on both sides of the second doping type deep well region 110a is a region where the first doping type source region is to be formed; the third medium Island 1043 covers the filled trenches
  • the step of filling the trench and forming a dielectric island on the first doping type epitaxial layer comprises: performing a deposition process, forming an epitaxial layer covering the first doping type and filling the trench a dielectric material layer of the trench; the dielectric material layer is patterned to form the dielectric island.
  • the filling of the trench can be placed in the same step as the formation of the dielectric island, which reduces the process flow and reduces the number of processes. Process cost.
  • a thermal oxidation process is performed to form a silicon oxide layer covering the sidewalls and bottom of the trench.
  • the dielectric material layer is one or a combination of an oxide layer, polysilicon, TEOS, and BPSG.
  • the width of the trench ranges from 0.5 ⁇ m to 2 ⁇ m
  • the step of filling the trench and forming the dielectric island on the first doped type epitaxial layer comprises: performing a thermal oxidation process to form a cover The first doping type epitaxial layer surface and an oxide layer filling the trench; the oxide layer is patterned to form the dielectric island.
  • the thickness of the dielectric island 104 ranges from The length of the dielectric island 103 ranges from 2 ⁇ m to 5 ⁇ m.
  • the thermal oxidation process is employed to simultaneously perform the covering process of the bottom and sidewalls of the trench, the filling process of the trench, and the step of forming the dielectric island, in order to reduce the coverage of the dielectric material layer and the filling trench in the trench.
  • steps of filling the trench and forming the dielectric island using the thermal oxidation process in the present embodiment are merely exemplary. Any method of filling trenches and forming dielectric islands is suitable for use in the present application.
  • the first doping type source region may be self-aligned with the second dielectric island as a mask, and the first doping type source region is deepened by the second doping type
  • the well regions 110a are spaced apart.
  • the third dielectric island covers the filled trench to form a closed trench structure, forming a complete isolation structure between the enhancement device and the depletion device for efficient implementation of the enhancement device and the depletion device isolation.
  • step S4 is performed: forming a first doping type channel on the epitaxial layers on both sides of the first dielectric island in the first region, the first doping type The channel extends to a region of the first region where the first doping type source region is to be formed.
  • a first doping type channel 105 which is located on both sides of the first dielectric island 1041, is formed in the first region 1 of the first doping type epitaxial layer 101, and the first doping type channel 105 is formed. Extending to a region of the second doping type deep well 1031 in the first region 1 where a source region is to be formed.
  • the step of forming a first doping type channel on both sides of the first dielectric island in the first region of the first doping type epitaxial layer comprises: first, in the first doping type epitaxy Forming a patterned mask layer on the layer, the patterned mask layer exposing a region on the two sides of the first dielectric island where the first doping type channel is to be formed; and the patterned mask layer Performing channel ion implantation with the first dielectric island as a mask, the first doping type channel on both sides of the first dielectric island; removing the patterned mask layer.
  • the ions ion-implanted into the channel are phosphorus ions, and the implantation energy ranges from 50 KeV to 200 KeV, and the implantation dose ranges from 5.0 E12/cm 2 to 5.0 E13/cm 2 .
  • ion implantation is performed using the first dielectric island as a mask, preventing ions from entering the region under the first dielectric island, so that the first doping type epitaxy under the first dielectric island.
  • the channel ion concentration of the layer whose channel ion concentration is minimized is minimized, so that the breakdown voltage of the depletion device is higher and the breakdown reliability is greatly improved.
  • the Vt adjusts the implanted ions to be phosphorus ions
  • the injected energy ranges from 100 KeV to 200 KeV
  • the implant dose ranges from 1.0 E12/cm 2 to 1.0 E13/cm 2 .
  • the step of performing a second annealing is performed, the temperature ranges from 1100 ° C to 1200 ° C, and the second annealing time ranges from 60 min to 180 min.
  • step S5 is performed to form a gate structure covering the first dielectric island and the third dielectric island on the first doping type epitaxial layer, and the gate structure exposes the second medium An island and an area in the first region and the second region, respectively, where the first doping type source region is to be formed.
  • the gate structure includes a gate dielectric layer and a gate material layer stacked in this order from bottom to top.
  • a gate structure 106 is first formed on a first doping type epitaxial layer 101, the gate structure 106 including a gate structure 1061 formed on the first region 1 and formed in the second region Gate structure 1062 on 2.
  • the gate structure 106 includes a gate dielectric layer 107 and a gate material layer 108, and the gate structure 1061 of the gate structure 106 on the first region 1 covers the portion located in the first region 1 a first dielectric island 1041, and exposing the second dielectric island 1042 and a region of the second doped deep well 1031 located in the first region 1 to form a first doping type source region;
  • the gate structure 1062 on the first region 1 covers the first dielectric island 1041 located in the second region 2, and exposes the second dielectric island 1042, and the second doping in the second region 2 A region of the type deep well 1032 where the source region of the first doping type is to be formed.
  • the gate structure 106 also covers the third dielectric island 1043.
  • the gate dielectric layer is a silicon dioxide material
  • the gate material layer is a polysilicon material.
  • the method of forming the gate structure may be any method well known to those skilled in the art, for example, process steps including deposition, photolithography, etching, etc., and will not be described herein.
  • the thickness of the gate dielectric layer ranges from The thickness of the gate material layer ranges from
  • the gate structure further covers the third dielectric island in the third region while forming the gate structure.
  • the gate structure 106 also covers the third dielectric island 1043.
  • step S6 performing first doping type source region ion implantation using the gate structure and the second dielectric island as a mask, respectively forming a first in the first region and the second region Doping type source region.
  • a first doping type source region ion implantation is performed using the gate structure 106 and the dielectric island 104 as a mask, and a second doping type deep well 1031 and a first doping region in the first region 1
  • a first doping type source region 110 on both sides of the gate structure is formed in the second doping type deep well 1032 of the second region 2, wherein the second doping type deep well 1031 of the first region 1 is located
  • the first doping type source region 110 is in contact with the first doping type channel 105, and the first doping type source region 110 located in the same second doping type deep well is located under the second dielectric island 1042
  • the second doping type deep well regions 110a are spaced apart.
  • a method of forming the first doping type source region is performed by using the gate structure and the second dielectric island as a mask to perform ion implantation. Since the second dielectric island is formed in the second doping type deep well of the first region and the second doping type deep well of the second region, the second medium may be used in forming the first doping type source region The island acts as a mask to form a first doping type source region, and the first doping type source region is located on both sides of the second dielectric island, that is, the first doped type is separated by the second doping type deep well region 110a. A lithographic plate is saved during the process, which reduces the process cost.
  • the ion implantation step of forming the first doping type source region 110 uses a phosphorus ion implantation step, the injected energy range is 50Kev to 150Kev, and the implantation dose ranges from 5.0E15/cm 2 to 1.0E16/cm. 2 .
  • a second doping type well region under the first doping type source region is formed. Forming the second doping type well region under the first doping type source region can significantly reduce the resistance of the parasitic transistor base region, greatly reducing the risk of parasitic transistor turn-on, and significantly improving the operational stability of the device.
  • a second doping type well region 109 is formed under the first doping type source region 110.
  • the method of forming the second doping type well region employs ion implantation with the gate structure and the second dielectric island as a mask.
  • the ion implantation step of forming the second doping type well region 109 is a boron ion implantation step, and the injected energy ranges from 150Kev to 300Kev, and the implantation dose ranges from 1.0E15/cm 2 to 5.0E15/ Cm 2 .
  • the step of forming a source includes: forming a dielectric layer on the first doping type epitaxial layer, the dielectric layer covering the gate structure and the first doping type source region and exposing Removing the second dielectric island; removing a portion of the dielectric layer to expose a portion of the first doping type source region; forming a source on the first doping type epitaxial layer
  • the source includes a first region source in contact with the second doping type deep well of the first region and a second region source in contact with the second doping type deep well of the second region, The source of the first region is not in contact with the source of the second region.
  • the step of forming the second doping type well region and the second doping type source region is further included before forming the source.
  • a process of forming a source after forming a second doping type source will be described below with reference to FIGS. 1F and 1G.
  • a dielectric covering the gate structure (including the gate dielectric layer 107 and the gate material layer 108) and the first doping type source region 110 is formed on the first doping type epitaxial layer 101.
  • the dielectric layer may be a dielectric material layer such as silicon dioxide or silicon nitride.
  • the method of forming the dielectric layer includes steps of deposition, photolithography, etching, etc., which are well known to those skilled in the art, and will not be described herein.
  • the second dielectric island 1042 and a portion of the dielectric layer are removed, thereby exposing a portion of the first region second doping type deep well 1031 and the second region second doping type deep well 1032.
  • the method of removing the second dielectric island and a portion of the dielectric layer may employ a method well known to those skilled in the art, such as etching, and will not be described herein.
  • a first electrode between the first doping type source region 110 and the second doping type deep well 1032 of the first region is formed.
  • the second doping type source region 112 is connected to the first doping type source region.
  • the ion implantation step of forming the second doping type source region uses the remaining dielectric layer 111 as a mask.
  • a second doping type source region is formed after the dielectric layer is partially removed, and a source region is formed, wherein the ion implantation forming the second doping type source region is more than the ion implantation forming the first doping type source region.
  • the dose is low, so that in the process of forming the second doping type source region, the exposed first doping type source region is not inverted, thereby separately forming the second doping type park ion implantation mask step, reducing Process flow to reduce process costs.
  • the second doping type source region is for enhancing contact between the source and the deep well.
  • the ion implantation step of forming the source region of the second doping type adopts a boron ion or boron difluoride ion implantation step, and the injected energy ranges from 50Kev to 200Kev, and the implantation dose ranges from 5.0E14/cm 2 to 5.0E15/cm 2 .
  • the formation of the second doping type source region here after the partial removal of the dielectric layer and before the formation of the source is merely exemplary, and any step of forming the source region of the second doping type is suitable for the present application.
  • an ion implantation step is performed to form another second doping type well region under the second doping type source region 112, and the other second doping type well region will be
  • the second doping type well regions 109 under the first doping type source region 110 are connected to form a complete second doping type under the first doping type source region 110 and the second doping type source region 112.
  • the ion implantation step of forming another second doping type well region, using the remaining dielectric layer 111 as a mask, using a boron ion implantation process the injected energy range is 150Kev to 300Kev, and the implantation dose range is 1.0E15/cm. 2 to 1.0E16/cm 2 .
  • annealing is performed after the ion implantation step of another second doping type well region is completed.
  • the annealing temperature ranges from 800 ° C to 1000 ° C, and the annealing time ranges from 30 min to 90 min.
  • the second doping type well region 1091 formed under the first doping type source region 110 and the second doping type source region 112 can significantly reduce the resistance of the parasitic transistor base region and greatly reduce the risk of parasitic transistor turn-on. This makes the device's working stability significantly improved.
  • the source 113 includes a first region source 1131 and a second region source 1132.
  • the first region source 1131 and the first of the first region 1 The doping type source region 110 is in contact with the second doping type source region 112, and the second region source 1132 and the second region 2 are in the first doping type source region 110 and the second doping type
  • the source region 112 is in contact, and the first region source 1131 is not in contact with the second region source 1132.
  • the source is a conventional alloy of one or more of aluminum and copper.
  • the step of forming the source 113 includes depositing a source material layer and patterning the source material layer to form the source.
  • the steps of etching the dielectric layer, depositing the source material layer, and patterning the source material layer are processes well known to those skilled in the art, and are not described herein again.
  • a step of forming a drain is also included.
  • the step of forming a drain includes: first, thinning a back surface of the first doping type semiconductor substrate; then depositing on a back side of the first doping type semiconductor substrate A drain is formed.
  • the drain is made of a conventional alloy of one or more of aluminum and copper.
  • a drain electrode 114 is formed on the back surface of the first doping type semiconductor substrate 100.
  • the manufacturing method of the semiconductor device of the present application has been exemplarily described, and the manufacturing method of the semiconductor device and the semiconductor device according to the present application are formed in the manufacturing process of the semiconductor device in which the enhancement device and the depletion device are integrated.
  • the ion concentration under the dielectric island is low, so that the breakdown reliability of the device in the on state is greatly improved;
  • the presence of the dielectric island increases the thickness of the gate dielectric layer, reduces the gate capacitance, and reduces the switching loss of the device.
  • the arrangement of the trenches in the epitaxial layer as an isolation structure for the enhancement device and the depletion mode device improves the isolation characteristics between the enhancement and depletion devices on the one hand, and reduces the chip area occupied by the isolation structure on the other hand.
  • the dielectric island is used as a mask, and the first doping type source region can be self-aligned, which saves a process step of forming a ion implantation mask by a lithography plate and a photolithography process, and reduces the process cost.
  • a source region of a second doping type is formed between the source regions of the first doping type, and the steps of forming the source and the drain are merely exemplary, and those skilled in the art may
  • the source and drain are formed using processes well known in the art and are not intended to limit the application to the scope of the described embodiments. The scope of protection of the application is defined by the appended claims and their equivalents.
  • VDMOS device in this embodiment is merely exemplary, and is not intended to limit the scope of the application. Those skilled in the art may form an IGBT device or the like as needed.
  • the semiconductor device according to the present application may also be provided as an IGBT device in which the semiconductor substrate of the above VDMOS device is set to a second doping type, such as a semiconductor substrate being a P+ type substrate, other component positions and doping The type is unchanged, a depletion IGBT device is formed in the first region, and an enhancement IGBT device is formed in the second region.
  • the IGBT device is used in parallel with a fast recovery diode to improve the current sharing effect of the device and the stability and reliability of the system operation.
  • the present application also provides an integrated semiconductor device comprising the integrated semiconductor device fabricated according to the method of embodiment 1.
  • the integrated semiconductor device includes: a semiconductor substrate 100, a semiconductor substrate 100, and in particular, may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, including multilayer structures composed of these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), insulators Upper silicon germanium (SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate in this embodiment is of a first doping type.
  • the first doping type and the second doping type generally refer to a P-type or an N-type, wherein the first doping type and the second doping type are opposite.
  • the first doping type is one of P type, low doped P-type, and highly doped P+ type
  • the second doping type is N type, low doped N-type, and highly doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and highly doped N+ type
  • the second doping type is P-type, low-doped P-type, and highly doped P+
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate having a doping concentration of 1 ⁇ 10 14 /cm 3 to 2 ⁇ 10 14 /cm. 3 .
  • a first doping type epitaxial layer 101 is formed on a front surface of the first doping type semiconductor substrate 100.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • Layer the N- epitaxial layer.
  • the thickness and resistivity of the first doping type epitaxial layer 101 may affect the withstand voltage capability of the device. The thicker the first doping type epitaxial layer 101, the greater the resistivity, and the withstand voltage capability of the device. The higher.
  • the first doping type epitaxial layer 101 has a thickness of 45 ⁇ m to 65 ⁇ m and a specific resistance of 15 ⁇ cm to 25 ⁇ cm.
  • the first doping type epitaxial layer 101 includes the first region 1, the second region 2, and the third region 3; the first region 1 is formed with a depletion type device, and the second region 2 is formed with an enhancement In the type of device, the third region is formed with a trench 102 that is filled with a dielectric material to isolate the depletion mode device and the enhancement device.
  • the isolation structure provided by the trench 102 blocks a current path that may be formed between the depletion device and the enhancement device on both sides of the trench, and isolates the depletion device and the enhancement device. effect.
  • the depth of the trench may be smaller than the thickness of the epitaxial layer of the first doping type, or may be equal to or greater than the thickness of the epitaxial layer of the first doping type, and each of them can have an isolation effect.
  • the number of the grooves affects the isolation effect, and the more the number of grooves, the better the isolation effect.
  • the present application adopts a trench to provide an isolation structure, which effectively reduces the area of the isolation structure and saves the chip area compared to the isolation structure provided by the deep well.
  • the depth of the trench is greater than or equal to the thickness of the first doping type epitaxial layer, that is, the trench penetrates the first doping type epitaxial layer.
  • a trench 102 penetrates the first doping type epitaxial layer 101 and extends into the semiconductor substrate 100, thereby forming a complete barrier located in the epitaxial layer on both sides of the trench.
  • the dielectric material filling the trench is of the same material as the material of the dielectric island. Further, by way of example, the dielectric material filling the trench and the material of the dielectric island are both thermal silicon oxide layers. Thereby reducing the process steps in the manufacturing process.
  • the semiconductor device of the present application further includes a second doping type deep well 103 formed in the first doping type epitaxial layer, wherein the second doping type deep well 103 includes the first At least two second doping type deep wells 1031 in zone 1 are located in at least two second doping type deep wells 1032 in the second zone 2.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • the layer, that is, the N- epitaxial layer, the second doping type deep well is a P well.
  • the semiconductor device of the present application further includes a plurality of dielectric islands 104 formed on the first doping type epitaxial layer 101, the dielectric islands 104 including a first dielectric island 1041 and a third dielectric island 1043.
  • a first dielectric island 1041 is located above a region between adjacent two second doping type deep wells 1031 in the first region 1 and adjacent two second doping types in the second region 2 Above the area between the deep wells 1032. Wherein, in the first region 1, the dielectric island 1041 is not in contact with the adjacent two second doping type deep wells 1031, and the dielectric island 1041 and the second region 2 are The adjacent two second doping type deep wells 1032 are not in contact.
  • the first dielectric island 1041 is formed over a region between the adjacent two second doping type deep wells in the first region and the second region, thereby forming a channel of the depletion device In this case, ion implantation is performed as a mask. Since the presence of the dielectric island blocks the implantation of the channel ions, the ion concentration under the dielectric island is low, so that the breakdown reliability of the device in the on state is greatly improved.
  • the third dielectric island 1043 covers the filled trench to form a closed trench structure, forming a complete isolation structure between the enhancement device and the depletion device for effective enhancement and depletion devices Isolation.
  • the filling material of the dielectric island and the trench is the same material.
  • the groove has a width of 0.5 ⁇ m to 2 ⁇ m.
  • the filling material of the dielectric island and the trench is a thermal oxide layer of the same material.
  • the semiconductor device of the present application further includes a gate structure 106 formed on the first region 1 and the second region 2, the gate structure 106 including a gate formed on the first layer 1.
  • the gate dielectric layer 107 and the gate material layer 108 are partially covered; the gate structure 1061 in the first region 1 partially covers the second doping type deep well 1031 adjacent to the first region 1
  • the gate structure 1062 in the second region 2 partially covers the adjacent second region second doping type deep well 1032 in the second region 2, and the gate structure 106 is covered with a plurality of dielectric islands 1041.
  • the first dielectric island 1041 is covered under the gate structure.
  • the gate structure 106 also covers the third dielectric island 1043.
  • the material of the gate structure 106 and the gate structure can be any material known to those skilled in the art.
  • the gate dielectric layer is a silicon dioxide material
  • the gate material layer is a polysilicon material.
  • the thickness of the gate dielectric layer ranges from The thickness of the gate material layer ranges from
  • the semiconductor device of the present application further includes a first doping type source region 110 formed in the second doping type deep well 103 formed on both sides of the gate structure 106, wherein the same location
  • the first doping type source region 110 in the second doping type deep well 103 is separated by a portion of the second doping type deep well 103.
  • the semiconductor device of the present application further includes a first doping type channel 105 on both sides of the dielectric island 104 in the first region 1, the first doping type channel extending laterally To the outside of the first doping type source region 110.
  • the semiconductor device further includes a second doping type deep formed in the second doping type deep well 1031 and the second region 2 respectively disposed in the first region 1.
  • a second doping type source region 112 in the well 1032, a second doping type source region 112 is located between the first doping type source regions 110, and the second doping type source region is used to enhance the source and Deep well contact.
  • the semiconductor device further includes a second doping type deep well 1031 and a second doping type in the second region 2 respectively disposed in the first region 1.
  • the second doping type well region 1091 formed under the first doping type source region 110 and the second doping type source region 112 can significantly reduce the resistance of the parasitic transistor base region and greatly reduce the risk of parasitic transistor turn-on. This makes the device's working stability significantly improved.
  • the semiconductor device further includes a source 113 formed on the first doping type epitaxial layer, the source 113 including a first region source 1131 and a second The source of the zone is 1132.
  • the first region source 1131 is in contact with the second doping type deep well 1021 in the first region 1 and the first doping type source region 110 in the second doping type deep well 1121.
  • the second region source 1132 is in contact with the second doping type deep well 1022 in the second region 2 and the first doping type source region 110 in the second doping type deep well 1022, wherein The first region source 1131 is not in contact with the second region source 1132.
  • a second doping type source region 112 is formed in the second doping type deep well 1021 in the first region 1 and the second doping type deep well 1022 in the second region 2,
  • the first region source 1131 is in contact with the first doping type source region 110 and the second doping type source region 112 in the first region 1, and the second region source 1132 and the second region 2 are
  • the first doping type source region 110 is in contact with the second doping type source region 112.
  • the semiconductor device further includes a drain 114 formed on a back side of the first doping type semiconductor substrate 100.
  • a complete integrated VDMOS device integrated with a depletion VDMOS device and an enhanced VDMOS device is formed.
  • the description of the VDMOS device in this embodiment is merely exemplary, and is not intended to limit the scope of the application. Those skilled in the art may form an IGBT device or the like as needed.
  • an IGBT device is provided according to the semiconductor device of the present application, wherein the semiconductor substrate of the above VDMOS device is set to a second doping type, that is, the semiconductor substrate is a P+ type substrate, and other component positions and doping types are unchanged. Then, a depletion type IGBT device is disposed in the first region, and an enhanced IGBT device is formed in the second region. Further, by way of example, the IGBT device is used in parallel with a fast recovery diode to improve the current sharing effect of the device and the stability and reliability of the system operation.
  • a plurality of semiconductor devices can be integrated as needed, such as integrating one or more diodes, transistors, resistors, capacitors, JFETs, current sensing VDMOS on the above integrated semiconductor device.
  • a semiconductor device such as CMOS, and an isolation structure between the depletion type semiconductor device and other types of semiconductor devices to prevent punch-through between the semiconductor devices.

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Abstract

半导体器件的制造方法和集成半导体器件，该制造方法包括在半导体衬底(100)上形成具有第一区(1)、第二区(2)和第三区(3)的外延层(101)，在第三区(3)中形成至少一个沟槽(102)，在第一区(1)中形成至少两个第二掺杂类型深阱(1031)，在第二区(2)中形成至少两个第二掺杂类型深阱(1032)；在第二掺杂类型深阱(1031, 1032)之间形成第一介质岛(1041)，在第二掺杂类型深阱(1031, 1032)上形成第二介质岛(1042)；在第一区(1)中的第一介质岛(1041)两侧形成第一掺杂类型沟槽(105)；在第一介质岛(1041)上形成栅极结构(106)；以第二介质岛(1042)为掩膜形成隔离的第一掺杂类型源区(110)，在第一区(1)中，第一掺杂类型沟槽(105)横向延伸至第一掺杂类型源区(110)。

Description

一种半导体器件的制造方法和集成半导体器件 技术领域
本申请涉及半导体制造领域，具体而言涉及一种半导体器件的制造方法和集成半导体器件。
背景技术
垂直双扩散金属氧化物场效应器件(VDMOS)包括增强型和耗尽型，其具有关开特性好、功耗低等优势，在LED驱动、电源适配器等方面具有广泛应用。但是现有的不同类型的VDMOS器件中大都采用独立封装，这样会带来工艺成本的增加，芯片面积过大等缺点。
发明内容
根据本申请的各种实施例提供一种半导体器件及其制造方法。
一种半导体器件的制造方法，至少包括：
提供半导体衬底，在所述半导体衬底的正面形成具有第一区、第二区和第三区的第一掺杂类型外延层，所述第三区位于所述第一区和所述第二区之间，在所述第三区中形成位于所述第一掺杂类型外延层中的至少一个沟槽；
在所述第一区和所述第二区中分别形成至少两个第二掺杂类型深阱；
填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛，所述介质岛包括第一介质岛、第二介质岛和第三介质岛，其中，所述第一介质岛部分覆盖所述第一区内的相邻两个所述第二掺杂类型深阱之间的区域，部分 覆盖所述第二区内的相邻两个所述第二掺杂类型深阱之间的区域，并且所述第一介质岛与所述的相邻两个所述第二掺杂类型深阱均不接触，所述第二介质岛部分覆盖位于所述第一区中的所述第二掺杂类型深阱中的部分区域，部分覆盖位于所述第二区中的所述第二掺杂类型深阱的部分区域，所述第一区内的所述第二介质岛两侧的第二掺杂类型深阱和所述第二区内的所述第二介质岛两侧的第二掺杂类型深阱为拟形成第一掺杂类型源区的区域，所述第三介质岛覆盖所述沟槽；
在所述第一区中的所述第一介质岛的两侧的外延层上分别形成第一掺杂类型沟道，所述第一掺杂类型沟道延伸至所述第一区中拟形成第一掺杂类型源区的区域；
在所述第一掺杂类型外延层上形成分别覆盖所述第一介质岛、所述第三介质岛的栅极结构，且所述栅极结构露出所述第二介质岛和分别位于所述第一区、所述第二区中的所述拟形成第一掺杂类型源区的区域；
以所述栅极结构和所述第二介质岛为掩膜执行第一掺杂类型源区离子注入，分别在所述第一区和所述第二区中形成第一掺杂类型源区；
其中，所述第一掺杂类型和所述第二掺杂类型相反。
一种集成半导体器件，所述集成半导体器件包括如上所述的方法制造的半导体器件。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一副或多副附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1A-1G为根据本申请的半导体器件的制造方法中形成的半导体器件的结构示意图；
图2为根据本申请的一个实施例的一种半导体器件的制造方法的流程 图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本申请，将在下列的描述中提出详细步骤以及结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
实施例一
为了解决现有技术中的技术问题，本申请提供了一种半导体器件的制造方法和集成半导体器件。
下面，以VDMOS半导体器件的制造过程为示例对本申请的半导体器件的制造方法和半导体器件进行示例性说明，需要理解的是，本实施例以VDMOS半导体器件的制造过程为示例进行说明仅仅是示例性的，任何集成耗尽型器件和增强型器件的半导体器件的制造方法，均适用于本申请。
下面参看图1A-1G、图2对本申请的所提出的一种半导体器件的制造方法进行示例性说明，图1A-1G为根据本申请的一个实施例的一种半导体器件的制造方法中形成的半导体器件的结构示意图；图2为根据本申请的一个实施例的一种半导体器件的制造方法的流程图。
首先，参看图2，执行步骤S1：提供半导体衬底，在所述半导体衬底的正面形成具有第一区、第二区和第三区的第一掺杂类型外延层，所述第三区位于所述第一区和所述第二区之间，在所述第三区中形成位于所述第一掺杂类型外延层中的沟槽。
如图1A所示，提供半导体衬底100，具体地，可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。示例性的，所述半导体衬底为第一掺杂类型。
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。示例性的，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，其掺杂浓度为1×10 14/cm 3～2×10 14/cm 3。
在所述第一掺杂类型的半导体衬底的正面形成第一掺杂类型外延层。参看图1A，所述第一掺杂类型的半导体衬底100上形成有第一掺杂类型外延层101，所述第一掺杂类型外延层101包括第一区1、第二区2以及第三区3，所述第三区3形成在所述第一区1和所述第二区2之间。其中，所述第一区1拟形成耗尽型半导体器件、所述第二区2拟形成增强型半导体器件，所述第三区中拟形成隔离所述耗尽型半导体器件和所述增强型半导体器件的隔离结构。
形成所述第一掺杂类型外延层101的方法包括离子掺杂气相外延等任何本领域技术人员所熟知的方法。在本实施例中，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，所述第一掺杂类型外延层为N型低 掺杂的外延层，即N-外延层。
所述第一掺杂类型外延层101的厚度和电阻率会影响器件的耐压能力，第一掺杂类型外延层101的厚度越厚，电阻率越大，器件的耐压能力越高。在本实施例中，形成的VDMOS半导体器件耐压要求在650V时，所述第一掺杂类型外延层101的厚度为45μm～65μm，电阻率为15Ω·cm～25Ω·cm。
在第一掺杂类型外延层101的第三区3中形成有至少一个沟槽102。在第一掺杂类型外延层101中设置位于所述第三区3中的至少一个沟槽102，从而在后续形成由所述沟槽102设置的隔离结构，对在所述沟槽两侧的耗尽型器件和增强型器件之间可能形成的电流通道进行阻隔，对耗尽型器件和增强型器件起到隔离效果。其中，所述沟槽的深度可以小于所述第一掺杂类型外延层的厚度，也可以等于或大于所述第一掺杂类型外延层的厚度，均能起到隔离的效果。所述沟槽的个数会影响隔离效果，沟槽的个数越多隔离效果越好。同时，本申请采用沟槽设置隔离结构，相较于采用深阱设置隔离结构，有效减少了隔离结构的面积，从而节省了芯片面积。
示例性的，所述沟槽的深度大于或等于所述第一掺杂类型外延层的厚度，即所述沟槽穿透所述第一掺杂类型外延层。如图1所示，沟槽102穿透所述第一掺杂类型外延层101而延伸入所述半导体衬底100中，从而形成彻底阻隔位于所述外延层中、所述沟槽两侧的耗尽型器件和增强型器件之间可能形成的电流通道，从而显著提升耗尽型器件和增强型器件的隔离特性，同时，在这样的设置中，不需要进一步设置多个隔离沟槽就能达到最大的隔离效果，进一步减少了隔离结构的面积，节省芯片面积。下面的描述中，将进一步介绍隔离结构的形成步骤。
示例性的，形成所述沟槽102的方法包括：首先，在所述第一掺杂类型外延层上形成图案化的掩膜层，所述图案化的掩膜层露出拟形成沟槽的位置；接着，以所述图案化的掩膜层为掩膜刻蚀所述第一掺杂类型外延层，通过终点检测、过蚀刻等技术手段使得所述沟槽穿透所述第一掺杂类型外延层；最后，去除所述图案化的掩膜层。需要理解的是，所述形成沟槽的步骤仅仅是 示例性的，任何形成所述沟槽的方法均适用于本申请。
示例性的，所述沟槽的宽度为0.5μm～2μm。将沟槽的宽度设置为0.5μm～2μm，从而在后续沟槽的填充过程中可以采用热氧化工艺在形成介质岛的同时填充沟槽，减少工艺的步骤，同时形成致密的填充材料。所述沟槽的深度根据所述第一掺杂类型外延层的厚度决定。可选的，所述沟槽的形状可以为矩形，方形，梯形，倒梯形，在此并不限定，进一步，所述沟槽的底部可以为圆弧型，圆锥型等。示例性的，所述沟槽的为梯形，所述沟槽的侧壁的倾角的范围可以为45°～90°。需要理解的是，本实施例给出的沟槽的尺寸、形貌和角度等仅仅是示例性的，任何位于第一外延层的沟槽均适用于本申请。
接着，继续参看图2，执行步骤S2：在所述第一区和所述第二区中分别形成至少两个第二掺杂类型深阱。
参看图1B，示出了在所述第一区和所述第二区中分别形成至少两个第二掺杂类型深阱的半导体器件的结构示意图。在所述第一掺杂类型外延层101中形成第二掺杂类型深阱103，其中，所述第二掺杂类型深阱103包括位于所述第一区1中的至少两个第二掺杂类型深阱1031和位于所述第二区2中的至少两个第二掺杂类型深阱1032。
形成所述第二掺杂类型深阱的方法包括：在所述第一掺杂类型外延层上形成图案化的掩膜层，所述图案化的掩膜层露出所述拟形成第二掺杂类型深阱的区域；执行第二掺杂类型阱区离子注入，在所述第一掺杂类型外延层上形成第二掺杂类型深阱；去除所述图案化的掩膜层。
在本实施例中，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，所述第一掺杂类型外延层为N型低掺杂的外延层，即N-外延层，所述第二掺杂类型深阱为P阱，所述第二掺杂类型阱区离子注入的离子为硼离子，注入的能量范围为50Kev～200Kev，注入剂量范围为5.0E13/cm 2～5.0E14/cm 2。
示例性的，在完成所述第二掺杂类型阱区离子注入之后，还包括执行第 二掺杂类型深阱退火的步骤。示例性的，所述的第一次退火的温度范围为1100℃～1200℃，时间范围为60min～300min。
接着，继续参看图2，执行步骤S3：填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛，所述介质岛包括第一介质岛、第二介质岛和第三介质岛，其中，所述第一介质岛部分覆盖所述第一区内的相邻两个所述第二掺杂类型深阱之间的区域，部分覆盖所述第二区内的相邻两个所述第二掺杂类型深阱之间的区域，并且所述第一介质岛与所述的相邻两个所述第二掺杂类型深阱均不接触，所述第二介质岛部分覆盖位于所述第一区中的所述第二掺杂类型深阱的部分区域，部分覆盖位于所述第二区中的所述第二掺杂类型深阱的部分区域，所述第一区内的所述第二介质岛两侧的第二掺杂类型深阱和所述第二区内的所述第二介质岛两侧的第二掺杂类型深阱为拟形成第一掺杂类型源区的区域，所述第三介质岛覆盖所述沟槽。
参看图1C，示出了填充所述沟槽、并形成位于所述第一掺杂外延层上的介质岛之后的半导体器件的结构示意图。沟槽102被填充，在所述第一掺杂类型外延层101上形成多个介质岛104，介质岛104包括第一介质岛1041、第二介质岛1042和第三介质岛1043。其中，所述第一介质岛1041位于所述第一区1中的相邻两个第二掺杂类型深阱1031之间的区域的上方和所述第二区2中相邻两个第二掺杂类型深阱1032之间的区域的上方，并且在所述第一区1中，所述第一介质岛1041与所述的相邻两个第二掺杂类型深阱1031不接触，在所述第二区2中所述第一介质岛1041与所述的相邻两个第二掺杂类型深阱1032不接触；所述第二介质岛1042位于第一区1中的第二掺杂类型深阱1031上和第二区2中的第二掺杂类型深阱1032上，所述第二掺杂类型深阱包括被所述第二介质岛覆盖的区域110a，区域110a位于拟形成的第一掺杂类型源区之间，即第二掺杂类型深阱区域110a两侧的第二掺杂类型深阱区域为拟形成第一掺杂类型源区的区域；所述第三介质岛1043覆盖所述已填充的沟槽102。
示例性的，所述填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛的步骤包括：执行沉积工艺，形成覆盖所述第一掺杂类型外延层并填充所述沟槽的介质材料层；图案化所述介质材料层，以形成所述介质岛。在这一过程中，当所述沟槽的介质材料层和形成介质岛的介质材料层材质一致时，可将沟槽的填充与介质岛的形成置于同一步骤，减少了工艺流程，减少了工艺成本。
示例性的，在所述执行沉积工艺的步骤之前，执行热氧化工艺，形成覆盖所述沟槽的侧壁和底部的氧化硅层。在填充沟槽之前形成覆盖所述沟槽的热氧化硅层，一方面降低沟槽形成过程中的应力，另一方面形成覆盖沟槽侧壁的致密的介质材料层，减少漏电。所述介质材料层为氧化层、多晶硅、TEOS和BPSG中的一种或几种的组合。
在本实施例中，沟槽的宽度范围为0.5μm～2μm，填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛的步骤包括：执行热氧化工艺，形成覆盖所述第一掺杂类型外延层表面和填充所述沟槽的氧化层；图案化所述氧化层，以形成所述介质岛。示例性的，所述介质岛104的厚度范围为
Figure PCTCN2018116633-appb-000001
所述介质岛103的长度范围为2μm～5μm。
在本实施例中采用热氧化工艺将沟槽底部和侧壁的覆盖过程、沟槽的填充过程以及形成介质岛的步骤同步进行，在减少在沟槽中再覆盖介质材料层和填充沟槽的步骤，减少工艺的步骤的同时形成致密的填充材料。
需要理解的是，本实施采用热氧化工艺进行沟槽的填充和介质岛的形成步骤仅仅是示例性的。任何填充沟槽、形成介质岛的方法均适用于本申请。
将第一介质岛形成在所述第一区、所述第二区内的相邻两个第二掺杂类型深阱之间的区域的上方，从而在形成耗尽型器件的沟道的过程中，将第一介质岛作为掩膜执行离子注入，阻止了离子进入第一介质岛下方的区域，使得第一介质岛下方的第一掺杂类型外延层的沟道离子浓度降到最低，使得耗尽型器件的击穿耐压更高，击穿可靠性大大提高；而对于增强型器件，根据公式C ox＝ε ox/t ox，可知由于第一介质岛的存在，使得栅介电层的厚度增加，起 到降低栅极电容，减少器件的开关损耗的作用。
将第二介质岛形成在所述第一区和所述第二区内的第二掺杂类型深阱区域110a上，即第二介质岛位于拟形成第一掺杂类型源区的区域之间，从而在形成第一掺杂类型源区的过程中可以以第二介质岛作为掩膜，自对准形成第一掺杂类型源区，第一掺杂类型源区被第二掺杂类型深阱区域110a隔开。在工艺过程中节省了光刻版和进行光刻工艺获得离子注入掩膜的步骤，使得工艺成本下降，形成所述第一掺杂类型源区的步骤将在后续的描述中进一步介绍。
第三介质岛覆盖被填充的沟槽，从而形成封闭的沟槽结构，形成位于增强型器件和耗尽型器件之间的完整的隔离结构，以对增强型器件和耗尽型器件进行有效的隔离。
接着，继续参看图2，执行步骤S4：在所述第一区中的所述第一介质岛的两侧的的外延层上分别形成第一掺杂类型沟道，所述第一掺杂类型沟道延伸至所述第一区中拟形成第一掺杂类型源区的区域。
如图1D所示，在第一掺杂类型外延层101的第一区1中形成位于第一介质岛1041两侧的第一掺杂类型沟道105，所述第一掺杂类型沟道105延伸至所述第一区1中所述第二掺杂类型深阱1031中拟形成源区的区域。
示例性的，在所述第一掺杂类型外延层的第一区中形成位于所第一介质岛的两侧的第一掺杂类型沟道的步骤包括：首先，在第一掺杂类型外延层上形成图案化的掩膜层，所述图案化的掩膜层露出位于所第一介质岛的两侧的拟形成第一掺杂类型沟道的区域；以所述图案化的掩膜层和第一介质岛为掩膜执行沟道离子注入，在所述位于所第一介质岛的两侧的第一掺杂类型沟道；去除所述图案化的掩膜层。
所述沟道离子注入的离子为磷离子，注入能量范围为50Kev～200Kev，注入剂量范围为5.0E12/cm 2～5.0E13/cm 2。
在形成耗尽型器件的沟道的过程中，将第一介质岛作为掩膜执行离子注 入，阻止了离子进入第一介质岛下方的区域，使得第一介质岛下方的第一掺杂类型外延层的沟道离子浓度降到最低的沟道离子浓度降到最低，使得耗尽型器件的击穿耐压更高，击穿可靠性大大提高。
示例性的，在形成介质岛之后，在所述第一区第一掺杂类型外延层中形成位于所述第一介质岛的两侧的第一掺杂类型沟道之前，还包括执行阈值电压(Vt)调整注入的步骤，用以调整器件的阈值电压，所述Vt调整注入的步骤以所述介质岛为掩膜进行。示例性的，所述Vt调整注入的离子为磷离子，注入的能量范围为100Kev～200Kev，注入剂量范围为1.0E12/cm 2～1.0E13/cm 2。示例性的，在执行所述Vt调整注入步骤之后还包括进行第二次退火的步骤，温度范围为1100℃～1200℃，所述的第二次退火的时间范围为60min～180min。
接着，执行步骤S5：在所述第一掺杂类型外延层上形成分别覆盖所述第一介质岛、所述第三介质岛的栅极结构，且所述栅极结构露出所述第二介质岛和分别位于所述第一区、所述第二区中的所述拟形成第一掺杂类型源区的区域。
示例性的，所述栅极结构包括从下到上依次层叠的栅介电层和栅极材料层。
参看图1E，首先在第一掺杂类型外延层101上形成栅极结构106，所述栅极结构106包括形成在所述第一区1上的栅极结构1061和形成在所述第二区2上的栅极结构1062。所述栅极结构106包括栅介电层107和栅极材料层108，所栅极结构106中位于所述第一区1上的栅极结构1061覆盖位于所述第一区1中的所述第一介质岛1041，并且露出第二介质岛1042和位于所述第一区1中的第二掺杂深阱1031中拟形成第一掺杂类型源区的区域；所栅极结构106中位于所述第一区1上的栅极结构1062覆盖位于所述第二区2中的所述第一介质岛1041，并且露出第二介质岛1042、位于所述第二区2的第二掺杂类型深阱1032中拟形成第一掺杂类型源区的区域。示例性的，所述栅极 结构106还覆盖第三介质岛1043。
对于增强型器件，根据公式C ox＝ε ox/t ox，可知由于第一介质岛的存在，使得栅介电层的厚度增加，起到降低栅极电容，减少器件的开关损耗的作用。
示例性的，所述栅介电层为二氧化硅材料，所述栅极材料层为多晶硅材料。形成栅极结构的方法可以是本领域技术人员所熟知的任何方法，例如包括沉积、光刻、刻蚀等工艺步骤，在此不再赘述。示例性的，所述的栅介电层的厚度范围为
Figure PCTCN2018116633-appb-000002
所述的栅极材料层的厚度范围为
Figure PCTCN2018116633-appb-000003
Figure PCTCN2018116633-appb-000004
在本实施例中，在形成栅极结构的同时，在所述第三区中，所述栅极结构还覆盖第三介质岛。如图1E所示，栅极结构106还覆盖第三介质岛1043。
接着，执行步骤S6：以所述栅极结构和所述第二介质岛为掩膜执行第一掺杂类型源区离子注入，分别在所述第一区和所述第二区中形成第一掺杂类型源区。
继续参看图1E，以所述栅极结构106和所述介质岛104为掩膜执行第一掺杂类型源区离子注入，在所述第一区1的第二掺杂类型深阱1031和第二区2的第二掺杂类型深阱1032中形成位于栅极结构两侧的第一掺杂类型源区110，其中位于所述第一区1的第二掺杂类型深阱1031中的所第一掺杂类型源区110与所述第一掺杂类型沟道105接触，位于同一第二掺杂类型深阱中的所述第一掺杂类型源区110被位于第二介质岛1042下方的第二掺杂类型深阱区域110a隔开。
形成所述第一掺杂类型源区的方法，采用以所述栅极结构和所述第二介质岛为掩膜，执行离子注入。由于第二介质岛形成在第一区的第二掺杂类型深阱和第二区的第二掺杂类型深阱中，从而在形成第一掺杂类型源区的过程中可以以第二介质岛作为掩膜，自对准形成第一掺杂类型源区，第一掺杂类型源区位于第二介质岛的两侧，即第一被第二掺杂类型深阱区域110a隔开，在工艺过程中节省了一次光刻版，使得工艺成本下降。在本实施例中，形成 所述第一掺杂类型源区110的离子注入步骤采用磷离子注入步骤，注入的能量范围为50Kev～150Kev，注入剂量范围为5.0E15/cm 2～1.0E16/cm 2。
示例性的，在形成第一掺杂类型源区之后，形成位于第一掺杂类型源区下方的第二掺杂类型阱区。在第一掺杂类型源区的下方形成第二掺杂类型阱区可以显著的减小寄生晶体管基区的电阻，大幅降低了寄生晶体管开启的风险，使得器件的工作稳定性显著提升。继续参看图1E，在第一掺杂类型源区110下方形成有第二掺杂类型阱区109。形成所述第二掺杂类型阱区的方法采用在所述栅极结构和所述第二介质岛作为掩膜的情况下进行离子注入。在本实施例中，形成所述第二掺杂类型阱区109的离子注入步骤为硼离子注入步骤，注入的能量范围为150Kev～300Kev，其注入剂量范围为1.0E15/cm 2～5.0E15/cm 2。
示例性的，在形成所述第一掺杂类型源区之后，还包括形成源极的步骤。示例性的，所述形成源极的步骤包括：在所述第一掺杂类型外延层上形成介质层，所述介质层覆盖所述栅极结构和所述第一掺杂类型源区并露出所述第二介质岛；去除所述第二介质岛；去除部分所述介质层以露出部分所述第一掺杂类型源区；在所述第一掺杂类型外延层上形成源极，所述源极包括与所述第一区的第二掺杂类型深阱接触的第一区源极和与所述第二区的第二掺杂类型深阱接触的第二区源极，所述第一区源极与第二区源极不接触。
示例性的，在形成源极之前还包括形成第二掺杂类型阱区和第二掺杂类型源区的步骤。下面参看图1F和图1G对形成第二掺杂类型源极之后形成源极的过程进行描述。
首先，参看图1F，在第一掺杂类型外延层101上形成覆盖所述栅极结构(包括栅介电层107和栅极材料层108)和所述第一掺杂类型源区110的介质层，所述介质层露出所述第二介质岛1042。所述介质层可以是二氧化硅、氮化硅等介电材料层。形成所述介质层的方法包括沉积、光刻、刻蚀等步骤，为本领域技术人员所熟知的步骤，在此不再赘述。
接着，继续参看图1F，去除所述第二介质岛1042和部分所述介质层， 从而露出部分所述第一区第二掺杂类型深阱1031和第二区第二掺杂类型深阱1032的中所述第一掺杂类型源区110以及位于所述第一掺杂类型源区110之间的区域。去除第二介质岛和部分介质层的方法可以采用刻蚀等本领域技术人员所熟知的方法，在此不再赘述。
接着，继续参看图1F，形成位于所述第一区第二掺杂类型深阱1031和第二区第二掺杂类型深阱1032的中所述第一掺杂类型源区110之间的第二掺杂类型源区112，所述第二掺杂类型源区112连接所第一掺杂类型源区。
所述形成第二掺杂类型源区的离子注入步骤，以剩余的介质层111为掩膜。本实施例中，在部分去除介质层之后、形成源极之前形成第二掺杂类型源区，其中，形成第二掺杂类型源区的离子注入较形成第一掺杂类型源区的离子注入的剂量低，从而在形成第二掺杂类型源区的过程中，暴露的第一掺杂类型源区并不会反型，从而单独形成第二掺杂类型园区离子注入掩膜的步骤，减少工艺流程，减少工艺成本。所述第二掺杂类型源区用以增强所述源极与所述深阱之间的接触。
在这一过程中，因为在形成第二掺杂类型源区之前部分去除介质层形成了暴露第一掺杂类型源区的开口，从而在形成第二掺杂类型源区之后不需要进一步去除介质层，而可以直接形成与第一掺杂类型源区和第二掺杂类型源区接触的源极。从而进一步减少了工艺的步骤，节省了工艺成本。
本实施例中，所述形成第二掺杂类型源区的离子注入步骤采用硼离子或二氟化硼离子注入步骤，注入的能量范围为50Kev～200Kev，注入剂量范围为5.0E14/cm 2～5.0E15/cm 2。
需要理解的是，这里将第二掺杂类型源区形成在部分去除介质层之后、形成源极之前，仅仅是示例性的，任何形成第二掺杂类型源区的步骤均适用于本申请。
接着，继续参看图1F，执行离子注入步骤，形成位于所述第二掺杂类型源区112下方的另一第二掺杂类型阱区，所述另一第二掺杂类型阱区将所述位于第一掺杂类型源区110下方的第二掺杂类型阱区109连接，从而形成位 于第一掺杂类型源区110和第二掺杂类型源区112下方的完整的第二掺杂类型阱区1091。所述形成另一第二掺杂类型阱区的离子注入步骤，以剩余的介质层111为掩膜，采用硼离子注入工艺，注入的能量范围为150Kev～300Kev，注入剂量范围为1.0E15/cm 2～1.0E16/cm 2。示例性的，完成另一第二掺杂类型阱区的离子注入步骤之后进行退火。所述退火的温度范围为800℃～1000℃，所述退火的时间范围为30min～90min。形成在第一掺杂类型源区110和第二掺杂类型源区112下方的第二掺杂类型阱区1091，可以显著的减小寄生晶体管基区的电阻，大幅降低了寄生晶体管开启的风险，使得器件的工作稳定性显著提升。
最后，参看图1G，形成源极113，所述源极113包括第一区源极1131和第二区源极1132，第一区源极1131与所述第一区1中的所述第一掺杂类型源区110和第二掺杂类型源区112接触，和第二区源极1132与所述第二区2中的与所述第一掺杂类型源区110和第二掺杂类型源区112接触，所述第一区源极1131与第二区源极1132不接触。所述源极采用常规的铝、铜的一种或几种的合金。
形成所述源极113的步骤包括：沉积源极材料层，并图案化源极材料层以形成所述源极。所述刻蚀介质层、沉积源极材料层、图案化源极材料层的步骤为本领域技术人员所熟知的工艺，在此不再赘述。
在形成源极之后，还包括形成漏极的步骤。示例性的，所述形成漏极的步骤包括：首先，对所述第一掺杂类型的半导体衬底的背面进行减薄；接着，在所述第一掺杂类型的半导体衬底的背面沉积形成漏极。所述漏极采用常规的铝、铜的一种或几种的合金。如图1G所示，在第一掺杂类型的半导体衬底100的背面形成漏极114。
至此，完成对本申请的半导体器件的制造方法进行了示例性的介绍，根据本申请的半导体器件的制造方法和半导体器件，在集成有增强型器件和耗尽型器件的半导体器件的制造过程中形成位于外延上的介质岛和位于外延层中的沟槽。在耗尽型器件形成沟道的过程中，由于介质岛的存在阻挡了沟道 离子的注入，介质岛下方的离子浓度低，使得器件在开态下的击穿可靠性大大提高；同时，由于介质岛的存在，使得栅介电层的厚度增加，降低了栅极电容，减小器件的开关损耗。设置位于外延层中的沟槽作为增强型器件和耗尽型器件的隔离结构，一方面提升了增强型与耗尽型器件之间的隔离特性，另一方面减少了隔离结构占据的芯片面积。另外，在制造过程中以介质岛作为掩膜，可以自对准形成第一掺杂类型源区，节省了一块光刻板和光刻工艺形成离子注入掩膜的工艺步骤，降低了工艺成本。
需要理解的是，本实施例中采用在第一掺杂类型的源区之间形成第二掺杂类型的源区，形成源极和漏极的步骤仅仅是示例性的，本领域技术人员可采用本领域熟知的工艺形成源极和漏极，而非意在将本申请限制于所描述的实施例范围内。本申请的保护范围由附属的权利要求书及其等效范围所界定。
同时，需要理解的是，本实施例以VDMOS器件为示例进行说明仅仅是示例性的，并非要限制本申请的范围，本领域技术人员根据需要，可以形成IGBT器件等。
示例性的，根据本申请的半导体器件还可以设置为IGBT器件，其中将上述VDMOS器件的半导体衬底设置为第二掺杂类型，如半导体衬底为P+型衬底，其他部件位置和掺杂类型不变，则在第一区中形成耗尽型IGBT器件，在第二区中形成增强型IGBT器件。进一步，示例性的，将所述IGBT器件与快恢复二极管并联使用，提升器件的均流效果，和系统工作的稳定性和可靠性。
实施例二
本申请还提供了一种集成半导体器件，所述集成半导体器件包括根据实施例一所述的方法制备的集成半导体器件。
下面参看图1G，对本申请的半导体器件的结构进行示例性描述。所述集成半导体器件包括：半导体衬底100，半导体衬底100，具体地，可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等， 或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。示例性的，本实施例中的半导体衬底为第一掺杂类型。
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反。比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，则第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，则第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。示例性的，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，其掺杂浓度为1×10 14/cm 3～2×10 14/cm 3。
在所述第一掺杂类型的半导体衬底100的正面上形成有第一掺杂类型外延层101。在本实施例中，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，所述第一掺杂类型外延层为N型低掺杂的外延层，即N-外延层。示例性的，所述第一掺杂类型外延层101的厚度和电阻率会影响器件的耐压能力，第一掺杂类型外延层101的厚度越厚，电阻率越大，器件的耐压能力越高。在本实施例中，形成的VDMOS半导体器件耐压要求在650V时，所述第一掺杂类型外延层101的厚度为45μm～65μm，电阻率为15Ω·cm～25Ω·cm。
所述第一掺杂类型外延层101包括所述第一区1、第二区2和第三区3；所述第一区1形成有耗尽型器件，所述第二区2形成有增强型器件，所述第三区形成有沟槽102，所述沟槽被介质材料填充用以对所述耗尽型器件和增强型器件进行隔离。由所述沟槽102设置的隔离结构，对在所述沟槽两侧的耗尽型器件和增强型器件之间可能形成的电流通道进行阻隔，对耗尽型器件和增强型器件起到隔离效果。其中，所述沟槽的深度可以小于所述第一掺杂类型外延层的厚度，也可以等于或大于所述第一掺杂类型外延层的厚度，均能起到隔离的效果。所述沟槽的个数会影响隔离效果，沟槽的个数越多隔离效果越好。同时，本申请采用沟槽设置隔离结构，相较于采用深阱设置隔离 结构，有效减少了隔离结构的面积，从而节省了芯片面积。
示例性的，所述沟槽的深度大于或等于所述第一掺杂类型外延层的厚度，即所述沟槽穿透所述第一掺杂类型外延层。如图1所示，沟槽102穿透所述第一掺杂类型外延层101而延伸入所述半导体衬底100中，从而形成彻底阻隔位于所述外延层中、所述沟槽两侧的耗尽型器件和增强型器件之间可能形成的电流通道，从而显著提升耗尽型器件和增强型器件的隔离特性，同时，在这样的设置中，不需要进一步设置多个隔离沟槽就能达到最大的隔离效果，进一步减少了隔离结构的面积，节省芯片面积。
示例性的，填充所述沟槽的所述介质材料与所述介质岛的材料为同一种材料。进一步，示例性的，填充所述沟槽的介质材料与所述介质岛的材料均为热氧化硅层。从而在制造过程中减少工艺步骤。
继续参看图1G，本申请所述半导体器件还包括形成在所述第一掺杂类型外延层中的第二掺杂类型深阱103，其中第二掺杂类型深阱103包括位于所述第一区1中的至少两个第二掺杂类型深阱1031、位于所述第二区2中的至少两个第二掺杂类型深阱1032。在本实施例中，所述第一掺杂类型的半导体衬底为N型低掺杂的衬底，即N-衬底，所述第一掺杂类型外延层为N型低掺杂的外延层，即N-外延层，所述第二掺杂类型深阱为P阱。
继续参看图1G，本申请所述半导体器件还包括形成在所述第一掺杂类型外延层101上的多个介质岛104，所介质岛104包括第一介质岛1041和第三介质岛1043。
第一介质岛1041位于所述第一区1中的相邻两个第二掺杂类型深阱1031之间的区域的上方和位于所述第二区2中相邻两个第二掺杂类型深阱1032之间的区域的上方。其中，在所述第一区1中，所述介质岛1041与所述的相邻两个第二掺杂类型深阱1031不接触，在所述第二区2中所述介质岛1041与所述的相邻两个第二掺杂类型深阱1032不接触。
第一介质岛1041形成在所述第一区、所述第二区内的相邻两个第二掺杂类型深阱之间的区域的上方，从而在形成耗尽型器件的沟道的过程中，将其 作为掩膜执行离子注入，由于介质岛的存在阻挡了沟道离子的注入，介质岛下方的离子浓度低，使得器件在开态下的击穿可靠性大大提高。
第三介质岛1043覆盖被填充的沟槽，从而形成封闭的沟槽结构，形成位于增强型器件和耗尽型器件之间的完整的隔离结构，以对增强型器件和耗尽型器件进行有效的隔离。示例性的，所述介质岛和所述沟槽的填充材料为同种材料。示例性的，所述沟槽的宽度为0.5μm～2μm。所述介质岛和所述沟槽的填充材料为同种材料均为热氧化层。
继续参看图1G，本申请所述半导体器件还包括形成在第一区1和第二区2上的栅极结构106，所述栅极结构106包括形成在所述第一层1上的栅极结构1061和形成在所述第二区2上的栅极结构1062。所述包括栅介电层107和栅极材料层108；所述第一区1中的栅极结构1061部分覆盖第一区1中相邻的所述第二掺杂类型深阱1031，所述第二区2中的栅极结构1062部分覆盖第二区2中相邻的所述第二区第二掺杂类型深阱1032，所述栅极结构106下方覆盖有多个介质岛1041。栅极结构下方覆盖第一介质岛1041，根据公式C ox＝ε ox/t ox，可知由于第一介质岛的存在，使得栅介电层的厚度增加，起到降低栅极电容，减少器件的开关损耗的作用。本实施例中，如图1G所示，栅极结构106还覆盖所述第三介质岛1043。
所述栅极结构106以及栅极结构的材料可以是本领域技术人员所熟知的任何材料。示例性的，所述栅介电层为二氧化硅材料，所述栅极材料层为多晶硅材料。示例性的，所述的栅介电层的厚度范围为
Figure PCTCN2018116633-appb-000005
所述的栅极材料层的厚度范围为
Figure PCTCN2018116633-appb-000006
继续参看图1G，本申请所述半导体器件还包括形成在所述栅极结构106两侧的位于所述第二掺杂类型深阱103中的第一掺杂类型源区110，其中位于同一所述第二掺杂类型深阱103中的所述第一掺杂类型源区110被部分所述第二掺杂类型深阱103的区域隔开。
继续参看图1G，本申请所述半导体器件还包括位于所述第一区1中的所述介质岛104两侧的第一掺杂类型沟道105，所述第一掺杂类型沟道横向延 伸至临近的所述第一掺杂类型源区110外侧。
示例性的，如图1G中所示，所述半导体器件还包括形成分别设置在所述第一区1中的第二掺杂类型深阱1031和第二区2中的第二掺杂类型深阱1032中第二掺杂类型源区112，所第二掺杂类型源区112位于所述第一掺杂类型源区110之间，所述第二掺杂类型源区用以增强源极与深阱的接触。
示例性的，如图1G中所示，所述半导体器件还包括分别设置在所述第一区1中的第二掺杂类型深阱1031和所述第二区2中的第二掺杂类型深阱1032中的第二掺杂类型阱区1091，所述第二掺杂类型阱区1091位于所述第一掺杂类型源区110和所述第二掺杂类型源区112下方。形成在第一掺杂类型源区110和第二掺杂类型源区112下方的第二掺杂类型阱区1091，可以显著的减小寄生晶体管基区的电阻，大幅降低了寄生晶体管开启的风险，使得器件的工作稳定性显著提升。
示例性的，如图1G中所示，所述半导体器件包括还包括形成在所述第一掺杂类型外延层上的源极113，所述源极113包括第一区源极1131和第二区源极1132。所述第一区源极1131与所述第一区1中的第二掺杂类型深阱1021和位于所述第二掺杂类型深阱1121中的第一掺杂类型源区110接触，所述第二区源极1132与所述第二区2中的第二掺杂类型深阱1022和位于所述第二掺杂类型深阱1022中的第一掺杂类型源区110接触，其中，所述第一区源极1131与第二区源极1132不接触。从而形成独立的耗尽型半导体器件的源极和增强型半导体器件的源极。在本实施例中，在第一区1中的第二掺杂类型深阱1021和第二区2中的第二掺杂类型深阱1022中形成有第二掺杂类型源区112，所述第一区源极1131与所述第一区1中的第一掺杂类型源区110和第二掺杂类型源区112接触，所述第二区源极1132与所述第二区2中的第一掺杂类型源区110和第二掺杂类型源区112接触。
示例性的，如图1G中所示，所述半导体器件还包括形成在所述第一掺杂类型的半导体衬底100背面的漏极114。从而形成完整的集成有耗尽型VDMOS器件和增强型VDMOS器件的集成的VDMOS器件。需要理解的是， 本实施例以VDMOS器件为示例进行说明仅仅是示例性的，并非要限制本申请的范围，本领域技术人员根据需要，可以形成IGBT器件等。
示例性的，根据本申请的半导体器件设置IGBT器件，其中将上述VDMOS器件的半导体衬底设置为第二掺杂类型，即半导体衬底为P+型衬底，其他部件位置和掺杂类型不变，则在第一区中设置耗尽型IGBT器件，在第二区中形成增强型IGBT器件。进一步，示例性的，将所述IGBT器件与快恢复二极管并联使用，提升器件的均流效果，和系统工作的稳定性和可靠性。同时，为了扩大器件的应用领域和效率，可根据需要将多种半导体器件集成在一起，如在上述集成的半导体器件上再集成一个或多个二极管、三极管、电阻、电容、JFET、电流感应VDMOS、CMOS等半导体器件，并且在耗尽型半导体器件与其他类型半导体器件之间设有隔离结构，防止半导体器件之间的穿通。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件的制造方法，至少包括：
    提供半导体衬底，在所述半导体衬底的正面形成具有第一区、第二区和第三区的第一掺杂类型外延层，所述第三区位于所述第一区和所述第二区之间，在所述第三区中形成位于所述第一掺杂类型外延层中的至少一个沟槽；
    在所述第一区和所述第二区中分别形成至少两个第二掺杂类型深阱；
    填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛，所述介质岛包括第一介质岛、第二介质岛和第三介质岛，其中，所述第一介质岛部分覆盖所述第一区中的相邻两个所述第二掺杂类型深阱之间的区域，部分覆盖所述第二区内的相邻两个所述第二掺杂类型深阱之间的区域，并且所述第一介质岛与所述的相邻两个所述第二掺杂类型深阱均不接触，所述第二介质岛部分覆盖位于所述第一区中的所述第二掺杂类型深阱的部分区域，部分覆盖位于所述第二区中的所述第二掺杂类型深阱的部分区域，所述第一区内的所述第二介质岛两侧的第二掺杂类型深阱和所述第二区内的所述第二介质岛两侧的第二掺杂类型深阱为拟形成第一掺杂类型源区的区域，所述第三介质岛覆盖所述沟槽；
    在所述第一区中的所述第一介质岛的两侧的外延层上分别形成第一掺杂类型沟道，所述第一掺杂类型沟道延伸至所述第一区中拟形成第一掺杂类型源区的区域；
    在所述第一掺杂类型外延层上形成分别覆盖所述第一介质岛、所述第三介质岛的栅极结构，且所述栅极结构露出所述第二介质岛和分别位于所述第一区、所述第二区中的所述拟形成第一掺杂类型源区的区域；
    以所述栅极结构和所述第二介质岛为掩膜执行第一掺杂类型源区离子注入，分别在所述第一区和所述第二区中形成第一掺杂类型源区；
    其中，所述第一掺杂类型和所述第二掺杂类型相反。
  2. 如权利要求1所述的制造方法，其中，所述沟槽的深度等于或大于所 述第一掺杂类型外延层的厚度。
  3. 如权利要求1所述的制造方法，其中，所述介质岛的厚度范围为
    Figure PCTCN2018116633-appb-100001
  4. 如权利要求1所述的制造方法，其中，所述介质岛的长度范围为2μm～5μm。
  5. 如权利要求1所述的制造方法，其中，所述沟槽的宽度范围为0.5μm～2μm。
  6. 如权利要求1所述的制造方法，其中，所述填充所述沟槽、并形成位于所述第一掺杂类型外延层上的介质岛的步骤包括：
    形成覆盖所述第一掺杂类型外延层并填充所述沟槽的介质材料层；
    图案化所述介质材料层，以形成所述介质岛。
  7. 如权利要求1所述的制造方法，其中，还包括在所述形成第一掺杂类型源区的步骤之后形成源极的步骤：
    在所述第一掺杂类型外延层上形成介质层，所述介质层覆盖所述栅极结构和所述第一掺杂类型源区并露出所述第二介质岛；
    去除所述第二介质岛和去除部分所述介质层以形成开口，所述开口露出位于所述第二掺杂类型深阱中的部分所述第一掺杂类型源区和位于所述第二介质岛下方的区域；
    在所述第一掺杂类型外延层上形成所述源极，所述源极填充所述开口；
    其中，所述源极包括第一区源极和第二区源极，所述第一区源极与位于所述第一区的所述第二掺杂类型深阱和位于所述第二掺杂类型深阱中的所述第一掺杂类型源区接触，所述第二区源极与位于所述第二区的所述第二掺杂类型深阱和位于所述第二掺杂类型深中的所述第一掺杂类型源区接触，所述第一区源极与第二区源极不接触。
  8. 如权利要求7所述的制造方法，其中，在所述形成第一掺杂类型源区的步骤之后、所述形成源极的步骤之前，以剩余的所述介质层为掩膜执行第二掺杂类型源区离子注入，以在所述第一掺杂类型源区之间的区域形成第二 掺杂类型源区；其中，形成所述第二掺杂类型源区离子注入的剂量小于所述第一掺杂类型源区离子注入的剂量。
  9. 如权利要求8所述的制造方法，其中，在所述形成第二掺杂类型源区的步骤之后、所述形成源极的步骤之前，在所述第二掺杂类型源区下方形成另一第二掺杂类型阱区，所述另一第二掺杂类型阱区连接其两侧的所述第二掺杂类型阱区。
  10. 如权利要求1所述的制造方法，其中，所述第一掺杂类型外延层的厚度为45μm～65μm。
  11. 如权利要求1所述的制造方法，其中，所述第一掺杂类型外延层的电阻率为15Ω·cm～25Ω·cm。
  12. 如权利要求1所述的制造方法，其中，所述沟槽的为梯形，所述沟槽的侧壁的倾角的范围为45°～90°。
  13. 如权利要求1所述的制造方法，其中，在所述填充所述沟槽之前还包括：
    形成所述沟槽侧壁和底部的热氧化硅层。
  14. 如权利要求1所述的制造方法，其中，在形成所述介质岛之后，以及在形成所述第一掺杂类型沟道之前，还包括阈值电压调整注入的步骤，用以调整器件的阈值电压。
  15. 如权利要求1所述的制造方法，在形成所述源极之后，还包括在所述第一掺杂类型的半导体衬底的背面形成漏极。
  16. 如权利要求1所述的制造方法，其中，所述执行第一掺杂类型源区离子注入的步骤中，离子注入的能量范围为50Kev～150Kev，注入剂量范围为5.0E15/cm 2～1.0E16/cm 2。
  17. 如权利要求8所述的制造方法，其中，所述执行第二掺杂类型源区离子注入的步骤中，离子注入的能量范围为50Kev～200Kev，注入剂量范围为5.0E14/cm 2～5.0E15/cm 2。
  18. 如权利要求1所述的制造方法，其中，在所述第二掺杂类型阱区离 子注入之后，还包括执行第二掺杂类型阱区退火工艺的步骤，其中，所述第二掺杂类型阱区退火工艺的温度范围1100℃～1200℃，时间范围为60min～300min。
  19. 如权利要求1-18任一项所述的制造方法，其中，所述半导体衬底为第一掺杂类型的半导体衬底，所述半导体器件包括VDMOS器件，在第一区形成耗尽型VDMOS器件，在所述第二区中形成增强型VDMOS器件；或者所述半导体衬底为第二掺杂类型的半导体衬底，所述半导体器件包括IGBT器件，在所述第一区中形成耗尽型IGBT器件，在所述第二区中形成增强型IGBT器件。
  20. 一种集成半导体器件，所述集成半导体器件包括如权利要求1-19中任意一项所述的制造方法制造的半导体器件。
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