WO2019128554A1 - Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs intégré - Google Patents

Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs intégré Download PDF

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WO2019128554A1
WO2019128554A1 PCT/CN2018/116633 CN2018116633W WO2019128554A1 WO 2019128554 A1 WO2019128554 A1 WO 2019128554A1 CN 2018116633 W CN2018116633 W CN 2018116633W WO 2019128554 A1 WO2019128554 A1 WO 2019128554A1
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region
doping type
forming
source
dielectric
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PCT/CN2018/116633
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English (en)
Chinese (zh)
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程诗康
顾炎
张森
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无锡华润上华科技有限公司
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Priority to JP2020535534A priority Critical patent/JP7083026B2/ja
Priority to KR1020207019554A priority patent/KR102363129B1/ko
Priority to US16/768,563 priority patent/US11257720B2/en
Publication of WO2019128554A1 publication Critical patent/WO2019128554A1/fr

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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular to a method of fabricating a semiconductor device and an integrated semiconductor device.
  • VDMOS Vertical double-diffused metal oxide field effect devices
  • VDMOS include enhanced and depletion modes, which have the advantages of good off-characteristics and low power consumption, and are widely used in LED drivers and power adapters.
  • most of the existing different types of VDMOS devices are individually packaged, which brings disadvantages such as an increase in process cost and an excessive chip area.
  • a semiconductor device and a method of fabricating the same are provided in accordance with various embodiments of the present application.
  • a method of fabricating a semiconductor device comprising at least:
  • a semiconductor substrate forming a first doping type epitaxial layer having a first region, a second region, and a third region on a front surface of the semiconductor substrate, the third region being located in the first region and the first Between the two regions, at least one trench in the first doping type epitaxial layer is formed in the third region;
  • the dielectric island including a first dielectric island, a second dielectric island, and a third dielectric island, wherein the first medium An island portion covers a region between two adjacent second doping type deep wells in the first region, partially covering two adjacent second doping type deep wells in the second region a region between the first dielectric island and the adjacent two of the second doping type deep wells, the second dielectric island portion covering a portion located in the first region a partial region in the second doping type deep well partially covering a partial region of the second doping type deep well in the second region, the second dielectric island in the first region a second doping type deep well on the side and a second doping type deep well on both sides of the second dielectric island in the second region are regions in which a source region of the first doping type is to be formed, the third a dielectric island covering the trench;
  • first doping type channel Forming a first doping type channel on the epitaxial layers on both sides of the first dielectric island in the first region, the first doping type channel extending into the first region to be formed a region of the first doping type source region;
  • first doping type and the second doping type are opposite.
  • An integrated semiconductor device comprising a semiconductor device fabricated by the method as described above.
  • FIG. 1A-1G are schematic structural views of a semiconductor device formed in a method of fabricating a semiconductor device according to the present application.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present application.
  • the present application provides a method of fabricating a semiconductor device and an integrated semiconductor device.
  • the manufacturing method of the semiconductor device of the present application and the semiconductor device are exemplified by taking the manufacturing process of the VDMOS semiconductor device as an example. It should be understood that the description of the manufacturing process of the VDMOS semiconductor device in this embodiment is merely exemplary. Any method of fabricating a semiconductor device that integrates a depletion device and an enhancement device is suitable for use in the present application.
  • FIG. 1A-1G and FIG. 2 a method for fabricating a semiconductor device according to the present application is exemplarily described.
  • FIGS. 1A-1G are formed in a method of fabricating a semiconductor device according to an embodiment of the present application.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present application.
  • step S1 is performed: providing a semiconductor substrate, forming a first doping type epitaxial layer having a first region, a second region, and a third region on a front surface of the semiconductor substrate, the third region Located between the first region and the second region, a trench in the first doping type epitaxial layer is formed in the third region.
  • a semiconductor substrate 100 is provided, and specifically, may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/
  • the V compound semiconductor further includes a multilayer structure composed of these semiconductors, or the like, or is silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), and silicon-on-insulator (on-silicon). SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate is of a first doping type.
  • the first doping type and the second doping type generally refer to P-type or N-type, for example, the first doping type is P-type, low-doped P-type, and highly doped P+ type.
  • One of the second doping types is one of an N-type, a low-doped N-type, and a highly doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, highly doped N+ type
  • the second doping type is P-type, low-doped P-type, and highly doped P+ type one of them.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate having a doping concentration of 1 ⁇ 10 14 /cm 3 to 2 ⁇ 10 14 /cm. 3 .
  • a first doping type epitaxial layer is formed on a front surface of the first doping type semiconductor substrate.
  • a first doping type epitaxial layer 101 is formed on the first doping type semiconductor substrate 100, and the first doping type epitaxial layer 101 includes a first region 1, a second region 2, and a first Three zones 3, the third zone 3 being formed between the first zone 1 and the second zone 2.
  • the first region 1 is intended to form a depletion type semiconductor device
  • the second region 2 is intended to form an enhancement type semiconductor device
  • the depletion type semiconductor device and the enhancement type are to be formed in the third region
  • the isolation structure of the semiconductor device is intended to form a depletion type semiconductor device.
  • the method of forming the first doping type epitaxial layer 101 includes any method known to those skilled in the art such as ion doping vapor phase epitaxy.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer. Layer, the N- epitaxial layer.
  • the thickness and resistivity of the first doping type epitaxial layer 101 may affect the withstand voltage capability of the device. The thicker the first doping type epitaxial layer 101, the higher the resistivity, and the higher the withstand voltage capability of the device. In the present embodiment, when the VDMOS semiconductor device is formed to have a withstand voltage requirement of 650 V, the first doping type epitaxial layer 101 has a thickness of 45 ⁇ m to 65 ⁇ m and a specific resistance of 15 ⁇ cm to 25 ⁇ cm.
  • At least one trench 102 is formed in the third region 3 of the first doping type epitaxial layer 101. At least one trench 102 located in the third region 3 is disposed in the first doping type epitaxial layer 101, thereby forming an isolation structure disposed by the trench 102, on both sides of the trench.
  • the current path that may be formed between the depletion device and the enhancement device is blocked, and the depletion device and the enhancement device are isolated.
  • the depth of the trench may be smaller than the thickness of the epitaxial layer of the first doping type, or may be equal to or greater than the thickness of the epitaxial layer of the first doping type, and each of them can have an isolation effect.
  • the number of the grooves affects the isolation effect, and the more the number of grooves, the better the isolation effect.
  • the present application adopts a trench to provide an isolation structure, which effectively reduces the area of the isolation structure compared to the isolation structure provided by the deep well, thereby saving chip area.
  • the depth of the trench is greater than or equal to the thickness of the first doping type epitaxial layer, that is, the trench penetrates the first doping type epitaxial layer.
  • a trench 102 penetrates the first doping type epitaxial layer 101 and extends into the semiconductor substrate 100, thereby forming a complete barrier located in the epitaxial layer on both sides of the trench.
  • the steps of forming the isolation structure will be further described.
  • the method of forming the trench 102 includes first forming a patterned mask layer on the first doping type epitaxial layer, the patterned mask layer exposing a position where the trench is to be formed And etching the first doping type epitaxial layer with the patterned mask layer as a mask, and the trench is penetrated by the first doping type by means of end point detection, over etching, or the like Epitaxial layer; Finally, the patterned mask layer is removed. It is to be understood that the steps of forming the trenches are merely exemplary and any method of forming the trenches is suitable for use in the present application.
  • the groove has a width of 0.5 ⁇ m to 2 ⁇ m.
  • the width of the trench is set to 0.5 ⁇ m to 2 ⁇ m, so that the thermal oxidation process can be used to fill the trench while forming the dielectric island during the subsequent trench filling process, reducing the number of process steps while forming a dense filling material.
  • the depth of the trench is determined according to the thickness of the first doping type epitaxial layer.
  • the shape of the groove may be a rectangle, a square, a trapezoid, or an inverted trapezoid, which is not limited thereto.
  • the bottom of the groove may be a circular arc shape, a conical shape or the like.
  • the groove is trapezoidal, and the inclination of the sidewall of the groove may range from 45° to 90°. It should be understood that the dimensions, topography, angles and the like of the trenches given in this embodiment are merely exemplary, and any trenches located in the first epitaxial layer are suitable for the present application.
  • step S2 is performed to form at least two second doping type deep wells in the first region and the second region, respectively.
  • FIG. 1B a schematic structural view of a semiconductor device in which at least two second doping type deep wells are respectively formed in the first region and the second region is illustrated.
  • a method of forming the second doping type deep well includes: forming a patterned mask layer on the first doping type epitaxial layer, the patterned mask layer exposing the pseudo-forming second doping A region of a deep well type; performing a second doping type well region ion implantation, forming a second doping type deep well on the first doping type epitaxial layer; removing the patterned mask layer.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • the second doping type deep well is a P well
  • the ions doped by the second doping type well region are boron ions
  • the injected energy ranges from 50 KeV to 200 Kev
  • the implantation dose range It is 5.0E13/cm 2 to 5.0E14/cm 2 .
  • a step of performing a second doping type deep well annealing is further included.
  • the first annealing has a temperature ranging from 1100 ° C to 1200 ° C and a time ranging from 60 min to 300 min.
  • step S3 is performed: filling the trench and forming a dielectric island on the first doping type epitaxial layer, the dielectric island including a first dielectric island, a second dielectric island, and a a three-medium island, wherein the first dielectric island portion covers an area between two adjacent second doping type deep wells in the first region, partially covering an adjacent portion in the second region a region between two of the second doping type deep wells, and the first dielectric island is not in contact with the two adjacent second doping type deep wells, the second dielectric island Partially covering a partial region of the second doping type deep well in the first region, partially covering a partial region of the second doping type deep well in the second region, the first a second doping type deep well on both sides of the second dielectric island in the region and a second doping type deep well on both sides of the second dielectric island in the second region are intended to form a first doping An area of the type source region, the third dielectric island covering the trench.
  • FIG. 1C a schematic structural view of a semiconductor device after filling the trench and forming a dielectric island on the first doped epitaxial layer is illustrated.
  • the trench 102 is filled, and a plurality of dielectric islands 104 are formed on the first doping type epitaxial layer 101.
  • the dielectric island 104 includes a first dielectric island 1041, a second dielectric island 1042, and a third dielectric island 1043.
  • the first dielectric island 1041 is located above a region between adjacent two second doping type deep wells 1031 in the first region 1 and adjacent two adjacent second portions in the second region 2 Above the region between the doping type deep wells 1032, and in the first region 1, the first dielectric islands 1041 are not in contact with the adjacent two second doping type deep wells 1031, The first dielectric island 1041 in the second region 2 is not in contact with the adjacent two second doping type deep wells 1032; the second dielectric island 1042 is located in the second region 1 in the first region 1 On the hetero-type deep well 1031 and the second doping type deep well 1032 in the second region 2, the second doping type deep well includes a region 110a covered by the second dielectric island, and the region 110a is located to be formed Between the first doping type source regions, that is, the second doping type deep well region on both sides of the second doping type deep well region 110a is a region where the first doping type source region is to be formed; the third medium Island 1043 covers the filled trenches
  • the step of filling the trench and forming a dielectric island on the first doping type epitaxial layer comprises: performing a deposition process, forming an epitaxial layer covering the first doping type and filling the trench a dielectric material layer of the trench; the dielectric material layer is patterned to form the dielectric island.
  • the filling of the trench can be placed in the same step as the formation of the dielectric island, which reduces the process flow and reduces the number of processes. Process cost.
  • a thermal oxidation process is performed to form a silicon oxide layer covering the sidewalls and bottom of the trench.
  • the dielectric material layer is one or a combination of an oxide layer, polysilicon, TEOS, and BPSG.
  • the width of the trench ranges from 0.5 ⁇ m to 2 ⁇ m
  • the step of filling the trench and forming the dielectric island on the first doped type epitaxial layer comprises: performing a thermal oxidation process to form a cover The first doping type epitaxial layer surface and an oxide layer filling the trench; the oxide layer is patterned to form the dielectric island.
  • the thickness of the dielectric island 104 ranges from The length of the dielectric island 103 ranges from 2 ⁇ m to 5 ⁇ m.
  • the thermal oxidation process is employed to simultaneously perform the covering process of the bottom and sidewalls of the trench, the filling process of the trench, and the step of forming the dielectric island, in order to reduce the coverage of the dielectric material layer and the filling trench in the trench.
  • steps of filling the trench and forming the dielectric island using the thermal oxidation process in the present embodiment are merely exemplary. Any method of filling trenches and forming dielectric islands is suitable for use in the present application.
  • the first doping type source region may be self-aligned with the second dielectric island as a mask, and the first doping type source region is deepened by the second doping type
  • the well regions 110a are spaced apart.
  • the third dielectric island covers the filled trench to form a closed trench structure, forming a complete isolation structure between the enhancement device and the depletion device for efficient implementation of the enhancement device and the depletion device isolation.
  • step S4 is performed: forming a first doping type channel on the epitaxial layers on both sides of the first dielectric island in the first region, the first doping type The channel extends to a region of the first region where the first doping type source region is to be formed.
  • a first doping type channel 105 which is located on both sides of the first dielectric island 1041, is formed in the first region 1 of the first doping type epitaxial layer 101, and the first doping type channel 105 is formed. Extending to a region of the second doping type deep well 1031 in the first region 1 where a source region is to be formed.
  • the step of forming a first doping type channel on both sides of the first dielectric island in the first region of the first doping type epitaxial layer comprises: first, in the first doping type epitaxy Forming a patterned mask layer on the layer, the patterned mask layer exposing a region on the two sides of the first dielectric island where the first doping type channel is to be formed; and the patterned mask layer Performing channel ion implantation with the first dielectric island as a mask, the first doping type channel on both sides of the first dielectric island; removing the patterned mask layer.
  • the ions ion-implanted into the channel are phosphorus ions, and the implantation energy ranges from 50 KeV to 200 KeV, and the implantation dose ranges from 5.0 E12/cm 2 to 5.0 E13/cm 2 .
  • ion implantation is performed using the first dielectric island as a mask, preventing ions from entering the region under the first dielectric island, so that the first doping type epitaxy under the first dielectric island.
  • the channel ion concentration of the layer whose channel ion concentration is minimized is minimized, so that the breakdown voltage of the depletion device is higher and the breakdown reliability is greatly improved.
  • the Vt adjusts the implanted ions to be phosphorus ions
  • the injected energy ranges from 100 KeV to 200 KeV
  • the implant dose ranges from 1.0 E12/cm 2 to 1.0 E13/cm 2 .
  • the step of performing a second annealing is performed, the temperature ranges from 1100 ° C to 1200 ° C, and the second annealing time ranges from 60 min to 180 min.
  • step S5 is performed to form a gate structure covering the first dielectric island and the third dielectric island on the first doping type epitaxial layer, and the gate structure exposes the second medium An island and an area in the first region and the second region, respectively, where the first doping type source region is to be formed.
  • the gate structure includes a gate dielectric layer and a gate material layer stacked in this order from bottom to top.
  • a gate structure 106 is first formed on a first doping type epitaxial layer 101, the gate structure 106 including a gate structure 1061 formed on the first region 1 and formed in the second region Gate structure 1062 on 2.
  • the gate structure 106 includes a gate dielectric layer 107 and a gate material layer 108, and the gate structure 1061 of the gate structure 106 on the first region 1 covers the portion located in the first region 1 a first dielectric island 1041, and exposing the second dielectric island 1042 and a region of the second doped deep well 1031 located in the first region 1 to form a first doping type source region;
  • the gate structure 1062 on the first region 1 covers the first dielectric island 1041 located in the second region 2, and exposes the second dielectric island 1042, and the second doping in the second region 2 A region of the type deep well 1032 where the source region of the first doping type is to be formed.
  • the gate structure 106 also covers the third dielectric island 1043.
  • the gate dielectric layer is a silicon dioxide material
  • the gate material layer is a polysilicon material.
  • the method of forming the gate structure may be any method well known to those skilled in the art, for example, process steps including deposition, photolithography, etching, etc., and will not be described herein.
  • the thickness of the gate dielectric layer ranges from The thickness of the gate material layer ranges from
  • the gate structure further covers the third dielectric island in the third region while forming the gate structure.
  • the gate structure 106 also covers the third dielectric island 1043.
  • step S6 performing first doping type source region ion implantation using the gate structure and the second dielectric island as a mask, respectively forming a first in the first region and the second region Doping type source region.
  • a first doping type source region ion implantation is performed using the gate structure 106 and the dielectric island 104 as a mask, and a second doping type deep well 1031 and a first doping region in the first region 1
  • a first doping type source region 110 on both sides of the gate structure is formed in the second doping type deep well 1032 of the second region 2, wherein the second doping type deep well 1031 of the first region 1 is located
  • the first doping type source region 110 is in contact with the first doping type channel 105, and the first doping type source region 110 located in the same second doping type deep well is located under the second dielectric island 1042
  • the second doping type deep well regions 110a are spaced apart.
  • a method of forming the first doping type source region is performed by using the gate structure and the second dielectric island as a mask to perform ion implantation. Since the second dielectric island is formed in the second doping type deep well of the first region and the second doping type deep well of the second region, the second medium may be used in forming the first doping type source region The island acts as a mask to form a first doping type source region, and the first doping type source region is located on both sides of the second dielectric island, that is, the first doped type is separated by the second doping type deep well region 110a. A lithographic plate is saved during the process, which reduces the process cost.
  • the ion implantation step of forming the first doping type source region 110 uses a phosphorus ion implantation step, the injected energy range is 50Kev to 150Kev, and the implantation dose ranges from 5.0E15/cm 2 to 1.0E16/cm. 2 .
  • a second doping type well region under the first doping type source region is formed. Forming the second doping type well region under the first doping type source region can significantly reduce the resistance of the parasitic transistor base region, greatly reducing the risk of parasitic transistor turn-on, and significantly improving the operational stability of the device.
  • a second doping type well region 109 is formed under the first doping type source region 110.
  • the method of forming the second doping type well region employs ion implantation with the gate structure and the second dielectric island as a mask.
  • the ion implantation step of forming the second doping type well region 109 is a boron ion implantation step, and the injected energy ranges from 150Kev to 300Kev, and the implantation dose ranges from 1.0E15/cm 2 to 5.0E15/ Cm 2 .
  • the step of forming a source includes: forming a dielectric layer on the first doping type epitaxial layer, the dielectric layer covering the gate structure and the first doping type source region and exposing Removing the second dielectric island; removing a portion of the dielectric layer to expose a portion of the first doping type source region; forming a source on the first doping type epitaxial layer
  • the source includes a first region source in contact with the second doping type deep well of the first region and a second region source in contact with the second doping type deep well of the second region, The source of the first region is not in contact with the source of the second region.
  • the step of forming the second doping type well region and the second doping type source region is further included before forming the source.
  • a process of forming a source after forming a second doping type source will be described below with reference to FIGS. 1F and 1G.
  • a dielectric covering the gate structure (including the gate dielectric layer 107 and the gate material layer 108) and the first doping type source region 110 is formed on the first doping type epitaxial layer 101.
  • the dielectric layer may be a dielectric material layer such as silicon dioxide or silicon nitride.
  • the method of forming the dielectric layer includes steps of deposition, photolithography, etching, etc., which are well known to those skilled in the art, and will not be described herein.
  • the second dielectric island 1042 and a portion of the dielectric layer are removed, thereby exposing a portion of the first region second doping type deep well 1031 and the second region second doping type deep well 1032.
  • the method of removing the second dielectric island and a portion of the dielectric layer may employ a method well known to those skilled in the art, such as etching, and will not be described herein.
  • a first electrode between the first doping type source region 110 and the second doping type deep well 1032 of the first region is formed.
  • the second doping type source region 112 is connected to the first doping type source region.
  • the ion implantation step of forming the second doping type source region uses the remaining dielectric layer 111 as a mask.
  • a second doping type source region is formed after the dielectric layer is partially removed, and a source region is formed, wherein the ion implantation forming the second doping type source region is more than the ion implantation forming the first doping type source region.
  • the dose is low, so that in the process of forming the second doping type source region, the exposed first doping type source region is not inverted, thereby separately forming the second doping type park ion implantation mask step, reducing Process flow to reduce process costs.
  • the second doping type source region is for enhancing contact between the source and the deep well.
  • the ion implantation step of forming the source region of the second doping type adopts a boron ion or boron difluoride ion implantation step, and the injected energy ranges from 50Kev to 200Kev, and the implantation dose ranges from 5.0E14/cm 2 to 5.0E15/cm 2 .
  • the formation of the second doping type source region here after the partial removal of the dielectric layer and before the formation of the source is merely exemplary, and any step of forming the source region of the second doping type is suitable for the present application.
  • an ion implantation step is performed to form another second doping type well region under the second doping type source region 112, and the other second doping type well region will be
  • the second doping type well regions 109 under the first doping type source region 110 are connected to form a complete second doping type under the first doping type source region 110 and the second doping type source region 112.
  • the ion implantation step of forming another second doping type well region, using the remaining dielectric layer 111 as a mask, using a boron ion implantation process the injected energy range is 150Kev to 300Kev, and the implantation dose range is 1.0E15/cm. 2 to 1.0E16/cm 2 .
  • annealing is performed after the ion implantation step of another second doping type well region is completed.
  • the annealing temperature ranges from 800 ° C to 1000 ° C, and the annealing time ranges from 30 min to 90 min.
  • the second doping type well region 1091 formed under the first doping type source region 110 and the second doping type source region 112 can significantly reduce the resistance of the parasitic transistor base region and greatly reduce the risk of parasitic transistor turn-on. This makes the device's working stability significantly improved.
  • the source 113 includes a first region source 1131 and a second region source 1132.
  • the first region source 1131 and the first of the first region 1 The doping type source region 110 is in contact with the second doping type source region 112, and the second region source 1132 and the second region 2 are in the first doping type source region 110 and the second doping type
  • the source region 112 is in contact, and the first region source 1131 is not in contact with the second region source 1132.
  • the source is a conventional alloy of one or more of aluminum and copper.
  • the step of forming the source 113 includes depositing a source material layer and patterning the source material layer to form the source.
  • the steps of etching the dielectric layer, depositing the source material layer, and patterning the source material layer are processes well known to those skilled in the art, and are not described herein again.
  • a step of forming a drain is also included.
  • the step of forming a drain includes: first, thinning a back surface of the first doping type semiconductor substrate; then depositing on a back side of the first doping type semiconductor substrate A drain is formed.
  • the drain is made of a conventional alloy of one or more of aluminum and copper.
  • a drain electrode 114 is formed on the back surface of the first doping type semiconductor substrate 100.
  • the manufacturing method of the semiconductor device of the present application has been exemplarily described, and the manufacturing method of the semiconductor device and the semiconductor device according to the present application are formed in the manufacturing process of the semiconductor device in which the enhancement device and the depletion device are integrated.
  • the ion concentration under the dielectric island is low, so that the breakdown reliability of the device in the on state is greatly improved;
  • the presence of the dielectric island increases the thickness of the gate dielectric layer, reduces the gate capacitance, and reduces the switching loss of the device.
  • the arrangement of the trenches in the epitaxial layer as an isolation structure for the enhancement device and the depletion mode device improves the isolation characteristics between the enhancement and depletion devices on the one hand, and reduces the chip area occupied by the isolation structure on the other hand.
  • the dielectric island is used as a mask, and the first doping type source region can be self-aligned, which saves a process step of forming a ion implantation mask by a lithography plate and a photolithography process, and reduces the process cost.
  • a source region of a second doping type is formed between the source regions of the first doping type, and the steps of forming the source and the drain are merely exemplary, and those skilled in the art may
  • the source and drain are formed using processes well known in the art and are not intended to limit the application to the scope of the described embodiments. The scope of protection of the application is defined by the appended claims and their equivalents.
  • VDMOS device in this embodiment is merely exemplary, and is not intended to limit the scope of the application. Those skilled in the art may form an IGBT device or the like as needed.
  • the semiconductor device according to the present application may also be provided as an IGBT device in which the semiconductor substrate of the above VDMOS device is set to a second doping type, such as a semiconductor substrate being a P+ type substrate, other component positions and doping The type is unchanged, a depletion IGBT device is formed in the first region, and an enhancement IGBT device is formed in the second region.
  • the IGBT device is used in parallel with a fast recovery diode to improve the current sharing effect of the device and the stability and reliability of the system operation.
  • the present application also provides an integrated semiconductor device comprising the integrated semiconductor device fabricated according to the method of embodiment 1.
  • the integrated semiconductor device includes: a semiconductor substrate 100, a semiconductor substrate 100, and in particular, may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, including multilayer structures composed of these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), insulators Upper silicon germanium (SiGeOI) and germanium on insulator (GeOI).
  • the semiconductor substrate in this embodiment is of a first doping type.
  • the first doping type and the second doping type generally refer to a P-type or an N-type, wherein the first doping type and the second doping type are opposite.
  • the first doping type is one of P type, low doped P-type, and highly doped P+ type
  • the second doping type is N type, low doped N-type, and highly doped N+ type.
  • the first doping type is one of N-type, low-doped N-type, and highly doped N+ type
  • the second doping type is P-type, low-doped P-type, and highly doped P+
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate having a doping concentration of 1 ⁇ 10 14 /cm 3 to 2 ⁇ 10 14 /cm. 3 .
  • a first doping type epitaxial layer 101 is formed on a front surface of the first doping type semiconductor substrate 100.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • Layer the N- epitaxial layer.
  • the thickness and resistivity of the first doping type epitaxial layer 101 may affect the withstand voltage capability of the device. The thicker the first doping type epitaxial layer 101, the greater the resistivity, and the withstand voltage capability of the device. The higher.
  • the first doping type epitaxial layer 101 has a thickness of 45 ⁇ m to 65 ⁇ m and a specific resistance of 15 ⁇ cm to 25 ⁇ cm.
  • the first doping type epitaxial layer 101 includes the first region 1, the second region 2, and the third region 3; the first region 1 is formed with a depletion type device, and the second region 2 is formed with an enhancement In the type of device, the third region is formed with a trench 102 that is filled with a dielectric material to isolate the depletion mode device and the enhancement device.
  • the isolation structure provided by the trench 102 blocks a current path that may be formed between the depletion device and the enhancement device on both sides of the trench, and isolates the depletion device and the enhancement device. effect.
  • the depth of the trench may be smaller than the thickness of the epitaxial layer of the first doping type, or may be equal to or greater than the thickness of the epitaxial layer of the first doping type, and each of them can have an isolation effect.
  • the number of the grooves affects the isolation effect, and the more the number of grooves, the better the isolation effect.
  • the present application adopts a trench to provide an isolation structure, which effectively reduces the area of the isolation structure and saves the chip area compared to the isolation structure provided by the deep well.
  • the depth of the trench is greater than or equal to the thickness of the first doping type epitaxial layer, that is, the trench penetrates the first doping type epitaxial layer.
  • a trench 102 penetrates the first doping type epitaxial layer 101 and extends into the semiconductor substrate 100, thereby forming a complete barrier located in the epitaxial layer on both sides of the trench.
  • the dielectric material filling the trench is of the same material as the material of the dielectric island. Further, by way of example, the dielectric material filling the trench and the material of the dielectric island are both thermal silicon oxide layers. Thereby reducing the process steps in the manufacturing process.
  • the semiconductor device of the present application further includes a second doping type deep well 103 formed in the first doping type epitaxial layer, wherein the second doping type deep well 103 includes the first At least two second doping type deep wells 1031 in zone 1 are located in at least two second doping type deep wells 1032 in the second zone 2.
  • the first doping type semiconductor substrate is an N-type low doped substrate, that is, an N-substrate
  • the first doping type epitaxial layer is an N-type low doped epitaxial layer.
  • the layer, that is, the N- epitaxial layer, the second doping type deep well is a P well.
  • the semiconductor device of the present application further includes a plurality of dielectric islands 104 formed on the first doping type epitaxial layer 101, the dielectric islands 104 including a first dielectric island 1041 and a third dielectric island 1043.
  • a first dielectric island 1041 is located above a region between adjacent two second doping type deep wells 1031 in the first region 1 and adjacent two second doping types in the second region 2 Above the area between the deep wells 1032. Wherein, in the first region 1, the dielectric island 1041 is not in contact with the adjacent two second doping type deep wells 1031, and the dielectric island 1041 and the second region 2 are The adjacent two second doping type deep wells 1032 are not in contact.
  • the first dielectric island 1041 is formed over a region between the adjacent two second doping type deep wells in the first region and the second region, thereby forming a channel of the depletion device In this case, ion implantation is performed as a mask. Since the presence of the dielectric island blocks the implantation of the channel ions, the ion concentration under the dielectric island is low, so that the breakdown reliability of the device in the on state is greatly improved.
  • the third dielectric island 1043 covers the filled trench to form a closed trench structure, forming a complete isolation structure between the enhancement device and the depletion device for effective enhancement and depletion devices Isolation.
  • the filling material of the dielectric island and the trench is the same material.
  • the groove has a width of 0.5 ⁇ m to 2 ⁇ m.
  • the filling material of the dielectric island and the trench is a thermal oxide layer of the same material.
  • the semiconductor device of the present application further includes a gate structure 106 formed on the first region 1 and the second region 2, the gate structure 106 including a gate formed on the first layer 1.
  • the gate dielectric layer 107 and the gate material layer 108 are partially covered; the gate structure 1061 in the first region 1 partially covers the second doping type deep well 1031 adjacent to the first region 1
  • the gate structure 1062 in the second region 2 partially covers the adjacent second region second doping type deep well 1032 in the second region 2, and the gate structure 106 is covered with a plurality of dielectric islands 1041.
  • the first dielectric island 1041 is covered under the gate structure.
  • the gate structure 106 also covers the third dielectric island 1043.
  • the material of the gate structure 106 and the gate structure can be any material known to those skilled in the art.
  • the gate dielectric layer is a silicon dioxide material
  • the gate material layer is a polysilicon material.
  • the thickness of the gate dielectric layer ranges from The thickness of the gate material layer ranges from
  • the semiconductor device of the present application further includes a first doping type source region 110 formed in the second doping type deep well 103 formed on both sides of the gate structure 106, wherein the same location
  • the first doping type source region 110 in the second doping type deep well 103 is separated by a portion of the second doping type deep well 103.
  • the semiconductor device of the present application further includes a first doping type channel 105 on both sides of the dielectric island 104 in the first region 1, the first doping type channel extending laterally To the outside of the first doping type source region 110.
  • the semiconductor device further includes a second doping type deep formed in the second doping type deep well 1031 and the second region 2 respectively disposed in the first region 1.
  • a second doping type source region 112 in the well 1032, a second doping type source region 112 is located between the first doping type source regions 110, and the second doping type source region is used to enhance the source and Deep well contact.
  • the semiconductor device further includes a second doping type deep well 1031 and a second doping type in the second region 2 respectively disposed in the first region 1.
  • the second doping type well region 1091 formed under the first doping type source region 110 and the second doping type source region 112 can significantly reduce the resistance of the parasitic transistor base region and greatly reduce the risk of parasitic transistor turn-on. This makes the device's working stability significantly improved.
  • the semiconductor device further includes a source 113 formed on the first doping type epitaxial layer, the source 113 including a first region source 1131 and a second The source of the zone is 1132.
  • the first region source 1131 is in contact with the second doping type deep well 1021 in the first region 1 and the first doping type source region 110 in the second doping type deep well 1121.
  • the second region source 1132 is in contact with the second doping type deep well 1022 in the second region 2 and the first doping type source region 110 in the second doping type deep well 1022, wherein The first region source 1131 is not in contact with the second region source 1132.
  • a second doping type source region 112 is formed in the second doping type deep well 1021 in the first region 1 and the second doping type deep well 1022 in the second region 2,
  • the first region source 1131 is in contact with the first doping type source region 110 and the second doping type source region 112 in the first region 1, and the second region source 1132 and the second region 2 are
  • the first doping type source region 110 is in contact with the second doping type source region 112.
  • the semiconductor device further includes a drain 114 formed on a back side of the first doping type semiconductor substrate 100.
  • a complete integrated VDMOS device integrated with a depletion VDMOS device and an enhanced VDMOS device is formed.
  • the description of the VDMOS device in this embodiment is merely exemplary, and is not intended to limit the scope of the application. Those skilled in the art may form an IGBT device or the like as needed.
  • an IGBT device is provided according to the semiconductor device of the present application, wherein the semiconductor substrate of the above VDMOS device is set to a second doping type, that is, the semiconductor substrate is a P+ type substrate, and other component positions and doping types are unchanged. Then, a depletion type IGBT device is disposed in the first region, and an enhanced IGBT device is formed in the second region. Further, by way of example, the IGBT device is used in parallel with a fast recovery diode to improve the current sharing effect of the device and the stability and reliability of the system operation.
  • a plurality of semiconductor devices can be integrated as needed, such as integrating one or more diodes, transistors, resistors, capacitors, JFETs, current sensing VDMOS on the above integrated semiconductor device.
  • a semiconductor device such as CMOS, and an isolation structure between the depletion type semiconductor device and other types of semiconductor devices to prevent punch-through between the semiconductor devices.

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Abstract

La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteurs, et un dispositif à semi-conducteurs intégré. Le procédé de fabrication consiste : sur un substrat semi-conducteur (100), à former une couche épitaxiale (101) ayant une première région (1), une deuxième région (2) et une troisième région (3); à former au moins une rainure (102) dans la troisième région (3), à former au moins deux seconds pièges profonds de dopage (1031) dans la première région (1), et à former au moins deux seconds pièges profonds de dopage (1032) dans la deuxième région (2); à former un premier îlot diélectrique (1041) entre les seconds pièges profonds de dopage (1031, 1032) et à former un second îlot diélectrique (1042) sur les seconds pièges profonds de dopage (1031, 1032); à former une première rainure de dopage (105) sur les deux côtés du premier îlot diélectrique (1041) dans la première région (1); à former une structure de grille (106) sur le premier îlot diélectrique (1041); à former une première région de source de dopage isolée (110) en utilisant le second îlot diélectrique (1042) comme masque, la première rainure de dopage (105) s'étendant horizontalement jusqu'à la première région de source de dopage (110) dans la première région (1).
PCT/CN2018/116633 2017-12-28 2018-11-21 Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs intégré WO2019128554A1 (fr)

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KR1020207019554A KR102363129B1 (ko) 2017-12-28 2018-11-21 반도체 디바이스의 제조 방법 및 집적 반도체 디바이스
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US11257720B2 (en) 2022-02-22
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CN109980009B (zh) 2020-11-03
KR102363129B1 (ko) 2022-02-14

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