WO2019127847A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2019127847A1
WO2019127847A1 PCT/CN2018/075140 CN2018075140W WO2019127847A1 WO 2019127847 A1 WO2019127847 A1 WO 2019127847A1 CN 2018075140 W CN2018075140 W CN 2018075140W WO 2019127847 A1 WO2019127847 A1 WO 2019127847A1
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Prior art keywords
dielectric insulating
insulating layer
layer
disposed
display panel
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PCT/CN2018/075140
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English (en)
French (fr)
Inventor
曾霜华
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武汉华星光电技术有限公司
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Priority to US15/764,662 priority Critical patent/US10685988B2/en
Publication of WO2019127847A1 publication Critical patent/WO2019127847A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the invention belongs to the technical field of display panel manufacturing, and in particular to a display panel, a manufacturing method thereof and a display device.
  • the scan line extends from the display area to the end of the non-display area and is suspended, without any components connected.
  • 1 is a schematic structural view of a display panel of the prior art. Referring to FIG. 1, the scan line 10 is suspended from the display area AA to the end of the non-display area NA, and has a second metal layer 20 forming a data line above the end of the scan line 10.
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1. Referring to FIG.
  • the tip end discharge of the scan line 10 is liable to cause electrostatic damage, and the second metal layer 20 is perpendicular to the scan line 10, and the edge of the second metal layer 20 is closer to the end of the scan line 10 due to the scan line.
  • the tip end of the 10 discharges the dielectric insulating layer 30, and the second metal layer 20 and the scanning line 10 are easily short-circuited, causing the different signals of the scanning line 10 and the second metal layer 20 to be short-circuited, and eventually an abnormality is displayed, and the flaw is caused.
  • the slight part is more difficult to detect and is easy to miss, which leads to loss of yield of the display panel and affects the success rate of the sample.
  • a display panel includes a plurality of scan lines and connection lines, the plurality of scan lines being disposed in parallel with each other, the connection lines being connected to ends of the plurality of scan lines,
  • the connecting line is made of intrinsic polysilicon.
  • the display panel further includes a plurality of connecting conductive layers, and the ends of the plurality of scanning lines are connected in one-to-one correspondence with the plurality of connecting conductive layers, and the connecting lines are connected to the plurality of connecting conductive layers.
  • the display panel further includes a first dielectric insulating layer and a second dielectric insulating layer, the first dielectric insulating layer is disposed on the connecting line, and the plurality of scan lines are disposed on the first dielectric insulating layer On the layer, the second dielectric insulating layer is disposed on the plurality of scan lines and the first dielectric insulating layer, and the plurality of connecting conductive layers are disposed on the second dielectric insulating layer, and each connection is electrically conductive A layer penetrates the second dielectric insulating layer to be connected to an end of a corresponding one of the scan lines, and each of the connection conductive layers penetrates the second dielectric insulating layer and the first dielectric insulating layer to be connected to the connecting line.
  • the display panel further includes a plurality of pixels and a plurality of data lines, the plurality of data lines being disposed in parallel with each other, the data lines and the scan lines crossing each other to define a plurality of pixel regions, each pixel The area corresponds to one pixel, and the pixel includes at least one thin film transistor connected to the corresponding scan line and data line.
  • the thin film transistor includes: an active layer formed simultaneously with the connecting line using intrinsic polysilicon; a source and a drain respectively disposed on two sides of the active layer; the first dielectric insulating a layer is further disposed on the active layer, the source, and the drain; a gate is formed on the first dielectric insulating layer simultaneously with the scan line, the gate and the corresponding a scan line connection, the second dielectric insulating layer is further disposed on the gate; a source contact layer and a drain contact layer are formed in the second dielectric insulation simultaneously with the connection conductive layer and the data line On the layer, the source contact layer and the drain contact layer are in contact with the source and the drain through the second dielectric insulating layer and the first dielectric insulating layer, respectively, and the source contacts The layer is connected to the corresponding data line.
  • the pixel further includes a liquid crystal cell or an organic light emitting diode connected to the thin film transistor.
  • a display device comprising the above display panel.
  • a method for fabricating a display panel comprising: step 1: providing a substrate, the substrate comprising a display area and a non-display area; and step 2: in the non-display area Forming a connecting line by using intrinsic polysilicon; Step 3: forming a first dielectric insulating layer in the display area and the non-display area, the first dielectric insulating layer is disposed on the connecting line; Step 4: Forming, in the display area, a plurality of scan lines extending into the non-display area, the scan lines being disposed on the first dielectric insulating layer; and step 5: in the display area and the non- Forming a second dielectric insulating layer in the display region, the second dielectric insulating layer being disposed on the plurality of scan lines and the first dielectric insulating layer; and step 6: the first in the non-display area Forming a plurality of first via holes and a plurality of second via holes in each of the two dielectric
  • step two an active layer, a source and a drain are formed in the display region, the active layer is made of intrinsic polysilicon; in step three, the first dielectric insulating layer And disposed on the active layer, the source and the drain; in step 4, simultaneously forming a gate disposed on the first dielectric insulating layer in the display region, the gate and the corresponding a scan line is connected; in step 5, the second dielectric insulating layer is further disposed on the gate; in step 7, simultaneously forming and forming the second dielectric insulating layer in the display region An upper source contact layer, a drain contact layer and a plurality of data lines, the source contact layer and the drain contact layer penetrating the second dielectric insulating layer and the first dielectric insulating layer respectively from the source The pole is in contact with the drain, and the source contact layer is connected to the corresponding data line.
  • the manufacturing method further includes: forming a liquid crystal cell or an organic light emitting diode that is in contact with the drain contact layer.
  • the invention has the beneficial effects that the invention adopts a connecting line formed by intrinsic silicon to connect the ends of all the scanning lines, since the intrinsic silicon is almost non-conductive, which does not affect the progressive opening of the scanning lines, and can also form intrinsic silicon.
  • the large resistance consumes power to prevent static electricity at the end of the scanning line, thereby solving the problem that static electricity is likely to occur at the end of the scanning line, thereby improving product quality.
  • FIG. 1 is a schematic structural view of a display panel of the prior art
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • FIG. 4 is a side view of a thin film transistor in accordance with an embodiment of the present invention.
  • Figure 5 is a cross-sectional view taken along line B-B of Figure 3;
  • FIG. 6 is a flow chart of a method of fabricating a display panel in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • a display panel includes a plurality of scan lines 100 and a connection line 200, and a plurality of scan lines 100 are disposed in parallel with each other, and the connection lines 200 are connected to ends of a plurality of scan lines 100, the connection lines 200 can be made from intrinsic polysilicon.
  • the intrinsic silicon Since the intrinsic silicon is almost non-conductive, this does not affect the scanning line 100 to be turned on step by step, and the intrinsic silicon large resistance power consumption can be formed to prevent static electricity at the end of the scanning line 100, so that the end of the scanning line 100 can be solved easily.
  • the problem of static electricity is generated to improve product quality.
  • the display panel according to the embodiment of the present invention further includes a plurality of connection conductive layers 600, and a connection conductive layer 600 corresponding to the end of each of the scan lines 100 is connected to the connection line 200.
  • the display panel according to an embodiment of the present invention further includes a substrate 300, a plurality of data lines 400, and a plurality of pixels PX.
  • the substrate 300 is generally divided into a display area AA and a non-display area NA on the side of the display area AA.
  • the plurality of scan lines 100 are disposed in parallel in the display area AA and extend to the non-display area NA, wherein the end of each of the scan lines 100 extends to the non-display area NA.
  • a plurality of data lines 400 are also disposed in parallel within the display area AA, and the data lines 400 are disposed across the scan lines 100 to define a plurality of pixel areas.
  • Each of the pixels PX is disposed in a corresponding one of the pixel regions, and each of the pixels PX includes at least one thin film transistor and a liquid crystal cell or an organic light emitting diode connected to the thin film transistor.
  • FIG. 3 although three data lines 400, two scanning lines 100, and four defined pixel regions are shown, the present invention is not limited to that shown in FIG.
  • FIG. 4 is a side view of a thin film transistor in accordance with an embodiment of the present invention.
  • a thin film transistor according to an embodiment of the present invention includes an active layer 510 disposed on a substrate 300, and a source 520a and a drain 520b disposed on opposite sides of the active layer 510, respectively.
  • the dielectric insulating layer 530 is disposed on the active layer 510, the source 520a and the drain 520b; the gate 540 is formed on the first dielectric insulating layer 530 simultaneously with the scan line 100, and the gate 540 is connected to the corresponding scan line 100.
  • a second dielectric insulating layer 550 disposed on the gate 540 and the first dielectric insulating layer 530; a source contact layer 560a and a drain contact layer 560b formed on the second dielectric insulating layer 550 simultaneously with the data line 400, the source The contact layer 560a and the drain contact layer 560b are in contact with the source 520a and the drain 520b, respectively, through the second dielectric insulating layer 550 and the first dielectric insulating layer 530, and the source contact layer 560a is connected to the corresponding data line 400.
  • a liquid crystal cell or an organic light emitting diode connected to the thin film transistor can also be fabricated.
  • Figure 5 is a cross-sectional view taken along line B-B of Figure 3 .
  • the connection line 200 is disposed on the substrate 300.
  • the connection line 200 and the active layer 510 are simultaneously formed using intrinsic polysilicon.
  • the first dielectric insulating layer 530 extends to the non-display area AA and is disposed on the connection line 200.
  • the end of the scan line 100 is disposed on the first dielectric insulating layer 530.
  • the second dielectric insulating layer 550 extends to the non-display area AA and is disposed on the end of the scan line 100.
  • a first via 551 and a second via 552 are formed in the second dielectric insulating layer 550.
  • the first via 551 exposes the end of the scan line 100
  • the second via 552 penetrates the first dielectric insulating layer 530 to connect the connection line 200.
  • the connection conductive layer 600 is formed simultaneously with the source contact layer 560a and the drain contact layer 560b using the same material, and the connection conductive layer 600 is located on the second dielectric insulation layer 550.
  • the connection conductive layer 600 is connected to the end of the scan line 100 and the connection line 200 through the first via 551 and the second via 552, respectively, so that the plurality of connection conductive layers 600 connect the ends of the plurality of scan lines 100 with the connection line 200.
  • the present invention provides a display device including the display panel shown in Fig. 3, a scan driver that supplies a signal to the scan line 100, and a data driver that supplies a signal to the data line 400.
  • the display device of the present invention may also include other necessary components such as a timing controller that controls the scan driver and the data driver.
  • FIG. 6 is a flow chart of a method of fabricating a display panel in accordance with an embodiment of the present invention.
  • a method for fabricating a display panel according to an embodiment of the present invention includes:
  • Step S610 providing a substrate 300.
  • the substrate 300 is generally divided into a display area AA and a non-display area NA on the side of the display area AA.
  • Step S620 forming the connecting line 200 by using intrinsic polysilicon in the non-display area NA.
  • the active layer 510, the source 520a, and the drain 520b are formed in the display area AA.
  • Step S630 forming a first dielectric insulating layer 530 in the non-display area NA and the display area AA, and the first dielectric insulating layer 530 is disposed on the connecting line 200. At the same time, the first dielectric insulating layer 530 is disposed on the active layer 510, the source 520a, and the drain 520b.
  • Step S640 forming a plurality of scanning lines 100 extending into the non-display area NA in the display area AA, and the scanning lines 100 are disposed on the first dielectric insulating layer 530.
  • a gate 540 disposed on the first dielectric insulating layer 530 is formed in the display area AA, and the gate 540 is connected to the corresponding one of the scan lines 100.
  • Step S650 forming a second dielectric insulating layer 550 formed in the display area AA and the non-display area NA, and the second dielectric insulating layer 550 is disposed on the plurality of scan lines 100 and the first dielectric insulating layer 530.
  • the second dielectric insulating layer 550 is also disposed on the gate 540.
  • Step S660 simultaneously forming a plurality of first vias 551 and a plurality of second vias 552 in the second dielectric insulating layer 550 in the non-display area NA, each of the first vias 551 exposing a corresponding one of the scan lines 110 At the end, a plurality of second vias 552 penetrate the first dielectric insulating layer 530 to expose the connection lines 200.
  • Step S670 forming a plurality of connection conductive layers 600 on the second dielectric insulating layer 550 in the non-display area NA, each of the connection conductive layers 600 passing through a corresponding one of the first via holes 551 and the corresponding one of the scan lines 100
  • the end connection contacts, each of the connection conductive layers 600 are connected to the connection line 200 through a corresponding one of the second via holes 552.
  • the source contact layer 560a, the drain contact layer 560b and the plurality of data lines 400 disposed on the second dielectric insulating layer 550 are formed in the display area AA, and the source contact layer 560a and the drain contact layer 560b penetrate the second medium.
  • the insulating layer 550 and the first dielectric insulating layer 530 are in contact with the source 520a and the drain 520b, respectively, and the source contact layer 560a is connected to the corresponding data line 400.
  • the ends of all the scan lines are connected by a connecting line formed by intrinsic silicon, since the intrinsic silicon is almost non-conductive, which does not affect the progressive opening of the scan lines.
  • the method of forming the intrinsic silicon large-resistance power consumption prevents static electricity at the end of the scanning line, thereby solving the problem that static electricity is likely to occur at the end of the scanning line, thereby improving product quality.

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Abstract

一种显示面板，其包括多条扫描线（100）和连接线（200），多条扫描线（100）彼此间隔设置，连接线（200）与多条扫描线（100）的末端连接，连接线（200）由本征硅制作而成。采用由本征硅制作形成的连接线（200）连接所有扫描线（100）的末端，由于本征硅几乎接近不导电，这样既不影响扫描线（100）逐级开启，还可以形成本征硅大电阻消耗功率的方式防止扫描线（100）末端的静电，从而可以解决扫描线（100）的末端容易发生静电的问题，从而提升产品品质。还提供了该显示面板的制作方法。

Description

显示面板及其制作方法、显示装置 技术领域
本发明属于显示面板制作技术领域，具体地讲，涉及一种显示面板及其制作方法、显示装置。
背景技术
在目前的低温多晶硅显示面板的设计制程中，扫描线由显示区延伸到非显示区的末端被悬空设计，未连接任何元件。图1是现有技术的显示面板的结构示意图。参照图1，扫描线10由显示区AA延伸到非显示区NA的末端被悬空，而在扫描线10的末端上方具有形成数据线的第二金属层20。图2是沿图1中A-A线的剖面图。参照图2，扫描线10的末端尖端放电容易发生静电炸伤，且第二金属层20与扫描线10垂直设计，第二金属层20的边缘与扫描线10的末端距离较近，因扫描线10的末端尖端放电炸伤介质绝缘层30，容易将第二金属层20和扫描线10短路，导致扫描线10和第二金属层20的不同信号短路在一块，最终出现显示异常，其中炸伤轻微的部分比较难检测出来，容易漏检，从而导致显示面板良率损失以及影响送样成功率。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种能够防止扫描线末端静电炸伤截止绝缘层的显示面板及其制作方法、显示装置。
根据本发明的一方面，提供了一种显示面板，其包括多条扫描线和连接线，所述多条扫描线彼此平行设置，所述连接线与所述多条扫描线的末端连接，所述连接线由本征多晶硅制作而成。
进一步地，所述显示面板还包括多个连接导电层，所述多条扫描线的末端与所述多个连接导电层一一对应连接，所述连接线与所述多个连接导电层连接。
进一步地，所述显示面板还包括第一介质绝缘层和第二介质绝缘层，所述第一介质绝缘层设置于所述连接线上，所述多条扫描线设置于所述第一介质绝缘层上，所述第二介质绝缘层设置于所述多条扫描线和所述第一介质绝缘层上，所述多个连接导电层设置于所述第二介质绝缘层上，每个连接导电层贯穿所述第二介质绝缘层以与对应的一条扫描线的末端连接，每个连接导电层贯穿所述第二介质绝缘层和所述第一介质绝缘层以与所述连接线连接。
进一步地，所述显示面板还包括多个像素和多条数据线，所述多条数据线彼此平行设置，所述数据线与所述扫描线彼此交叉以限定出多个像素区，每个像素区对应设置一个像素，所述像素包括至少一个连接到对应的扫描线和数据线的薄膜晶体管。
进一步地，所述薄膜晶体管包括：有源层，与所述连接线采用本征多晶硅同时制成；源极和漏极，分别设置于所述有源层的两侧；所述第一介质绝缘层还设置在所述有源层、所述源极和所述漏极上；栅极，与所述扫描线同时形成在所述第一介质绝缘层上，所述栅极与对应的所述扫描线连接，所述第二介质绝缘层还设置于所述栅极上；源极接触层和漏极接触层，与所述连接导电层和所述数据线同时形成于所述第二介质绝缘层上，所述源极接触层和所述漏极接触层贯穿所述第二介质绝缘层和所述第一介质绝缘层分别与所述源极和所述漏极接触，所述源极接触层与对应的所述数据线连接。
进一步地，所述像素还包括与所述薄膜晶体管连接的液晶单元或者有机发光二极管。
根据本发明的另一方面，还提供了一种显示装置，其包括上述的显示面板。
根据本发明的又一方面，又提供了一种显示面板的制作方法，其包括：步骤一：提供一基板，所述基板包括显示区和非显示区；步骤二：在所述非显示区中采用本征多晶硅制作形成连接线；步骤三：在所述显示区和所述非显示区中制作形成第一介质绝缘层，所述第一介质绝缘层设置于所述连接线上；步骤四：在所述显示区中制作形成多条末端延伸到所述非显示区中的扫描线，所述扫描线设置于所述第一介质绝缘层上；步骤五：在所述显示区和所述非显示区中制作形成第二介质绝缘层，所述第二介质绝缘层设置于多条所述扫描线和所述第一介质绝缘层上；步骤六：在所述非显示区中的所述第二介质绝缘层中同 时制作形成多个第一过孔和多个第二过孔，每个第一过孔暴露对应的一条所述扫描线的末端，多个第二过孔贯穿所述第一介质绝缘层以暴露所述连接线；步骤七：在所述非显示区中的所述第二介质绝缘层上制作形成多个连接导电层，每个连接导电层分别通过对应的一个第一过孔与对应的一条扫描线的末端连接接触，每个连接导电层分别通过对应的一个第二过孔与所述连接线连接接触。
进一步地，在步骤二中，同时在所述显示区中制作形成有源层、源极和漏极，所述有源层由本征多晶硅制成；在步骤三中，所述第一介质绝缘层还设置于所述有源层、源极和漏极上；在步骤四中，同时在所述显示区中制作形成设置于所述第一介质绝缘层上的栅极，所述栅极与对应的一条扫描线连接；在步骤五中，所述第二介质绝缘层还设置于所述栅极上；在步骤七中，同时在所述显示区中制作形成设置于所述第二介质绝缘层上源极接触层、漏极接触层和多条数据线，所述源极接触层和所述漏极接触层贯穿所述第二介质绝缘层和所述第一介质绝缘层分别与所述源极和所述漏极接触，所述源极接触层与对应的所述数据线连接。
进一步地，所述制作方法还包括：制作形成与所述漏极接触层连接接触的液晶单元或者有机发光二极管。
本发明的有益效果：本发明采用由本征硅制作形成的连接线连接所有扫描线的末端，由于因本征硅几乎接近不导电，这样既不影响扫描线逐级开启，还可以形成本征硅大电阻消耗功率的方式防止扫描线末端的静电，从而可以解决扫描线的末端容易发生静电的问题，从而提升产品品质。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是现有技术的显示面板的结构示意图；
图2是沿图1中A-A线的剖面图；
图3是根据本发明的实施例的显示面板的结构示意图；
图4是根据本发明的实施例的薄膜晶体管的侧视图；
图5是沿图3中的B-B线的剖面图；
图6是根据本发明的实施例的显示面板的制作方法的流程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚起见，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
图3是根据本发明的实施例的显示面板的结构示意图。
参照图3，根据本发明的实施例的显示面板包括多条扫描线100和连接线200，多条扫描线100彼此平行设置，连接线200与多条扫描线100的末端连接，所述连接线200可以由本征多晶硅制作而成。
由于因本征硅几乎接近不导电，这样既不影响扫描线100逐级开启，还可以形成本征硅大电阻消耗功率的方式防止扫描线100末端的静电，从而可以解决扫描线100的末端容易发生静电的问题，从而提升产品品质。
进一步地，根据本发明的实施例的显示面板还包括多个连接导电层600，每条扫描线100的末端对应的一个连接导电层600与连接线200进行连接。
此外，根据本发明的实施例的显示面板还包括基板300、多条数据线400、多个像素PX。
基板300通常被划分为显示区AA和位于显示区AA一侧的非显示区NA。多条扫描线100平行设置于显示区AA内且延伸到非显示区NA，其中每条扫描线100的末端延伸到非显示区NA。多条数据线400也平行设置于显示区AA内，并且数据线400与扫描线100交叉设置，以限定出多个像素区域。每个像 素PX设置于对应的一个像素区域内，每个像素PX至少包括一个薄膜晶体管以及与薄膜晶体管连接的液晶单元或者有机发光二极管。
在图3中，虽然示出了三条数据线400、两条扫描线100以及限定出的四个像素区域，但本发明并不以图3所示为限。
以下先对显示区AA中的薄膜晶体管的结构进行描述。图4是根据本发明的实施例的薄膜晶体管的侧视图。
参照图3和图4，根据本发明的实施例的薄膜晶体管包括：有源层510，设置于基板300上；源极520a和漏极520b，分别设置于有源层510的两侧；第一介质绝缘层530，设置在有源层510、源极520a和漏极520b上；栅极540，与扫描线100同时形成在第一介质绝缘层530上，栅极540与对应的扫描线100连接；第二介质绝缘层550，设置于栅极540和第一介质绝缘层530上；源极接触层560a和漏极接触层560b，与数据线400同时形成于第二介质绝缘层550上，源极接触层560a和漏极接触层560b贯穿第二介质绝缘层550和第一介质绝缘层530分别与源极520a和漏极520b接触，源极接触层560a与对应的数据线400连接。
此外，需要说明的是，在制作完成薄膜晶体管之后，还可以制作与薄膜晶体管连接的液晶单元或者有机发光二极管。
图5是沿图3中的B-B线的剖面图。参照图5，连接线200设置于基板300上。这里，连接线200与有源层510采用本征多晶硅同时制成。第一介质绝缘层530延伸到非显示区AA且设置于连接线200上。扫描线100的末端设置于第一介质绝缘层530上。第二介质绝缘层550延伸到非显示区AA且设置于扫描线100的末端上。第二介质绝缘层550中形成第一过孔551和第二过孔552，第一过孔551将扫描线100的末端暴露，第二过孔552贯穿第一介质绝缘层530而将连接线200。连接导电层600与源极接触层560a和漏极接触层560b采用同种材料同时形成，并且连接导电层600位于第二介质绝缘层550上。连接导电层600通过第一过孔551和第二过孔552分别与扫描线100的末端和连接线200，从而多个连接导电层600将多条扫描线100的末端与连接线200连接。
此外，本发明还提供了一种显示装置，其包括图3所示的显示面板、向扫 描线100提供信号的扫描驱动器以及向数据线400提供信号的数据驱动器。当然，本发明的显示装置还可以包括其他必要的部件，例如控制扫描驱动器和数据驱动器的时序控制器。
图6是根据本发明的实施例的显示面板的制作方法的流程图。
参照图6，一并结合参照图3至图5，根据本发明的实施例的显示面板的制作方法包括：
步骤S610：提供一基板300。基板300通常被划分为显示区AA和位于显示区AA一侧的非显示区NA。
步骤S620：在非显示区NA中采用本征多晶硅制作形成连接线200。同时在显示区AA中制作形成有源层510、源极520a和漏极520b。
步骤S630：在非显示区NA和显示区AA中制作形成第一介质绝缘层530，第一介质绝缘层530设置于连接线200上。同时第一介质绝缘层530设置于有源层510、源极520a和漏极520b上。
步骤S640：在显示区AA中制作形成多条末端延伸到非显示区NA中的扫描线100，扫描线100设置于第一介质绝缘层530上。同时在显示区AA中制作形成设置于第一介质绝缘层530上的栅极540，栅极540与对应的一条扫描线100连接。
步骤S650：在显示区AA和所述非显示区NA中制作形成第二介质绝缘层550，第二介质绝缘层550设置于多条扫描线100和第一介质绝缘层530上。第二介质绝缘层550还设置于栅极540上。
步骤S660：在非显示区NA中的第二介质绝缘层550中同时制作形成多个第一过孔551和多个第二过孔552，每个第一过孔551暴露对应的一条扫描线110的末端，多个第二过孔552贯穿第一介质绝缘层530以暴露连接线200。
步骤S670：在非显示区NA中的第二介质绝缘层550上制作形成多个连接导电层600，每个连接导电层600分别通过对应的一个第一过孔551与对应的一条扫描线100的末端连接接触，每个连接导电层600分别通过对应的一个第 二过孔552与连接线200连接接触。同时在显示区AA中制作形成设置于第二介质绝缘层550上源极接触层560a、漏极接触层560b和多条数据线400，源极接触层560a和漏极接触层560b贯穿第二介质绝缘层550和第一介质绝缘层530分别与源极520a和漏极520b接触，源极接触层560a与对应的数据线400连接。
综上所述，根据本发明的实施例，采用由本征硅制作形成的连接线连接所有扫描线的末端，由于因本征硅几乎接近不导电，这样既不影响扫描线逐级开启，还可以形成本征硅大电阻消耗功率的方式防止扫描线末端的静电，从而可以解决扫描线的末端容易发生静电的问题，从而提升产品品质。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种显示面板，其中，包括多条扫描线和连接线，所述多条扫描线彼此间隔设置，所述连接线与所述多条扫描线的末端连接，所述连接线由本征硅制作而成。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个连接导电层，所述多条扫描线的末端与所述多个连接导电层一一对应连接，所述连接线与所述多个连接导电层连接。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括第一介质绝缘层和第二介质绝缘层，所述第一介质绝缘层设置于所述连接线上，所述多条扫描线设置于所述第一介质绝缘层上，所述第二介质绝缘层设置于所述多条扫描线和所述第一介质绝缘层上，所述多个连接导电层设置于所述第二介质绝缘层上，每个连接导电层贯穿所述第二介质绝缘层以与对应的一条扫描线的末端连接，每个连接导电层贯穿所述第二介质绝缘层和所述第一介质绝缘层以与所述连接线连接。
  4. 根据权利要求2所述的显示面板，其中，所述显示面板还包括多个像素和多条数据线，所述多条数据线彼此平行设置，所述数据线与所述扫描线彼此交叉以限定出多个像素区，每个像素区对应设置一个像素，所述像素包括至少一个连接到对应的扫描线和数据线的薄膜晶体管。
  5. 根据权利要求3所述的显示面板，其中，所述显示面板还包括多个像素和多条数据线，所述多条数据线彼此平行设置，所述数据线与所述扫描线彼此交叉以限定出多个像素区，每个像素区对应设置一个像素，所述像素包括至少一个连接到对应的扫描线和数据线的薄膜晶体管。
  6. 根据权利要求4所述的显示面板，其中，所述薄膜晶体管包括：
    有源层，与所述连接线采用本征多晶硅同时制成；
    源极和漏极，分别设置于所述有源层的两侧；所述第一介质绝缘层还设置在所述有源层、所述源极和所述漏极上；
    栅极，与所述扫描线同时形成在所述第一介质绝缘层上，所述栅极与对应的所述扫描线连接，所述第二介质绝缘层还设置于所述栅极上；
    源极接触层和漏极接触层，与所述连接导电层和所述数据线同时形成于所述第二介质绝缘层上，所述源极接触层和所述漏极接触层贯穿所述第二介质绝缘层和所述第一介质绝缘层分别与所述源极和所述漏极接触，所述源极接触层与对应的所述数据线连接。
  7. 根据权利要求5所述的显示面板，其中，所述薄膜晶体管包括：
    有源层，与所述连接线采用本征多晶硅同时制成；
    源极和漏极，分别设置于所述有源层的两侧；所述第一介质绝缘层还设置在所述有源层、所述源极和所述漏极上；
    栅极，与所述扫描线同时形成在所述第一介质绝缘层上，所述栅极与对应的所述扫描线连接，所述第二介质绝缘层还设置于所述栅极上；
    源极接触层和漏极接触层，与所述连接导电层和所述数据线同时形成于所述第二介质绝缘层上，所述源极接触层和所述漏极接触层贯穿所述第二介质绝缘层和所述第一介质绝缘层分别与所述源极和所述漏极接触，所述源极接触层与对应的所述数据线连接。
  8. 根据权利要求4所述的显示面板，其中，所述像素还包括与所述薄膜晶体管连接的液晶单元或者有机发光二极管。
  9. 根据权利要求5所述的显示面板，其中，所述像素还包括与所述薄膜晶体管连接的液晶单元或者有机发光二极管。
  10. 一种显示装置，其中，包括权利要求1所述的显示面板。
  11. 一种显示面板的制作方法，其中，包括：
    步骤一：提供一基板，所述基板包括显示区和非显示区；
    步骤二：在所述非显示区中采用本征多晶硅制作形成连接线；
    步骤三：在所述显示区和所述非显示区中制作形成第一介质绝缘层，所述第一介质绝缘层设置于所述连接线上；
    步骤四：在所述显示区中制作形成多条末端延伸到所述非显示区中的扫描线，所述扫描线设置于所述第一介质绝缘层上；
    步骤五：在所述显示区和所述非显示区中制作形成第二介质绝缘层，所述第二介质绝缘层设置于多条所述扫描线和所述第一介质绝缘层上；
    步骤六：在所述非显示区中的所述第二介质绝缘层中同时制作形成多个第一过孔和多个第二过孔，每个第一过孔暴露对应的一条所述扫描线的末端，多个第二过孔贯穿所述第一介质绝缘层以暴露所述连接线；
    步骤七：在所述非显示区中的所述第二介质绝缘层上制作形成多个连接导电层，每个连接导电层分别通过对应的一个第一过孔与对应的一条扫描线的末端连接接触，每个连接导电层分别通过对应的一个第二过孔与所述连接线连接接触。
  12. 根据权利要求11所述的显示面板的制作方法，其中，
    在步骤二中，同时在所述显示区中制作形成有源层、源极和漏极，所述有源层由本征多晶硅制成；
    在步骤三中，所述第一介质绝缘层还设置于所述有源层、源极和漏极上；
    在步骤四中，同时在所述显示区中制作形成设置于所述第一介质绝缘层上的栅极，所述栅极与对应的一条扫描线连接；
    在步骤五中，所述第二介质绝缘层还设置于所述栅极上；
    在步骤七中，同时在所述显示区中制作形成设置于所述第二介质绝缘层上源极接触层、漏极接触层和多条数据线，所述源极接触层和所述漏极接触层贯穿所述第二介质绝缘层和所述第一介质绝缘层分别与所述源极和所述漏极接触，所述源极接触层与对应的所述数据线连接。
  13. 根据权利要求12所述的显示面板的制作方法，其中，所述制作方法 还包括：制作形成与所述漏极接触层连接接触的液晶单元或者有机发光二极管。
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