WO2019119888A1 - 阵列基板的制作方法、阵列基板和液晶显示面板 - Google Patents

阵列基板的制作方法、阵列基板和液晶显示面板 Download PDF

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Publication number
WO2019119888A1
WO2019119888A1 PCT/CN2018/105061 CN2018105061W WO2019119888A1 WO 2019119888 A1 WO2019119888 A1 WO 2019119888A1 CN 2018105061 W CN2018105061 W CN 2018105061W WO 2019119888 A1 WO2019119888 A1 WO 2019119888A1
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Prior art keywords
layer
light shielding
metal layer
array substrate
metal
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PCT/CN2018/105061
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English (en)
French (fr)
Inventor
杨春辉
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/772,907 priority Critical patent/US11372291B2/en
Publication of WO2019119888A1 publication Critical patent/WO2019119888A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present application relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, an array substrate, and a liquid crystal display panel.
  • An exemplary liquid crystal display includes an array substrate and a color filter substrate.
  • the array substrate includes M1/AS/M2/PV/ITO five-pass process, which requires five masks.
  • the color filter substrate also includes BM/R/G/B/PS five-way process, and also requires five masks. .
  • the function of the black matrix process of the color filter substrate shields light leakage caused by disorder of the liquid crystal alignment caused by the disturbance of the electric field near the data line and the gate line.
  • Embodiments of the present application provide a method for fabricating an array substrate, an array substrate, and a liquid crystal display panel to improve the display effect and product yield of the liquid crystal display device.
  • the present application provides a method for fabricating an array substrate, comprising the steps of: forming a light shielding layer and a first metal layer on a transparent substrate such that the light shielding layer is located between the transparent substrate and the first metal layer and The light shielding layer is consistent with the first metal layer pattern; an insulating layer, a channel layer and an ohmic contact layer are sequentially formed on the first metal layer; a second metal layer is formed on the ohmic contact layer; Forming a passivation layer on the metal layer and forming a contact hole in the passivation layer; and forming a pixel electrode layer on the passivation layer and connecting the pixel electrode layer to the second metal layer through the contact hole .
  • the light shielding layer and the first metal layer are formed on the transparent substrate such that the light shielding layer is located between the transparent substrate and the first metal layer and the light shielding layer is
  • the first metal layer pattern is uniform, comprising: forming a black light shielding material layer on the transparent substrate; forming a first metal material layer on the black light shielding material layer; forming a photoresist material on the first metal material layer a layer; exposing and developing the photoresist layer to obtain a patterned photoresist layer; using the patterned photoresist layer as a mask to the first metal material layer and the black shading material
  • the layer is sequentially subjected to wet etching and dry etching; and the residual photoresist material layer is removed after the dry etching to obtain the light shielding layer and the first metal layer.
  • the material of the light shielding layer is a black photoresist containing carbon black.
  • the light shielding layer and the first metal layer are formed by the same reticle process.
  • the first metal layer includes a scan line, a common electrode, and a gate of a thin film transistor.
  • the ohmic contact layer includes a first region and a second region that are separated from each other on the channel layer.
  • the second metal layer includes a source of a thin film transistor, a drain of the thin film transistor, and a data line, the data line is connected to the source, and the drain passes through the contact hole
  • the pixel electrode layer is connected, the source is connected to a first region of the ohmic contact layer, and the drain is connected to a second region of the ohmic contact layer.
  • the transparent substrate may be made of glass, quartz or an organic polymer.
  • the embodiment of the present application further provides an array substrate, including: a transparent substrate; a light shielding layer disposed on the transparent substrate; a first metal layer disposed on the light shielding layer, wherein the light shielding layer is located in the transparent Between the substrate and the first metal layer and the light shielding layer is consistent with the first metal layer pattern; an insulating layer disposed on the first metal layer; a channel layer disposed on the insulating layer; ohmic a contact layer disposed on the channel layer; a second metal layer disposed on the ohmic contact layer; a passivation layer disposed on the second metal layer and formed with a contact hole; and a pixel electrode layer disposed The second metal layer is connected to the passivation layer and through the contact hole.
  • the material of the light shielding layer is a black photoresist containing carbon black.
  • the first metal layer includes a scan line, a common electrode, and a gate of a thin film transistor.
  • the second metal layer includes a source of a thin film transistor, a drain of the thin film transistor, and a data line, the data line is connected to the source, and the drain passes through the contact hole The pixel electrode layer is connected.
  • the first metal layer and the light shielding layer are in direct contact.
  • the embodiment of the present application further provides a liquid crystal display panel, including:
  • An array substrate comprising: a transparent substrate; a light shielding layer disposed on the transparent substrate; a first metal layer disposed on the light shielding layer, wherein the light shielding layer is located on the transparent substrate and the first metal layer And the light shielding layer is consistent with the first metal layer pattern; an insulating layer is disposed on the first metal layer; a channel layer is disposed on the insulating layer; and an ohmic contact layer is disposed on the channel a second metal layer disposed on the ohmic contact layer; a passivation layer disposed on the second metal layer and formed with a contact hole; and a pixel electrode layer disposed on the passivation layer Connecting the second metal layer through the contact hole;
  • the color filter substrate disposed opposite to the array substrate, the color filter substrate including a black matrix layer;
  • the liquid crystal layer is disposed between the array substrate and the color filter substrate.
  • the material of the light shielding layer is a black photoresist containing carbon black.
  • the first metal layer includes a scan line, a common electrode, and a gate of a thin film transistor.
  • the second metal layer includes a source of a thin film transistor, a drain of the thin film transistor, and a data line, the data line is connected to the source, and the drain passes through the contact hole The pixel electrode layer is connected.
  • the first metal layer and the light shielding layer are in direct contact.
  • the light shielding layer on the array substrate is the same as the material of the black matrix layer on the color filter substrate.
  • the transparent substrate may be made of glass, quartz or an organic polymer.
  • the present invention provides a light shielding layer between the transparent substrate on the array substrate and the first metal layer, which overcomes the leakage of the data line and the common electrode side caused by the alignment deviation problem occurring when the array substrate and the color filter substrate are paired with the package.
  • the display effect of the liquid crystal display panel and the product pass rate of the liquid crystal display panel are improved.
  • 1a-1j are schematic cross-sectional views showing a process of fabricating an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
  • FIG. 3 is a cross-sectional view of the array substrate along section line A of FIG. 1;
  • FIG. 4 is a cross-sectional view of the array substrate along section line B of FIG. 1;
  • FIG. 5 is a schematic structural diagram of a liquid crystal display panel according to still another embodiment of the present application.
  • an embodiment of the present application provides a method for fabricating an array substrate 100, which specifically includes:
  • a light shielding layer SL and a first metal layer M1 are formed on the transparent substrate 110 such that the light shielding layer SL is located between the transparent substrate 110 and the first metal layer M1.
  • the light shielding layer SL is in direct contact with the first metal layer M1.
  • the light-shielding layer SL and the first metal layer M1 are formed by a mask M process, so that the light-shielding layer SL is consistent with the pattern of the first metal layer M1, and specifically includes:
  • the photoresist material layer PR is exposed and developed by the mask M to obtain a patterned photoresist material layer PR.
  • the mask M is engraved with a specific pattern.
  • the photoresist material layer PR is exposed through the mask M using ultraviolet rays UV, and the pattern on the mask M is transferred onto the photoresist layer PR.
  • the developer is sprayed on the photoresist layer PR, and the photoresist material exposed to ultraviolet light is dissolved in the developer to obtain a patterned photoresist layer PR as shown in FIG. 1c.
  • the first metal material layer M1' and the black light-shielding material layer SL' are sequentially wet-etched and dry-etched using the patterned photoresist layer PR as a mask, as shown in Figs. 1d and 1e.
  • the ohmic contact layer NS includes a first region NS1 and a second region NS2 which are separated from each other on the channel layer AS, as shown in FIG. 1g.
  • a second metal layer M2 is formed on the ohmic contact layer NS.
  • the second metal layer M2 includes a source S of the thin film transistor, a drain D of the thin film transistor, and a data line 150 (not shown in FIG. 1h).
  • the data line 150 is connected to the source S, the source S is connected to the first region NS1 of the ohmic contact layer NS, and the drain D is connected to the second region NS2 of the ohmic contact layer NS.
  • a passivation layer PSN is formed on the second metal layer M2 and a contact hole CH is formed in the passivation layer PSN as shown in FIG. 1i.
  • a pixel electrode layer PE is formed on the passivation layer PSN.
  • the pixel electrode layer PE is connected to the drain D of the thin film transistor through the contact hole CH of the passivation layer PSN. At this point, the array substrate is manufactured.
  • a light shielding layer is added before the first metal layer of the array substrate, and the first metal layer and the light shielding layer are sequentially wet-etched and dry-etched by using the same patterned photoresist material layer as a mask.
  • the light shielding layer and the first metal layer share the reticle, which simplifies the manufacturing process and saves manufacturing costs.
  • FIG. 2 and FIG. 4 another embodiment of the present application provides an array substrate 100 including a transparent substrate 110, a light shielding layer SL, a first metal layer M1, an insulating layer GSN, a channel layer AS, and an ohm.
  • the light shielding layer SL is disposed on the transparent substrate 110, and is sequentially provided with a first metal layer M1, an insulating layer GSN, a channel layer AS, an ohmic contact layer NS, a second metal layer M2, a passivation layer PSN, and a passivation layer.
  • a contact hole CH is formed on the PSN, and the pixel electrode layer PE is disposed on the passivation layer PSN and connected to the second metal layer M2 through the contact hole CH.
  • the transparent substrate 110 may be made of, for example, glass, quartz, an organic polymer, or other applicable materials.
  • the material of the light shielding layer SL may be an opaque material such as a black photoresist containing carbon black, which has a function of blocking light.
  • the light shielding layer SL is consistent with the pattern of the first metal layer M1, that is, the shape and size of the light shielding layer SL and the first metal layer M1 are completely the same.
  • the first metal layer M1 is a conductive layer, and the material may be molybdenum, aluminum, copper, titanium, tungsten or the like.
  • the first metal layer M1 includes a scan line 131 and a common electrode 133.
  • the second metal layer M2 includes a data line 150.
  • the scan line 131 and the data line 150 are mainly used to transfer driving signals for driving all the pixel units 170 on the array substrate 100.
  • the extending direction of the scanning line 131 is different from the extending direction of the data line 150.
  • the extending direction of the scanning line 131 is perpendicular to the extending direction of the data line 150, that is, the scanning line 131 and the data line 150 are perpendicularly arranged to intersect each other.
  • the plurality of scan lines 131 and the plurality of data lines 150 intersect to form a plurality of interleaved regions distributed in a matrix, and an interlaced region is named as one pixel unit 170 for convenience of explanation.
  • each of the pixel units 170 is provided with, for example, a thin film transistor 171 and a pixel electrode 173.
  • the thin film transistor 171 includes a gate G, an insulating layer GSN, a channel layer AS, an ohmic contact layer NS, a source S, a drain D, and a passivation layer PSN.
  • the first metal layer M1 further includes a gate G of the thin film transistor 171.
  • the gate G is connected to the scanning line 131.
  • the insulating layer GSN is located above the gate 131
  • the channel layer AS is located above the insulating layer GSN and corresponds to the gate G
  • the ohmic contact layer NS comprises a first region NS1 and a second region NS2 which are located on the channel layer AS and are separated from each other.
  • the second metal layer M2 further includes a source S of the thin film transistor 171 and a drain D of the thin film transistor 171.
  • the source S and the drain D are located above the channel layer AS, and the source S is connected to the data line 150.
  • the source S is connected to the first region NS1 of the ohmic contact layer NS
  • the drain D is connected to the second region NS2 of the ohmic contact layer NS.
  • the passivation layer PSN covers the source S and the drain D and the data line 150, and a contact hole CH is formed at a position corresponding to the drain D for connecting the drain D and the pixel electrode 173.
  • the pixel electrode 173 is a portion where the pixel electrode layer PE is located in an interlaced region where the scanning line 131 and the data line 150 intersect.
  • the material of the pixel electrode 173 may be a transparent oxide material such as Indium-tin-oxide (ITO).
  • the common electrode 133 is disposed on the light shielding layer SL in a U shape, and surrounds the pixel electrode 173 on three sides, but is not in contact with the pixel electrode 173, and is separated by an insulating layer GSN and a passivation layer PSN.
  • the projection of the common electrode 133 on the transparent substrate 110 partially overlaps with the projection of the pixel electrode 173 on the transparent substrate 110 such that the common electrode 133 and the pixel electrode 173 form a storage capacitor.
  • the light shielding layer between the transparent substrate on the array substrate and the first metal layer of the array substrate of the present embodiment is used to overcome the alignment deviation caused when the array substrate and the color filter substrate are paired with the package.
  • the problem of light leakage caused by a misalignment between the black matrix on the color filter substrate and the data line on the array substrate improves the display effect of the liquid crystal display device and the product yield of the liquid crystal display device.
  • a liquid crystal display panel 10 including an array substrate 100 , a color filter substrate 300 , and a liquid crystal layer 500 .
  • the array substrate 100 is disposed opposite to the color filter substrate 300.
  • the liquid crystal layer 500 is disposed between the array substrate 100 and the color filter substrate 300.
  • the array substrate 100 is the array substrate described in the above embodiments for transmitting and controlling electrical signals.
  • the color filter substrate 300 is used to realize display of colors.
  • the color filter substrate 300 includes a black matrix 310.
  • the material of the black matrix 310 may be a material such as a black photoresist containing carbon black for absorbing and shielding light.
  • the material of the black matrix 310 is the same as the material of the light shielding layer SL in the array substrate 100, and is manufactured. In the process, no additional material is required, which can reduce the manufacturing cost of the liquid crystal display device.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

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Abstract

一种阵列基板的制作方法，包括步骤：在透明基底（110）上形成遮光层（SL）和第一金属层（M1），从而所述遮光层（SL）位于所述透明基底（110）和所述第一金属层（M1）之间；在所述第一金属层（M1）上依次形成绝缘层（GSN）、通道层（AS）和欧姆接触层（NS）；在所述欧姆接触层（NS）上形成第二金属层（M2）；在所述第二金属层（M2）上形成钝化层（PSN）并在所述钝化层（PSN）中形成接触孔（CH）；以及在所述钝化层（PSN）上形成像素电极层（PE）并使所述像素电极层（PE）通过所述接触孔（CH）连接所述第二金属层（M2）。此外，还公开了一种阵列基板和一种液晶显示面板。

Description

阵列基板的制作方法、阵列基板和液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板的制作方法、一种阵列基板以及一种液晶显示面板。
背景技术
示例性液晶显示器包括阵列基板和彩色滤光片基板。生产过程中，阵列基板包括M1/AS/M2/PV/ITO五道制程，需要五道光罩，彩色滤光片基板也包括BM/R/G/B/PS五道制程，也需要五道光罩。其中，彩色滤光片基板的黑色矩阵制程的作用遮蔽由于数据线与栅极线附近电场紊乱导致的液晶导向紊乱所引起的漏光。
但在实际生产过程中，特别是液晶显示面板对盒时极易导致黑色矩阵与数据线的错位，在数据线侧会发生漏光。这严重影响到了产品的合格率。示例性技术中，有通过增大彩色滤光片基板上的黑色矩阵的宽度来减小漏光的可能，虽然能起到一定的防漏光效果，但对产品穿透率有较大影响。
发明内容
本申请的实施例提供一种阵列基板的制作方法、一种阵列基板和一种液晶显示面板，以提升液晶显示装置的显示效果和产品合格率。
本申请提供了一种阵列基板的制作方法，包括步骤：在透明基底上形成遮光层和第一金属层，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；在所述第一金属层上依次形成绝缘层、通道层和欧姆接触层；在所述欧姆接触层上形成第二金属层；在所述第二 金属层上形成钝化层并在所述钝化层中形成接触孔；以及在所述钝化层上形成像素电极层并使所述像素电极层通过所述接触孔连接所述第二金属层。
在本申请的一个实施例中，所述在透明基底上形成遮光层和第一金属层，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致，包括：在所述透明基底上形成黑色遮光材料层；在所述黑色遮光材料层上形成第一金属材料层；在所述第一金属材料层上形成光阻材料层；利用光罩对所述光阻材料层进行曝光显影以得到图案化光阻材料层；以所述图案化光阻材料层为掩膜对所述第一金属材料层和所述黑色遮光材料层依序进行湿蚀刻和干蚀刻；以及在所述干蚀刻后去除残余的光阻材料层，以得到所述遮光层和所述第一金属层。
在本申请的一个实施例中，所述遮光层的材料为含碳黑的黑色光阻。
在本申请的一个实施例中，所述遮光层和所述第一金属层共用同一道光罩工艺形成。
在本申请的一个实施例中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
在本申请的一个实施例中，所述欧姆接触层包括位于所述通道层上相互分离的第一区域和第二区域。
在本申请的一个实施例中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层，所述源极与所述欧姆接触层的第一区域连接，所述漏极与所述欧姆接触层的第二区域连接。
在本申请的一个实施例中，所述透明基底可以由玻璃、石英或有机聚合物 制成。
本申请实施例还提供了一种阵列基板，包括：透明基底；遮光层，设置在所述透明基底上；第一金属层，设置在所述遮光层上，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；绝缘层，设置在所述第一金属层上；通道层，设置在所述绝缘层上；欧姆接触层，设置在所述通道层上；第二金属层，设置在所述欧姆接触层上；钝化层，设置在所述第二金属层上且形成有接触孔；以及像素电极层，设置在所述钝化层上并通过所述接触孔连接所述第二金属层。
在本申请的一个实施例中，所述遮光层的材料为含碳黑的黑色光阻。
在本申请的一个实施例中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
在本申请的一个实施例中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层。
在本申请的一个实施例中，所述第一金属层和所述遮光层直接接触。
本申请实施例还提供了一种液晶显示面板，包括：
阵列基板，其包括：透明基底；遮光层，设置在所述透明基底上；第一金属层，设置在所述遮光层上，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；绝缘层，设置在所述第一金属层上；通道层，设置在所述绝缘层上；欧姆接触层，设置在所述通道层上；第二金属层，设置在所述欧姆接触层上；钝化层，设置在所述第二金属层上且形成有接触孔；以及像素电极层，设置在所述钝化层上并通过所述接触孔连接 所述第二金属层；
彩色滤光片基板，与阵列基板相对设置，所述彩色滤光片基板包括黑色矩阵层；以及
液晶层，设置于所述阵列基板和彩色滤光片基板之间。
在本申请的一个实施例中，所述遮光层的材料为含碳黑的黑色光阻。
在本申请的一个实施例中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
在本申请的一个实施例中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层。
在本申请的一个实施例中，所述第一金属层和所述遮光层直接接触。
在本申请的一个实施例中，所述阵列基板上的所述遮光层与所述彩色滤光片基板上的所述黑色矩阵层的材料相同。
在本申请的一个实施例中，所述透明基底可以由玻璃、石英或有机聚合物制成。
本申请在阵列基板上的透明基底和第一金属层之间设置遮光层，克服了阵列基板和彩色滤光片基板对盒时出现的对准偏差问题导致的数据线和公共电极侧的漏光，提升了液晶显示面板的显示效果和液晶显示面板的产品合格率。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳 动的前提下，还可以根据这些附图获得其他的附图。
图1a-图1j为本申请一实施例提供的一种阵列基板的制造方法过程剖面示意图。
图2为本申请另一实施例提供的一种阵列基板的结构示意图；
图3为沿着图1的剖面线A的阵列基板的剖面示意图；
图4为沿着图1的剖面线B的阵列基板的剖面示意图；
图5为本申请再一实施例提供的一种液晶显示面板的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1a-图1j所示，本申请一实施例提供了一种阵列基板100的制作方法，具体包括：
(a)如图1a-1f所示，在透明基底110上形成遮光层SL和第一金属层M1，从而遮光层SL位于透明基底110和第一金属层M1之间。可选地，遮光层SL和第一金属层M1直接接触。遮光层SL和第一金属层M1共用一道光罩M工艺形成，使得遮光层SL与第一金属层M1图案一致，具体包括：
(a1)在透明基底110上形成黑色遮光材料层SL’，接着在黑色遮光材料层SL’上形成第一金属材料层M1’，然后在第一金属材料层上M1’形成光阻材料层PR，如图1a所示。
(a2)如图1b所示，利用光罩M对光阻材料层PR进行曝光、显影以得到图案化光阻材料层PR。光罩M上刻有特定的图案。使用紫外线UV通过光罩M对光阻材料层PR进行曝光，将光罩M上的图案转印到光阻材料层PR上。在光阻材料层PR上喷涂显影剂，将曝光于紫外线下的光阻材料溶解于显影剂，得到图案化的光阻材料层PR，如图1c所示。
(a3)以图案化光阻材料层PR为掩膜对第一金属材料层M1’和黑色遮光材料层SL’依序进行湿蚀刻和干蚀刻，如图1d、图1e所示。
(a4)在干蚀刻后去除残余的光阻材料层PR，以得到遮光层SL和第一金属层M1，如图1f所示。
(b)在第一金属层M1上依次形成绝缘层GSN、通道层AS和欧姆接触层NS。欧姆接触层NS包括位于通道层AS上相互分离的第一区域NS1和第二区域NS2,如图1g所示。
(h)如图1h所示，在欧姆接触层NS上形成第二金属层M2。第二金属层M2包括薄膜晶体管的源极S、薄膜晶体管的漏极D和数据线150(图1h中未给出)。数据线150连接源极S，源极S与欧姆接触层NS的第一区域NS1连接，漏极D与欧姆接触层NS的第二区域NS2连接。
(i)在第二金属层M2上形成钝化层PSN并在钝化层PSN中形成接触孔CH,如图1i所示。
(j)如图1j所示,在钝化层PSN上形成像素电极层PE。像素电极层PE通过钝化层PSN的接触孔CH与薄膜晶体管的漏极D连接。至此，阵列基板制造完成。
综上所述，本实施例在阵列基板的第一金属层之前增加遮光层，且利用同 一图案化的光阻材料层为掩膜对第一金属层和遮光层依次进行湿蚀刻和干蚀刻，实现了遮光层和第一金属层共用光罩，简化了制造过程，节约了制造成本。
如图2、图3和图4所示，本申请另一实施例提供了一种阵列基板100，包括透明基底110、遮光层SL、第一金属层M1、绝缘层GSN、通道层AS、欧姆接触层NS、第二金属层M2、钝化层PSN以及像素电极层PE。遮光层SL设置于透明基底110之上，并向上依次设置有第一金属层M1、绝缘层GSN、通道层AS、欧姆接触层NS、第二金属层M2、钝化层PSN，且钝化层PSN上形成有接触孔CH，像素电极层PE设置在钝化层PSN上并通过接触孔CH连接第二金属层M2。
具体地，透明基底110可以由例如玻璃、石英、有机聚合物或是其它可适用的材料制成。遮光层SL的材料可以是不透明材料如含碳黑的黑色光阻，具有遮挡光线的功能。可选地，遮光层SL与第一金属层M1的图案一致，即遮光层SL与第一金属层M1的形状和尺寸完全相同。
第一金属层M1为导电层，材料可为钼、铝、铜、钛、钨等。第一金属层M1包括扫描线131和公共电极133。第二金属层M2包括数据线150。扫描线131、数据线150主要用来传递驱动阵列基板100上所有像素单元170的驱动信号。扫描线131的延伸方向与数据线150的延伸方向不相同，可选的是扫描线131的延伸方向与数据线150的延伸方向垂直，即扫描线131和数据线150相互垂直交叉布置。多条扫描线131和多条数据线150交叉形成多个呈矩阵分布的交错区域，此处为便于说明将一个交错区域命名为一个像素单元170。
如图3所示，每个像素单元170内设置有如薄膜晶体管171和像素电极173。薄膜晶体管171包括栅极G、绝缘层GSN、通道层AS、欧姆接触层NS、 源极S、漏极D、钝化层PSN。
具体地，第一金属层M1还包括薄膜晶体管171的栅极G。栅极G与扫描线131连接。绝缘层GSN位于栅极131上方，通道层AS位于绝缘层GSN的上方且对应栅极G，欧姆接触层NS包括位于通道层AS上且相互分离的第一区域NS1和第二区域NS2。第二金属层M2还包括薄膜晶体管171的源极S和薄膜晶体管171的漏极D。源极S和漏极D位于通道层AS的上方，且源极S与数据线150连接。源极S与欧姆接触层NS的第一区域NS1连接，漏极D与欧姆接触层NS的第二区域NS2连接。钝化层PSN覆盖于源极S和漏极D以及数据线150之上，且在与漏极D对应位置形成有接触孔CH，用于连接漏极D和像素电极173。像素电极173为像素电极层PE位于扫描线131和数据线150交叉形成的交错区域的部分。像素电极173的材料可以是如采用氧化锡铟(Indium-tin-oxide，ITO)等透明氧化物材料。
如图4所示，公共电极133设置于遮光层SL之上，呈U形，三面环绕像素电极173，但不与像素电极173接触，两者之间隔有绝缘层GSN和钝化层PSN。公共电极133在透明基底110上的投影与像素电极173在透明基底110上的投影部分重叠，以使公共电极133与像素电极173形成存储电容。
综上所述，本实施例的阵列基板在阵列基板上的透明基底和第一金属层之间的遮光层，用于克服当阵列基板和彩色滤光片基板对盒时由于存在对准偏差导致彩色滤光片基板上的黑色矩阵与阵列基板上的数据线发生错位发生的漏光问题，提高液晶显示装置的显示效果和液晶显示装置的产品合格率。
如图5所示，本申请再一实施例提供了一种液晶显示面板10，包括：阵列基板100、彩色滤光片基板300、液晶层500。阵列基板100与彩色滤光片基板 300相对设置。液晶层500设置于阵列基板100和彩色滤光片基板300之间。
阵列基板100为上述实施例所述的阵列基板，用于传输和控制电信号。
彩色滤光片基板300用于实现色彩的显示。彩色滤光片基板300包括黑色矩阵310。黑矩阵310的材料可以是如含碳黑的黑色光阻等材料，用以吸收和遮蔽光线，可选地，黑色矩阵310的材料与阵列基板100中的遮光层SL的材料相同，则在制造过程中，不需要额外备料，可降低液晶显示装置的制造成本。
该显示装置10的实施和技术效果可以参见上述阵列基板制作方法的实施例，重复之处不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多路单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修 改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (20)

  1. 一种阵列基板的制作方法，包括步骤：
    在透明基底上形成遮光层和第一金属层，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；
    在所述第一金属层上依次形成绝缘层、通道层和欧姆接触层；
    在所述欧姆接触层上形成第二金属层；
    在所述第二金属层上形成钝化层并在所述钝化层中形成接触孔；以及
    在所述钝化层上形成像素电极层并使所述像素电极层通过所述接触孔连接所述第二金属层。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述在透明基底上形成遮光层和第一金属层，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致，包括：
    在所述透明基底上形成黑色遮光材料层；
    在所述黑色遮光材料层上形成第一金属材料层；
    在所述第一金属材料层上形成光阻材料层；
    利用光罩对所述光阻材料层进行曝光显影以得到图案化光阻材料层；
    以所述图案化光阻材料层为掩膜对所述第一金属材料层和所述黑色遮光材料层依序进行湿蚀刻和干蚀刻；以及
    在所述干蚀刻后去除残余的光阻材料层，以得到所述遮光层和所述第一金属层。
  3. 如权利要求1所述的阵列基板的制作方法，其中，所述遮光层的材料为含碳黑的黑色光阻。
  4. 如权利要求1所述的阵列基板的制作方法，其中，所述遮光层和所述 第一金属层共用同一道光罩工艺形成。
  5. 如权利要求1所述的阵列基板的制作方法，其中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
  6. 如权利要求1所述的阵列基板的制作方法，其中，所述欧姆接触层包括位于所述通道层上相互分离的第一区域和第二区域。
  7. 如权利要求6所述的阵列基板的制作方法，其中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层，所述源极与所述欧姆接触层的第一区域连接，所述漏极与所述欧姆接触层的第二区域连接。
  8. 如权利要求1所述的阵列基板的制作方法，其中，所述透明基底可以由玻璃、石英或有机聚合物制成。
  9. 一种阵列基板，包括：
    透明基底；
    遮光层，设置在所述透明基底上；
    第一金属层，设置在所述遮光层上，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；
    绝缘层，设置在所述第一金属层上；
    通道层，设置在所述绝缘层上；
    欧姆接触层，设置在所述通道层上；
    第二金属层，设置在所述欧姆接触层上；
    钝化层，设置在所述第二金属层上且形成有接触孔；以及
    像素电极层，设置在所述钝化层上并通过所述接触孔连接所述第二金属 层。
  10. 如权利要求9所述的阵列基板，其中，所述遮光层的材料为含碳黑的黑色光阻。
  11. 如权利要求9所述的阵列基板，其中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
  12. 如权利要求9所述的阵列基板，其中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层。
  13. 如权利要求9所述的阵列基板，其中，所述第一金属层和所述遮光层直接接触。
  14. 一种液晶显示面板，包括：
    阵列基板，其包括：
    透明基底；
    遮光层，设置在所述透明基底上；
    第一金属层，设置在所述遮光层上，从而所述遮光层位于所述透明基底和所述第一金属层之间且所述遮光层与所述第一金属层图案一致；
    绝缘层，设置在所述第一金属层上；
    通道层，设置在所述绝缘层上；
    欧姆接触层，设置在所述通道层上；
    第二金属层，设置在所述欧姆接触层上；
    钝化层，设置在所述第二金属层上且形成有接触孔；以及
    像素电极层，设置在所述钝化层上并通过所述接触孔连接所述第二金 属层；
    彩色滤光片基板，与阵列基板相对设置，所述彩色滤光片基板包括黑色矩阵层；以及
    液晶层，设置于所述阵列基板和彩色滤光片基板之间。
  15. 如权利要求14所述的液晶显示面板，其中，所述遮光层的材料为含碳黑的黑色光阻。
  16. 如权利要求14所述的液晶显示面板，其中，所述第一金属层包括扫描线、公共电极和薄膜晶体管的栅极。
  17. 如权利要求14所述的液晶显示面板，其中，所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极和数据线，所述数据线连接所述源极，所述漏极通过所述接触孔连接所述像素电极层。
  18. 如权利要求14所述的液晶显示面板，其中，所述第一金属层和所述遮光层直接接触。
  19. 如权利要求14所述的液晶显示面板，其中，所述阵列基板上的所述遮光层与所述彩色滤光片基板上的所述黑色矩阵层的材料相同。
  20. 如权利要求14所述的液晶显示面板，其中，所述透明基底可以由玻璃、石英或有机聚合物制成。
PCT/CN2018/105061 2017-12-21 2018-09-11 阵列基板的制作方法、阵列基板和液晶显示面板 WO2019119888A1 (zh)

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