WO2019114456A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2019114456A1
WO2019114456A1 PCT/CN2018/113746 CN2018113746W WO2019114456A1 WO 2019114456 A1 WO2019114456 A1 WO 2019114456A1 CN 2018113746 W CN2018113746 W CN 2018113746W WO 2019114456 A1 WO2019114456 A1 WO 2019114456A1
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WIPO (PCT)
Prior art keywords
light shielding
layer
forming
light
substrate
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Application number
PCT/CN2018/113746
Other languages
English (en)
French (fr)
Inventor
陈延青
谢建云
李伟
李成
郭攀
李岩锋
秦伟达
王宁
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/343,485 priority Critical patent/US11404582B2/en
Priority to EP18859964.1A priority patent/EP3731007A4/en
Publication of WO2019114456A1 publication Critical patent/WO2019114456A1/zh
Priority to US17/845,568 priority patent/US11728435B2/en
Priority to US18/343,279 priority patent/US20230343874A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/56—Substrates having a particular shape, e.g. non-rectangular

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device.
  • the edge of the display area is also required to have a non-rectangular irregular shape, which can satisfy the user's appearance on the display device. Diversified needs.
  • Embodiments of the present invention provide an array substrate, a method of manufacturing the same, and a display device.
  • an array substrate in a first aspect of the present disclosure, includes: a substrate having a display area and a peripheral area surrounding the display area, the display area having a plurality of pixels arranged in an array, the plurality of pixels including a light transmitting area and a light shielding area, And a light blocking block covering at least a portion of the light transmissive region of the pixel adjacent to the peripheral region of at least one of the plurality of pixels.
  • the array substrate further includes a thin film transistor on the substrate and located in the light shielding region, the thin film transistor includes an active layer on the substrate, and the array substrate further includes a light shielding layer between the active layer and the substrate, wherein the light shielding block is disposed in the same layer as the light shielding layer.
  • the array substrate further includes a thin film transistor on the substrate and located in the light shielding region, the thin film transistor including an active layer, a gate electrode, and the active layer and the a gate dielectric layer between the gate electrodes, the light shielding block being disposed in the same layer as the gate electrode.
  • the array substrate further includes a thin film transistor on the substrate, the thin film transistor including an active layer, a gate electrode, the active layer, and the gate electrode a gate dielectric layer and source/drain electrodes disposed on the active layer, the light shielding block being disposed in the same layer as the source/drain electrodes.
  • the light shielding block includes a first portion and a second portion respectively covering opposite ends of the at least one light transmitting region of the pixel near the peripheral region.
  • the light shielding block further includes a third portion between the first portion and the second portion.
  • a ratio of an area of the light shielding block to an area of the edge pixel is set to one of N values constituting an arithmetic progression, wherein 3 ⁇ N ⁇ 101, the The first item of the difference column is 0, and the last item is 100%.
  • an absolute value of a difference between the one of the N values and a desired set value depending on an edge shape of the display area is smaller than other values of the N values The absolute value of the difference from the desired set value.
  • a display device in a second aspect of the present disclosure, includes any one of the array substrates described in the first aspect of the present disclosure.
  • a method for fabricating an array substrate comprising: providing a substrate having a display area and a peripheral area surrounding the display area, the display area having an array a plurality of pixels of the cloth, the plurality of pixels including a light transmissive area and a light blocking area; and at least a portion of the light transmissive area forming a light shielding block to cover at least one of the plurality of pixels near the peripheral area.
  • the method further includes forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor includes: forming a light shielding material layer on the substrate; a light shielding material layer to form a light shielding layer in the light shielding region and to form the light shielding block; forming a first insulating layer on the light shielding layer and the light shielding block; in the light shielding region and in the first An active layer is formed on the insulating layer; a second insulating layer as a gate dielectric layer is formed on the active layer; and a gate electrode is formed in the light shielding region and on the second insulating layer.
  • the method further includes forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor includes: on the substrate and in the light shielding region Forming an active layer; forming a third insulating layer as a gate dielectric layer on the active layer; forming a first conductive layer on the third insulating layer; and patterning the first conductive layer to A gate electrode is formed in the light shielding region and the light shielding block is formed.
  • the method further includes forming a light shielding layer on the substrate and in the light shielding region, and forming a fourth insulation layer on the light shielding layer before forming the active layer .
  • the method further includes forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor includes: forming a second conductive layer on the substrate; patterning The second conductive layer forms a gate electrode in the light shielding region and forms the light shielding block; forms a fourth insulating layer on the gate electrode and the light shielding block; and in the light shielding region An active layer is formed on the fourth insulating layer.
  • the method further includes forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor includes: forming a third conductive layer on the substrate; patterning The third conductive layer forms a gate electrode in the light shielding region; a fifth insulating layer as a gate dielectric layer is formed on the gate electrode; in the light shielding region and in the fifth insulation Forming an active layer on the layer; forming a fourth conductive material layer on the active layer; and patterning the fourth conductive material layer to form source/drain electrodes in the light-shielding region and forming the light-shielding block.
  • forming the light shielding block in the light transmissive region of the edge pixel includes forming a first portion and a second portion that respectively cover opposite ends of the light transmissive region of the edge pixel.
  • a third portion between the first portion and the second portion is also formed.
  • a ratio of an area of the light shielding block to an area of the edge pixel is set to one of N values constituting an arithmetic progression, wherein 3 ⁇ N ⁇ 101, the The first item of the difference column is 0, and the last item is 100%.
  • an absolute value of a difference between the one of the N values and a desired set value depending on an edge shape of the display area is smaller than other values of the N values The absolute value of the difference from the desired set value.
  • Figure 1 is a schematic view showing the structure of a display device
  • FIG. 2 is a partial schematic view showing an array substrate of the display device shown in FIG. 1;
  • FIG. 3 illustrates a partial schematic view of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates a cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 5 illustrates a cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure
  • FIG. 6 illustrates a cross-sectional view of an array substrate in accordance with still another embodiment of the present disclosure
  • FIG. 7 illustrates a cross-sectional view of an array substrate in accordance with still another embodiment of the present disclosure
  • FIGS. 8A and 8B are diagrams showing the structure of a pixel according to an embodiment of the present disclosure.
  • FIGS. 9A and 9B are diagrams showing the structure of edge pixels according to an embodiment of the present disclosure.
  • FIG. 10 illustrates a flow chart of a method for fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 11 shows a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • an element or layer when an element or layer is referred to as being “on” another element or layer, it may be directly on the other element or layer, or an element or layer may be present; likewise, when the element or layer is When the other element or layer is "under”, it may be directly under the other element or layer, or there may be at least one intermediate element or layer; when the element or layer is referred to as being between the two or two layers It may be a single element or layer between two or two layers, or more than one intermediate element or layer may be present.
  • FIG. 1 shows a schematic view of the structure of a display device.
  • FIG. 2 is a partial schematic view showing an array substrate of the display device shown in FIG. 1.
  • the edge of the display area a of the display device has a rounded shape in a macroscopic view.
  • the pixels b in the display area a are generally rectangular in shape, and the edges of the display area a appear jagged due to the uneven arrangement of the pixels b at the edges. Therefore, at the time of display, the edge of the display area a has a grainy feeling and a sawtooth feeling, which affects the display effect of the display device.
  • FIG. 3 shows a partial schematic view of an array substrate 1 in accordance with an embodiment of the present disclosure.
  • the array substrate 1 may include a substrate 10.
  • the substrate 10 has a display area 100 and a peripheral area 120 surrounding the display area 100.
  • the peripheral area 120 may be disposed corresponding to a black matrix (not shown) on a color filter substrate (not shown).
  • the display area 100 has a plurality of pixels 140 arranged in an array, and the pixels 140 may be disposed corresponding to color blocks (not shown) on the color filter substrate.
  • the pixel 140 includes a light transmissive region 142 and a light blocking region 144.
  • the pixels located outside the display area 100 constitute a plurality of edge pixels 160, that is, pixels close to the peripheral area.
  • the array substrate 1 may further include a light shielding block 20 that covers at least a portion of the light transmitting region 142 of the edge pixel 160 to block transmission of light.
  • the light shielding block 20 covers at least a portion of the light transmitting region 142 of the edge pixel 160 of the array substrate 1, the light transmittance of the edge pixel 160 (ie, the area of the light transmitting region and the area of the light shielding block) The ratio of the difference to the area of the light-transmitting area is reduced, the brightness of the edge pixel 160 is lowered, thereby reducing the acuity of the human eye to capture the edge of the display area having a non-rectangular shape, and finally reducing the presence of particles at the edge of the display area.
  • the sense of sensation and jaggedness enhances the display.
  • FIG. 3 only shows a part of the array substrate having non-rectangular edges.
  • the number of pixels there is no limitation on the number of pixels, and the number of pixels can be set according to actual needs.
  • FIG. 4 illustrates a cross-sectional view of an edge pixel of the array substrate 1 in accordance with one embodiment of the present disclosure.
  • the array substrate 1 may further include a thin film transistor 30 located on the substrate 10 and located in the light shielding region 144.
  • the thin film transistor 30 includes an active layer 320, a gate dielectric layer 340, and a gate electrode 360 which are sequentially disposed on the substrate 10, that is, the thin film transistor 30 has a top gate structure.
  • the material of the active layer may include LTPS (Low Temperature Poly-silicon).
  • the array substrate 1 further includes a light shielding layer 40 between the active layer 320 and the substrate 10, and the light shielding layer 40 can prevent light from being irradiated to the active layer, thereby affecting the performance of the thin film transistor 30.
  • the light shielding block 20 in the light transmitting region 142 of the edge pixel 160 may be disposed in the same layer as the light shielding layer 40.
  • “same layer setting" means that the same film layer is formed. The material of the light shielding layer 40 and the light shielding block 20 can thus be the same.
  • the light shielding layer 40 and the light shielding block 20 can be simultaneously formed by one mask, exposure, and etching process, thereby simplifying the process flow.
  • an insulating layer 50 is further disposed between the light shielding layer 40 and the active layer 320.
  • the process flow can be simplified by arranging the light shielding block 20 in the same layer as the light shielding layer 40.
  • FIG. 5 illustrates a cross-sectional view of an edge pixel of the array substrate 1 in accordance with another embodiment of the present disclosure.
  • the array substrate 1 may further include a thin film transistor 30 located on the substrate 10 and located in the light shielding region 144.
  • the thin film transistor 30 includes an active layer 320, a gate dielectric layer 340, and a gate electrode 360 which are sequentially disposed on the substrate 10.
  • the array substrate 1 further includes a light shielding layer 40 between the active layer 320 and the substrate 10, and an insulating layer 50 disposed between the light shielding layer 40 and the active layer 320.
  • the light blocking block 20 in the light transmitting region 142 of the edge pixel 160 may be disposed in the same layer as the gate electrode 360.
  • the material of the light blocking block 20 and the gate electrode 360 may be the same.
  • the light shielding block 20 and the gate electrode 360 can be simultaneously formed by one masking, exposure, and etching processes, thereby simplifying the process flow.
  • FIG. 6 illustrates a cross-sectional view of an edge pixel of the array substrate 1 in accordance with still another embodiment of the present disclosure.
  • the array substrate 1 may further include a thin film transistor 32 located on the substrate 10 and located in the light shielding region 144.
  • the thin film transistor 32 includes a gate electrode 360, a gate dielectric layer 340, and an active layer 320 which are sequentially disposed on the substrate 10, that is, the thin film transistor 32 has a bottom gate structure.
  • the light blocking block 20 in the light transmitting region 142 of the edge pixel 160 may be disposed in the same layer as the gate electrode 360.
  • the material of the light blocking block 20 and the gate electrode 360 may be the same. In this case, the light shielding block 20 and the gate electrode 360 can be simultaneously formed by one mask, exposure, and etching process, thereby simplifying the process flow.
  • the process flow can be simplified by arranging the light blocking block 20 in the same layer as the gate electrode 360.
  • FIG. 7 illustrates a cross-sectional view of an edge pixel of the array substrate 1 in accordance with still another embodiment of the present disclosure.
  • the array substrate 1 may further include a thin film transistor 34 located on the substrate 10 and located in the light shielding region 144.
  • the thin film transistor 34 includes a gate electrode 360, a gate dielectric layer 340, and an active layer 320 which are sequentially disposed on the substrate 10, that is, the thin film transistor 34 has a bottom gate structure.
  • the thin film transistor 34 may further include a source electrode 382 / a drain electrode 384 disposed on the active layer 320.
  • the light blocking block 20 in the light transmitting region 142 of the edge pixel 160 may be disposed in the same layer as the source electrode 382 / the drain electrode 384.
  • the material of the light blocking block 20 and the source electrode 382 / the drain electrode 384 may be the same.
  • the light shielding block 20 and the source electrode 382/drain electrode 384 can be simultaneously formed by one mask, exposure, and etching process, thereby simplifying the process flow.
  • the process flow can be simplified by arranging the light blocking block 20 in the same layer as the source electrode 382 / drain electrode 384.
  • FIGS. 8A and 8B are schematic diagrams showing the structure of a pixel 140 according to an embodiment of the present disclosure.
  • the pixel 140 and the edge pixel 160 may include three in the light-transmitting region 142.
  • the sub-pixels 1402 may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively, which may be disposed corresponding to corresponding color blocks (not shown) on the color filter substrate.
  • the light blocking block 20 may be disposed in the three sub-pixels 1402 to block the transmission of light.
  • each sub-pixel 1402 may have the same area, so that each sub-pixel 1402 in the same edge pixel 160 has the same light transmittance, avoiding the problem that one of the sub-pixels 1402 is too bright. Causes the generation of chromatic aberration.
  • the light blocking block 20 may include opposite ends of a light transmissive region respectively covering the edge pixel 160.
  • the first portion 202 and the second portion 204 of the portion In this way, the edge pixels 160 can be finely covered to achieve a better display effect.
  • the light blocking block 20 may further include a third portion 206 between the first portion 202 and the second portion 204. In this way, the edge pixels 160 can be further refined to achieve a better display effect.
  • the area size of the light shielding block 20 of each of the edge pixels 160 may be set according to the desired edge shape of the display area 100.
  • the area of each shading block may be different from each other depending on the edge shape, it is necessary to separately design a mask for each shading block, which potentially increases the number of masks.
  • the ratio of the area of the light blocking block 20 of the edge pixel 160 to the area of the edge pixel 160 may be set to one of the N values constituting the arithmetic progression, specifically, 3 ⁇ N ⁇ 101.
  • the first item of the difference series is 0, and the last item is 100%. This setting can reduce the number of reticle in the manufacturing process.
  • N is equal to 9
  • the arithmetic progression may be 0, 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, 87.5%, 100%.
  • an absolute value of a difference between one of the N values and a desired set value depending on an edge shape of the display area may be less than other values of the N values and the desired set value The absolute value of the difference between.
  • the area of the light shielding block 20 of one of the edge pixels 160 to the area of the edge pixel 160 may be The ratio of the area of the edge pixel 160 is set to 62.5%, that is, the value closest to 68% is selected from the above-mentioned arithmetic progression.
  • N is equal to 3
  • the arithmetic progression may be 0, 50%, 100%.
  • N is equal to 4
  • the arithmetic progression may be 0, 33.3%, 66.6%, 100%. It can be understood that the above N values may not constitute an arithmetic progression column, and may be set according to actual needs.
  • FIG. 10 illustrates a flow chart of a method for fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the method for manufacturing an array substrate may include the following steps:
  • S102 forming a light shielding block to cover at least a portion of the light transmissive area of the edge pixel of the substrate.
  • the substrate has a display area and a peripheral area surrounding the display area.
  • the display area has a plurality of pixels arranged in an array, and the pixels include a light transmitting area and a light blocking area.
  • the pixels located outside the display area constitute a plurality of edge pixels.
  • the light blocking block may include a first portion and a second portion respectively covering opposite ends of the light transmitting region of the edge pixel. This allows fine-grained coverage of the edge pixels for better display.
  • the light shielding block further includes a third portion between the first portion and the second portion. This can further refine the edge pixels to achieve a better display.
  • an area size of a light shielding block of each edge pixel may be set according to a desired edge shape of the display area.
  • the ratio of the area of the light blocking block 20 of the edge pixel 160 to the area of the edge pixel 160 may be set to one of N values constituting the arithmetic progression, specifically, 3 ⁇ N ⁇ 101.
  • the first item of the difference series is 0, and the last item is 100%. This setting can reduce the number of reticle in the manufacturing process.
  • N is equal to 9
  • the arithmetic progression may be 0, 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, 87.5%, 100%.
  • N is equal to 3, and the arithmetic progression may be 0, 50%, 100%. In yet another example embodiment, N is equal to 4, and the arithmetic progression may be 0, 33.3%, 66.6%, 100%. It can be understood that the above N values may not constitute an arithmetic progression column, and may be set according to actual needs.
  • the light shielding block covers the light transmissive area of the edge pixel, the light transmittance of the edge pixel is reduced, and the brightness of the edge pixel is reduced, thereby reducing the human eye to capture the edge of the display area having a non-rectangular shape.
  • the acuity finally reduces the problem of graininess and jaggedness at the edges of the display area, improving the display effect.
  • a method for manufacturing an array substrate may further include further forming a thin film transistor on the substrate and in the light shielding region.
  • the step of forming the thin film transistor may include S201 to S206.
  • a method for manufacturing an array substrate may further include further forming a thin film transistor on the substrate and in the light shielding region.
  • the step of forming the thin film transistor may include S301 to S304.
  • S304 patterning the first conductive layer to form a gate electrode in the light shielding region and forming a light shielding block.
  • the method may further include forming a light shielding layer on the substrate and in the light shielding region, and forming a fourth insulating layer on the light shielding layer before S301.
  • the method provided by this embodiment is used in the array substrate shown in FIG. 5 described in the foregoing embodiment, and its structure, function and/or advantages are the same as those of the array substrate in the foregoing embodiment, and More details.
  • a method for manufacturing an array substrate may further include further forming a thin film transistor on the substrate and in the light shielding region.
  • the step of forming the thin film transistor may include S401 to S404.
  • S402 patterning the second conductive layer to form a gate electrode in the light shielding region and forming a light shielding block;
  • a method for fabricating an array substrate may further include further forming a thin film transistor on the substrate and in the light shielding region.
  • the step of forming the thin film transistor may include S501 to S506.
  • S506 patterning a fourth conductive material layer to form source/drain electrodes in the light-shielding region and forming a light-shielding block.
  • the method provided by this embodiment is used for the array substrate shown in FIG. 7 described in the foregoing embodiment, and its structure, function and/or advantages are the same as those of the array substrate in the foregoing embodiment, and More details.
  • FIG. 11 shows a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • the display device 2 according to the present disclosure includes the aforementioned array substrate 1.
  • the light shielding block covering at least a portion of the light-transmitting region of the edge pixel of the array substrate of the display device, the light transmittance of the edge pixel can be reduced, thereby reducing the problem of graininess and jaggedness at the edge of the display region, thereby improving the problem. display effect.

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Abstract

一种阵列基板及其制造方法、显示装置。该阵列基板包括：基板（10），其中，基板（10）具有显示区域（100）和围绕显示区域（100）的周边区域（120），显示区域（100）具有以阵列形式排布的多个像素（140），所述多个像素（140）包括透光区域（142）和遮光区域（144）；以及遮光块（20），覆盖所述多个像素（140）中至少一个靠近周边区域（120）的像素（140）的透光区域（142）的至少一部分。

Description

阵列基板及其制造方法、显示装置
相关申请的交叉引用
本申请要求于2017年12月12日递交的中国专利申请第201711313230.3号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
对于具有不规则形状(例如圆形、圆角、U形等)的全屏显示装置或智能穿戴显示装置，需要显示区域的边缘也为非矩形的不规则形状，这样可以满足用户对显示装置的外形的多样化需求。
发明内容
本发明实施例提供了一种阵列基板及其制造方法、显示装置。
在本公开的第一方面中，提供一种阵列基板。阵列基板包括：基板，所述基板具有显示区域和围绕所述显示区域的周边区域，所述显示区域具有以阵列形式排布的多个像素，所述多个像素包括透光区域和遮光区域，；以及遮光块，覆盖所述多个像素中至少一个靠近周边区域的像素的透光区域的至少一部分。
在本公开的实施例中，所述阵列基板还包括位于所述基板上且位于所述遮光区域的薄膜晶体管，所述薄膜晶体管包括在所述基板上的有源层，所述阵列基板还包括位于所述有源层和所述基板之间的遮光层，其中，所述遮光块与所述遮光层同层设置。
在本公开的实施例中，所述阵列基板还包括位于所述基板上且位于所 述遮光区域的薄膜晶体管，所述薄膜晶体管包括有源层、栅极电极以及所述有源层和所述栅极电极之间的栅极介质层，所述遮光块与所述栅极电极同层设置。
在本公开的实施例中，所述阵列基板还包括位于所述基板上的薄膜晶体管，所述薄膜晶体管包括有源层、栅极电极、所述有源层和所述栅极电极之间的栅极介质层以及设置在所述有源层上的源/漏电极，所述遮光块与所述源/漏电极同层设置。
在本公开的实施例中，所述遮光块包括分别覆盖所述至少一个靠近周边区域的像素的透光区域的相对端部的第一部分和第二部分。
在本公开的实施例中，所述遮光块还包括位于所述第一部分和所述第二部分之间的第三部分。
在本公开的实施例中，所述遮光块的面积与所述边缘像素的面积的比值被设定为构成等差数列的N个值中的一个，其中，3≤N≤101，所述等差数列的首项为0，末项为100％。
在本公开的实施例中，所述N个值中的所述一个与依赖于所述显示区域的边缘形状的希望设定值之间的差的绝对值小于所述N个值中的其他值与所述希望设定值之间的差的绝对值。
在本公开的第二方面中，提供一种显示装置。该显示装置包括在本公开第一方面中所描述的任意一种阵列基板。
在本公开的第三方面中，提供一种用于制造阵列基板的方法，包括：提供基板，所述基板具有显示区域和围绕所述显示区域的周边区域，所述显示区域具有以阵列形式排布的多个像素，所述多个像素包括透光区域和遮光区域；以及形成遮光块以覆盖所述多个像素中至少一个靠近周边区域的像素的透光区域的至少一部分。
在本公开的实施例中，所述方法还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：在所述基板上形成遮光材料层；构图所述遮光材料层以在所述遮光区域中形成遮光层以及 形成所述遮光块；在所述遮光层和所述遮光块上形成第一绝缘层；在所述遮光区域中且在所述第一绝缘层上形成有源层；在所述有源层上形成作为栅极介质层的第二绝缘层；以及在所述遮光区域中且在所述第二绝缘层上形成栅极电极。
在本公开的实施例中，所述方法还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：在所述基板上且在所述遮光区域中形成有源层；在所述有源层上形成作为栅极介质层的第三绝缘层；在所述第三绝缘层上形成第一导电层；以及构图所述第一导电层以在所述遮光区域中形成栅极电极以及形成所述遮光块。
在本公开的实施例中，所述方法还包括在形成所述有源层之前，在所述基板上且在所述遮光区域中形成遮光层，以及在所述遮光层上形成第四绝缘层。
在本公开的实施例中，所述方法还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：在所述基板上形成第二导电层；构图所述第二导电层以在所述遮光区域中形成栅极电极以及形成所述遮光块；在所述栅极电极和所述遮光块上形成第四绝缘层；以及在所述遮光区域中且在所述第四绝缘层上形成有源层。
在本公开的实施例中，所述方法还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：在所述基板上形成第三导电层；构图所述第三导电层以在所述遮光区域中形成栅极电极；在所述栅极电极上形成作为栅极介质层的第五绝缘层；在所述遮光区域中且在所述第五绝缘层上形成有源层；在所述有源层上形成第四导电材料层；以及构图所述第四导电材料层以在所述遮光区域中形成源/漏电极以及形成所述遮光块。
在本公开的实施例中，在所述边缘像素的所述透光区域中形成遮光块包括：形成分别覆盖所述边缘像素的透光区域的相对端部的第一部分和第二部分。
在本公开的实施例中，还形成位于所述第一部分和所述第二部分之间的第三部分。
在本公开的实施例中，所述遮光块的面积与所述边缘像素的面积的比值被设定为构成等差数列的N个值中的一个，其中，3≤N≤101，所述等差数列的首项为0，末项为100％。
在本公开的实施例中，所述N个值中的所述一个与依赖于所述显示区域的边缘形状的希望设定值之间的差的绝对值小于所述N个值中的其他值与所述希望设定值之间的差的绝对值。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在说明的目的，并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1示出了一种显示装置的结构的示意图；
图2示出了图1所示的显示装置的阵列基板的局部示意图；
图3示出了根据本公开实施例的阵列基板的局部示意图；
图4示出了根据本公开一个实施例的阵列基板的截面图；
图5示出了根据本公开另一实施例的阵列基板的截面图；
图6示出了根据本公开又一实施例的阵列基板的截面图；
图7示出了根据本公开再一实施例的阵列基板的截面图；
图8A和8B示出了根据本公开实施例的像素的结构示意图；
图9A和9B示出了根据本公开实施例的边缘像素的结构示意图；
图10示出了根据本公开实施例的用于制造阵列基板的方法的流程图；以及
图11示出了根据本公开的实施例的显示装置的示意图。
具体实施方式
现将参考附图详细描述各种实施例，其作为本公开的示例性示例而提供，以使得本领域技术人员能够实现本公开的技术方案。
值得注意的是，以下附图和示例并不意味着限制本公开的范围。在使用已知的组件(或方法或过程)可以部分或全部实现本公开的特定元件的情况下，将仅描述对理解本公开所需要的这种已知组件(或方法或过程)的那些部分，并且这种已知组件的其它部分的详细描述将被省略以便不会混淆本公开的技术方案。进一步地，各种实施例通过说明的方式包含与在此涉及的组件等同的现在和未来已知的等同物。
本公开中描绘的流程图仅仅是一个例子。在不脱离本公开精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
在本公开的描述中，术语“上”、“之上”、“下”、“之下”、“之间”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，当元件或层被称为在另一元件或层“上”时，它可以直接在该另一元件或层上，或者可以存在中间的元件或层；同样，当元件或层被称为在另一元件或层“下”时，它可以直接在该另一元件或层下，或者可以存在至少一个中间的元件或层；当元件或层被称为在两元件或两层“之间”时，其可以为该两元件或两层之间的唯一的元件或层，或者可以存在一个以上的中间元件或层。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括 相应术语的复数。相似地，用语“包含”、“包括”、“含有”和“具有”及其语法变型旨在包括性的并且表示可以存在除所列要素之外的另外的要素。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
图1示出了一种显示装置的结构的示意图。图2示出了图1所示的显示装置的阵列基板的局部示意图。如图1所示，显示装置的显示区域a的边缘在宏观上具有圆角形状。然而，在微观上，如图2所示，显示区域a中的像素b通常为矩形形状，并且由于像素b在边缘处的排列参差不齐，使得显示区域a的边缘呈现为锯齿状。因此，在显示时，显示区域a的边缘会有颗粒感和锯齿感，影响显示装置的显示效果。
图3示出了根据本公开实施例的阵列基板1的局部示意图。如图3所示，阵列基板1可包括基板10。基板10具有显示区域100和围绕显示区域100的周边区域120。周边区域120可与彩膜基板(未示出)上的黑矩阵(未示出)对应设置。显示区域100具有以阵列形式排布的多个像素140，像素140可与彩膜基板上的彩色阻块(未示出)对应设置。像素140包括透光区域142和遮光区域144。位于显示区域100的外侧的像素构成多个边缘像素160，即，靠近周边区域的像素。根据本公开的实施例，阵列基板1还可包括遮光块20，其覆盖边缘像素160的透光区域142的至少一部分以阻挡光的透过。
根据本公开的实施例，由于遮光块20覆盖阵列基板1的边缘像素160的透光区域142的至少一部分，使得边缘像素160的透光率(即，透光区域的面积与遮光块的面积之差与透光区域的面积的比值)减少，降低了边缘像素160的亮度，从而降低人眼对具有非矩形形状的显示区域的边缘进行捕捉的敏锐度，最终能够减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效果。
需要说明的是，图3仅示出了具有非矩形边缘的阵列基板的一部分。此外，对像素的数量不做限制，可以根据实际需要设定像素的数量。
图4示出了根据本公开一个实施例的阵列基板1的边缘像素的截面图。根据本公开的实施例，阵列基板1还可包括位于基板10上并且位于遮光区域144的薄膜晶体管30。薄膜晶体管30包括在基板10上依次设置的有源层320、栅极介质层340以及栅极电极360，即该薄膜晶体管30为顶栅结构。根据本公开的实施例，该有源层的材料可以包括LTPS(Low Temperature Poly-silicon)。阵列基板1还包括位于有源层320和基板10之间的遮光层40，遮光层40可以避免光线照射到有源层，从而影响薄膜晶体管30的性能。根据本公开的实施例，边缘像素160的透光区域142中的遮光块20可与遮光层40同层设置。需要说明的是，在本公开的实施例中，“同层设置”都是指由同一膜层形成。遮光层40与遮光块20的材料由此可以相同。在该情况下，可以通过一次掩模、曝光、刻蚀工艺同时形成遮光层40与遮光块20，从而简化工艺流程。此外，遮光层40与有源层320之间还设置有绝缘层50。
通过以上描述可以看出，通过在阵列基板1的边缘像素160的透光区域142中设置遮光块20，可以使得边缘像素160的透光率减少，从而减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效果。此外，通过将遮光块20可与遮光层40同层设置，可以简化工艺流程。
图5示出了根据本公开另一实施例的阵列基板1的边缘像素的截面图。根据本公开的实施例，阵列基板1还可包括位于基板10上且位于遮光区域144的薄膜晶体管30。与图4所示的薄膜晶体管30相同，薄膜晶体管30包括在基板10上依次设置的有源层320、栅极介质层340以及栅极电极360。阵列基板1还包括位于有源层320和基板10之间的遮光层40，以及设置在遮光层40与有源层320之间的绝缘层50。根据本公开的实施例，边缘像素160的透光区域142中的遮光块20可与栅极电极360同层设置。遮光块20与栅极电极360的材料可以相同。在该情况下，可以通过一次掩 模、曝光、刻蚀工艺同时形成遮光块20与栅极电极360，从而简化工艺流程。
图6示出了根据本公开又一实施例的阵列基板1的边缘像素的截面图。根据本公开的实施例，阵列基板1还可包括位于基板10上且位于遮光区域144的薄膜晶体管32。薄膜晶体管32包括在基板10上依次设置的栅极电极360、栅极介质层340以及有源层320，即该薄膜晶体管32为底栅结构。根据本公开的实施例，边缘像素160的透光区域142中的遮光块20可与栅极电极360同层设置。遮光块20与栅极电极360的材料可以相同。在该情况下，可以通过一次掩模、曝光、刻蚀工艺同时形成遮光块20与栅极电极360，从而简化工艺流程。
通过以上描述可以看出，通过覆盖阵列基板1的边缘像素160的透光区域142的至少一部分设置遮光块20，可以使得边缘像素160的透光率减少，从而减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效果。此外，通过将遮光块20可与栅极电极360同层设置，可以简化工艺流程。
图7示出了根据本公开再一实施例的阵列基板1的边缘像素的截面图。根据本公开的实施例，阵列基板1还可包括位于基板10上且位于遮光区域144的薄膜晶体管34。薄膜晶体管34包括在基板10上依次设置的栅极电极360、栅极介质层340以及有源层320，即该薄膜晶体管34为底栅结构。根据本公开的实施例，薄膜晶体管34还可包括设置在有源层320上的源电极382/漏电极384。边缘像素160的透光区域142中的遮光块20可与源电极382/漏电极384同层设置。遮光块20与源电极382/漏电极384的材料可以相同。在该情况下，可以通过一次掩模、曝光、刻蚀工艺同时形成遮光块20与源电极382/漏电极384，从而简化工艺流程。
通过以上描述可以看出，通过覆盖阵列基板1的边缘像素160的透光区域142的至少一部分设置遮光块20，可以使得边缘像素160的透光率减少，从而减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效 果。此外，通过将遮光块20可与源电极382/漏电极384同层设置，可以简化工艺流程。
根据本公开的实施例，图8A和8B示出了根据本公开实施例的像素140的结构示意图，如图8A和8B所示，像素140和边缘像素160可包含位于透光区域142中的三个子像素1402。子像素1402可分别是红色子像素、绿色子像素以及蓝色子像素，它们可与彩膜基板上的相应彩色阻块(未示出)对应设置。对于边缘像素160，如图8B所示，遮光块20可设置在三个子像素1402内以阻挡光的透过。具体地，各个子像素1402内的遮光块20可具有相同的面积，从而使得同一个边缘像素160中的各个子像素1402具有相同的透光率，避免其中一个子像素1402出现过亮的问题，导致色差的产生。
根据本公开的实施例，图9A和9B示出了根据本公开实施例的边缘像素160的结构示意图，如图9A所示，遮光块20可包括分别覆盖边缘像素160的透光区域的相对端部的第一部分202和第二部分204。这样可以对边缘像素160进行细化覆盖，以达到更好的显示效果。根据本公开的实施例，如图9B所示，遮光块20还可包括位于第一部分202和第二部分204之间的第三部分206。这样可以对边缘像素160进一步进行细化覆盖，以达到更好的显示效果。
根据本公开的实施例，各个边缘像素160的遮光块20的面积大小可根据所期望的显示区域100的边缘形状来设定。然而，由于每个遮光块的面积可能因依赖于边缘形状而彼此不同，因此需要针对每个遮光块单独设计掩模，这潜在地增加了掩模的数量。为了减小掩模的数量，边缘像素160的遮光块20的面积与该边缘像素160的面积的比值可被设定为构成等差数列的N个值中的一个，具体地，3≤N≤101。该等差数列的首项为0，末项为100％。该设定可以减少制造过程中掩模板的数量。在一个示例实施例中，N等于9，该等差数列可以是0、12.5％、25％、37.5％、50％、62.5％、75％、87.5％、100％。根据本公开的实施例，该N个值中的一个与依赖于 显示区域的边缘形状的希望设定值之间的差的绝对值可以小于该N个值中的其他值与该希望设定值之间的差的绝对值。例如，根据显示区域100的边缘形状，如果其中一个边缘像素160的遮光块20的面积与该边缘像素160的面积的比值应当为68％，则可以将该边缘像素160的遮光块20的面积与该边缘像素160的面积的比值设定为62.5％，即从上述等差数列中选取与68％最接近的值。在另一个示例实施例中，N等于3，该等差数列可以为0、50％、100％。在又一个示例实施例中，N等于4，该等差数列可以是0、33.3％、66.6％、100％。可以理解，上述N个值可以不构成等差数列，可以根据实际需要来设定。
在本公开的另一方面中，提供一种用于制造本文描述的阵列基板的方法。图10示出了根据本公开实施例的用于制造阵列基板的方法的流程图。
用于制造阵列基板的方法可包括以下步骤：
S101：提供基板；
S102：形成遮光块以覆盖基板的边缘像素的透光区域的至少一部分。
在该实施例中，基板具有显示区域和围绕显示区域的周边区域。显示区域具有以阵列形式排布的多个像素，像素包括透光区域和遮光区域。位于显示区域的外侧的像素构成多个边缘像素。
根据本公开的实施例，步骤S102中，遮光块可以包括分别覆盖边缘像素的透光区域的相对端部的第一部分和第二部分。这样可以对边缘像素进行细化覆盖，以达到更好的显示效果。根据本公开的实施例，这遮光块还包括位于第一部分和第二部分之间的第三部分。这样可以对边缘像素进一步进行细化覆盖，以达到更好的显示效果。
根据本公开的实施例，各个边缘像素的遮光块的面积大小可根据所期望的显示区域的边缘形状来设定。边缘像素160的遮光块20的面积与该边缘像素160的面积的比值可被设定为构成等差数列的N个值中的一个，具体地，3≤N≤101。该等差数列的首项为0，末项为100％。该设定可以减少制造过程中掩模板的数量。在一个示例实施例中，N等于9，该等差数 列可以是0、12.5％、25％、37.5％、50％、62.5％、75％、87.5％、100％。在另一个示例实施例中，N等于3，该等差数列可以为0、50％、100％。在又一个示例实施例中，N等于4，该等差数列可以是0、33.3％、66.6％、100％。可以理解，上述N个值可以不构成等差数列，可以根据实际需要来设定。
通过以上描述可以看出，由于遮光块覆盖边缘像素的透光区域，使得边缘像素的透光率减少，降低了边缘像素的亮度，从而降低人眼对具有非矩形形状的显示区域的边缘进行捕捉的敏锐度，最终能够减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效果。
根据本公开的一个实施例，用于制造阵列基板的方法还可包括进一步在基板上且在遮光区域中形成薄膜晶体管。具体地，形成该薄膜晶体管的步骤可包括S201至S206。
S201：在基板上形成遮光材料层；
S202：构图遮光材料层，以在遮光区域中形成遮光层以及形成遮光块；
S203：在遮光层和遮光块上形成第一绝缘层；
S204：在遮光区域中且在第一绝缘层上形成有源层；
S205：在有源层上形成作为栅极介质层的第二绝缘层；
S206：在遮光区域中且在第二绝缘层上形成栅极电极。
该实施例提供的方法用于前述实施例描述的图4示出的阵列基板，其结构、功能和/或优点与前述实施例中的阵列基板的结构、功能和/或优点相同，在此不再详述。
根据本公开的另一实施例，用于制造阵列基板的方法还可包括进一步在基板上且在遮光区域中形成薄膜晶体管。具体地，形成该薄膜晶体管的步骤可包括S301至S304。
S301：在基板上且在遮光区域中形成有源层；
S302：在有源层上形成作为栅极介质层的第三绝缘层；
S303：在第三绝缘层上形成第一导电层；
S304：构图第一导电层以在遮光区域中形成栅极电极以及形成遮光块。
在该实施例中，方法还可包括在S301之前，在基板上且在遮光区域中形成遮光层，以及在遮光层上形成第四绝缘层。
该实施例提供的方法用于前述实施例描述的图5示出的阵列基板，其结构、功能和/或优点与前述实施例中的阵列基板的结构、功能和/或优点相同，在此不再详述。
根据本公开的又一实施例，用于制造阵列基板的方法还可包括进一步在基板上且在遮光区域中形成薄膜晶体管。具体地，形成该薄膜晶体管的步骤可包括S401至S404。
S401：在基板上形成第二导电层；
S402：构图第二导电层以在遮光区域中形成栅极电极以及形成遮光块；
S403：在栅极电极和遮光块上形成第四绝缘层；
S404：在遮光区域中且在第四绝缘层上形成有源层。
该实施例提供的方法用于前述实施例描述的图6示出的阵列基板，其结构、功能和/或优点与前述实施例中的阵列基板的结构、功能和/或优点相同，在此不再详述。
根据本公开的再一实施例，用于制造阵列基板的方法还可包括进一步在基板上且在遮光区域中形成薄膜晶体管。具体地，形成该薄膜晶体管的步骤可包括S501至S506。
S501：在基板上形成第三导电层；
S502：构图第三导电层以在遮光区域中形成栅极电极；
S503：在栅极电极上形成作为栅极介质层的第五绝缘层；
S504：在遮光区域中且在第五绝缘层上形成有源层；
S505：在有源层上形成第四导电材料层；
S506：构图第四导电材料层以在遮光区域中形成源/漏电极以及形成遮光块。
该实施例提供的方法用于前述实施例描述的图7示出的阵列基板，其结构、功能和/或优点与前述实施例中的阵列基板的结构、功能和/或优点相同，在此不再详述。
在本公开的又一方面中，还提供了一种包括前述实施例描述的阵列基板的显示装置。图11示出了根据本公开的实施例的显示装置的示意图。如图11所示，根据本公开的显示装置2包括前述阵列基板1。通过覆盖在显示装置的阵列基板的边缘像素的透光区域的至少一部分设置遮光块，可以使得边缘像素的透光率减少，从而减小显示区域的边缘存在颗粒感和锯齿感的问题，提升了显示效果。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    基板，所述基板具有显示区域和围绕所述显示区域的周边区域，所述显示区域具有以阵列形式排布的多个像素，所述多个像素包括透光区域和遮光区域，以及
    遮光块，覆盖所述多个像素中至少一个靠近周边区域的像素的透光区域的至少一部分。
  2. 根据权利要求1所述的阵列基板，还包括位于所述基板上且位于所述遮光区域的薄膜晶体管，所述薄膜晶体管包括在所述基板上的有源层，所述阵列基板还包括位于所述有源层和所述基板之间的遮光层，其中，所述遮光块与所述遮光层同层设置。
  3. 根据权利要求1所述的阵列基板，还包括位于所述基板上且位于所述遮光区域的薄膜晶体管，所述薄膜晶体管包括有源层、栅极电极以及所述有源层和所述栅极电极之间的栅极介质层，所述遮光块与所述栅极电极同层设置。
  4. 根据权利要求1所述的阵列基板，其中所述显示区域具有非矩形形状。
  5. 根据权利要求1所述的阵列基板，还包括位于所述基板上且位于所述遮光区域的薄膜晶体管，其中，所述薄膜晶体管包括有源层、栅极电极、所述有源层和所述栅极电极之间的栅极介质层以及设置在所述有源层上的源/漏电极，所述遮光块与所述源/漏电极同层设置。
  6. 根据权利要求1-5所述的阵列基板，其中，所述遮光块包括分别覆盖所述至少一个靠近周边区域的像素的透光区域的相对端部的第一部分和第二部分。
  7. 根据权利要求6所述的阵列基板，其中，所述遮光块还包括位于所述第一部分和所述第二部分之间的第三部分。
  8. 根据权利要求1所述的阵列基板，其中，所述遮光块的面积与所述 至少一个靠近周边区域的像素的面积的比值被设定为构成等差数列的N个值中的一个，其中，3≤N≤101，所述等差数列的首项为0，末项为100％。
  9. 根据权利要求8所述的方法，其中，所述N个值中的所述一个与依赖于所述显示区域的边缘形状的希望设定值之间的差的绝对值小于所述N个值中的其他值与所述希望设定值之间的差的绝对值。
  10. 一种显示装置，包括根据权利要求1-9中任一项所述的阵列基板。
  11. 一种用于制造阵列基板的方法，包括：
    提供基板，所述基板具有显示区域和围绕所述显示区域的周边区域，所述显示区域具有以阵列形式排布的多个像素，所述多个像素包括透光区域和遮光区域；以及
    形成遮光块以覆盖所述多个像素中至少一个靠近周边区域的像素的透光区域的至少一部分。
  12. 根据权利要求11所述的方法，还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：
    在所述基板上形成遮光材料层；
    构图所述遮光材料层以在所述遮光区域中形成遮光层以及形成所述遮光块；
    在所述遮光层和所述遮光块上形成第一绝缘层；
    在所述遮光区域中且在所述第一绝缘层上形成有源层；
    在所述有源层上形成作为栅极介质层的第二绝缘层；以及
    在所述遮光区域中且在所述第二绝缘层上形成栅极电极。
  13. 根据权利要求11所述的方法，还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：
    在所述基板上且在所述遮光区域中形成有源层；
    在所述有源层上形成作为栅极介质层的第三绝缘层；
    在所述第三绝缘层上形成第一导电层；以及
    构图所述第一导电层以在所述遮光区域中形成栅极电极以及形成所 述遮光块。
  14. 根据权利要求13所述的方法，还包括在形成所述有源层之前，在所述基板上且在所述遮光区域中形成遮光层，以及在所述遮光层上形成第四绝缘层。
  15. 根据权利要求11所述的方法，还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：
    在所述基板上形成第二导电层；
    构图所述第二导电层以在所述遮光区域中形成栅极电极以及形成所述遮光块；
    在所述栅极电极和所述遮光块上形成第四绝缘层；以及
    在所述遮光区域中且在所述第四绝缘层上形成有源层。
  16. 根据权利要求11所述的方法，还包括在所述基板上且在所述遮光区域中形成薄膜晶体管，其中，形成所述薄膜晶体管包括：
    在所述基板上形成第三导电层；
    构图所述第三导电层以在所述遮光区域中形成栅极电极；
    在所述栅极电极上形成作为栅极介质层的第五绝缘层；
    在所述遮光区域中且在所述第五绝缘层上形成有源层；
    在所述有源层上形成第四导电材料层；以及
    构图所述第四导电材料层以在所述遮光区域中形成源/漏电极以及形成所述遮光块。
  17. 根据权利要求11-16所述的方法，其中，在所述至少一个靠近周边区域的像素的所述透光区域中形成遮光块包括：形成分别覆盖所述至少一个靠近周边区域的像素的所述透光区域的相对端部的第一部分和第二部分。
  18. 根据权利要求17所述的方法，其中，还形成位于所述第一部分和所述第二部分之间的第三部分。
  19. 根据权利要求11所述的方法，其中，设定所述遮光块的面积与所 述至少一个靠近周边区域的像素的面积的比值为构成等差数列的N个值中的一个，其中，3≤N≤101，所述等差数列的首项为0，末项为100％。
  20. 根据权利要求19所述的方法，其中，所述N个值中的所述一个与依赖于所述显示区域的边缘形状的希望设定值之间的差的绝对值小于所述N个值中的其他值与所述希望设定值之间的差的绝对值。
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