WO2017000425A1 - 像素结构、显示面板和像素结构的制作方法 - Google Patents

像素结构、显示面板和像素结构的制作方法 Download PDF

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Publication number
WO2017000425A1
WO2017000425A1 PCT/CN2015/092075 CN2015092075W WO2017000425A1 WO 2017000425 A1 WO2017000425 A1 WO 2017000425A1 CN 2015092075 W CN2015092075 W CN 2015092075W WO 2017000425 A1 WO2017000425 A1 WO 2017000425A1
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Prior art keywords
pixel
common electrode
line
lines
layer
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PCT/CN2015/092075
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English (en)
French (fr)
Inventor
贾纬华
杨海鹏
金在光
尹傛俊
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/113,542 priority Critical patent/US10263017B2/en
Publication of WO2017000425A1 publication Critical patent/WO2017000425A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to a dual gate line driven pixel structure, a display panel including the pixel structure, and a method of fabricating the pixel structure.
  • a double-gate-driven pixel structure in which the number of gate lines is compared with a conventional single-gate-driven pixel structure. Doubled and the number of data lines is reduced by half.
  • a display having such a double gate line driven pixel structure there is a problem in that since adjacent pixels in the same row are driven by gate lines of different rows, pixels of adjacent columns display different gradations, resulting in The display is uneven in brightness and darkness, and since the human eye is most sensitive to green sub-pixel flicker, it feels low grayscale multi-line.
  • the present invention is directed to solving the above technical problems in the prior art.
  • a pixel structure comprising:
  • One data line is disposed between two adjacent pixel units in the first direction, and two gate lines are disposed between two adjacent pixel units in the second direction;
  • Each of the pixel units includes two pixel regions arranged side by side in the first direction, each of the pixel regions includes one pixel electrode, and each of the pixel units includes a common electrode formed to cover the two pixel regions.
  • each of the pixel units includes a first common electrode line extending in a first direction and a second common electrode line extending in a second direction, the first common electrode line and the second common electrode line being mutually connected at an intersection Electrical connection;
  • first common electrode lines of the pixel units adjacent in the first direction are electrically connected to each other, and
  • the second common electrode lines of the pixel cells adjacent in the second direction are electrically connected to each other.
  • the pixel structure includes a first metal layer, a pixel electrode layer, and an insulating layer between the first metal layer and the pixel electrode layer,
  • the first common electrode line, the second common electrode line and the gate line are located in the first metal layer;
  • the pixel electrode is located in the pixel electrode layer
  • the first common electrode lines of the pixel units adjacent in the first direction continuously extend in the first metal layer to be electrically connected to each other;
  • the second common electrode lines of the pixel cells adjacent in the second direction are disconnected by the gate lines, and the second common electrode lines are electrically connected to each other through the connection lines in the pixel electrode layers via via holes in the insulating layer,
  • the connection line spans the gate line between the pixel cells adjacent in the second direction.
  • the connecting line is formed of the same material as the pixel electrode.
  • the first common electrode line, the second common electrode line, and the gate line are formed of the same material.
  • the common electrode is located in a common electrode layer, and the first common electrode line and the second common electrode line are electrically connected to the common electrode.
  • the first common electrode line is disposed at an edge of each pixel unit in a first direction
  • the second common electrode line is disposed at a boundary line between the two pixel regions in the second direction.
  • each pixel region comprises a thin film transistor
  • each thin film transistor is electrically connected to a gate line, and the source of each thin film transistor is electrically connected to one data line, and the drain of each thin film transistor is electrically connected to the pixel electrode of the pixel region in which it is located;
  • the gates of the thin film transistors corresponding to the two pixel regions in each pixel unit are electrically connected to the gate lines on both sides of the pixel unit, respectively.
  • the thin film transistors corresponding to the two pixel regions in each pixel unit are diagonally disposed at the two corners of the pixel unit.
  • the pixel structure further includes a second metal layer formed between the first metal layer and the pixel electrode layer, wherein the data line, the source and the drain of the thin film transistor are located in the second metal In the layer.
  • an insulating layer is respectively disposed between the first metal layer, the second metal layer, and the pixel electrode layer.
  • the first common electrode line and the second common electrode line of each pixel unit are respectively aligned with each other.
  • a display panel comprising the pixel structure of the various embodiments of the first aspect.
  • a method of fabricating a pixel structure including:
  • Forming the first metal layer over the common electrode layer patterning the first metal layer to form a plurality of gate lines extending in parallel in the first direction, a plurality of first common electrode lines extending along the first direction, and along Extended in the second direction a plurality of second common electrode lines, wherein the second direction intersects with the first direction, and the first common electrode line and the second common electrode line are electrically connected to each other at the intersection;
  • the gate line and the data line define a plurality of pixel units
  • One data line is disposed between two adjacent pixel units in the first direction, and two gate lines are disposed between two adjacent pixel units in the second direction;
  • Each of the pixel units includes two pixel regions arranged side by side in the first direction, each of the pixel regions includes one pixel electrode, and each of the pixel units includes a common electrode formed to cover the two pixel regions.
  • each of the pixel units includes a corresponding first common electrode line and a second common electrode line;
  • first common electrode lines of the pixel units adjacent in the first direction are electrically connected to each other, and
  • the second common electrode lines of the pixel cells adjacent in the second direction are electrically connected to each other.
  • the source and drain of the thin film transistor are also formed while patterning the second metal layer to form the data line.
  • the method further includes: patterning the second insulating layer to form a first via hole penetrating the first insulating layer and the second insulating layer and passing through the second insulating layer for connecting the thin film transistor a second via of the drain and the pixel electrode.
  • connection line is also formed, the connection line crossing the gate line between the pixel cells adjacent in the second direction.
  • the first common electrode lines of the pixel cells adjacent in the first direction continuously extend in the first metal layer to be electrically connected to each other;
  • a second common electrode line of the pixel unit adjacent in the second direction is broken by the gate line, and the second common electrode line passes through the first via hole in the first insulating layer and the second insulating layer and via the pixel
  • the connecting lines in the electrode layer are electrically connected to each other.
  • the first common electrode line and the second common electrode line are made to be in conductive contact with the common electrode when the first common electrode line and the second common electrode line are formed.
  • the quality of the product is improved, in particular, the adjacent pixels are gated by different rows.
  • the pixels of adjacent columns caused by the line drive have low gray-scale unevenness and flicker.
  • a common electrode mesh inside the display region is formed in the horizontal and vertical directions, which can effectively reduce the common electrode resistance in the display region and balance the common voltage in the entire display screen. , thereby further improving the quality of the product, especially the phenomenon of greenish, residual images and the like.
  • FIG. 1 is a schematic diagram of a pixel structure in accordance with an embodiment of the present invention.
  • Figure 2 is an enlarged view of one of the pixel units of Figure 1;
  • FIG. 3 is a schematic view showing a positional relationship between a common electrode line and a common electrode of the pixel unit in FIG. 2;
  • FIGS. 4-8 are schematic diagrams showing a process of fabricating the pixel structure of Fig. 1 in accordance with one embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a pixel structure in accordance with one embodiment of the present invention.
  • the pixel structure shown in FIG. 1 includes a plurality of gate lines 1 extending in parallel in the lateral direction (first direction) in the drawing, and a plurality of data lines 2 extending in parallel in the longitudinal direction (second direction) in the drawing.
  • the plurality of gate lines 1 and the plurality of data lines 2 define a plurality of pixel units 3.
  • One data line 2 is disposed between every two pixel units 3 adjacent in the lateral direction
  • two gate lines 1 are disposed between every two pixel units adjacent in the longitudinal direction. Note that only a portion of the pixel unit 3 is shown in FIG. 1, but those skilled in the art will appreciate that the pixel structure shown in FIG. 1 may extend in the lateral and longitudinal directions.
  • FIG. 2 is an enlarged view of one pixel unit 3 of FIG. 1.
  • FIG. 3 is a schematic view showing a positional relationship between a common electrode line and a common electrode of the pixel unit 3 of FIG. 2.
  • each of the pixel units 3 includes two pixel regions 31 and 32 which are arranged side by side in the lateral direction, and each of the pixel regions includes one pixel electrode 30.
  • the pixel electrode 30 may be any one of a red pixel, a green pixel, and a blue pixel.
  • the pixel region 31 may include a red pixel electrode.
  • the pixel region 32 may include a green pixel electrode.
  • each of the pixel units 3 further includes a common electrode 40 integrally formed to cover the two pixel regions 31 and 32, that is, the common electrodes of the two pixel regions 31 and 32 are connected to each other to form an integral body. Common electrode.
  • each of the pixel units 3 includes a first common electrode line 33 extending in the lateral direction and a second common electrode line 34 extending in the longitudinal direction, the first common electrode line 33 and the second common electrode line 34 being The intersections are electrically connected to each other.
  • the first common electrode lines 33 of the pixel units 3 adjacent in the lateral direction are electrically connected to each other, and the second common electrode lines 34 of the pixel units 3 adjacent in the longitudinal direction are also electrically connected to each other.
  • the first common electrode line 33 and the second common electrode line 34 of each pixel unit 3 are respectively aligned with each other, thereby forming a grid-like common electrode line network.
  • FIGS. 4-8 are schematic diagrams showing a process of fabricating the pixel structure of Fig. 1 in accordance with one embodiment of the present invention.
  • the pixel structure as shown in FIG. 1 includes a first metal layer, a pixel electrode layer, and an insulating layer between the first metal layer and the pixel electrode layer.
  • the first common electrode line 33, the second common electrode line 34, and the gate line 1 are located in the first metal layer.
  • the pixel electrode 30 is located in the pixel electrode layer. Accordingly, the first common electrode lines 33 of the pixel units 3 adjacent in the lateral direction continuously extend in the first metal layer to be electrically connected to each other, and the second common electrode lines 34 of the pixel units 3 adjacent in the longitudinal direction are The gate line 1 is turned off (see Fig. 5).
  • the second common electrode lines 34 of the pixel units 3 adjacent in the longitudinal direction may be electrically connected to each other via the via holes 35 (see FIG. 7) in the insulating layer and the connection lines 36 in the pixel electrode layer, the connection lines 36 crossing The gate line 1 between the adjacent pixel cells 3 in the longitudinal direction (see Fig. 8).
  • first common electrode line 33 and the second common electrode line 34 are formed in the same metal layer as the gate line 1, the first common electrode line 33, the second common electrode line 33, and the gate line 1 can be the same conductive. Metal materials such as copper, chromium, and the like are formed by one patterning process. Similarly, since the connection line 36 is formed in the pixel electrode layer, the connection line 36 may be formed by one patterning process together with the pixel electrode 30 by the same material as the pixel electrode 30, according to one embodiment.
  • the pixel structure shown in FIG. 1 further includes a common electrode layer, the common electrode layer being located on a side of the first metal layer opposite to the pixel electrode layer.
  • the common electrode 40 is located in the common electrode layer, and the first common electrode line 33 and the second common electrode line 34 are directly formed on the common electrode 40, and are electrically connected to the common electrode 40 by conductive contact.
  • a first common electrode line 33 is disposed laterally at the edge of each pixel unit 3, according to one embodiment. Although the first common electrode line 33 is illustrated as being disposed at the top edge of the pixel unit 3, it may be disposed at the bottom edge of the pixel unit 3.
  • the second common electrode 34 line is disposed in the longitudinal direction at a boundary line between the two pixel regions 31 and 32.
  • each of the pixel regions 31 and 32 includes a thin film transistor 5, and the gate of each thin film transistor 5 is electrically connected to one gate line 1, and the source of each thin film transistor 5 is One data line 2 is electrically connected, and the drain of each thin film transistor 5 is electrically connected to the pixel electrode 30 of the pixel region 31 or 32 in which it is located.
  • the gates of the thin film transistors 5 in the two pixel regions 31 and 32 in each of the pixel units 3 are electrically connected to the gate lines 1 on both sides of the pixel unit 3, respectively.
  • the gate of the thin film transistor 5 in the pixel region 31 is electrically connected to the gate line 1 on the upper side of the pixel unit 3, and the gate of the thin film transistor 5 in the pixel region 32 and the gate on the lower side of the pixel unit 3 Line 1 is electrically connected.
  • the thin film transistors 5 in the two pixel regions 31 and 32 in each pixel unit 3 are diagonally disposed in the pixel unit 3. Two corners.
  • the thin film transistor 5 in the pixel region 31 is disposed at the upper left corner of the pixel unit 3
  • the thin film transistor 5 of the pixel region 32 is disposed at the lower right corner of the pixel unit 3.
  • the pixel structure shown in FIG. 1 further includes a second metal layer formed between the first metal layer and the pixel electrode layer, the data line 2, the source and drain of the thin film transistor 5 being located In the second metal layer (see Figure 6).
  • a gate insulating layer made of an insulating material such as silicon nitride may be disposed between the first metal layer and the second metal layer, and an insulating material such as silicon nitride may be disposed between the second metal layer and the pixel electrode layer.
  • a passivation layer may be disposed between the first metal layer and the second metal layer, and an insulating material such as silicon nitride may be disposed between the second metal layer and the pixel electrode layer.
  • An embodiment of another aspect of the present invention provides a display panel including the pixel structure according to the foregoing embodiment.
  • the display panel further includes a known structure such as a color filter substrate, and the description thereof is omitted here.
  • the display panel according to the present invention can be used in various display devices such as a television, a computer, a mobile phone, a digital camera, and the like.
  • FIG. 1 The process of fabricating the pixel structure shown in FIG. 1 will be specifically described below with reference to FIGS. 4-8.
  • Figures 4-8 only show some of the steps in the process of making the pixel structure shown in Figure 1, not showing all of the steps.
  • a glass substrate is prepared.
  • a transparent common electrode layer is deposited on the glass substrate, for example by a sputtering method.
  • the material of the common electrode layer may be, for example, materials commonly used in the art such as ITO or IZO.
  • the common electrode layer is patterned by, for example, a photolithography process such as exposure, development, etching, or the like using a mask to form a common electrode pattern as described in FIG.
  • a portion of the common electrode 40 is shown in FIG. 4, however, those skilled in the art will appreciate that the common electrode pattern shown in FIG. 4 may extend in the lateral and longitudinal directions.
  • a conductive first metal layer is formed on the common electrode layer on which the common electrode pattern has been formed by vapor deposition or magnetron sputtering, and the material is, for example, Mo, Cu, Cr, Al, Ag, or the like.
  • the conductive metal layer is patterned by a photolithography process such as exposure, development, etching, etc. by using a mask to form a gate line 1, a gate of a thin film transistor connected to the gate line 1, a first common electrode line 33, and The second common electrode line 34 is as shown in FIG. Among them, two gate lines 1 are formed between the pixel units 3 adjacent in the longitudinal direction.
  • the first common electrode 33 is continuously formed along the top edge of each pixel unit 3, and the second common electrode line 34 extends along a boundary line between the two pixel regions 31 and 32 in each pixel unit. Specifically, the second common electrode line 34 extends along the longitudinal symmetry line of the pixel unit 3, reducing the common resistance in the second direction (see FIG. 3).
  • a gate insulating layer is formed on the patterned first metal layer by chemical vapor deposition (CVD), and the material is, for example, silicon nitride, silicon oxide or the like.
  • a channel layer is formed by chemical vapor deposition on the gate insulating layer, and a second metal layer is formed by magnetron sputtering or the like above the channel layer.
  • the material of the channel layer is, for example, polysilicon, low temperature polysilicon, etc., second metal
  • the material of the layer is, for example, Mo, Al, Cu, Ag, or the like.
  • the channel layer and the second metal layer are patterned by a photolithography process using a semi-transmissive film mask to form a data line 2, a source and a drain of the thin film transistor, and the like, and are formed between adjacent pixel units 3 in the lateral direction.
  • a data line 2 as shown in Figure 6.
  • an insulating passivation layer is formed by chemical vapor deposition on the patterned second metal layer, such as silicon oxide, silicon nitride, or the like.
  • the passivation layer is then patterned by a photolithography process using a mask to form vias 37 for connecting the drain and pixel electrodes of the thin film transistor through the passivation layer and through the passivation layer and gate insulation
  • the via 35 for connecting the second common electrode line 34 is as shown in FIG.
  • a transparent pixel electrode layer is formed on the passivation layer by a process such as evaporation or magnetron sputtering, and the material is, for example, indium oxide, indium tin oxide or other transparent oxide.
  • the pixel electrode layer is patterned by a photolithography process using a mask to form a pattern of the pixel electrode 30 and the connection line 36 connecting the second common electrode line 34, as shown in FIG. So far, the pixel structure shown in FIG. 8 has been basically formed.
  • the pixel structure and the display panel according to the above embodiments of the present invention are advantageous in that the pixel structure of the double gate line driving when the gate signal signal line is doubled is halved for the data signal line, and the common electrode between the adjacent pixels is connected as one.
  • the structure is thus connected to the common electrode between adjacent pixels, thereby balancing the common voltage between adjacent pixels, improving low-gray unevenness and flicker caused by the difference in common voltage of adjacent pixels, thereby improving product quality.
  • the common electrode wire made of the gate metal layer forms a common electrode mesh inside the display region in the horizontal and vertical directions, thereby reducing the overall resistance in the plane and improving the common electrode resistance distribution of the entire display panel, thereby improving the product. Quality, especially the phenomenon of greenish, afterimages.

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Abstract

一种像素结构、显示面板和像素结构的制作方法。所述像素结构，包括：沿第一方向平行延伸的栅极线（1）；沿第二方向平行延伸的数据线（2）；和由栅极线（1）和数据线（2）限定的多个像素单元（3），其中，在第一方向上相邻的两个像素单元（3）之间设置一条数据线（2），在第二方向上相邻的两个像素单元（3）之间设置两条栅极线（1）；并且，每个像素单元（3）包括在第一方向上并排设置的两个像素区域（31，32），每个像素区域（31，32）包括一个像素电极（30），每个像素单元（3）包括覆盖两个像素区域（31，32）且形成为一体的共通电极（40）。通过将每个像素单元（3）中的相邻像素的共通电极（40）形成为一体，能平衡相邻像素间的共通电压，改善因相邻像素共通电压差异引起的低灰阶亮暗不均及闪烁现象。

Description

像素结构、显示面板和像素结构的制作方法
本申请要求于2015年6月29日递交中国专利局的、申请号为201510375221.1的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本发明的实施例涉及显示技术领域，尤其涉及一种双栅线驱动的像素结构、包括该像素结构的显示面板及该像素结构的制作方法。
背景技术
在液晶显示器中，出于降低驱动芯片的数量从而实现成本降低的考虑，已提出一种双栅线驱动的像素结构，其中，与通常的单栅线驱动的像素结构相比，栅线的数量增加一倍，而数据线的数目减少一半。在具有这种双栅线驱动的像素结构的显示器中，存在的一个问题是：由于同一行中相邻的像素由不同行的栅极线驱动，因而相邻列的像素显示不同灰度，造成显示画面亮暗不均，又由于人眼对绿色亚像素闪烁最为敏感，所以感觉低灰阶多线。
发明内容
本发明旨在解决现有技术中的上述技术问题。
根据本发明的一个方面，提供一种像素结构，包括：
沿第一方向平行延伸的多条栅极线；
沿第二方向平行延伸的多条数据线；；和
由栅极线和数据线限定的多个像素单元，
其中，
在第一方向上相邻的两个像素单元之间设置一条数据线，在第二方向上相邻的两个像素单元之间设置两条栅极线；并且
其中，每个像素单元包括在第一方向上并排设置的两个像素区域，每个像素区域包括一个像素电极，每个像素单元包括覆盖两个像素区域的形成为一体的共通电极。
根据一个实施例，每个像素单元包括沿第一方向延伸的第一共通电极线和沿第二方向延伸的第二共通电极线，第一共通电极线和第二共通电极线在交叉点处相互电连接；且
其中，在第一方向上相邻的像素单元的第一共通电极线相互电连接，且
在第二方向上相邻的像素单元的第二共通电极线相互电连接。
根据一个实施例，所述的像素结构，包括第一金属层、像素电极层以及位于第一金属层和像素电极层之间的绝缘层，
其中，第一共通电极线、第二共通电极线与栅极线位于第一金属层中；
所述像素电极位于所述像素电极层中；
在第一方向上相邻的像素单元的第一共通电极线在第一金属层中连续延伸以相互电连接；
在第二方向上相邻的像素单元的第二共通电极线被栅极线断开，且第二共通电极线经由绝缘层中的过孔通过像素电极层中的连接线相互电连接，所述连接线跨过在第二方向上相邻的像素单元之间的栅极线。
根据一个实施例，所述连接线由与像素电极相同的材料形成。
根据一个实施例，第一共通电极线、第二共通电极线与栅极线由相同的材料形成。
根据一个实施例，所述的像素结构，所述共通电极位于共通电极层中，所述第一共通电极线和第二共通电极线与共通电极电连接。
根据一个实施例，第一共通电极线沿第一方向设置在每个像素单元的边缘处；
第二共通电极线沿第二方向设置在两个像素区域之间的分界线处。
根据一个实施例，每个像素区域包括一个薄膜晶体管，
每个薄膜晶体管的栅极与一条栅极线电连接，每个薄膜晶体管的源极与一条数据线电连接，每个薄膜晶体管的漏极与其所在像素区域的像素电极电连接；
每个像素单元中的两个像素区域对应的薄膜晶体管的栅极分别与所述像素单元两侧的栅极线电连接。
根据一个实施例，每个像素单元中的两个像素区域对应的薄膜晶体管对角地设置在像素单元的两个角部。
根据一个实施例，所述的像素结构，还包括形成在第一金属层和像素电极层之间的第二金属层，所述数据线、所述薄膜晶体管的源极和漏极位于第二金属层中。
根据一个实施例，在第一金属层、第二金属层和像素电极层之间分别设置有绝缘层。
根据一个实施例，各个像素单元的第一共通电极线和第二共通电极线分别相互对齐。
根据本发明的另一方面，提供一种显示面板，包括第一方面的各个实施例所述的像素结构。
根据本发明的另一方面，提供一种像素结构的制作方法，包括：
提供一基板；
在基板上方形成共通电极层，图案化共通电极层，以形成共通电极；
在共通电极层上方形成所述第一金属层，图案化第一金属层，以形成沿第一方向平行延伸的多条栅极线、沿第一方向延伸的多条第一共通电极线和沿第二方向延伸的 多条第二共通电极线，其中，第二方向与第一方向交叉，第一共通电极线和第二共通电极线在交叉点处相互电连接；
在第一金属层上方形成第一绝缘层；
在第一绝缘层上方形成第二金属层，图案化第二金属层，以形成沿第二方向平行延伸的多条数据线；
在第二金属层上方形成第二绝缘层；和
在第二绝缘层上方形成透明的像素电极层，图案化像素电极层，以形成像素电极；
其中，所述栅极线和所述数据线限定多个像素单元，
在第一方向上相邻的两个像素单元之间设置一条数据线，在第二方向上相邻的两个像素单元之间设置两条栅极线；并且
其中，每个像素单元包括在第一方向上并排设置的两个像素区域，每个像素区域包括一个像素电极，每个像素单元包括覆盖两个像素区域的形成为一体的一个共通电极。
根据一个实施例，每个像素单元包括相应的第一共通电极线和第二共通电极线；且
其中，在第一方向上相邻的像素单元的第一共通电极线相互电连接，且
在第二方向上相邻的像素单元的第二共通电极线相互电连接。
根据一个实施例，在图案化第二金属层以形成数据线的同时，还形成薄膜晶体管的源极和漏极。
根据一个实施例，所述方法还包括：图案化第二绝缘层，以形成穿过第一绝缘层和第二绝缘层的第一过孔和穿过第二绝缘层的用于连接薄膜晶体管的漏极与像素电极的第二过孔。
根据一个实施例，在图案化像素电极层以形成像素电极的同时，还形成连接线，所述连接线跨过在第二方向上相邻的像素单元之间的栅极线。
根据一个实施例，在第一方向上相邻的像素单元的第一共通电极线在第一金属层中连续延伸以相互电连接；
在第二方向上相邻的像素单元的第二共通电极线被栅极线断开，且第二共通电极线通过第一绝缘层和第二绝缘层中的所述第一过孔并经由像素电极层中的所述连接线相互电连接。
根据一个实施例，在形成第一共通电极线和第二共通电极线时，使得第一共通电极线和第二共通电极线与共通电极导电接触。
根据本发明的实施例，通过将每个像素单元中的相邻像素的共通电极连接起来，从而平衡相邻像素间的共通电压，改善产品的品质，特别是相邻像素由不同行的栅极线驱动引起的相邻列的像素低灰阶亮暗不均及闪烁现象。
进一步地，通过设计在横向和纵向上相互电连接的共通电极线，在横竖向上构成显示区域内部的共通电极网，能够有效降低显示区域内的共通电极电阻，平衡整个显示屏面内的共通电压，从而进一步改善产品的品质，特别是泛绿(Greenish)、残像等现象。
为了使本发明的目的、特征及优点能更加明显易懂，下面结合附图和具体实施例对本发明作进一步说明。
附图说明
图1是根据本发明的一个实施例的像素结构的示意图；
图2是图1中的一个像素单元的放大图；
图3是显示图2中的像素单元的共通电极线和共通电极的位置关系的示意图；以及
图4-8是显示根据本发明的一个实施例的制作图1的像素结构的过程的示意图。
具体实施方式
在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。另外，说明书中所采用的表述“……设置在……上”可以是一部件设置在另一部件的直接上方，也可能是一部件设置在另一部件的上方，并且在两个部件之间存在中间层。
图1是根据本发明的一个实施例的像素结构的示意图。如图1所示的像素结构包括沿图中的横向方向(第一方向)平行延伸的多条栅极线1，沿图中的纵向方向(第二方向)平行延伸的多条数据线2。所述多条栅级线1和所述多条数据线2限定多个像素单元3。在横向上相邻的每两个像素单元3之间设置一条数据线2，在纵向上相邻的每两个像素单元之间设置两条栅极线1。注意，图1中仅示出了部分像素单元3，但本领域技术人员应当理解，图1中所示的像素结构可以在横向和纵向上延伸。
图2是图1中的一个像素单元3的放大图；图3是显示图2中的像素单元3的共通电极线和共通电极的位置关系的示意图。如图2所示，每个像素单元3包括在横向上并排设置的两个像素区域31和32，每个像素区域包括一个像素电极30。像素电极30可以为红色像素、绿色像素和蓝色像素中的任一个。例如，像素区域31可以包括红色像素电极。像素区域32可以包括绿色像素电极。
如图3所示，每个像素单元3还包括覆盖两个像素区域31和32的形成为一体的一个共通电极40，即两个像素区域31和32的共通电极相互连接，形成为一个整体的共通电极。
另外，如图3所示，每个像素单元3包括沿横向延伸的第一共通电极线33和沿纵向延伸的第二共通电极线34，第一共通电极线33和第二共通电极线34在交叉点处相互电连接。
如图1所示，在横向上相邻的像素单元3的第一共通电极线33相互电连接，且在纵向上相邻的像素单元3的第二共通电极线34也相互电连接。根据图1所示的实施例，各个像素单元3的第一共通电极线33和第二共通电极线34分别相互对齐，从而形成网格状的共通电极线网络。
图4-8是显示根据本发明的一个实施例的制作图1的像素结构的过程的示意图。
根据一个实施例，如图1所示的像素结构包括第一金属层、像素电极层以及位于第一金属层和像素电极层之间的绝缘层。第一共通电极线33、第二共通电极线34与栅极线1位于第一金属层中。像素电极30位于所述像素电极层中。相应地，在横向上相邻的像素单元3的第一共通电极线33在第一金属层中连续延伸以相互电连接，而在纵向上相邻的像素单元3的第二共通电极线34被栅极线1断开(参见图5)。在纵向上相邻的像素单元3的第二共通电极线34可经由绝缘层中的过孔35(参见图7)和像素电极层中的连接线36相互电连接，所述连接线36跨过在纵向上相邻的像素单元3之间的栅极线1(参见图8)。
由于第一共通电极线33、第二共通电极线34与栅极线1形成在同一金属层中，因此，第一共通电极线33、第二共通电极线33与栅极线1可由相同的导电金属材料例如铜、铬等通过一次构图工艺形成。类似地，由于连接线36形成在像素电极层中，因此，根据一个实施例，连接线36可由与像素电极30相同的材料例如ITO与像素电极30一起通过一次构图工艺形成。
根据本发明的一个实施例，图1所示的像素结构还包括共通电极层，所述共通电极层位于第一金属层的与像素电极层相反的一侧。参见图3和4，共通电极40位于共通电极层中，所述第一共通电极线33和第二共通电极线34直接形成在共通电极40上，与共通电极40通过导电接触而形成电连接。
参见图1-3，特别是图3，根据一个实施例，第一共通电极线33沿横向设置在每个像素单元3的边缘处。虽然图中所示为第一共通电极线33设置在像素单元3的顶部边缘，但也可以设置在像素单元3的底部边缘。第二共通电极34线沿纵向设置在两个像素区域31和32之间的分界线处。
如图1、2和6所示，每个像素区域31和32各自包括一个薄膜晶体管5，每个薄膜晶体管5的栅极与一条栅极线1电连接，每个薄膜晶体管5的源极与一条数据线2电连接，每个薄膜晶体管5的漏极与其所在像素区域31或32的像素电极30电连接。 每个像素单元3中的两个像素区域31和32中的薄膜晶体管5的栅极分别与所述像素单元3两侧的栅极线1电连接。例如，像素区域31中的薄膜晶体管5的栅极与像素单元3上侧的栅极线1电连接，而像素区域32中的薄膜晶体管5的栅极与所述像素单元3下侧的栅极线1电连接。
如图2所示，为便于连接栅级线1和数据线2，根据一个实施例，每个像素单元3中的两个像素区域31和32中的薄膜晶体管5对角地设置在像素单元3的两个角部。例如，像素区域31中的薄膜晶体管5设置在像素单元3的左上角，像素区域32的薄膜晶体管5设置在像素单元3的右下角。
根据一个实施例，图1所示的像素结构还包括形成在第一金属层和像素电极层之间的第二金属层，所述数据线2、所述薄膜晶体管5的源极和漏极位于第二金属层中(参见图6)。
在第一金属层和第二金属层之间可以设置例如氮化硅等绝缘材料制成的栅级绝缘层，在第二金属层和像素电极层之间可以设置例如氮化硅等绝缘材料制成的钝化层。
本发明另一方面的实施例提供一种显示面板，包括根据前述实施例的像素结构。所述显示面板还包括彩膜基板等已知结构，在这里省略其说明。根据本发明的显示面板，可以用于各种显示设备中，例如电视机、电脑、手机、数码相机等。
以下参照图4-8具体说明制作图1所示的像素结构的过程。图4-8只是示出了制作图1所示的像素结构的过程的一些步骤，并未示出全部步骤。
首先，制备一块玻璃基板。在该玻璃基板上例如通过溅射方法沉积一层透明的共通电极层。共通电极层的材料例如可以为ITO、IZO等本领域常用的材料。然后，例如利用掩模板，通过曝光、显影、刻蚀等光刻工艺图案化所述共通电极层，形成如图4所述的共通电极图案。图4中示出了部分共通电极40，但是，本领域技术人员可以理解，图4所示的共通电极图案可以在横向和纵向上延伸。
接着，在已经形成共通电极图案的共通电极层上通过蒸镀或磁控溅射等工艺制作一层导电的第一金属层，材料例如为Mo、Cu、Cr、Al、Ag等。例如利用掩模板，通过曝光、显影、刻蚀等光刻工艺图案化所述导电金属层，形成栅极线1、与栅极线1连接的薄膜晶体管的栅极、第一共通电极线33和第二共通电极线34，如图5所示。其中，在纵向上相邻的像素单元3之间形成两条栅极线1。第一共通电极33沿着各像素单元3的顶部边缘连续地形成，第二共通电极线34沿着每个像素单元中的两个像素区域31和32之间的分界线延伸。具体地，第二共通电极线34沿像素单元3的纵向对称线延伸，降低第二方向上的共通电阻(参见图3)。
接着，在图案化的第一金属层上通过化学气相沉积(CVD)制作一层栅极绝缘层，材料例如为氮化硅、氧化硅等。
接着，在栅极绝缘层上通过化学气相沉积制作沟道层，并在沟道层上方通过磁控溅射等方法制作第二金属层。沟道层的材料例如为多晶硅、低温多晶硅等，第二金属 层的材料例如为Mo、Al、Cu、Ag等。然后利用半透膜掩模板，通过光刻工艺图案化所述沟道层及第二金属层，形成数据线2和薄膜晶体管的源漏极等，在横向上相邻的像素单元3之间形成一条数据线2，如图6所示。
接着，在图案化的第二金属层上通过化学气相沉积制作绝缘的钝化层，材料例如为氧化硅、氮化硅等。然后利用掩模板，通过光刻工艺图案化所述钝化层，以形成穿过钝化层的用于连接薄膜晶体管的漏极和像素电极的过孔37以及穿过钝化层和栅极绝缘层的用于连接第二共通电极线34的过孔35，如图7所示。
接着，在钝化层上通过蒸镀或磁控溅射等工艺制作一层透明的像素电极层，材料例如为氧化铟、氧化铟锡或其他透明氧化物等。然后利用掩模板，通过光刻工艺图案化所述像素电极层，形成像素电极30和连接第二共通电极线34的连接线36的图案，如图8所示。至此，基本上形成了图8所示的像素结构。
根据本发明上述实施例的像素结构和显示面板的优点在于：针对数据信号线减半，栅极驱动信号线加倍时的双栅线驱动的像素结构，将相邻像素间的共通电极连接为一体结构，从而，通过相邻像素间共通电极相连，能平衡相邻像素间的共通电压，改善因相邻像素共通电压差异引起的低灰阶亮暗不均及闪烁现象，从而改善产品的品质。
另一方面，通过栅极金属层制成的共通电极线，在横竖向上构成显示区域内部的共通电极网，能够降低面内的整体电阻，改善显示面板整体的共通电极电阻分布，从而改善产品的品质，特别是泛绿(Greenish)、残像等现象。
上述实施例仅示例性的说明了本发明的原理及构造，而非用于限制本发明，本领域的技术人员应明白，在不偏离本发明的总体构思的情况下，对本发明所作的任何改变和改进都在本发明的范围内。本发明的保护范围，应如本申请的权利要求书所界定的范围为准。应注意，措词“包括”不排除其它元件或步骤，措词“一”或“一个”不排除多个。另外，权利要求的任何元件标号不应理解为限制本发明的范围。

Claims (20)

  1. 一种像素结构，包括：
    沿第一方向平行延伸的多条栅极线；
    沿第二方向平行延伸的多条数据线；和
    由栅极线和数据线限定的多个像素单元，
    其中，
    在第一方向上相邻的两个像素单元之间设置一条数据线，在第二方向上相邻的两个像素单元之间设置两条栅极线；并且
    其中，每个像素单元包括在第一方向上并排设置的两个像素区域，每个像素区域包括一个像素电极，每个像素单元包括覆盖两个像素区域的形成为一体的共通电极。
  2. 根据权利要求1所述的像素结构，其中，
    每个像素单元包括沿第一方向延伸的第一共通电极线和沿第二方向延伸的第二共通电极线，第一共通电极线和第二共通电极线在交叉点处相互电连接；且
    其中，在第一方向上相邻的像素单元的第一共通电极线相互电连接，且
    在第二方向上相邻的像素单元的第二共通电极线相互电连接。
  3. 根据权利要求2所述的像素结构，包括第一金属层、像素电极层以及位于第一金属层和像素电极层之间的绝缘层，
    其中，第一共通电极线、第二共通电极线与栅极线位于第一金属层中；
    所述像素电极位于所述像素电极层中；
    在第一方向上相邻的像素单元的第一共通电极线在第一金属层中连续延伸以相互电连接；
    在第二方向上相邻的像素单元的第二共通电极线被栅极线断开，且在第二方向上相邻的像素单元的第二共通电极线经由绝缘层中的过孔通过像素电极层中的连接线相互电连接，所述连接线跨过在第二方向上相邻的像素单元之间的栅极线。
  4. 根据权利要求3所述的像素结构，其中，所述连接线由与像素电极相同的材料形成。
  5. 根据权利要求3所述的像素结构，其中，第一共通电极线、第二共通电极线与栅极线由相同的材料形成。
  6. 根据权利要求3所述的像素结构，其中，所述共通电极位于共通电极层中，所述第一共通电极线和第二共通电极线与共通电极电连接。
  7. 根据权利要求2-6任一项所述的像素结构，其中，
    第一共通电极线沿第一方向设置在每个像素单元的边缘处；
    第二共通电极线沿第二方向设置在两个像素区域之间的分界线处。
  8. 根据权利要求6所述的像素结构，其中，
    每个像素区域包括一个薄膜晶体管，
    每个薄膜晶体管的栅极与一条栅极线电连接，每个薄膜晶体管的源极与一条数据线电连接，每个薄膜晶体管的漏极与其所在像素区域的像素电极通过过孔实现电连接；
    每个像素单元中的两个像素区域对应的薄膜晶体管的栅极分别与所述像素单元两侧的栅极线电连接。
  9. 根据权利要求8所述的像素结构，其中，
    每个像素单元中的两个像素区域对应的薄膜晶体管对角地设置在像素单元的两个角部。
  10. 根据权利要求8所述的像素结构，还包括形成在第一金属层和像素电极层之间的第二金属层，所述数据线、所述薄膜晶体管的源极和漏极位于第二金属层中。
  11. 根据权利要求10所述的像素结构，在第一金属层、第二金属层和像素电极层之间分别设置有绝缘层。
  12. 根据权利要求2所述的像素结构，其中，
    各个像素单元的第一共通电极线和第二共通电极线分别相互对齐。
  13. 一种显示面板，包括如权利要求1-12中任一项所述的像素结构。
  14. 一种像素结构的制作方法，包括：
    提供一基板；
    在基板上方形成共通电极层，图案化共通电极层，以形成共通电极；
    在共通电极层上方形成所述第一金属层，图案化第一金属层，以形成沿第一方向平行延伸的多条栅极线、沿第一方向延伸的多条第一共通电极线和沿第二方向延伸的多条第二共通电极线，其中，第一共通电极线和第二共通电极线在交叉点处相互电连接；
    在第一金属层上方形成第一绝缘层；
    在第一绝缘层上方形成第二金属层，图案化第二金属层，以形成沿第二方向平行延伸的多条数据线；
    在第二金属层上方形成第二绝缘层；和
    在第二绝缘层上方形成透明的像素电极层，图案化像素电极层，以形成像素电极；
    其中，
    所述栅极线和所述数据线限定多个像素单元，
    在第一方向上相邻的两个像素单元之间设置一条数据线，在第二方向上相邻的两个像素单元之间设置两条栅极线；并且
    其中，每个像素单元包括在第一方向上并排设置的两个像素区域，每个像素区域包括一个像素电极，每个像素单元包括覆盖两个像素区域的形成为一体的共通电极。
  15. 根据权利要求14所述的方法，其中，
    每个像素单元包括相应的第一共通电极线和第二共通电极线；且
    其中，在第一方向上相邻的像素单元的第一共通电极线相互电连接，且
    在第二方向上相邻的像素单元的第二共通电极线相互电连接。
  16. 根据权利要求15所述的方法，其中，在图案化第二金属层以形成数据线的同时，还形成薄膜晶体管的源极和漏极。
  17. 根据权利要求16所述的方法，还包括：图案化第二绝缘层，以形成穿过第一绝缘层和第二绝缘层的第一过孔和穿过第二绝缘层的用于连接薄膜晶体管的漏极与像素电极的第二过孔。
  18. 根据权利要求17所述的方法，其中，在图案化像素电极层以形成像素电极的同时，还形成连接线，所述连接线跨过在第二方向上相邻的像素单元之间的栅极线。
  19. 根据权利要求18所述的方法，其中，
    在第一方向上相邻的像素单元的第一共通电极线在第一金属层中连续延伸以相互电连接；
    在第二方向上相邻的像素单元的第二共通电极线被栅极线断开，且第二共通电极线通过第一绝缘层和第二绝缘层中的所述第一过孔并经由像素电极层中的所述连接线相互电连接。
  20. 根据权利要求19所述的方法，其中，在形成第一共通电极线和第二共通电极线时，使得第一共通电极线和第二共通电极线与共通电极导电接触。
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