WO2018201776A1 - 阵列基板及其制作方法、液晶显示面板和显示装置 - Google Patents

阵列基板及其制作方法、液晶显示面板和显示装置 Download PDF

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Publication number
WO2018201776A1
WO2018201776A1 PCT/CN2018/076657 CN2018076657W WO2018201776A1 WO 2018201776 A1 WO2018201776 A1 WO 2018201776A1 CN 2018076657 W CN2018076657 W CN 2018076657W WO 2018201776 A1 WO2018201776 A1 WO 2018201776A1
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Prior art keywords
substrate
data line
layer
pixel electrodes
array substrate
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PCT/CN2018/076657
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English (en)
French (fr)
Inventor
许志财
毕瑞琳
郭建东
刘珠林
张手强
张逵
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/328,719 priority Critical patent/US20190196288A1/en
Publication of WO2018201776A1 publication Critical patent/WO2018201776A1/zh
Priority to US16/892,918 priority patent/US11073734B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • Embodiments of the present disclosure generally relate to the field of display technologies, and in particular, to an array substrate, a method of fabricating the same, a liquid crystal display panel, and a display device.
  • Liquid crystal display has the advantages of light weight, thin thickness, low power consumption, easy driving, and no harmful rays. It has been widely used in modern information equipment such as TVs, notebook computers, mobile phones, and personal digital assistants. , has a broad development prospects. For individual users, the surface display has a better viewing experience and display than a flat display. Therefore, the curved liquid crystal display panel technology is an important development direction of the liquid crystal display panel.
  • a twisted nematic (TN) type liquid crystal display panel is formed by rotating liquid crystal between the array substrate and the counter substrate by 90 degrees.
  • the normally white mode liquid crystal display panel when a black screen is displayed, the light leakage phenomenon in the non-display area causes the contrast of the image to decrease.
  • the twisted nematic liquid crystal display panel can avoid light leakage in the normally white mode due to the distribution pattern of the liquid crystal, so that the twisted nematic liquid crystal display panel has a great advantage in surface display.
  • the curved liquid crystal display panel technology needs to bend the liquid crystal display panel. During the bending process, the opposite substrate and the array substrate of the liquid crystal panel are easily displaced, resulting in light leakage of the liquid crystal display panel. In the prior art, light leakage is prevented by increasing the size of the black matrix, which tends to lower the aperture ratio of the liquid crystal display panel.
  • An array substrate provided by the embodiment of the present disclosure includes: a substrate substrate, a data line disposed on the substrate substrate, and a pixel electrode layer disposed on the layer where the data line is located;
  • the pixel electrode layer includes a plurality of columns of pixel electrodes spaced apart from each other;
  • An orthographic projection of the data line on the substrate substrate covers an orthographic projection of a gap between two adjacent columns of the pixel electrodes on the substrate, and a width of the data line is greater than the adjacent The width of the gap between the two columns of the pixel electrodes.
  • an orthographic projection of the data line on the substrate substrate covers an orthographic projection of two adjacent columns of the pixel electrode on the substrate substrate.
  • the orthographic projection of the data line on the base substrate has the same width as the overlapping area of the orthographic projections of two adjacent columns of the pixel electrodes on the substrate.
  • the array substrate further includes: a color resist layer disposed between the layer where the data line is located and the pixel electrode layer.
  • the array substrate further includes: a flat layer disposed between the color resist layer and the pixel electrode layer.
  • the array substrate further includes: a gate line extending in the first direction between the substrate and the layer where the data line is located, and a plurality of strips disposed in the same layer as the gate line a common electrode line and a plurality of second common electrode lines, wherein the plurality of first common electrode lines extend in the first direction, and the plurality of second common electrode lines extend in the second direction, the first direction being orthogonal to the second direction.
  • each of the second common electrode lines is in one-to-one correspondence with each of the column of pixel electrodes.
  • An orthographic projection of each of the second common electrode lines on the base substrate is located at a midline position of an orthographic projection of the column of the pixel electrodes on the substrate.
  • the embodiment of the present disclosure further provides a liquid crystal display panel including the above array substrate and a counter substrate disposed opposite to the array substrate.
  • the liquid crystal display panel further includes: a black matrix disposed on a side of the opposite substrate facing the array substrate; or
  • a black matrix disposed on a side of the array substrate facing the opposite substrate, and the black matrix is located at a gap between the color resists in the color resist layer.
  • the embodiment of the present disclosure further provides a display device including the above liquid crystal display panel.
  • the embodiment of the present disclosure further provides a method for fabricating the above array substrate, including:
  • a pixel electrode layer including a plurality of columns of pixel electrodes spaced apart from each other;
  • An orthographic projection of the data line on the substrate substrate covers an orthographic projection of a gap between two adjacent columns of the pixel electrodes on the substrate, and a width of the data line is greater than the adjacent The width of the gap between the two columns of the pixel electrodes.
  • the method before the pixel electrode layer including the plurality of pixel electrodes spaced apart from each other is formed on the layer of the data line, the method further includes:
  • a color resist layer is formed on the layer where the data line is located.
  • the method before the pixel electrode layer including the plurality of columns of pixel electrodes spaced apart from each other is formed on the layer where the data line is located, and at the layer where the data line is located, the method further includes: forming a flat layer on the color resist layer.
  • the method before forming the data line on the base substrate, the method further includes:
  • a gate line extending along the first direction on the substrate, and a plurality of first common electrode lines and a plurality of second common electrode lines, wherein the plurality of first common electrode lines extend along the first direction, and The second common electrode line extends in the second direction, and the first direction and the second direction are orthogonal;
  • Each of the second common electrode lines is in one-to-one correspondence with each of the column of pixel electrodes
  • An orthographic projection of each of the second common electrode lines on the base substrate is located at a midline position of an orthographic projection of the column of the pixel electrodes on the substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing a relative position relationship between a second common electrode line and a pixel electrode in an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a flow chart of fabricating an array substrate according to an embodiment of the present disclosure
  • 4a to 4g are schematic structural views of the method for fabricating the array substrate shown in FIG. 3 after performing the respective steps;
  • FIG. 5 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present disclosure.
  • each film layer in the drawings does not reflect its true proportion in the array substrate or the liquid crystal display panel, and the purpose is only to schematically illustrate the present disclosure.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 1 , comprising: a substrate substrate 101 , a data line 102 disposed on the substrate substrate 101 , and a pixel electrode layer 103 disposed above the layer where the data line 102 is located ;among them,
  • the pixel electrode layer 103 includes a plurality of columns of pixel electrodes 1031 spaced apart from each other;
  • the orthographic projection of the data line 102 on the base substrate 101 covers the orthographic projection of the gap between the adjacent two columns of pixel electrodes on the base substrate 101, and the width a of the data line 102 is larger than that of the adjacent two columns of pixel electrodes.
  • the orthographic projection of the data line 102 on the substrate substrate 101 covers the orthographic projection of the gap between the adjacent two columns of pixel electrodes on the substrate 101, and the data line
  • the width a of the 102 is greater than the width b of the gap between the adjacent two columns of pixel electrodes, so that the longitudinal electric field line of the direction between the data line 102 and the pixel electrode 1031 from the array substrate to the opposite substrate can be formed.
  • the base substrate 101 may be a flexible substrate substrate, such as polyethylene ether phthalate, polyethylene naphthalate, polycarbonate, polyfang.
  • a plastic substrate having excellent heat resistance and durability such as a base compound, a polyetherimide, a polyether sulfone, or a polyimide; or a rigid substrate, such as a glass substrate, is not limited herein.
  • the orthographic projection of the data lines 102 on the base substrate 101 may partially cover the orthographic projection of the adjacent two columns of pixel electrodes on the base substrate 101 so as not to affect normal display.
  • the orthogonal projection of the data line 102 on the base substrate 101 has the same overlapping area as the orthographic projection of the adjacent two columns of pixel electrodes on the base substrate 101.
  • the width c which simplifies the process.
  • the orthogonal projection of the data line 102 on the base substrate 101 and the orthogonal projection of the adjacent two columns of pixel electrodes on the base substrate 101 may also have different widths. This is not limited.
  • an overlapping region between the data line 102 and the pixel electrode 1031 in the array substrate may cause data.
  • a certain capacitance is formed between the line 102 and the pixel electrode 1031 in the overlapping region, and the capacitance may cause a certain degree of interference to the stable voltage on the pixel electrode 1031, thereby affecting the display effect.
  • the array substrate provided according to an embodiment of the present disclosure may further include: a color resist layer 104 disposed between the layer where the data line 102 is located and the pixel electrode layer 103.
  • the distance between the data line 102 and the pixel electrode 1031 is increased, thereby reducing the capacitance between the two, reducing the risk of the capacitance between the two disturbing the stable voltage on the pixel electrode 1031.
  • the color resist layer 104 is disposed on the array substrate, and the problem that the color resist layer 104 and the pixel electrode 1031 are not strictly aligned can be avoided, so that the aperture ratio of the liquid crystal display panel can be improved, and the brightness of the liquid crystal display panel can be increased.
  • the array substrate may further include: a flat layer 105 disposed between the color resist layer 104 and the pixel electrode layer 103, thereby further increasing the distance between the data line 102 and the pixel electrode 1031, The capacitance between the data line 102 and the pixel electrode 1031 is further reduced.
  • the color resist layer 104 is composed of a plurality of color resistors of different colors, and any adjacent two color resistors may generate a certain degree of overlapping regions during the manufacturing process, thereby generating a gap, and the liquid crystal above the overlapping region There will be a phenomenon of backward confusion due to the fault, which will seriously affect the display effect.
  • a flat layer 105 is disposed on the color resist layer 104, so that the difference between the two adjacent color resists in the color resist layer 104 due to the overlap can be reduced, thereby improving the display quality.
  • the material of the flat layer 105 may be organic such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, urethane acrylate resin, phenolic epoxy acrylic resin, etc. Insulating material is not limited here.
  • the array substrate may further include: a thin film transistor, which may be a bottom gate type structure; or the thin film transistor may also be a top gate type structure, which is not limited herein.
  • the thin film transistor in the array substrate is a bottom gate type structure.
  • the source/drain 404 are both located above the active layer 403, and the gate 401 is located.
  • a gate insulating layer 402 is disposed between the gate 401 and the active layer 403, and a passivation layer 405 is disposed over the layer on which the source/drain 404 is located.
  • the array substrate further includes a color resist layer 104 over the gate insulating layer 402 and a flat layer 105 over the color resist layer 104.
  • the array substrate further includes a pixel electrode 1031 located above the source/drain 404 in the corresponding thin film transistor, and each pixel electrode 1031 passes through a via hole penetrating through the passivation layer 405, the color resist layer 104, and the flat layer 105.
  • the source/drain 404 in the thin film transistor is electrically connected.
  • the material of the gate 401 and the source/drain 404 may be one of molybdenum, aluminum, tungsten, titanium, copper or a combination of alloys, which is not limited herein.
  • the material of the gate insulating layer 402 and the passivation layer 405 may be one or a combination of silicon oxide and silicon nitride, which is not limited herein.
  • the material of the active layer 403 may be a polysilicon semiconductor material, an amorphous silicon semiconductor material, an oxide semiconductor material or an organic semiconductor material, which is not limited herein.
  • an array substrate provided by an embodiment of the present disclosure may further include: a gate line 106 disposed between the substrate 101 and the layer where the data line 102 is located, and the same as the gate line 106.
  • a plurality of first common electrode lines 107a and a plurality of second common electrode lines 107b are provided in the layer.
  • the gate line 106 is for supplying a scan signal to each of the pixel electrodes 1031, extending in a first direction; the data line extends in a second direction, and the second direction is substantially orthogonal to the first direction.
  • Each of the first common electrode lines 107a and the respective second common electrode lines 107b is for supplying a common voltage signal to the common electrode.
  • the first common electrode line 107a of the array substrate extends in the first direction, for example, in the lateral direction
  • the second common electrode line 107b extends in the second direction, for example. Extending in the longitudinal direction.
  • the gate line 106, the plurality of first common electrode lines 107a, and the plurality of second common electrode lines 107b may be simultaneously prepared using one patterning process.
  • the gate line 106 and the plurality of first common electrode lines 107a and the plurality of second common electrode lines 107b may be separately prepared by using a second patterning process, which is not limited herein.
  • the material of the gate line 106, the plurality of first common electrode lines 107a, and the plurality of second common electrode lines 107b may be one of molybdenum, aluminum, tungsten, titanium, copper, or an alloy combination, which is not limited herein.
  • the source/drain 404 and the data line 102 may be simultaneously prepared using one patterning process.
  • the source/drain 404 and the data line 102 can be separately prepared by using a secondary patterning process, which is not limited herein.
  • the material of the source/drain 404 and the data line 102 may be one of molybdenum, aluminum, tungsten, titanium, copper or a combination of alloys, which is not limited herein.
  • each of the second common electrode lines 107b in the array substrate is in one-to-one correspondence with each column of pixel electrodes, so that the display screen is uniform.
  • the orthographic projection of the second common electrode line 107b on the base substrate 101 is located at the midline position of the orthographic projection of each column of pixel electrodes on the base substrate 101.
  • FIG. 2 shows the relative positional relationship between the orthographic projection of a second common electrode line 107b on the substrate 101 and the orthographic projection of any one of the pixel electrodes 1031 on the substrate 101.
  • the effective display area corresponding to the pixel electrode 1031 can be bilaterally symmetrical, so that the uniformity of the display screen can be improved.
  • the color resist layer 104 above the layer where each of the second common electrode lines 107b is thick is thick, even if the orthographic projection of each of the second common electrode lines 107b on the base substrate 101 is located in each column of the pixel electrodes on the substrate The position of the center line of the orthographic projection on the substrate 101 does not see the second common electrode lines 107b on the display side of the liquid crystal display panel, that is, does not affect the aperture ratio of the liquid crystal display panel.
  • the embodiment of the present disclosure provides a method for fabricating the above array substrate.
  • the principle of solving the problem is similar to the principle of solving the problem of the array substrate. Therefore, the implementation of the manufacturing method provided by the embodiment of the present disclosure may be performed. Referring to the implementation of the above array substrate provided by the embodiments of the present disclosure, the repeated description is omitted.
  • the method for fabricating the above array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, may specifically include the following steps:
  • the orthographic projection of the data line on the base substrate covers the orthographic projection of the gap between the adjacent two columns of pixel electrodes on the substrate, and the width of the data line is greater than the width of the gap between the adjacent two columns of pixel electrodes.
  • the method before forming a pixel electrode layer including a plurality of columns of pixel electrodes spaced apart from each other on a layer where the data line is located, the method further includes: forming a color on the layer where the data line is located The resist layer, thereby reducing the capacitance between the data line and the pixel electrode.
  • the method may include forming a flat layer on the color resist layer, thereby further reducing a capacitance between the data line and the pixel electrode.
  • the method before forming the data line on the base substrate, the method further includes: simultaneously forming a gate line extending along the first direction on the base substrate, and a plurality of extending along the first direction a first common electrode line and a plurality of second common electrode lines extending in the second direction; wherein each of the second common electrode lines is in one-to-one correspondence with each column of pixel electrodes; and each of the second common electrode lines is on the base substrate
  • the orthographic projection is located at the midline position of the orthographic projection of each column of pixel electrodes on the substrate, whereby the display screen uniformity of the pixel electrodes can be improved.
  • the embodiments of the present disclosure further provide a schematic structural view of the array substrate obtained after performing the steps of the above method, as shown in FIG. 4a to FIG. 4g.
  • the thin film transistor in the array substrate may be a bottom gate type structure; or may be a top gate type structure, which is not limited herein.
  • a thin film transistor is used as a bottom gate type structure as an example for description.
  • a substrate substrate 101 is provided, and a pattern of the gate electrode 401 and the gate line 106 is formed on the substrate substrate 101 by using a patterning process, as shown in FIG. 4a, thereby simplifying the fabrication process of the array substrate and reducing the number of masks;
  • a pattern of a flat layer 105 having vias that are electrically connected to the vias of the color resist layer 104 is formed on the color resist layer 104, as shown in FIG. 4e;
  • Via holes are formed in the passivation layer 405 above the source/drain 404 and the layer where the data line is located, as shown in FIG. 4f;
  • a pattern of the pixel electrode layer 103 is formed on the flat layer 105.
  • the pixel electrode 1031 is electrically connected to the source/drain 404 in the corresponding thin film transistor through a via hole penetrating through the passivation layer 405, the color resist layer 104, and the flat layer 105. As shown in Figure 4g.
  • the patterning process involved in forming each layer structure may include not only deposition, photoresist coating, mask masking, exposure, development, and etching.
  • Part or all of the process, such as photoresist stripping may also include other processes, which are specifically determined by the pattern forming the desired pattern in the actual manufacturing process, and are not limited herein.
  • a post-baking process may also be included after development and prior to etching.
  • the deposition process may be a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or a physical vapor deposition method, which is not limited herein;
  • the mask used in the mask process may be a halftone mask (Half Tone Mask). ), Modifide Single Mask, Single Slit Mask, or Gray Tone Mask, which is not limited herein;
  • etching may be dry etching or wet The etching method is not limited herein.
  • an embodiment of the present disclosure provides a liquid crystal display panel.
  • the principle of the liquid crystal display panel is similar to that of the above array substrate. Therefore, the implementation of the liquid crystal display panel provided by the embodiment of the present disclosure is implemented.
  • the implementation of the above array substrate provided by the embodiment of the present disclosure may be referred to, and the repeated description is omitted.
  • a liquid crystal display panel includes the above array substrate and a counter substrate opposite to the array substrate.
  • the liquid crystal display panel in order to prevent light leakage between the color resists in the color resist layer 104, as shown in FIG. 5, the liquid crystal display panel further includes a black matrix 501 disposed on a side of the opposite substrate facing the array substrate.
  • the black matrix may be disposed on a side of the array substrate facing the opposite substrate, and the black matrix is located at a gap between the color resists in the color resist layer.
  • the black matrix 501 can not only prevent light leakage between the respective color resists, but also increase the contrast of colors.
  • the material of the black matrix 501 can be divided into two types, one of which is a metal thin film, such as an oxide film, and the other is a resin type black photoresist film, and carbon black is used as a main material.
  • the metal thin film can be selected as the black matrix 501.
  • the red color resist and the blue color resist may be superimposed and set as the black matrix 501.
  • the shading effect it is not limited herein.
  • the liquid crystal display panel further includes: a plurality of photoresist spacers 502 disposed between the array substrate and the opposite substrate (Photo) Spacer, PS).
  • the opposite substrate in the liquid crystal display panel provided by the embodiment of the present disclosure generally has other film layer structures such as a common electrode layer, a protective layer, etc., and the specific structures may have various embodiments. This is not limited.
  • the preparation process of the above liquid crystal display panel is described in detail below by taking the liquid crystal display panel as shown in FIG. 5 as an example.
  • the specific preparation process includes the following steps:
  • the steps (1) and (2) are not limited to the sequence described in the preparation process of the liquid crystal display panel, and the step (2) may be performed first, and then the step (1) is performed. , not limited here.
  • the substrate substrate 101 of the array substrate and the substrate substrate 503 of the opposite substrate are subjected to the box processing, and then immersed.
  • the liquid crystal molecules are added to the liquid crystal display panel after the box; or the step (1) in the process of fabricating the liquid crystal display panel provided by the embodiment of the present disclosure may be sequentially obtained by using the method for fabricating the array substrate.
  • the liquid crystal molecules are dripped on the base substrate 101 of the array substrate; or, the steps in the manufacturing process of the liquid crystal display panel provided by the embodiment of the present disclosure may be performed ( 2) After sequentially forming a protective layer (see FIG.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned liquid crystal display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame. , Navigator, smart watch, fitness wristband, personal digital assistant, etc. Any product or component with display function.
  • a display device including the above-mentioned liquid crystal display panel provided by the embodiment of the present disclosure, which may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame. , Navigator, smart watch, fitness wristband, personal digital assistant, etc. Any product or component with display function.
  • the display device reference may be made to the embodiment of the liquid crystal display panel described above, and the repeated description is omitted.
  • the array substrate, the method for fabricating the same, and the liquid crystal display panel and the display device provided by the embodiment of the present disclosure include: a substrate substrate, a data line disposed on the substrate substrate, and a pixel electrode layer disposed on the layer where the data line is located Wherein the pixel electrode layer comprises a plurality of columns of pixel electrodes spaced apart from each other; an orthographic projection of the data lines on the substrate substrate covers an orthographic projection of a gap between adjacent two columns of pixel electrodes on the substrate, and the data lines The width is greater than the width of the gap between the adjacent two columns of pixel electrodes.
  • the orthographic projection of the data line on the substrate substrate covers the orthographic projection of the gap between the adjacent two columns of pixel electrodes on the substrate, and the width of the data line is greater than the width of the gap between the adjacent two columns of pixel electrodes.
  • the second electric field line which is directed from the array substrate to the opposite substrate can be formed between the data line and the pixel electrode, thereby preventing the light leakage in the direction of the data line by controlling the twist of the liquid crystal, and at the same time, no black is needed.
  • the matrix prevents light leakage and effectively increases the aperture ratio.

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Abstract

一种阵列基板、其制作方法及液晶显示面板、显示装置，包括：衬底基板(101)，设置于衬底基板(101)上的数据线(102)，以及设置于数据线(102)所在层之上的包括多个像素电极(1031)的像素电极层(103)；数据线(102)在衬底基板(101)上的正投影覆盖相邻的两列像素电极(1031)之间间隙在衬底基板(101)上的正投影，且数据线(102)的宽度(a)大于相邻的两列像素电极(1031)之间间隙的宽度(b)。由于数据线(102)在衬底基板(101)上的正投影覆盖相邻的两列像素电极(1031)之间间隙在衬底基板(101)上的正投影，且数据线(102)的宽度(a)大于相邻的两列像素电极(1031)之间间隙的宽度(b)，这样，可使数据线(102)与像素电极(1031)之间形成方向由阵列基板指向对向基板的纵向电场线，从而可通过控制液晶的扭转，防止数据线(102)方向漏光，同时，避免了使用黑矩阵(501)来防止漏光，有效提高了开口率。

Description

阵列基板及其制作方法、液晶显示面板和显示装置
相关申请的交叉引用
本申请要求于2017年5月4日提交的、名称为“一种阵列基板、其制作方法及液晶显示面板、显示装置”的中国专利申请NO.201710309241.8的优先权，该专利申请的公开内容通过引用方式整体并入本文。
技术领域
本公开的实施例一般地涉及显示技术领域，尤其涉及一种阵列基板、其制作方法及液晶显示面板、显示装置。
背景技术
液晶显示面板(Liquid Crystal Display，LCD)具有重量轻、厚度薄、功耗低、易于驱动、不含有害射线等优点，已经广泛应用在电视、笔记本电脑、移动电话、个人数字助理等现代信息设备，有着广阔的发展前景。对个人使用者而言，曲面显示具有比平面显示更好的视角体验和显示效果。因此，曲面液晶显示面板技术是液晶显示面板的一个重要发展方向。
扭转向列(Twisted Nematic，TN)型液晶显示面板由液晶在阵列基板与对向基板间旋转90度而形成。对于常白模式的液晶显示面板，显示一幅黑画面时，非显示区域产生的漏光现象，会使图像的对比度下降。而扭转向列型液晶显示面板由于其液晶的分布方式，可以在常白模式下避免漏光，使得扭转向列型液晶显示面板在曲面显示方面具有较大的优势。
然而，曲面液晶显示面板技术需要将液晶显示面板进行弯曲，在弯曲的过程中，液晶面板的对向基板和阵列基板容易发生位移，导致液晶显示面板出现漏光现象。现有技术中通过增大黑矩阵的尺寸来防止漏光，这样势必会降低液晶显示面板的开口率。
因此，现有技术中至少存在如何在防止漏光的同时，有效提高液晶显示面 板的开口率的技术问题。
发明内容
本公开本公开实施例提供的一种阵列基板，包括：衬底基板，设置于所述衬底基板上的数据线，以及设置于所述数据线所在层之上的像素电极层；其中，
所述像素电极层包括多列彼此间隔开的像素电极；且
所述数据线在所述衬底基板上的正投影覆盖相邻的两列所述像素电极之间间隙在所述衬底基板上的正投影，且所述数据线的宽度大于所述相邻的两列所述像素电极之间间隙的宽度。
在一个实施例中，所述数据线在所述衬底基板上的正投影部分覆盖相邻的两列所述像素电极在所述衬底基板上的正投影。
在一个实施例中，所述数据线在所述衬底基板上的正投影与相邻的两列所述像素电极在所述衬底基板上的正投影的交叠区域具有相同的宽度。
在一个实施例中，阵列基板还包括：设置于所述数据线所在层与所述像素电极层之间的色阻层。
在一个实施例中，阵列基板还包括：设置于所述色阻层与所述像素电极层之间的平坦层。
在一个实施例中，阵列基板还包括：设置于所述衬底基板与所述数据线所在层之间的沿第一方向延伸的栅线，以及与所述栅线同层设置的多条第一公共电极线和多条第二公共电极线，其中多条第一公共电极线沿第一方向延伸，多条第二公共电极线沿第二方向延伸，第一方向和第二方向正交。
在一个实施例中，各所述第二公共电极线与各列所述像素电极一一对应；并且
各所述第二公共电极线在所述衬底基板上的正投影位于各列所述像素电极在所述衬底基板上的正投影的中线位置。
本公开实施例还提供了一种液晶显示面板，包括上述阵列基板，以及与所 述阵列基板相对而置的对向基板。
在一个实施例中，液晶显示面板还包括：设置于所述对向基板面向所述阵列基板一侧的黑矩阵；或，
设置于所述阵列基板面向所述对向基板一侧的黑矩阵，且所述黑矩阵位于色阻层中各色阻之间的间隙处。
本公开实施例还提供了一种显示装置，包括上述液晶显示面板。
本公开实施例还提供了一种上述阵列基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成数据线；
在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层；其中，
所述数据线在所述衬底基板上的正投影覆盖相邻的两列所述像素电极之间间隙在所述衬底基板上的正投影，且所述数据线的宽度大于所述相邻的两列所述像素电极之间间隙的宽度。
在一个实施例中，在本公开实施例提供的上述制作方法中，在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，还包括：
在所述数据线所在层上形成色阻层。
在一个实施例中，在本公开实施例提供的上述制作方法中，在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，且在所述数据线所在层上形成色阻层之后，还包括：在所述色阻层上形成平坦层。
在一个实施例中，在本公开实施例提供的上述制作方法中，在所述衬底基板上形成数据线之前，还包括：
在所述衬底基板上同时形成沿第一方向延伸的栅线，以及多条第一公共电极线和多条第二公共电极线，其中多条第一公共电极线沿第一方向延伸，多条第二公共电极线沿第二方向延伸，第一方向和第二方向正交；
各所述第二公共电极线与各列所述像素电极一一对应；
各所述第二公共电极线在所述衬底基板上的正投影位于各列所述像素电极在所述衬底基板上的正投影的中线位置。
附图说明
图1为本公开的实施例提供的阵列基板的结构示意图；
图2为本公开的实施例提供的阵列基板中第二公共电极线与像素电极的相对位置关系示意图；
图3为本公开的实施例提供的阵列基板的制作流程图；
图4a至图4g分别为图3所示的阵列基板的制作方法在执行各步骤后的结构示意图；
图5为本公开的实施例提供的液晶显示面板的结构示意图。
具体实施方式
下面结合附图，对本公开的多个实施例提供的阵列基板、其制作方法及液晶显示面板、显示装置的具体实施方式进行详细的说明。
附图中各膜层的形状和大小不反映其在阵列基板或液晶显示面板中的真实比例，目的只是示意地说明本公开内容。
本公开的一个实施例提供一种阵列基板，如图1所示，包括：衬底基板101、设置于衬底基板101上的数据线102以及设置于数据线102所在层上方的像素电极层103；其中，
像素电极层103包括多列彼此间隔开的像素电极1031；
数据线102在衬底基板101上的正投影覆盖相邻的两列像素电极之间的间隙在衬底基板101上的正投影，且数据线102的宽度a大于相邻的两列像素电极之间的间隙的宽度b。
在本公开的实施例提供的上述阵列基板中，由于数据线102在衬底基板101上的正投影覆盖相邻的两列像素电极之间间隙在衬底基板101上的正投影， 且数据线102的宽度a大于相邻的两列像素电极之间间隙的宽度b，这样设置，可以使数据线102与像素电极1031之间形成方向由阵列基板指向对向基板的纵向电场线，从而可以通过控制与像素电极边缘附近对应的液晶的扭转，防止沿数据线102的延伸方向的漏光，与此同时，不需要再使用例如用以遮光的黑矩阵或其他遮光部件来防止漏光，有效提高了开口率。
在本公开实施例提供的上述阵列基板中，衬底基板101可以是柔性衬底基板，例如由聚乙烯醚邻苯二甲酸酯、聚萘二甲酸乙二醇酯、聚碳酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜或聚酰亚胺等具有优良的耐热性和耐久性的塑料基板；还可以是刚性衬底基板，例如玻璃基板，在此不做限定。
在本公开的一个实施例中，数据线102在衬底基板101上的正投影可以部分覆盖相邻的两列像素电极在衬底基板101上的正投影，从而不影响正常显示。
在本公开的一个实施例中，如图1所示，数据线102在衬底基板101上的正投影与相邻的两列像素电极在衬底基板101上的正投影的交叠区域具有相同的宽度c，从而简化工艺制作。
在本公开的其他实施例中，数据线102在衬底基板101上的正投影与相邻的两列像素电极在衬底基板101上的正投影的交叠区域也可以具有不同的宽度，在此不做限定。
一般地，在数据线102对像素电极1031充电的过程中需要稳压一段时间，在本公开的一个实施例中，阵列基板中的数据线102与像素电极1031之间存在交叠区域可能导致数据线102与像素电极1031之间在交叠区域形成一定的电容，该电容可能会对像素电极1031上的稳定电压造成一定程度的干扰，进而影响显示效果。根据本公开的实施例提供的阵列基板还可以包括：设置于数据线102所在层与像素电极层103之间的色阻层104。这样，使得数据线102与像素电极1031之间的距离增大，从而减小了二者之间的电容，降低了二者之间的电容扰动像素电极1031上的稳定电压的风险。此外，将色阻层104设置在阵列基板上，还可以避免色阻层104与像素电极1031未严格对准的问题， 从而可以提高液晶显示面板的开口率，增加液晶显示面板的亮度。
在本公开的一个实施例中，阵列基板还可以包括：设置于色阻层104与像素电极层103之间的平坦层105，从而进一步增大数据线102与像素电极1031之间的距离，以进一步减小数据线102与像素电极1031之间的电容。
一般地，色阻层104由多个不同颜色的色阻组成，任意相邻的两个色阻在制作过程中会产生一定程度的交叠区域，进而产生断差，该交叠区域上方的液晶会因断差出现倒向错乱的现象，这种现象会严重影响显示效果。在本实施例中，在色阻层104上设置一层平坦层105，可以减小色阻层104中任意相邻的两个色阻之间因重叠产生的断差，从而提高显示品质。
在本实施例中，平坦层105的材料可以为聚丙烯酸树脂、聚环氧丙烯酸树脂、感光性聚酰亚胺树脂、聚酯丙烯酸酯、聚氨酯丙烯酸酯树脂、酚醛环氧压克力树脂等有机绝缘材料，在此不做限定。
在本公开的一个实施例中，阵列基板还可以包括：薄膜晶体管，该薄膜晶体管具体可以为底栅型结构；或者，该薄膜晶体管也可以为顶栅型结构，在此不做限定。
在本公开的一个实施例中，阵列基板中的薄膜晶体管为底栅型结构，例如参照图4g，在阵列基板中，源/漏极404均位于有源层403的上方，栅极401位于有源层403的下方，栅极401与有源层403之间设置有栅绝缘层402，源/漏极404所在层之上设置有钝化层405。阵列基板还包括在栅绝缘层402之上的色阻层104和位于色阻层104之上的平坦层105。阵列基板还包括像素电极1031，位于对应的薄膜晶体管中的源/漏极404的上方，并且，每个像素电极1031通过贯穿钝化层405、色阻层104和平坦层105的过孔与对应的薄膜晶体管中的源/漏极404电性连接。
在本实施例中，栅极401和源/漏极404的材料可以是钼、铝，钨、钛、铜其中之一或合金组合，在此不做限定。栅绝缘层402和钝化层405的材料可以为氧化硅、氮化硅其中之一或组合，在此不做限定。有源层403的材料可以为 多晶硅半导体材料、非晶硅半导体材料、氧化物半导体材料或有机半导体材料，在此不做限定。
在具体实施时，如图2所示，本公开的一个实施例提供的阵列基板还可以包括：设置于衬底基板101与数据线102所在层之间的栅线106，以及与栅线106同层设置的多条第一公共电极线107a和多条第二公共电极线107b。在本实施例中，栅线106用于向各像素电极1031提供扫描信号，沿第一方向延伸；数据线沿第二方向延伸，第二方向与第一方向大体正交。各条第一公共电极线107a和各条第二公共电极线107b用于向公共电极提供公共电压信号。在本实施例中，如图2所示的实施例中，阵列基板的第一公共电极线107a沿第一方向延伸，例如沿横向方向延伸，第二公共电极线107b沿第二方向延伸，例如沿纵向方向延伸。
根据本公开的实施例，为简化制作工艺，节省制作成本，提高生产效率，可以使用一次构图工艺同时制备出栅线106、多条第一公共电极线107a和多条第二公共电极线107b。当然，也可以采用二次构图工艺，分别制备出栅线106，以及多条第一公共电极线107a和多条第二公共电极线107b，在此不做限定。此外，栅线106、多条第一公共电极线107a和多条第二公共电极线107b的材料可以是钼、铝，钨、钛、铜其中之一或合金组合，在此不做限定。
根据本公开的实施例，为简化制作工艺，节省制作成本，提高生产效率，还可以使用一次构图工艺同时制备出源/漏极404和数据线102。当然，也可以采用二次构图工艺，分别制备出源/漏极404和数据线102，在此不做限定。此外，源/漏极404和数据线102的材料可以是钼、铝，钨、钛、铜其中之一或合金组合，在此不做限定。
在本公开的一个实施例中，阵列基板中的各第二公共电极线107b与各列像素电极一一对应，使得显示画面均匀。
在本公开的一个实施例中，第二公共电极线107b在衬底基板101上的正投影位于各列像素电极在衬底基板101上的正投影的中线位置。参照图2，图 2示出一条第二公共电极线107b在衬底基板101上的正投影与其对应的一列像素电极中的任一像素电极1031在衬底基板101上的正投影的相对位置关系的示意图。
这样设置，可以使与像素电极1031对应的有效显示区域左右对称，从而可以提高显示画面的均匀性。并且，由于各第二公共电极线107b所在层之上的色阻层104较厚，因此，即使设置各第二公共电极线107b在衬底基板101上的正投影位于各列像素电极在衬底基板101上的正投影的中线位置，在液晶显示面板的显示侧也不会看到各第二公共电极线107b，即不会影响液晶显示面板的开口率。
相应地，本公开的实施例提供了一种制作上述阵列基板的方法，由于该方法解决问题的原理与上述阵列基板解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述阵列基板的实施，重复之处不再赘述。
具体地，本公开实施例提供的一种制作上述阵列基板的方法，如图3所示，具体可以包括以下步骤：
S301、提供一衬底基板；
S302、在衬底基板上形成数据线；
S303、在数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层；其中，
数据线在衬底基板上的正投影覆盖相邻的两列像素电极之间的间隙在衬底基板上的正投影，且数据线的宽度大于相邻的两列像素电极之间间隙的宽度。
在具体实施时，在本公开实施例提供的上述方法中，在数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，还可以包括：在数据线所在层上形成色阻层，由此减小数据线与像素电极之间的电容。
具体地，在本公开实施例提供的上述方法中，在数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，且在数据线所在层上形成色阻 层之后，还可以包括：在色阻层上形成平坦层，由此进一步减小数据线与像素电极之间的电容。
在本公开实施例提供的上述方法中，在衬底基板上形成数据线之前，还可以包括：在衬底基板上同时形成沿第一方向延伸的栅线，以及多条沿第一方向延伸的第一公共电极线和多条沿第二方向延伸的第二公共电极线；其中，各第二公共电极线与各列像素电极一一对应；并且，各第二公共电极线在衬底基板上的正投影位于各列像素电极在衬底基板上的正投影的中线位置，由此可以提高像素电极的显示画面均匀性。
为了更好地理解本公开实施例提供的上述方法，本公开实施例还提供了实施上述方法的各步骤后所得的阵列基板的结构示意图，如图4a至图4g所示。
根据本公开的实施例，上述阵列基板中的薄膜晶体管具体可以为底栅型结构；或者，也可以为顶栅型结构，在此不做限定。下面以薄膜晶体管为底栅型结构为例进行说明。
提供一衬底基板101，采用一次构图工艺，在衬底基板101上形成栅极401和栅线106的图形，如图4a所示，这样，可以简化阵列基板的制作工艺，减少掩模次数；
在形成有栅极401和栅线106的衬底基板101上依次形成栅极绝缘层402、有源层403、源/漏极404和数据线的图形，如图4b所示；
在源/漏极404和数据线所在层之上形成钝化层405的图形，如图4c所示；
在钝化层405上形成具有过孔的色阻层104的图形，如图4d所示；
在色阻层104上形成具有与色阻层104的过孔导通的过孔的平坦层105的图形，如图4e所示；
在源/漏极404和数据线所在层之上的钝化层405中形成与色阻层104和平坦层105的过孔导通的过孔，如图4f所示；
在平坦层105上形成像素电极层103的图形，像素电极1031通过贯穿钝化层405、色阻层104和平坦层105中的过孔与对应的薄膜晶体管中的源/漏极 404电性连接，如图4g所示。
需要说明的是，在本公开实施例四提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、半透掩膜板(Modifide Single Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
基于同一发明构思，本公开实施例提供了一种液晶显示面板，由于该液晶显示面板解决问题的原理与上述阵列基板解决问题的原理相似，因此，本公开实施例提供的该液晶显示面板的实施可以参见本公开实施例提供的上述阵列基板的实施，重复之处不再赘述。
本公开实施例提供的一种液晶显示面板，如图5所示，包括上述阵列基板，以及与阵列基板相对而置的对向基板。
在本公开的实施例中，为了防止色阻层104中各色阻间的漏光，如图5所示，液晶显示面板还包括：设置于对向基板面向阵列基板一侧的黑矩阵501。当然，本公开的另一实施例中，黑矩阵可以设置于阵列基板面向对向基板一侧，且黑矩阵位于色阻层中各色阻之间的间隙处。
在本实施例中，黑矩阵501不仅可以防止各色阻间的漏光，而且可以增加色彩的对比性。一般地，黑矩阵501的材料可分为两种，其中一种为金属薄膜，例如氧化膜；另一种为树脂型黑色光阻薄膜，且以碳黑为主要材料。在本实施例中，由于金属薄膜的线路蚀刻容易，而且遮光效果较好，可以选择金属薄膜作为黑矩阵501。
值得注意的是，在本公开实施例提供的上述显示面板中，除了采用金属薄膜或黑色树脂作为黑矩阵501之外，还可以将红光色阻与蓝光色阻叠加设置后作为黑矩阵501，以实现遮光效果，在此不做限定。
在本公开的实施例中，如图5所示，为了提高液晶显示面板的抗挤压能力，液晶显示面板还包括：设置于阵列基板与对向基板之间多个光阻间隔物502(Photo Spacer，PS)。
在具体实施时，在本公开实施例提供的上述液晶显示面板中的对向基板上一般还会具有诸如公共电极层、保护层等其他膜层结构，这些具体结构可以有多种实施例，在此不做限定。
下面以制备如图5所示的液晶显示面板为例，对上述液晶显示面板的制备过程进行详细地说明，具体制备过程包括以下几个步骤：
(1)、采用上述阵列基板的制作方法，依次得到如图4a至图4g所示的阵列基板；
(2)、在对向基板的衬底基板503上依次形成保护层、黑矩阵501、公共电极层(图中未示出)和光阻间隔物502；
(3)、将阵列基板的衬底基板101与对向基板的衬底基板503进行对盒处理。
需要说明的是，在具体实施时，步骤(1)和步骤(2)并不限于上述液晶显示面板的制备过程中描述的先后顺序，还可以先执行步骤(2)，再执行步骤(1)，在此不做限定。
具体地，可以在执行本公开实施例提供的上述液晶显示面板的制作过程中的步骤(3)将阵列基板的衬底基板101与对向基板的衬底基板503进行对盒处理之后，通过浸泡的方式将液晶分子加入对盒后的液晶显示面板中；或者，也可以在执行本公开实施例提供的上述液晶显示面板的制作过程中的步骤(1)采用上述阵列基板的制作方法，依次得到如图4a至图4g所示的阵列基板之后，在阵列基板的衬底基板101上滴注液晶分子；或者，还可以在执行本公开实施 例提供的上述液晶显示面板的制作过程中的步骤(2)在对向基板的衬底基板503上依次形成保护层(参见图1)、黑矩阵501、公共电极层(图中未示出)和光阻间隔物502之后，在对向基板的衬底基板503上滴注液晶分子，在此不做限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述液晶显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述液晶显示面板的实施例，重复之处不再赘述。
本公开实施例提供的上述阵列基板、其制作方法及液晶显示面板、显示装置，包括：衬底基板，设置于衬底基板上的数据线，以及设置于数据线所在层之上的像素电极层；其中，像素电极层包括多列彼此间隔开的像素电极；数据线在衬底基板上的正投影覆盖相邻的两列像素电极之间间隙在衬底基板上的正投影，且数据线的宽度大于相邻的两列像素电极之间间隙的宽度。由于数据线在衬底基板上的正投影覆盖相邻的两列像素电极之间间隙在衬底基板上的正投影，且数据线的宽度大于相邻的两列像素电极之间间隙的宽度，这样设置，可以使数据线与像素电极之间形成方向由阵列基板指向对向基板的第二电场线，从而可以通过控制液晶的扭转，防止数据线方向漏光，与此同时，不需要再使用黑矩阵来防止漏光，有效提高了开口率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开的权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种阵列基板，包括：衬底基板、设置于所述衬底基板上的数据线以及设置于所述数据线所在层上方的像素电极层；其中，
    所述像素电极层包括多列彼此间隔开的像素电极；且
    所述数据线在所述衬底基板上的正投影覆盖相邻的两列所述像素电极之间的间隙在所述衬底基板上的正投影，且所述数据线的宽度大于所述相邻的两列所述像素电极之间间隙的宽度。
  2. 如权利要求1所述的阵列基板，其中，所述数据线在所述衬底基板上的正投影部分地覆盖相邻的两列所述像素电极在所述衬底基板上的正投影。
  3. 如权利要求2所述的阵列基板，其中，所述数据线在所述衬底基板上的正投影与相邻的两列所述像素电极在所述衬底基板上的正投影的交叠区域具有相同的宽度。
  4. 如权利要求1所述的阵列基板，还包括：设置于所述数据线所在层与所述像素电极层之间的色阻层。
  5. 如权利要求4所述的阵列基板，还包括：设置于所述色阻层与所述像素电极层之间的平坦层。
  6. 如权利要求1所述的阵列基板，还包括：设置于所述衬底基板与所述数据线所在层之间的沿第一方向延伸的栅线，以及与所述栅线同层设置的多条第一公共电极线和多条第二公共电极线，其中多条第一公共电极线沿第一方向延伸，多条第二公共电极线沿第二方向延伸，第一方向和第二方向正交。
  7. 如权利要求6所述的阵列基板，其中，各所述第二公共电极线与各列所述像素电极一一对应；并且
    每条所述第二公共电极线在所述衬底基板上的正投影位于对应的一列所述像素电极在所述衬底基板上的正投影的中线位置。
  8. 一种液晶显示面板，包括：如权利要求1-7任一项所述的阵列基板， 以及与所述阵列基板相对而置的对向基板。
  9. 如权利要求8所述的液晶显示面板，还包括：设置于所述对向基板面向所述阵列基板一侧的黑矩阵；或，
    设置于所述阵列基板面向所述对向基板一侧的黑矩阵，且阵列基板还包括设置于所述数据线所在层与所述像素电极层之间的色阻层，所述黑矩阵位于色阻层中各色阻之间的间隙处。
  10. 如权利要求9所述的液晶显示面板，其中设置于所述阵列基板面向所述对向基板一侧的黑矩阵由红光色阻与蓝光色阻叠加而成。
  11. 一种显示装置，包括：如权利要求8-10中任一项所述的液晶显示面板。
  12. 一种如权利要求1-7任一项所述的制作阵列基板的方法，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上形成数据线；
    在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层；其中，
    所述数据线在所述衬底基板上的正投影覆盖相邻的两列所述像素电极之间的间隙在所述衬底基板上的正投影，且所述数据线的宽度大于所述相邻的两列所述像素电极之间间隙的宽度。
  13. 如权利要求12所述的方法，其中，在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，还包括：
    在所述数据线所在层上形成色阻层。
  14. 如权利要求13所述的方法，其中，在所述数据线所在层上形成包括多列彼此间隔开的像素电极的像素电极层之前，且在所述数据线所在层上形成色阻层之后，还包括：在所述色阻层上形成平坦层。
  15. 如权利要求12所述的方法，其中，在所述衬底基板上形成数据线之前，还包括：
    在所述衬底基板上同时形成沿第一方向延伸的栅线，以及多条第一公共电极线和多条第二公共电极线，其中多条第一公共电极线沿第一方向延伸，多条第二公共电极线沿第二方向延伸，第一方向和第二方向正交；
    各所述第二公共电极线与各列所述像素电极一一对应；
    每条所述第二公共电极线在所述衬底基板上的正投影位于对应的一列所述像素电极在所述衬底基板上的正投影的中线位置。
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