WO2020232926A1 - 阵列基板以及阵列基板的制作方法 - Google Patents

阵列基板以及阵列基板的制作方法 Download PDF

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WO2020232926A1
WO2020232926A1 PCT/CN2019/106316 CN2019106316W WO2020232926A1 WO 2020232926 A1 WO2020232926 A1 WO 2020232926A1 CN 2019106316 W CN2019106316 W CN 2019106316W WO 2020232926 A1 WO2020232926 A1 WO 2020232926A1
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layer
array substrate
patterned
substrate
insulating layer
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PCT/CN2019/106316
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English (en)
French (fr)
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艾飞
宋德伟
尹国恒
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武汉华星光电技术有限公司
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Priority to US16/605,417 priority Critical patent/US11315958B2/en
Publication of WO2020232926A1 publication Critical patent/WO2020232926A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate and a manufacturing method of the array substrate.
  • LCD Liquid Crystal Display
  • LTPS Low Temperature Poly-Silicon
  • the light utilization rate of the LCD screen has not been easily improved for a long time, and the light transmittance is limited.
  • the present disclosure provides an array substrate including a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filling the plurality of thin film transistors and the substrate. The area formed between the substrates.
  • the thin film transistor includes a molybdenum light-shielding layer disposed on the substrate, a buffer layer covering the molybdenum light-shielding layer, an active layer disposed on the buffer layer, and a gate A polar insulating layer is covered on the active layer, a patterned gate layer is arranged on the gate insulating layer, an interlayer insulating layer is covered on the patterned gate layer, and a source/drain layer is arranged On the interlayer insulating layer and connected to the active layer through the first channel layer.
  • the array substrate in an embodiment of the present disclosure further includes a transparent common conductive layer disposed on the planarization layer, a passivation layer disposed on the transparent common conductive layer, and a transparent pixel electrode disposed on the passivation layer .
  • planarization layer and the transparent common conductive layer further include a patterned metal layer and an insulating layer.
  • the active layer further includes a polysilicon layer, lightly doped regions located on both sides of the polysilicon layer, and a heavily doped region connected to the lightly doped region.
  • the present disclosure also provides a manufacturing method of the array substrate, including the following steps:
  • a planarization layer is formed to cover the array substrate.
  • the manufacturing method of the array substrate further includes:
  • the step of providing an array substrate with a source/drain layer completed includes:
  • a source/drain layer is formed on the interlayer insulating layer.
  • the patterned active layer includes polysilicon material.
  • the patterned active layer includes a polysilicon layer, lightly doped regions located on both sides of the polysilicon layer, and two lightly doped regions located on the lightly doped regions. Side heavily doped area.
  • the buffer layer, the gate insulating layer, and the layer between the thin film transistor and the substrate is cut out and replaced with a planarization layer to fill the area formed between the plurality of thin film transistors and the substrate. Therefore, the light absorption, reflection, refraction, or scattering effect between the layers can be reduced, and the transparency can be improved. Light rate.
  • FIG. 1 shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic flow chart of the steps of providing an array substrate with source/drain layers according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a step of providing an array substrate with source/drain layers according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram showing the steps of forming a patterned photoresist layer to cover the array substrate by using a halftone mask development process according to an embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of the step of etching the source/drain layer according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of the step of etching the interlayer insulating layer, the gate insulating layer, and the buffer layer according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of steps of a manufacturing method of an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of steps of a manufacturing method of an array substrate according to an embodiment of the present disclosure.
  • the present disclosure provides an array substrate 1000, including a substrate 100, a plurality of thin film transistors (Thin Film Transistor, TFT) 200 is disposed on the substrate 100, and a planarization layer (Planarization Layer, PLN) 300 covers the plurality of thin film transistors 200 and fills the space between the plurality of thin film transistors 200 and the substrate 100 The formed area.
  • TFT Thin Film Transistor
  • PLN Planarization Layer
  • the thin film transistor 200 includes a molybdenum (Molybdenum, Mo) light shielding layer 10 disposed on the substrate, and a buffer layer (Buffer Layer, BL) 20 is coated on the molybdenum light shielding layer 10, the active layer 30 is disposed on the buffer layer 20, and the gate insulating layer (Gate Insulator, GI) 40 is coated on the active layer 30, a patterned gate (Gate) layer 50 is disposed on the gate insulating layer 40, and an interlayer insulating layer (Inter Layer Dielectric, ILD) 60 is coated on the The patterned gate layer 50 and the source/drain (Source/Drain) layer 70 are disposed on the interlayer insulating layer 60 and connected to the active layer 30 through the first channel electrical layer Via_1.
  • Mo molybdenum
  • Buffer Layer, BL buffer layer
  • GI gate Insulator
  • ILD interlayer insulating layer
  • the array substrate 1000 of an embodiment of the present disclosure further includes a transparent common (Common) conductive layer 400 disposed on the planarization layer 300, and a passivation layer (Passivation Layer, PV) 500 is disposed on the transparent common conductive layer 400, and the transparent pixel electrode 600 is disposed on the passivation layer 500.
  • a transparent common (Common) conductive layer 400 disposed on the planarization layer 300
  • a passivation layer (Passivation Layer, PV) 500 is disposed on the transparent common conductive layer 400
  • the transparent pixel electrode 600 is disposed on the passivation layer 500.
  • the material of the transparent common conductive layer 400 may be indium tin oxide (Indium Tin Oxide). Oxide, ITO).
  • the transparent pixel electrode 600 may be made of indium tin oxide (Indium tin oxide) Tin Oxide, ITO).
  • the transparent common conductive layer 400 is electrically connected to the source/drain layer 70 through the second channel layer Via_2.
  • the transparent pixel electrode 600 is electrically connected to the source/drain layer 70 through the third channel layer Via_3 and the second channel layer Via_2.
  • planarization layer 300 and the transparent common conductive layer 400 further include a patterned metal layer (Metal Layer) 700 and an insulating layer (Insulator Layer, IL) 800.
  • Metal Layer Metal Layer
  • IL Insulating Layer
  • the patterned metal layer 700 is located above the molybdenum light shielding layer 10 to avoid affecting the light transmittance or causing light scattering.
  • the transparent common conductive layer 400 can be used as a common electrode of an in-cell touch panel, and there is a certain distance between the patterned metal layer 700 and the patterned gate (Gate) layer 50 to avoid inter-signal Crosstalk.
  • the active layer 30 further includes a poly-silicon (Poly-Silicon) layer 31 and light dopped regions on both sides of the poly-silicon layer 31 32. And a heavy dopped region 33 connected to the lightly doped region 32.
  • a poly-silicon Poly-Silicon
  • the heavily doped region 33 is used to reduce the junction resistance between the metal material of the first channel electric layer Via_1 and the semiconductor material of the active layer 30.
  • the lightly doped region 32 is used to reduce the width of the depletion region between the heavily doped region 33 and the polysilicon layer 31.
  • the present disclosure also provides a manufacturing method of an array substrate, including the following steps:
  • Step S100 Provide an array substrate with source/drain layers completed
  • step S200 using a half tone mask (Half Tone Mask) development process to form a patterned photoresist layer PR covering the array substrate;
  • a half tone mask Half Tone Mask
  • the halftone mask development process can simultaneously form patterned photoresist layers PR of different shades.
  • step S300 etching the source/drain layer 70;
  • step S400 etching the interlayer insulating layer 60, the gate insulating layer 40 and the buffer layer 20;
  • step S500 perform ashing (Ash) processing on the patterned photoresist layer PR;
  • Step S600 Perform a second etching on the source/drain layer 70 to form a patterned source/drain layer
  • Step S700 forming a planarization layer 300 to cover the array substrate.
  • the manufacturing method of the array substrate according to an embodiment of the present disclosure further includes:
  • Step S800 forming a transparent common conductive layer 400 on the planarization layer
  • Step S900 forming a passivation layer 500 on the transparent common conductive layer 400.
  • Step S1000 forming a transparent pixel electrode 600 on the passivation layer 500.
  • the step S100 of providing an array substrate with a source/drain layer completed includes:
  • Step S110 Provide a substrate 100
  • Step S120 forming a patterned molybdenum light shielding layer 10 on the substrate 100;
  • Step S130 Cover the buffer layer 20 on the patterned molybdenum light shielding layer 10;
  • Step S140 forming a patterned active layer 30 on the buffer layer 20;
  • Step S150 cover the gate insulating layer 40 on the patterned active layer 30;
  • Step S160 forming a patterned gate layer 50 on the gate insulating layer 40;
  • Step S170 cover the interlayer insulating layer 60 on the patterned gate layer 50.
  • Step S180 forming a source/drain layer 70 on the interlayer insulating layer 60.
  • the patterned active layer includes polysilicon material.
  • the patterned active layer includes a polysilicon layer, lightly doped regions located on both sides of the polysilicon layer, and The heavily doped area on both sides of the doped area.
  • the heavily doped region 33 is used to reduce the junction resistance between the metal material of the first channel electric layer Via_1 and the semiconductor material of the active layer 30.
  • the lightly doped region 32 is used to reduce the width of the depletion region between the heavily doped region 33 and the polysilicon layer 31.
  • the buffer layer, the gate insulating layer, and the interlayer insulating layer between the thin film transistor and the substrate are excavated and replaced with a planarization layer
  • the area formed between the plurality of thin film transistors and the substrate can reduce light absorption, reflection, refraction, or scattering between layers, and increase light transmittance.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本揭示提供一种阵列基板以及一种阵列基板的制作方法。所述阵列基板包括基板、多个薄膜晶体管设置于所述基板上、以及平坦化层覆盖所述多个薄膜晶体管并填充于所述多个薄膜晶体管与所述基板之间所形成的区域。

Description

阵列基板以及阵列基板的制作方法 技术领域
本揭示涉及显示技术领域，特别涉及一种阵列基板以及一种阵列基板的制作方法。
 背景技术
液晶显示屏(Liquid Crystal Display, LCD)是目前显示器的主流，但是其光线利用率长久以来不易提升，透光率有限。
采用低温多晶硅(Low Temperature Poly-Silicon, LTPS)技术制作薄膜晶体管的通道，因为其载子迁移率较高而可获得较高的电流，相应的可缩小薄膜晶体管的尺寸而增加每个子像素的透光区域面积，但是提高的透光率仍有限。
因此，目前亟需一种显示面板以解决上述问题。
 技术问题
液晶显示屏光线利用率长久以来不易提升，透光率有限。
 技术解决方案
为解决上述技术问题，本揭示提供一种阵列基板，包括基板、多个薄膜晶体管设置于所述基板上、以及平坦化层覆盖所述多个薄膜晶体管并填充于所述多个薄膜晶体管与所述基板之间所形成的区域。
于本揭示一实施例的阵列基板，其中，所述薄膜晶体管包括钼遮光层设置于所述基板上、缓冲层包覆于所述钼遮光层上、主动层设置于所述缓冲层上、栅极绝缘层包覆于所述主动层上、图案化栅极层设置于所述栅极绝缘层上、层间绝缘层包覆于所述图案化栅极层上、以及源/漏极层设置于所述层间绝缘层上并透过第一通道层接于所主动层。
于本揭示一实施例的阵列基板，还包括透明共导电层设置于所述平坦化层上、钝化层设置于所述透明共导电层上、以及透明画素电极设置于所述钝化层上。
于本揭示一实施例的阵列基板，其中，所述平坦化层与所述透明共导电层之间更包括图案化金属层及绝缘层。
于本揭示一实施例的阵列基板，其中，所述主动层更包括多晶硅层、位于所述多晶硅层两侧的轻掺杂区、以及与所述轻掺杂区相接的重掺杂区。
本揭示还提供一种阵列基板的制作方法，包括下列步骤：
提供一完成源/漏极层的阵列基板；
使用半色调光罩显影制程形成一图案化光阻层覆盖于所述阵列基板上；
蚀刻所述源/漏极层；
蚀刻所述层间绝缘层、栅极绝缘层以及所述缓冲层；
对所述图案化光阻层进行灰化处理；
对所述源/漏极层进行第二次蚀刻以形成图案化源/漏极层；以及
形成平坦化层覆盖于所述阵列基板上。
于本揭示一实施例的阵列基板的制作方法，还包括：
于所述平坦化层上形成一透明共导电层；
于所述透明共导电层上形成一钝化层；
以及于所述钝化层上形成一透明画素电极。
于本揭示一实施例的阵列基板的制作方法，其中，所述提供一完成源/漏极层的阵列基板的步骤包括：
提供一基板；
于所述基板上制作图案化钼遮光层；
于所述图案化钼遮光层上覆盖缓冲层；
于所述缓冲层上制作图案化主动层；
于所述图案化主动层覆盖栅极绝缘层；
于所述栅极绝缘层上制作图案化栅极层；
于所述图案化栅极层上覆盖层间绝缘层；以及
于所述层间绝缘层上制作源/漏极层。
于本揭示一实施例的阵列基板的制作方法，其中，图案化主动层包括多晶硅材料。
于本揭示一实施例的述的阵列基板的制作方法，其中，所述所述图案化主动层包括多晶硅层、位于所述多晶硅层两侧的轻掺杂区以及位于所述轻掺杂区两侧的重掺杂区。
 有益效果
相较于现有技术，为解决上述技术问题，由于本揭示的实施例的阵列基板以及阵列基板的制作方法中，所述薄膜晶体管与所述基板之间的缓冲层、栅极绝缘层、层间绝缘层被挖除、改以平坦化层填充于所述多个薄膜晶体管与所述基板之间所形成的区域，因此可以以降低层间的光线吸收、反射、折射或散射作用，提高透光率。
 附图说明
图1显示根据本揭示的一实施例的阵列基板的结构示意图；
图2显示根据本揭示的一实施例的阵列基板的结构示意图；
图3显示根据本揭示的一实施例的阵列基板的制作方法的流程示意图；
图4显示根据本揭示的一实施例的提供一完成源/漏极层的阵列基板的步骤的流程示意图；
图5显示根据本揭示的一实施例的提供一完成源/漏极层的阵列基板的步骤的示意图；
图6显示根据本揭示的一实施例的使用半色调光罩显影制程形成一图案化光阻层覆盖于所述阵列基板上的步骤的示意图；
图7显示根据本揭示的一实施例的蚀刻所述源/漏极层的步骤的示意图；
图8显示根据本揭示的一实施例的蚀刻所述层间绝缘层、栅极绝缘层以及所述缓冲层的步骤的示意图；
图9显示根据本揭示的一实施例的阵列基板的制作方法的步骤示意图；以及
图10显示根据本揭示的一实施例的阵列基板的制作方法的步骤示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1，本揭示提供一种阵列基板1000，包括基板100、多个薄膜晶体管(Thin Film Transistor, TFT)200设置于所述基板100上、以及平坦化层(Planarization Layer, PLN)300覆盖所述多个薄膜晶体管200并填充于所述多个薄膜晶体管200与所述基板100之间所形成的区域。
参照图1，于本揭示一实施例的阵列基板1000，其中，所述薄膜晶体管200包括钼(Molybdenum, Mo)遮光层10设置于所述基板上、缓冲层(Buffer Layer, BL)20包覆于所述钼遮光层10上、主动层30设置于所述缓冲层20上、栅极绝缘层(Gate Insulator, GI)40包覆于所述主动层30上、图案化栅极(Gate)层50设置于所述栅极绝缘层40上、层间绝缘层(Inter Layer Dielectric, ILD)60包覆于所述图案化栅极层50上、以及源/漏极(Source/Drain)层70设置于所述层间绝缘层60上并透过第一通道电层Via_1接于所主动层30。
参照图1，于本揭示一实施例的阵列基板1000，还包括透明共(Common)导电层400设置于所述平坦化层300上、钝化层(Passivation Layer, PV)500设置于所述透明共导电层400上、以及透明画素电极600设置于所述钝化层500上。
具体的，所述透明共导电层400的材料可为氧化铟锡(Indium Tin Oxide, ITO)。所述透明画素电极600的材料可为氧化铟锡(Indium Tin Oxide, ITO)。
具体的，所述透明共导电层400透过第二通道层Via_2与所述源/漏极层70电连接。所述透明画素电极600透过第三通道层Via_3及第二通道层Via_2与所述源/漏极层70电连接。
参照图2，于本揭示一实施例的阵列基板1000’，其中，所述平坦化层300与所述透明共导电层400之间更包括图案化金属层(Metal Layer)700及绝缘层(Insulator Layer, IL)800。
具体的，所述图案化金属层700位于所述钼遮光层10上方，以避免影响透光率或造成光线散射。
具体的，所述透明共导电层400可作为内嵌式触控面板的共电极，所述图案化金属层700与所述图案化栅极(Gate)层50之间有一些距离以避免讯号间的串扰。
参照图1，于本揭示一实施例的阵列基板1000，其中，所述主动层30更包括多晶硅(Poly-Silicon)层31、位于所述多晶硅层31两侧的轻掺杂(Light Dopped)区32、以及与所述轻掺杂区32相接的重掺杂(Heavy Dopped)区33。
具体的，所述重掺杂区33用以降低第一通道电层Via_1的金属材料与所述主动层30的半导体材料之间的接面电阻。所述轻掺杂区32用以减小所述重掺杂区33与所述多晶硅层31之间的空乏区宽度。
参照图3，本揭示还提供一种阵列基板的制作方法，包括下列步骤：
步骤S100：提供一完成源/漏极层的阵列基板；
参照图3及图6，步骤S200：使用半色调光罩(Half Tone Mask)显影制程形成一图案化光阻层PR覆盖于所述阵列基板上；
具体的，半色调光罩显影制程可以同时形成不同深浅的图案化光阻层PR。
参照图3及图7，步骤S300：蚀刻所述源/漏极层70；
参照图3及图8，步骤S400：蚀刻所述层间绝缘层60、栅极绝缘层40以及所述缓冲层20；
参照图3及图9，步骤S500：对所述图案化光阻层PR进行灰化(Ash)处理；
步骤S600：对所述源/漏极层70进行第二次蚀刻以形成图案化源/漏极层；以及
步骤S700：形成平坦化层300覆盖于所述阵列基板上。
参照图3及图10，于本揭示一实施例的阵列基板的制作方法，还包括：
步骤S800：于所述平坦化层上形成一透明共导电层400；
步骤S900：于所述透明共导电层400上形成一钝化层500；以及
步骤S1000：于所述钝化层500上形成一透明画素电极600。
参照图4及图5，于本揭示一实施例的阵列基板的制作方法，其中，所述提供一完成源/漏极层的阵列基板的步骤S100包括：
步骤S110：提供一基板100；
步骤S120：于所述基板100上制作图案化钼遮光层10；
步骤S130：于所述图案化钼遮光层10上覆盖缓冲层20；
步骤S140：于所述缓冲层20上制作图案化主动层30；
步骤S150：于所述图案化主动层30覆盖栅极绝缘层40；
步骤S160：于所述栅极绝缘层40上制作图案化栅极层50；
步骤S170：于所述图案化栅极层50上覆盖层间绝缘层60；以及
步骤S180：于所述层间绝缘层60上制作源/漏极层70。
于本揭示一实施例的阵列基板的制作方法，其中，图案化主动层包括多晶硅材料。
参照图1，于本揭示一实施例的述的阵列基板的制作方法，其中，所述所述图案化主动层包括多晶硅层、位于所述多晶硅层两侧的轻掺杂区以及位于所述轻掺杂区两侧的重掺杂区。
具体的，所述重掺杂区33用以降低第一通道电层Via_1的金属材料与所述主动层30的半导体材料之间的接面电阻。所述轻掺杂区32用以减小所述重掺杂区33与所述多晶硅层31之间的空乏区宽度。
由于本揭示的实施例的阵列基板以及阵列基板的制作方法中，所述薄膜晶体管与所述基板之间的缓冲层、栅极绝缘层、层间绝缘层被挖除、改以平坦化层填充于所述多个薄膜晶体管与所述基板之间所形成的区域，因此可以以降低层间的光线吸收、反射、折射或散射作用，提高透光率。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (14)

  1. 一种阵列基板，其特征在于，包括：
    基板；
    多个薄膜晶体管设置于所述基板上；以及
    平坦化层覆盖所述多个薄膜晶体管并填充于所述多个薄膜晶体管与所述基板之间所形成的区域。
  2. 如权利要求1所述的阵列基板，其特征在于，所述薄膜晶体管包括：
    钼遮光层设置于所述基板上；
    缓冲层包覆于所述钼遮光层上；
    主动层设置于所述缓冲层上；
    栅极绝缘层包覆于所述主动层上；
    图案化栅极层设置于所述栅极绝缘层上；
    层间绝缘层包覆于所述图案化栅极层上；以及
    源/漏极层设置于所述层间绝缘层上并透过第一通道层接于所主动层。
  3. 如权利要求1所述的阵列基板，其特征在于，还包括：
    透明共导电层设置于所述平坦化层上；
    钝化层设置于所述透明共导电层上；以及
    透明画素电极设置于所述钝化层上。
  4. 如权利要求3所述的阵列基板，其特征在于，所述平坦化层与所述透明共导电层之间更包括图案化金属层及绝缘层。
  5. 如权利要求3所述的阵列基板，其特征在于，所述主动层更包括：
    多晶硅层；
    位于所述多晶硅层两侧的轻掺杂区；以及
    与所述轻掺杂区相接的重掺杂区。
  6. 一种阵列基板的制作方法，其特征在于，包括下列步骤：
    提供一完成源/漏极层的阵列基板；
    使用半色调光罩显影制程形成一图案化光阻层覆盖于所述阵列基板上；
    蚀刻所述源/漏极层；
    蚀刻所述层间绝缘层、栅极绝缘层以及所述缓冲层；
    对所述图案化光阻层进行灰化处理；
    对所述源/漏极层进行第二次蚀刻以形成图案化源/漏极层；以及
    形成平坦化层覆盖于所述阵列基板上。
  7. 如权利要求6所述的阵列基板的制作方法，其特征在于，还包括：
    于所述平坦化层上形成一透明共导电层；
    于所述透明共导电层上形成一钝化层；以及
    于所述钝化层上形成一透明画素电极。
  8. 如权利要求1所述的阵列基板的制作方法，其特征在于，所述提供一完成源/漏极层的阵列基板的步骤包括：
    提供一基板；
    于所述基板上制作图案化钼遮光层；
    于所述图案化钼遮光层上覆盖缓冲层；
    于所述缓冲层上制作图案化主动层；
    于所述图案化主动层覆盖栅极绝缘层；
    于所述栅极绝缘层上制作图案化栅极层；
    于所述图案化栅极层上覆盖层间绝缘层；以及
    于所述层间绝缘层上制作源/漏极层。
  9. 如权利要求8所述的阵列基板的制作方法，其特征在于，图案化主动层包括多晶硅材料。
  10. 如权利要求8所述的阵列基板的制作方法，其特征在于，所述所述图案化主动层包括多晶硅层、位于所述多晶硅层两侧的轻掺杂区以及位于所述轻掺杂区两侧的重掺杂区。
  11.      一种阵列基板，其特征在于，包括：
    基板；
    多个薄膜晶体管设置于所述基板上；
    平坦化层覆盖所述多个薄膜晶体管并填充于所述多个薄膜晶体管与所述基板之间所形成的区域；
    透明共导电层设置于所述平坦化层上；
    钝化层设置于所述透明共导电层上；以及
    透明画素电极设置于所述钝化层上，其中，所述薄膜晶体管包括：
    钼遮光层设置于所述基板上；
    缓冲层包覆于所述钼遮光层上；
    主动层设置于所述缓冲层上；
    栅极绝缘层包覆于所述主动层上；
    图案化栅极层设置于所述栅极绝缘层上；
    层间绝缘层包覆于所述图案化栅极层上；以及
    源/漏极层设置于所述层间绝缘层上并透过第一通道层接于所主动层。
  12. 如权利要求11所述的阵列基板，其特征在于，所述平坦化层与所述透明共导电层之间更包括图案化金属层及绝缘层。
  13. 如权利要求12所述的阵列基板，其特征在于，所述图案化金属层位于所述钼遮光层上方。
  14. 如权利要求13所述的阵列基板，其特征在于，所述主动层更包括：
    多晶硅层；
    位于所述多晶硅层两侧的轻掺杂区；以及
    与所述轻掺杂区相接的重掺杂区。
PCT/CN2019/106316 2019-05-17 2019-09-18 阵列基板以及阵列基板的制作方法 WO2020232926A1 (zh)

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