WO2019100489A1 - 背沟道蚀刻型tft基板及其制作方法 - Google Patents

背沟道蚀刻型tft基板及其制作方法 Download PDF

Info

Publication number
WO2019100489A1
WO2019100489A1 PCT/CN2017/117321 CN2017117321W WO2019100489A1 WO 2019100489 A1 WO2019100489 A1 WO 2019100489A1 CN 2017117321 W CN2017117321 W CN 2017117321W WO 2019100489 A1 WO2019100489 A1 WO 2019100489A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon oxide
oxide film
layer
hydrophobicity
back channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/117321
Other languages
English (en)
French (fr)
Inventor
姜春生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/749,096 priority Critical patent/US10332988B2/en
Publication of WO2019100489A1 publication Critical patent/WO2019100489A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H10P14/6519—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a back channel etch type TFT substrate and a method of fabricating the same.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used in applications such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens and notebook computers. Screen, etc.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in current liquid crystal display devices and active matrix OLED display devices, and is directly related to the development direction of high performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various, and an amorphous silicon (a-Si) material is a relatively common one.
  • the conventional a-Si has a mobility of only about 1 cm 2 /(Vs) which cannot meet the requirements, and indium gallium zinc oxide (IGZO) has a mobility of more than 10 cm 2 /(Vs) or more, and the preparation of the corresponding thin film transistor is compatible with the existing a-Si semiconductor-driven production line, and has rapidly become a recent Show the focus of research and development in the field.
  • IGZO indium gallium zinc oxide
  • IGZO TFTs Compared to traditional a-Si TFTs, IGZO TFTs have the following advantages:
  • the resolution of the IGZO TFT display backplane can be more than twice that of the a-Si TFT, and the carrier concentration in the IGZO material is high.
  • the mobility is large, which can reduce the size of the TFT and ensure the resolution is improved;
  • IGZO TFT has a leakage current of less than 1pA; the driving frequency is reduced from the original 30-50Hz to 2-5Hz, and even 1Hz can be achieved through a special process.
  • the alignment of the liquid crystal molecules can be maintained without affecting the quality of the picture, thereby reducing the power consumption of the display backplane; in addition, the high mobility of the IGZO semiconductor material allows a smaller size TFT to provide sufficient The charging capacity and the higher capacitance value, and the aperture ratio of the liquid crystal panel is increased, the effective area of light penetration is increased, and the same brightness can be achieved with less backplane components or low power consumption, thereby reducing energy consumption;
  • IGZO as a semiconductor active layer TFT generally adopts an etch barrier (ESL) structure, and an etch barrier (Etch Stop Layer, ESL) exists, and a source/drain etching process is performed.
  • ESL etch barrier
  • ESL Etch Stop Layer
  • the barrier layer can effectively protect IGZO from being affected, ensuring that the TFT has excellent semiconductor characteristics.
  • the preparation process of the IGZO TFT of the ESL structure is complicated, and it requires 6 times of yellow light process, which is not conducive to cost reduction. Therefore, the industry generally pursues the IGZO TFT of the Back Channel Etching (BCE) structure with less yellow light process. Development.
  • the IGZO TFT device with back-channel etched structure has two balances after preparation: the first balance is the decomposition of H 2 O into electrons and polar water molecules; the second equilibrium is the unbalanced O - ion to obtain electrons to form electron traps. state. When any balance is broken, the performance of the TFT device is affected.
  • the first balance when the H 2 O in the air on the surface of the passivation layer increases, the equilibrium shifts toward the decomposition of H 2 O, and electrons and polar water molecules increase.
  • the semiconductor For the N-type electron conductive TFT device, the semiconductor The characteristic curve drifts in the negative direction, and the device performance is affected.
  • An object of the present invention is to provide a method for fabricating a back channel etched TFT substrate, which can ensure that the surface of the passivation layer in contact with air has strong hydrophobicity, prevents external water vapor from entering the back channel, and ensures the passivation layer and
  • the contact surface of the IGZO active layer has a lower oxygen content, which reduces the probability of forming an unbalanced O - ion at the interface between the passivation layer and the IGZO active layer, and prevents the source and drain from being oxidized to ensure stable device performance.
  • Another object of the present invention is to provide a back channel etch type TFT substrate with a strong device Stability.
  • the present invention provides a method for fabricating a back channel etched TFT substrate, comprising:
  • first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of Si:O atoms, both of which are 1:X, wherein X is less than 2; the first silicon oxide film and the second silicon oxide film are passivated.
  • Floor depositing a first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition, and depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of Si:O atoms, both of which are 1:X, wherein X is less than 2; the first silicon oxide film and the second silicon oxide film are passivated.
  • Floor depositing a first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition, and depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of
  • Oxygen element implantation is performed on the superficial layer of the second silicon oxide film by an ion implantation method, so that the ratio of Si:O atoms in the superficial layer of the second silicon oxide film is close to the ratio of Si:O atoms in SiO 2 or The same, that is, the ratio of Si:O atoms in the superficial layer of the second silicon oxide film is 1:Y, wherein Y is between 1.8 and 2, and Y is greater than X, and a back channel etched TFT substrate is obtained. .
  • the deposition power of the second silicon oxide film is greater than the deposition power of the first silicon oxide film
  • the bond angle of the Si-O-Si bond in the second silicon oxide film is smaller than the bond angle of the Si-O-Si bond in the first silicon oxide film, so that the hydrophobicity of the second silicon oxide film is greater than The hydrophobicity of the first layer of silicon oxide film.
  • the superficial layer of the second silicon oxide film is more hydrophobic than the other regions of the second silicon oxide film except the superficial layer, and the second layer of the silicon oxide film is other than the superficial layer.
  • the hydrophobicity of the region is greater than the hydrophobicity of the first layer of silicon oxide film.
  • the thickness of the second silicon oxide film is greater than the thickness of the first silicon oxide film.
  • the thickness of the first silicon oxide film is The thickness of the second silicon oxide film is
  • the present invention provides a back channel etch type TFT substrate, comprising: a substrate substrate, a gate electrode disposed on the substrate substrate, a gate insulating layer disposed on the gate electrode, and the gate electrode An active layer on the insulating layer, a source and a drain disposed on the active layer and spaced apart from each other, and a passivation layer disposed on the source, the drain and the active layer;
  • the passivation layer includes a first silicon oxide film disposed on the source, the drain, and the active layer, and a second silicon oxide film disposed on the first silicon oxide film;
  • the ratio of Si:O atoms in the superficial layer of the two-layer silicon oxide film is close to or the same as the ratio of Si:O atoms in the SiO 2 , that is, the ratio of Si:O atoms in the superficial layer of the second silicon oxide film is 1 Y, wherein Y is between 1.8 and 2; the area other than the superficial layer of the second silicon oxide film is the same as the ratio of Si:O atoms in the first silicon oxide film, both are 1 :X, where X is less than Y.
  • the bond angle of the Si—O—Si bond in the second silicon oxide film is smaller than the bond angle of the Si—O—Si bond in the first silicon oxide film, and thus the hydrophobicity of the second silicon oxide film It is larger than the hydrophobicity of the first silicon oxide film.
  • the superficial layer of the second silicon oxide film is more hydrophobic than the other regions of the second silicon oxide film except the superficial layer, and the second layer of the silicon oxide film is other than the superficial layer.
  • the hydrophobicity of the region is greater than the hydrophobicity of the first layer of silicon oxide film.
  • the thickness of the second silicon oxide film is greater than the thickness of the first silicon oxide film.
  • the thickness of the first silicon oxide film is The thickness of the second silicon oxide film is
  • the present invention also provides a method for fabricating a back channel etched TFT substrate, comprising:
  • first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of Si:O atoms, both of which are 1:X, wherein X is less than 2; the first silicon oxide film and the second silicon oxide film are passivated.
  • Floor depositing a first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition, and depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of Si:O atoms, both of which are 1:X, wherein X is less than 2; the first silicon oxide film and the second silicon oxide film are passivated.
  • Floor depositing a first silicon oxide film on the source, drain and active layers by plasma enhanced chemical vapor deposition, and depositing a second silicon oxide film on the first silicon oxide film,
  • the silicon oxide film and the second silicon oxide film have the same ratio of
  • Oxygen element implantation is performed on the superficial layer of the second silicon oxide film by an ion implantation method, so that the ratio of Si:O atoms in the superficial layer of the second silicon oxide film is close to the ratio of Si:O atoms in SiO 2 or The same, that is, the ratio of Si:O atoms in the superficial layer of the second silicon oxide film is 1:Y, wherein Y is between 1.8 and 2, and Y is greater than X, and a back channel etched TFT substrate is obtained. ;
  • the deposition power of the second silicon oxide film is greater than the deposition power of the first silicon oxide film. Therefore, the bond angle of the Si—O—Si bond in the second silicon oxide film is smaller than the bond angle of the Si—O—Si bond in the first silicon oxide film, so that the second silicon oxide film is hydrophobic. Is greater than the hydrophobicity of the first layer of silicon oxide film;
  • hydrophobicity of the superficial layer of the second silicon oxide film is greater than the hydrophobicity of the region other than the superficial layer of the second silicon oxide film, except for the superficial layer of the second silicon oxide film
  • the hydrophobicity of the other regions is greater than the hydrophobicity of the first silicon oxide film
  • the thickness of the second silicon oxide film is greater than the thickness of the first silicon oxide film
  • the thickness of the first silicon oxide film is The thickness of the second silicon oxide film is
  • the method for fabricating a back channel etched TFT substrate of the present invention uses a low deposition power and a low oxygen content to deposit a first silicon oxide film, and then increases deposition power to maintain a low oxygen content deposition on the first silicon oxide film.
  • the first silicon oxide film and the second silicon oxide film form a passivation layer, and finally an oxygen implantation is performed on the superficial layer of the second silicon oxide film by an ion implantation method to make a second
  • the proportion of Si:O atoms in the superficial layer of the silicon oxide film is close to or the same as the ratio of Si:O atoms in SiO 2 , ensuring that the side of the passivation layer in contact with air has strong hydrophobicity, preventing external water vapor from entering the back trench.
  • the circuit ensures that the side of the passivation layer in contact with the IGZO active layer has a lower oxygen content, reduces the probability of forming a non-equilibrium O - ion at the interface between the passivation layer and the IGZO active layer, and prevents the source and drain from being oxidized.
  • the device performance is stable.
  • the back channel etch type TFT substrate of the present invention is obtained by the above method and has strong device stability.
  • FIG. 1 is a flow chart showing a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step S1 of a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step S2 of a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 4 and FIG. 5 are schematic diagrams showing the step S3 of the method for fabricating the back channel etched TFT substrate of the present invention
  • FIG. 5 is a schematic structural view of the back channel etched TFT substrate of the present invention.
  • the present invention provides a method for fabricating a back channel etched TFT substrate, including the following steps:
  • Step S1 as shown in FIG. 2, a base substrate 10 is provided, on which the gate electrode 20, the gate insulating layer 30 and the active layer 40 are sequentially formed from bottom to top, in the active layer 40 upper shape
  • the source 51 and the drain 52 are disposed at intervals.
  • the material of the gate insulating layer 30 includes silicon oxide (SiO x ); the material of the active layer 40 includes indium gallium zinc oxide (IGZO); the materials of the source 51 and the drain 52 include Copper (Cu).
  • Step S2 depositing a first silicon oxide film 61 on the source 51, the drain 52, and the active layer 40 by plasma enhanced chemical vapor deposition (PECVD), in the first
  • PECVD plasma enhanced chemical vapor deposition
  • a second silicon oxide film 62 is deposited on the silicon oxide film 61.
  • the ratio of Si:O atoms in the first silicon oxide film 61 and the second silicon oxide film 62 are both 1:X, wherein X is smaller than 2; the first silicon oxide film 61 and the second silicon oxide film 62 constitute a passivation layer 60.
  • the deposition power of the second silicon oxide film 62 is greater than that of the first silicon oxide film.
  • the deposition power of 61 so that the bond angle of the Si-O-Si bond in the second silicon oxide film 62 is smaller than the bond angle of the Si-O-Si bond in the first silicon oxide film 61, so that the The hydrophobicity of the two-layer silicon oxide film 62 is greater than the hydrophobicity of the first silicon oxide film 61.
  • the theoretical basis is that as the deposition power of plasma enhanced chemical vapor deposition increases, the vibration absorption peak of the Si-O-Si bond inside the silicon oxide film shifts blue, the bond angle gradually decreases, and the contact angle of the silicon oxide film (Hydrophilicity) gradually increases, and when the contact angle is maximum, the bond angle of the Si-O-Si bond inside the silicon oxide film is close to 112°, which is very close to the bond angle of water molecules of 105°, when Si-O-Si bond When the bond angle is close to the bond angle of the water molecule, the contact angle (hydrophobicity) of the silicon oxide film is the largest.
  • the purpose of depositing the first silicon oxide film 61 with lower power is to prevent the excessive energy of the plasma from bombarding the active layer 40 to cause damage to the surface of the active layer 40.
  • the process of depositing the first silicon oxide film 61 and the second silicon oxide film 62 by plasma enhanced chemical vapor deposition maintains a low oxygen content, thereby ensuring that the first silicon oxide film 61 has a low oxygen content.
  • the probability of forming an unbalanced O - ion at the interface between the first silicon oxide film 61 and the IGZO active layer 40 is reduced, and the performance of the TFT device is stabilized.
  • the thickness of the second silicon oxide film 62 is greater than the thickness of the first silicon oxide film 61.
  • the thickness of the first silicon oxide film 61 is The thickness of the second silicon oxide film 62 is
  • Step S3 the shallow layer 621 of the second silicon oxide film 62 is implanted with oxygen by an ion implantation method to make the Si in the superficial layer 621 of the second silicon oxide film 62.
  • the ratio of O atoms to the ratio of Si:O atoms in SiO 2 is close to or the same, that is, the ratio of Si:O atoms in the superficial layer 621 of the second silicon oxide film 62 is 1:Y, wherein Y is between 1.8 and Between 2 and Y is larger than X, a back channel etch type TFT substrate is obtained.
  • the first silicon oxide film 61 and the second silicon oxide film 62 both contain a large amount of oxygen vacancies, when the water molecules and the first When the silicon oxide film 61 is in contact with the second silicon oxide film 62, it is attracted by oxygen vacancies, so that the first silicon oxide film 61 and the second silicon oxide film 62 exhibit a certain degree of hydrophilicity;
  • the ratio of Si:O atoms in the superficial layer 621 of the second silicon oxide film 62 is close to or the same as the ratio of Si:O atoms in the SiO 2 , that is,
  • the superficial layer 621 of the second silicon oxide film 62 has no or a small amount of oxygen vacancies inside, and lattice oxygen is repelled when water molecules are in contact with the second silicon oxide film 62, and the second silicon oxide film 62 is
  • the superficial layer 621 exhibits a strong hydrophobicity, ensuring that H 2 O in the environment cannot enter the back channel of the TFT device through the second silicon oxide film 62, thereby preventing the polarity of water molecules in the environment from affecting the performance of the TFT; due to the lower oxygen content of the first layer of silicon oxide film 61, reducing the first silicon oxide film 61 and the IGZO active layer 40 formed at the interface unbalanced O - probability of ions, the source and drain can be prevented while making copper
  • the electrode 52 is
  • the hydrophobicity of the superficial layer 621 of the second silicon oxide film 62 is greater than the hydrophobicity of the region other than the superficial layer 621 of the second silicon oxide film 62, the second silicon oxide film.
  • the hydrophobicity of the region other than the superficial layer 621 in 62 is greater than the hydrophobicity of the first silicon oxide film 61.
  • the method for fabricating the back channel etched TFT substrate of the present invention uses a low deposition power and a low oxygen content to deposit a first silicon oxide film 61, and then increases the deposition power to maintain a low oxygen content and deposits a second layer on the first silicon oxide film 61.
  • the silicon oxide film 62, the first silicon oxide film 61 and the second silicon oxide film 62 constitute a passivation layer 60, and finally the oxygen layer is implanted into the superficial layer 621 of the second silicon oxide film 62 by an ion implantation method.
  • the ratio of Si:O atoms in the superficial layer 621 of the second silicon oxide film 62 is close to or the same as the ratio of Si:O atoms in the SiO 2 , ensuring that the side of the passivation layer 60 in contact with the air has a strong hydrophobicity.
  • the probability is that the source and drain electrodes 52 are prevented from being oxidized to ensure stable device performance.
  • the present invention further provides a back channel etch type TFT substrate, comprising: a base substrate 10 and a gate disposed on the base substrate 10 a gate electrode 30 disposed on the gate electrode 20, an active layer 40 disposed on the gate insulating layer 30, and a source 51 disposed on the active layer 40 and spaced apart from each other And a drain 52, and a passivation layer 60 disposed on the source 51, the drain 52 and the active layer 40;
  • the passivation layer 60 includes a first silicon oxide film 61 disposed on the source 51, the drain 52, and the active layer 40, and a second layer oxide disposed on the first silicon oxide film 61.
  • the Si:O atomic ratio in the surface layer 621 is 1:Y, wherein Y is between 1.8 and 2; the second silicon oxide film 62 has a region other than the superficial layer 621 and the first layer of silicon oxide.
  • the ratio of Si:O atoms in the film 61 is the same, both being 1:X, where X is less than Y.
  • a bond angle of the Si—O—Si bond in the second silicon oxide film 62 is smaller than a bond angle of the Si—O—Si bond in the first silicon oxide film 61 , and thus the second layer is oxidized.
  • the hydrophobicity of the silicon thin film 62 is greater than the hydrophobicity of the first silicon oxide thin film 61.
  • the shallowness of the second silicon oxide film 62 is The surface layer 621 exhibits a stronger hydrophobicity than the other regions except the superficial layer 621 of the second silicon oxide film 62 and the first silicon oxide film 61.
  • the hydrophobicity of the superficial layer 621 of the second silicon oxide film 62 is greater than the hydrophobicity of the region other than the superficial layer 621 of the second silicon oxide film 62, the second silicon oxide film.
  • the hydrophobicity of the region other than the superficial layer 621 in 62 is greater than the hydrophobicity of the first silicon oxide film 61.
  • the material of the gate insulating layer 30 includes silicon oxide (SiO x ); the material of the active layer 40 includes indium gallium zinc oxide (IGZO); the materials of the source 51 and the drain 52 include Copper (Cu).
  • the thickness of the second silicon oxide film 62 is greater than the thickness of the first silicon oxide film 61.
  • the thickness of the first silicon oxide film 61 is The thickness of the second silicon oxide film 62 is
  • the back channel etched TFT substrate of the present invention is obtained by the above method, and the passivation layer 60 includes a first silicon oxide film 61 and a second silicon oxide film 62 disposed on the first silicon oxide film 61.
  • the proportion of Si:O atoms in the superficial layer 621 of the second silicon oxide film 62 is close to or the same as the ratio of Si:O atoms in the SiO 2 , and the oxygen content of the first silicon oxide film 61 is lower than
  • the oxygen content in the superficial layer 621 of the second silicon oxide film 62 ensures that the surface of the passivation layer 60 in contact with the air has a strong hydrophobicity, preventing external water vapor from entering the back channel, and ensuring the passivation layer 60 and the IGZO.
  • the side in contact with the active layer 40 has a lower oxygen content, reducing the probability of the interface between the passivation layer 60 and the IGZO active layer 40 forming an unbalanced O - ion, while preventing the source and drain electrodes 52 from being oxidized, and ensuring stable device performance.
  • the present invention provides a back channel etch type TFT substrate and a method of fabricating the same.
  • the method for fabricating the back channel etched TFT substrate of the present invention uses a low deposition power and a low oxygen content to deposit a first silicon oxide film, and then increases the deposition power to maintain a low oxygen content to deposit a second silicon oxide on the first silicon oxide film.
  • the first silicon oxide film and the second silicon oxide film form a passivation layer, and finally an oxygen implantation method is performed on the superficial layer of the second silicon oxide film by an ion implantation method to make the second silicon oxide film
  • the proportion of Si:O atoms in the superficial layer is close to or the same as the ratio of Si:O atoms in SiO 2 , ensuring that the side of the passivation layer in contact with the air has strong hydrophobicity, preventing external water vapor from entering the back channel and ensuring bluntness.
  • the side of the layer that is in contact with the IGZO active layer has a lower oxygen content, which reduces the probability of forming a non-equilibrium O - ion at the interface between the passivation layer and the IGZO active layer, and prevents the source and drain from being oxidized to ensure stable device performance.
  • the back channel etch type TFT substrate of the present invention is obtained by the above method and has strong device stability.

Landscapes

  • Thin Film Transistor (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)

Abstract

一种背沟道蚀刻型TFT基板及其制作方法。所述制作方法采用低沉积功率低氧含量沉积第一层氧化硅薄膜，之后提高沉积功率维持低氧含量在第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层，最后利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，保证钝化层与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层与IGZO有源层接触的一面具有较低氧含量，减少钝化层和IGZO有源层界面形成非平衡O-离子的几率。

Description

背沟道蚀刻型TFT基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型TFT基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕和笔记本电脑屏幕等。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅(a-Si)材料是比较常见的一种。
随着液晶显示装置和OLED显示装置朝着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/(Vs)左右的迁移率已经无法满足要求，以铟镓锌氧化物(IGZO)为代表的金属氧化物材料具备超过10cm2/(Vs)以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡(ESL)结构，由于有刻蚀阻挡层(Etch Stop Layer，ESL)存在，源漏极(Source/Drain)的蚀刻过程时，刻蚀阻挡层可以有效的保护IGZO不受到影响，保证TFT具有优异的半导体特性。但是ESL结构的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求黄光工艺更少的背沟道蚀刻(Back Channel Etching，BCE)结构的IGZO TFT的开发。
背沟道蚀刻结构的IGZO TFT器件在制备完成后，具有两个平衡：第一个平衡是H2O分解为电子和极性水分子；第二个平衡是非平衡O-离子获得电子形成电子陷阱态。任意一个平衡被破坏时，TFT器件的性能都会受到影响。针对第一个平衡，当钝化层表面的空气中的H2O增加时，平衡向H2O分解方向移动，电子和极性水分子增加，对于N型电子导电性TFT器件而言，半导体特性曲线向负向飘移，器件性能受到影响；针对第二个平衡，当钝化层和IGZO有源层界面的氧含量过高时，形成非平衡O-离子，平衡向形成电子陷阱态移动并俘获电子，对于N型电子导电性TFT器件而言，半导体特性曲线向正向飘移，器件性能受到影响。
发明内容
本发明的目的在于提供一种背沟道蚀刻型TFT基板的制作方法，能够保证钝化层与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层与IGZO有源层接触的一面具有较低氧含量，减少钝化层和IGZO有源层界面形成非平衡O-离子的几率，同时能够防止源漏极被氧化，保证器件性能稳定。
本发明的目的还在于提供一种背沟道蚀刻型TFT基板，具有较强的器 件稳定性。
为实现上述目的，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上从下到上依次形成栅极、栅极绝缘层及有源层，在所述有源层上形成间隔设置的源极与漏极；
采用等离子体增强化学气相沉积法在所述源极、漏极及有源层上沉积第一层氧化硅薄膜，在所述第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于2；所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层；
利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介于1.8与2之间，且Y大于X，制得背沟道蚀刻型TFT基板。
采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜与第二层氧化硅薄膜时，所述第二层氧化硅薄膜的沉积功率大于所述第一层氧化硅薄膜的沉积功率，因此所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，从而所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性。
所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性。
所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度。
所述第一层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000001
所述第二层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000002
本发明提供一种背沟道蚀刻型TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上且间隔设置的源极与漏极、以及设于所述源极、漏极及有源层上的钝化层；
所述钝化层包括设于所述源极、漏极及有源层上的第一层氧化硅薄膜与设于所述第一层氧化硅薄膜上的第二层氧化硅薄膜；所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介 于1.8与2之间；所述第二层氧化硅薄膜中除浅表层以外的其它区域与所述第一层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于Y。
所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，因此所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性。
所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性。
所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度。
所述第一层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000003
所述第二层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000004
本发明还提供一种背沟道蚀刻型TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上从下到上依次形成栅极、栅极绝缘层及有源层，在所述有源层上形成间隔设置的源极与漏极；
采用等离子体增强化学气相沉积法在所述源极、漏极及有源层上沉积第一层氧化硅薄膜，在所述第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于2；所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层；
利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介于1.8与2之间，且Y大于X，制得背沟道蚀刻型TFT基板；
其中，采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜与第二层氧化硅薄膜时，所述第二层氧化硅薄膜的沉积功率大于所述第一层氧化硅薄膜的沉积功率，因此所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，从而所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性；
其中，所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性；
其中，所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度；
其中，所述第一层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000005
所述第二层氧化硅薄膜的厚度为
Figure PCTCN2017117321-appb-000006
本发明的有益效果：本发明的背沟道蚀刻型TFT基板的制作方法采用低沉积功率低氧含量沉积第一氧化硅薄膜，之后提高沉积功率维持低氧含量在第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层，最后利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，保证钝化层与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层与IGZO有源层接触的一面具有较低氧含量，减少钝化层和IGZO有源层界面形成非平衡O-离子的几率，同时能够防止源漏极被氧化，保证器件性能稳定。本发明的背沟道蚀刻型TFT基板采用上述方法制得，具有较强的器件稳定性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的背沟道蚀刻型TFT基板的制作方法的流程图；
图2为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S1的示意图；
图3为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S2的示意图；
图4与图5为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S3的示意图且图5为本发明的背沟道蚀刻型TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供衬底基板10，在所述衬底基板10上从下到上依次形成栅极20、栅极绝缘层30及有源层40，在所述有源层40上形 成间隔设置的源极51与漏极52。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiOx)；所述有源层40的材料包括铟镓锌氧化物(IGZO)；所述源极51与漏极52的材料包括铜(Cu)。
步骤S2、如图3所示，采用等离子体增强化学气相沉积法(PECVD)在所述源极51、漏极52及有源层40上沉积第一层氧化硅薄膜61，在所述第一层氧化硅薄膜61上沉积第二层氧化硅薄膜62，所述第一层氧化硅薄膜61与第二层氧化硅薄膜62中的Si：O原子比例相同，均为1：X，其中X小于2；所述第一层氧化硅薄膜61与第二层氧化硅薄膜62组成钝化层60。
具体的，采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜61与第二层氧化硅薄膜62时，所述第二层氧化硅薄膜62的沉积功率大于所述第一层氧化硅薄膜61的沉积功率，因此所述第二层氧化硅薄膜62中Si-O-Si键的键角小于所述第一层氧化硅薄膜61中Si-O-Si键的键角，从而所述第二层氧化硅薄膜62的疏水性大于所述第一层氧化硅薄膜61的疏水性。理论依据为：随着等离子体增强化学气相沉积的沉积功率的增大，氧化硅薄膜内部Si-O-Si键的振动吸收峰发生蓝移，键角逐渐减小，而氧化硅薄膜的接触角(疏水性)逐渐增大，接触角最大时，氧化硅薄膜内部Si-O-Si键的键角接近112°，这与水分子的键角105°非常接近，当Si-O-Si键的键角接近水分子的键角时，氧化硅薄膜的接触角(疏水性)最大。
具体的，采用较低功率来沉积所述第一层氧化硅薄膜61的目的是防止能量过高的等离子体对有源层40进行轰击造成有源层40表面受到损害。
具体的，采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜61与第二层氧化硅薄膜62的过程均保持低氧含量，保证第一层氧化硅薄膜61具有较低的氧含量，减少第一层氧化硅薄膜61和IGZO有源层40界面形成非平衡O-离子的几率，保证TFT器件性能稳定。
具体的，所述第二层氧化硅薄膜62的厚度大于所述第一层氧化硅薄膜61的厚度。
优选的，所述第一层氧化硅薄膜61的厚度为
Figure PCTCN2017117321-appb-000007
所述第二层氧化硅薄膜62的厚度为
Figure PCTCN2017117321-appb-000008
步骤S3、如图4与图5所示，利用离子注入方法对第二层氧化硅薄膜62的浅表层621进行氧元素注入，使所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例为1：Y，其中Y介于1.8与2之间，且Y大于X，制得背沟道蚀刻型TFT基板。
具体的，对第二层氧化硅薄膜62进行氧元素注入之前，所述第一层氧化硅薄膜61与第二层氧化硅薄膜62内部均含有大量的氧空位，当水分子与所述第一层氧化硅薄膜61与第二层氧化硅薄膜62接触时被氧空位吸引，从而所述第一层氧化硅薄膜61与第二层氧化硅薄膜62表现为一定程度的亲水性；
对第二层氧化硅薄膜62进行氧元素注入之后，由于所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜62的浅表层621内部没有或含有少量的氧空位，当水分子与第二层氧化硅薄膜62接触时晶格氧排斥，所述第二层氧化硅薄膜62的浅表层621体现出较强的疏水性，保证环境中的H2O无法通过第二层氧化硅薄膜62进入TFT器件的背沟道，防止环境中水分子的极性对TFT性能造成影响；同时，由于第一层氧化硅薄膜61中的氧含量较低，减少了第一层氧化硅薄膜61和IGZO有源层40界面形成非平衡O-离子的几率，同时能够防止采用铜制作的源漏极52被氧化，保证制得的背沟道蚀刻型TFT基板的性能稳定。
具体的，所述第二层氧化硅薄膜62的浅表层621的疏水性大于所述第二层氧化硅薄膜62中除浅表层621以外的其它区域的疏水性，所述第二层氧化硅薄膜62中除浅表层621以外的其它区域的疏水性大于所述第一层氧化硅薄膜61的疏水性。
本发明的背沟道蚀刻型TFT基板的制作方法采用低沉积功率低氧含量沉积第一层氧化硅薄膜61，之后提高沉积功率维持低氧含量在第一层氧化硅薄膜61上沉积第二层氧化硅薄膜62，所述第一层氧化硅薄膜61与第二层氧化硅薄膜62组成钝化层60，最后利用离子注入方法对第二层氧化硅薄膜62的浅表层621进行氧元素注入，使所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，保证钝化层60与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层60与IGZO有源层40接触的一面具有较低氧含量，减少钝化层60和IGZO有源层40界面形成非平衡O-离子的几率，同时能够防止源漏极52被氧化，保证器件性能稳定。
请参阅图5，基于上述背沟道蚀刻型TFT基板的制作方法，本发明还提供一种背沟道蚀刻型TFT基板，包括：衬底基板10、设于所述衬底基板10上的栅极20、设于所述栅极20上的栅极绝缘层30、设于所述栅极绝缘层30上的有源层40、设于所述有源层40上且间隔设置的源极51与漏极52、以及设于所述源极51、漏极52及有源层40上的钝化层60；
所述钝化层60包括设于所述源极51、漏极52及有源层40上的第一层氧化硅薄膜61与设于所述第一层氧化硅薄膜61上的第二层氧化硅薄膜62；所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例为1：Y，其中Y介于1.8与2之间；所述第二层氧化硅薄膜62中除浅表层621以外的其它区域与所述第一层氧化硅薄膜61中的Si：O原子比例相同，均为1：X，其中X小于Y。
具体的，所述第二层氧化硅薄膜62中Si-O-Si键的键角小于所述第一层氧化硅薄膜61中Si-O-Si键的键角，因此所述第二层氧化硅薄膜62的疏水性大于所述第一层氧化硅薄膜61的疏水性。
具体的，由于所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，因此所述第二层氧化硅薄膜62的浅表层621相较于所述第二层氧化硅薄膜62中除浅表层621以外的其它区域及第一层氧化硅薄膜61表现出较强的疏水性。
具体的，所述第二层氧化硅薄膜62的浅表层621的疏水性大于所述第二层氧化硅薄膜62中除浅表层621以外的其它区域的疏水性，所述第二层氧化硅薄膜62中除浅表层621以外的其它区域的疏水性大于所述第一层氧化硅薄膜61的疏水性。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiOx)；所述有源层40的材料包括铟镓锌氧化物(IGZO)；所述源极51与漏极52的材料包括铜(Cu)。
具体的，所述第二层氧化硅薄膜62的厚度大于所述第一层氧化硅薄膜61的厚度。
优选的，所述第一层氧化硅薄膜61的厚度为
Figure PCTCN2017117321-appb-000009
所述第二层氧化硅薄膜62的厚度为
Figure PCTCN2017117321-appb-000010
本发明的背沟道蚀刻型TFT基板采用上述方法制得，其钝化层60包括第一层氧化硅薄膜61与设于所述第一层氧化硅薄膜61上的第二层氧化硅薄膜62；所述第二层氧化硅薄膜62的浅表层621中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，所述第一层氧化硅薄膜61的氧含量低于所述第二层氧化硅薄膜62的浅表层621中的氧含量，保证钝化层60与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层60与IGZO有源层40接触的一面具有较低氧含量，减少钝化层60和IGZO有源层40界面形成非平衡O-离子的几率，同时能够防止源漏极52被氧化，保证器件性能稳定。
综上所述，本发明提供一种背沟道蚀刻型TFT基板及其制作方法。本发明的背沟道蚀刻型TFT基板的制作方法采用低沉积功率低氧含量沉积第一层氧化硅薄膜，之后提高沉积功率维持低氧含量在第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层，最后利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，保证钝化层与空气接触的一面具有较强的疏水性，防止外界水汽进入背沟道，同时保证钝化层与IGZO有源层接触的一面具有较低氧含量，减少钝化层和IGZO有源层界面形成非平衡O-离子的几率，同时能够防止源漏极被氧化，保证器件性能稳定。本发明的背沟道蚀刻型TFT基板采用上述方法制得，具有较强的器件稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种背沟道蚀刻型TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上从下到上依次形成栅极、栅极绝缘层及有源层，在所述有源层上形成间隔设置的源极与漏极；
    采用等离子体增强化学气相沉积法在所述源极、漏极及有源层上沉积第一层氧化硅薄膜，在所述第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于2；所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层；
    利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介于1.8与2之间，且Y大于X，制得背沟道蚀刻型TFT基板。
  2. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜与第二层氧化硅薄膜时，所述第二层氧化硅薄膜的沉积功率大于所述第一层氧化硅薄膜的沉积功率，因此所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，从而所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性。
  3. 如权利要求2所述的背沟道蚀刻型TFT基板的制作方法，其中，所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性。
  4. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度。
  5. 如权利要求4所述的背沟道蚀刻型TFT基板的制作方法，其中，所述第一层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100001
    所述第二层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100002
  6. 一种背沟道蚀刻型TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上且间隔设置的源极与漏极、以及设于所述源极、漏 极及有源层上的钝化层；
    所述钝化层包括设于所述源极、漏极及有源层上的第一层氧化硅薄膜与设于所述第一层氧化硅薄膜上的第二层氧化硅薄膜；所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介于1.8与2之间；所述第二层氧化硅薄膜中除浅表层以外的其它区域与所述第一层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于Y。
  7. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，因此所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性。
  8. 如权利要求7所述的背沟道蚀刻型TFT基板，其中，所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性。
  9. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度。
  10. 如权利要求9所述的背沟道蚀刻型TFT基板，其中，所述第一层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100003
    所述第二层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100004
  11. 一种背沟道蚀刻型TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上从下到上依次形成栅极、栅极绝缘层及有源层，在所述有源层上形成间隔设置的源极与漏极；
    采用等离子体增强化学气相沉积法在所述源极、漏极及有源层上沉积第一层氧化硅薄膜，在所述第一层氧化硅薄膜上沉积第二层氧化硅薄膜，所述第一层氧化硅薄膜与第二层氧化硅薄膜中的Si：O原子比例相同，均为1：X，其中X小于2；所述第一层氧化硅薄膜与第二层氧化硅薄膜组成钝化层；
    利用离子注入方法对第二层氧化硅薄膜的浅表层进行氧元素注入，使所述第二层氧化硅薄膜的浅表层中的Si：O原子比例与SiO2中的Si：O原子比例接近或相同，即所述第二层氧化硅薄膜的浅表层中的Si：O原子比例为1：Y，其中Y介于1.8与2之间，且Y大于X，制得背沟道蚀刻型TFT基板；
    其中，采用等离子体增强化学气相沉积法沉积第一层氧化硅薄膜与第二层氧化硅薄膜时，所述第二层氧化硅薄膜的沉积功率大于所述第一层氧 化硅薄膜的沉积功率，因此所述第二层氧化硅薄膜中Si-O-Si键的键角小于所述第一层氧化硅薄膜中Si-O-Si键的键角，从而所述第二层氧化硅薄膜的疏水性大于所述第一层氧化硅薄膜的疏水性；
    其中，所述第二层氧化硅薄膜的浅表层的疏水性大于所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性，所述第二层氧化硅薄膜中除浅表层以外的其它区域的疏水性大于所述第一层氧化硅薄膜的疏水性；
    其中，所述第二层氧化硅薄膜的厚度大于所述第一层氧化硅薄膜的厚度；
    其中，所述第一层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100005
    所述第二层氧化硅薄膜的厚度为
    Figure PCTCN2017117321-appb-100006
PCT/CN2017/117321 2017-11-21 2017-12-20 背沟道蚀刻型tft基板及其制作方法 Ceased WO2019100489A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/749,096 US10332988B2 (en) 2017-11-21 2017-12-20 Back-channel-etched TFT substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711167354.5A CN107978560B (zh) 2017-11-21 2017-11-21 背沟道蚀刻型tft基板及其制作方法
CN201711167354.5 2017-11-21

Publications (1)

Publication Number Publication Date
WO2019100489A1 true WO2019100489A1 (zh) 2019-05-31

Family

ID=62010882

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/117321 Ceased WO2019100489A1 (zh) 2017-11-21 2017-12-20 背沟道蚀刻型tft基板及其制作方法

Country Status (3)

Country Link
US (2) US10332988B2 (zh)
CN (1) CN107978560B (zh)
WO (1) WO2019100489A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119427B (zh) * 2018-07-02 2020-07-28 深圳市华星光电半导体显示技术有限公司 背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板
CN110942974B (zh) * 2018-09-25 2023-06-09 长鑫存储技术有限公司 半导体结构的形成方法及在晶圆上形成氧化硅膜的方法
CN111599869A (zh) * 2020-05-27 2020-08-28 Tcl华星光电技术有限公司 薄膜晶体管和薄膜晶体管制备方法
DE102021108764A1 (de) 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitende metalloxidtransistoren mit einem strukturierten gate und verfahren zum bilden derselben
US11757047B2 (en) * 2020-05-29 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Semiconducting metal oxide transistors having a patterned gate and methods for forming the same
CN112071864B (zh) * 2020-09-10 2023-12-01 Tcl华星光电技术有限公司 一种阵列基板及其制作方法
CN112038289B (zh) * 2020-11-04 2021-02-02 成都中电熊猫显示科技有限公司 一种阵列基板、显示面板以及阵列基板的制作方法
CN113314463B (zh) * 2021-07-29 2021-10-22 深圳市柔宇科技股份有限公司 薄膜晶体管基板的制备方法、薄膜晶体管基板和显示装置
CN116014453B (zh) * 2022-10-27 2023-08-15 电子科技大学 一种基于MXene与笼状结构三维泡沫的超疏水太赫兹吸波器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824887A (zh) * 2014-02-24 2014-05-28 昆山龙腾光电有限公司 金属氧化物半导体薄膜晶体管及其制作方法
CN105324835A (zh) * 2013-06-28 2016-02-10 株式会社神户制钢所 薄膜晶体管及其制造方法
US9484442B2 (en) * 2014-11-27 2016-11-01 Joled Inc. Method of fabricating thin-film transistor substrate
CN107068767A (zh) * 2012-11-16 2017-08-18 株式会社半导体能源研究所 半导体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080023703A1 (en) * 2006-07-31 2008-01-31 Randy Hoffman System and method for manufacturing a thin-film device
US9082857B2 (en) * 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
US8952377B2 (en) * 2011-07-08 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN104335332B (zh) * 2012-05-28 2017-09-05 夏普株式会社 半导体装置及其制造方法
US9287411B2 (en) * 2012-10-24 2016-03-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TWI620323B (zh) * 2012-11-16 2018-04-01 半導體能源研究所股份有限公司 半導體裝置
CN103413832B (zh) * 2013-07-08 2016-01-20 复旦大学 一种金属氧化物薄膜晶体管及其制备方法
TW202431651A (zh) * 2013-10-10 2024-08-01 日商半導體能源研究所股份有限公司 液晶顯示裝置
US9991392B2 (en) * 2013-12-03 2018-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6676316B2 (ja) * 2014-09-12 2020-04-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR102279884B1 (ko) * 2014-12-05 2021-07-22 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
KR102518392B1 (ko) * 2014-12-16 2023-04-06 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판
KR102397799B1 (ko) * 2015-06-30 2022-05-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 포함하는 표시장치
CN105355647B (zh) * 2015-11-26 2018-05-25 上海天马有机发光显示技术有限公司 一种封装结构、显示装置及其制作方法
JP2018129430A (ja) * 2017-02-09 2018-08-16 株式会社ジャパンディスプレイ 半導体装置
WO2018180723A1 (ja) * 2017-03-27 2018-10-04 シャープ株式会社 アクティブマトリクス基板およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068767A (zh) * 2012-11-16 2017-08-18 株式会社半导体能源研究所 半导体装置
CN105324835A (zh) * 2013-06-28 2016-02-10 株式会社神户制钢所 薄膜晶体管及其制造方法
CN103824887A (zh) * 2014-02-24 2014-05-28 昆山龙腾光电有限公司 金属氧化物半导体薄膜晶体管及其制作方法
US9484442B2 (en) * 2014-11-27 2016-11-01 Joled Inc. Method of fabricating thin-film transistor substrate

Also Published As

Publication number Publication date
CN107978560A (zh) 2018-05-01
US10332988B2 (en) 2019-06-25
US20190157430A1 (en) 2019-05-23
US10727322B2 (en) 2020-07-28
US20190267477A1 (en) 2019-08-29
CN107978560B (zh) 2019-12-03

Similar Documents

Publication Publication Date Title
CN107978560B (zh) 背沟道蚀刻型tft基板及其制作方法
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
CN107689345B (zh) Tft基板及其制作方法与oled面板及其制作方法
CN107611085B (zh) Oled背板的制作方法
CN106847743B (zh) Tft基板及其制作方法
CN105390551B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
CN104218094B (zh) 一种薄膜晶体管、显示基板及显示装置
CN112366210A (zh) 阵列基板及其制备方法、显示面板及装置
CN110534577B (zh) 一种薄膜晶体管及制备方法
CN107808885B (zh) 背沟道蚀刻型氧化物半导体tft基板及其制作方法
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2019100464A1 (zh) 背沟道蚀刻型氧化物半导体tft基板的制作方法
CN106356306A (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
CN105097950A (zh) 薄膜晶体管及制作方法、阵列基板、显示装置
CN117476662A (zh) 显示面板及其制作方法、显示装置
CN104167447B (zh) 一种薄膜晶体管及其制备方法、显示基板和显示设备
WO2019100488A1 (zh) 背沟道蚀刻型tft基板及其制作方法
CN106992189A (zh) 氧化物半导体tft基板结构及氧化物半导体tft基板的制作方法
US11329194B2 (en) Display panel and display device
WO2019100492A1 (zh) 背沟道蚀刻型tft基板及其制作方法
WO2020113622A1 (zh) Tft基板的制作方法及tft基板
US11239262B2 (en) Array substrate combining sensing material with thin film transistor, method of fabricating same, and display panel including same
CN203179888U (zh) 阵列基板及显示装置
CN114551475A (zh) 显示面板的制造方法及显示面板
WO2020172959A1 (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17932707

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17932707

Country of ref document: EP

Kind code of ref document: A1