WO2019087002A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2019087002A1 WO2019087002A1 PCT/IB2018/058226 IB2018058226W WO2019087002A1 WO 2019087002 A1 WO2019087002 A1 WO 2019087002A1 IB 2018058226 W IB2018058226 W IB 2018058226W WO 2019087002 A1 WO2019087002 A1 WO 2019087002A1
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- WIPO (PCT)
- Prior art keywords
- insulating layer
- layer
- film
- semiconductor
- semiconductor layer
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Definitions
- One embodiment of the present invention relates to a semiconductor device.
- One embodiment of the present invention relates to a display device.
- One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device.
- a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics.
- An oxide semiconductor using a metal oxide has attracted attention as a semiconductor material applicable to a transistor.
- a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the oxide semiconductor layer to be a channel contains indium and gallium, and the ratio of indium is the ratio of gallium
- the field effect mobility (simply referred to as mobility or ⁇ FE in some cases) is increased by making the size larger than that.
- a metal oxide that can be used for the semiconductor layer can be formed by a sputtering method or the like, and thus can be used for a semiconductor layer of a transistor included in a large display device.
- a metal oxide since it is possible to improve and use a part of a production facility of a transistor using polycrystalline silicon or amorphous silicon, facility investment can be suppressed.
- a transistor using a metal oxide since a transistor using a metal oxide has higher field effect mobility than the case where amorphous silicon is used, a high-performance display device provided with a driver circuit can be realized.
- Patent Document 2 has a low resistance region including, as a dopant, at least one of the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead in a source region and a drain region.
- a thin film transistor to which an oxide semiconductor film is applied is disclosed.
- An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with stable electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable display device.
- One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. It is.
- the second insulating layer is located on the first insulating layer.
- the semiconductor layer is located on the second insulating layer and has an island shape.
- the third insulating layer and the first conductive layer are provided over the semiconductor layer.
- the second insulating layer has an island shape having an end portion outside the region overlapping with the semiconductor layer.
- the fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, and is in contact with part of the top surface of the semiconductor layer and the second insulating layer.
- the semiconductor layer comprises a metal oxide
- the second insulating layer and the third insulating layer comprise an oxide
- the first insulating layer comprises a metal oxide or a nitride
- the fourth insulating layer comprises a metal nitride including.
- the fourth insulating layer preferably contains aluminum.
- the first insulating layer preferably contains at least one of aluminum and hafnium and oxygen.
- the top surface shapes of the second insulating layer and the semiconductor layer be substantially the same.
- the second insulating layer have a portion whose end is located outside the region overlapping with the first conductive layer.
- the second insulating layer have a portion whose end is located in a region overlapping with the first conductive layer.
- the second conductive layer be provided below the first insulating layer, and the second conductive layer have a region overlapping with both the semiconductor layer and the first conductive layer.
- the second insulating layer have a portion located outside the region where the end portion overlaps with the second conductive layer.
- the second insulating layer have a portion located in a region where an end portion of the second insulating layer overlaps with the second conductive layer.
- a semiconductor device with favorable electrical characteristics can be provided.
- a semiconductor device with stable electrical characteristics can be provided.
- a highly reliable display device can be provided.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 2 is a cross-sectional view of a display device.
- FIG. 6A and 6B are a block diagram and a circuit diagram of a display device.
- FIG. 14 is a block diagram of a display device.
- Configuration example of display module Configuration example of an electronic device.
- Configuration example of an electronic device Configuration example of an electronic device.
- Configuration example of an electronic device Configuration example of an electronic device.
- the functions of the source and the drain of the transistor may be interchanged when employing transistors of different polarities or when the direction of current changes in circuit operation. Therefore, the terms source and drain can be used interchangeably.
- the term “electrically connected” includes the case where they are connected via "something having an electrical function".
- the “thing having an electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connection targets.
- “those having some electrical action” include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, elements having various other functions, and the like.
- membrane and the term “layer” can be interchanged with each other.
- conductive layer and “insulating layer” may be interchangeable with the terms “conductive film” and “insulating film” in some cases.
- an off-state current is a drain current when the transistor is in an off state (also referred to as a non-conduction state or a cutoff state) unless otherwise specified.
- the off-state means a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth (higher than Vth in the p-channel transistor) in the n-channel transistor.
- a display panel which is one mode of a display device has a function of displaying (outputting) an image or the like on a display surface.
- the display panel is an aspect of the output device.
- a substrate in which a connector such as a flexible printed circuit (FPC) or a TCP (Tape Carrier Package) is attached to a substrate of a display panel, or an IC by a COG (Chip On Glass) method or the like on a substrate What was implemented may be called a display panel module, a display module, or simply a display panel or the like.
- a touch panel which is an aspect of a display device has a function of displaying an image or the like on a display surface, and a touch or touch of a detected object such as a finger or a stylus on the display surface. And a function as a touch sensor to detect. Therefore, the touch panel is an aspect of the input / output device.
- the touch panel can also be called, for example, a display panel with a touch sensor (or a display device) or a display panel with a touch sensor function (or a display device).
- the touch panel can also be configured to have a display panel and a touch sensor panel. Alternatively, the inside or the surface of the display panel may have a function as a touch sensor.
- a touch panel module one in which a connector or an IC is mounted on a substrate of a touch panel may be referred to as a touch panel module, a display module, or simply a touch panel or the like.
- Embodiment 1 the semiconductor device of one embodiment of the present invention, a display device, and a manufacturing method thereof will be described.
- a semiconductor layer in which a channel is formed, a gate insulating layer (also referred to as a third insulating layer) over the semiconductor layer, and a gate electrode over the gate insulating layer are formed over a formation surface.
- the semiconductor layer preferably includes a metal oxide exhibiting semiconductor characteristics (hereinafter, also referred to as an oxide semiconductor).
- the top surfaces of the gate electrode and the gate insulating layer preferably have substantially the same shape.
- the gate electrode and the gate insulating layer are preferably processed so that the side surfaces are continuous.
- the conductive film can be formed by performing processing using the same etching mask.
- the gate insulating layer may be formed by processing the insulating film using the previously processed gate electrode as a hard mask.
- the semiconductor layer includes a channel formation region in which a channel can be formed and a pair of low resistance regions functioning as a source region and a drain region.
- the channel formation region is a region overlapping with the gate electrode in the semiconductor layer.
- the low resistance region is a region having a lower resistance than the channel formation region.
- An insulating layer containing metal nitride (also referred to as a fourth insulating layer) is provided in contact with the surface of the low-resistance region of the semiconductor layer.
- a metal nitride By providing the insulating layer containing a metal nitride in contact with the semiconductor layer, an effect of enhancing the conductivity of the low resistance region is exhibited. Furthermore, it is preferable to perform heat treatment in a state where an insulating film containing metal nitride is provided in contact with the semiconductor layer, because the reduction of resistance can be further promoted.
- the metal nitride contains aluminum.
- an aluminum nitride film formed by reactive sputtering using aluminum as a sputtering target and a gas containing nitrogen as a film forming gas can appropriately control the flow rate of nitrogen gas with respect to the total flow rate of the film forming gas.
- the film can have extremely high insulation and very high blocking ability to hydrogen and oxygen. Therefore, by providing an insulating film containing such a metal nitride in contact with the semiconductor layer, not only the resistance of the semiconductor layer can be reduced, but also oxygen is desorbed from the semiconductor layer, and hydrogen is diffused into the semiconductor layer. Can be suitably prevented.
- the thickness of the insulating film containing the aluminum nitride is preferably 5 nm or more. Even with such a thin film, it is possible to achieve both the high blocking property to hydrogen and oxygen and the function of reducing the resistance of the semiconductor layer.
- the thickness of the insulating layer may be any thickness, it is preferably 500 nm or less, preferably 200 nm or less, more preferably 50 nm or less in consideration of productivity.
- an insulating layer containing an oxide (also referred to as a second insulating layer) is preferably provided in contact with the lower surface of the semiconductor layer.
- One embodiment of the present invention is a structure in which the second insulating layer has an island shape. Further, an insulating layer (also referred to as a first insulating layer) having high blocking ability to water, hydrogen, and oxygen is provided below the second insulating layer. Further, upper surfaces and side surfaces of end portions of the second insulating layer are covered with an insulating layer (a fourth insulating layer) containing the metal nitride. In addition, the first insulating layer and the fourth insulating layer are in contact with each other in a region outside the end portion of the island-like second insulating layer, whereby the second insulating layer, the semiconductor layer, and the like can be first-insulated. A configuration in which the layer and the fourth insulating layer surround (seal) can be employed. Thus, oxygen released from the second insulating layer can be effectively suppressed from being released to the outside, and most of the oxygen can be supplied to the semiconductor layer.
- the transistor characteristics may be adversely affected.
- it is possible to control the amount of oxygen that can be supplied to the semiconductor layer by changing the area of the second insulating layer processed into an island shape.
- the area can be appropriately designed according to the amount of oxygen which the second insulating layer can release, the area of the semiconductor layer overlapping with the second insulating layer, the thickness of the second insulating layer, and the like. Become.
- FIG. 1A is a top view of the transistor 100
- FIG. 1B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line A1-A2 in FIG. 1A
- FIG. 1A corresponds to a cross-sectional view taken along a dashed-dotted line B1-B2 shown in FIG.
- FIG. 1A some of components of the transistor 100 (a gate insulating layer or the like) are omitted.
- the direction of the dashed-dotted line A1-A2 may be referred to as a channel length direction
- the direction of the dashed-dotted line B1-B2 may be referred to as a channel width direction.
- FIG. 1A some of the components may be omitted and illustrated in the following drawings.
- the transistor 100 is provided over the substrate 102 and includes an insulating layer 103, an insulating layer 104, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, and the like.
- the insulating layer 104 is provided over the insulating layer 103, and the semiconductor layer 108 is provided over the insulating layer 104.
- the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked in this order over the semiconductor layer 108.
- the insulating layer 116 is provided to cover the top and side surfaces of the insulating layer 104, the top and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 110, the side surfaces of the metal oxide layer 114, and the top and side surfaces of the conductive layer 112. .
- the insulating layer 118 is provided to cover the insulating layer 116.
- a part of the conductive layer 112 functions as a gate electrode.
- a part of the insulating layer 110 functions as a gate insulating layer.
- the transistor 100 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.
- the semiconductor layer 108 preferably contains a metal oxide.
- the semiconductor layer 108 is made of indium, M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, It is preferable to have zinc and one or more selected from hafnium, tantalum, tungsten, or magnesium.
- M is preferably aluminum, gallium, yttrium or tin.
- an oxide containing indium, gallium, and zinc is preferably used as the semiconductor layer 108.
- the semiconductor layer 108 may have a stacked structure in which layers different in composition, layers different in crystallinity, or layers different in impurity concentration are stacked.
- the semiconductor layer 108 includes a region overlapping with the conductive layer 112 and a low-resistance region 108 n sandwiching the region.
- An insulating layer 116 is provided in contact with the region 108 n.
- a region of the semiconductor layer 108 which overlaps with the conductive layer 112 functions as a channel formation region of the transistor 100.
- the region 108 n functions as a source region or a drain region of the transistor 100.
- the transistor 100 may include the conductive layer 120 a and the conductive layer 120 b over the insulating layer 118.
- the conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode.
- the conductive layer 120 a and the conductive layer 120 b are electrically connected to the region 108 n through the opening 141 a or the opening 141 b provided in the insulating layer 118 and the insulating layer 116, respectively.
- the top surface shapes of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 substantially match each other.
- the top surface shapes substantially match means that at least a part of the contours overlap between the stacked layers and the layers.
- the outlines do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.
- the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side.
- a material which is less permeable to oxygen than at least the insulating layer 110 can be used.
- the metal oxide layer 114 can prevent oxygen from being diffused from the insulating layer 110 to the conductive layer 112 even when a metal such as aluminum or copper which can easily absorb oxygen is used for the conductive layer 112. Further, even when the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110 is suppressed. As a result, the carrier density of the channel formation region of the semiconductor layer 108 can be extremely low.
- the metal oxide layer 114 an insulating material or a conductive material can be used.
- the metal oxide layer 114 has insulating properties, it functions as part of the gate insulating layer.
- the metal oxide layer 114 has conductivity, it functions as part of the gate electrode.
- an insulating material having a higher dielectric constant than silicon oxide is preferably used as the metal oxide layer 114.
- the metal oxide layer 114 is preferably formed using a sputtering apparatus.
- oxygen can be favorably added to the insulating layer 110 and the semiconductor layer 108 by forming the film in an atmosphere containing oxygen gas.
- the film density can be increased, which is preferable.
- an insulating film containing metal nitride can be used as the insulating layer 116.
- the insulating layer 116 preferably contains at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium, and nitrogen.
- metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium, and nitrogen.
- the use of a film containing aluminum and nitrogen is preferable because it has extremely high insulation.
- a film satisfying the composition formula AlN x (x is a real number greater than 0 and 2 or less, preferably x is a real number greater than 0.5 and 1.5 or less) Is preferred.
- the film can be excellent in insulating properties and thermal conductivity; therefore, the heat dissipation property of heat generated when the transistor 100 is driven can be improved.
- an aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116.
- the region 108 n is a part of the semiconductor layer 108 and has a lower resistance than the channel formation region.
- a region where metallic indium is deposited or a region with high indium concentration is formed in the vicinity of the interface on the insulating layer 116 side of the region 108n. May be Such a region may be observed by an analysis method such as X-ray photoelectron spectroscopy (XPS), for example.
- XPS X-ray photoelectron spectroscopy
- the region 108 n can also be referred to as a region where the carrier density is higher than that of the channel formation region, a region where the oxygen defect density is high, or a region which is n-type.
- an oxide film is preferably used for the insulating layer 104 and the insulating layer 110 which are in contact with the channel formation region of the semiconductor layer 108.
- an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. Accordingly, oxygen released from the insulating layer 104 and the insulating layer 110 is supplied to the channel formation region of the semiconductor layer 108 by heat treatment or the like in the manufacturing process of the transistor 100, and oxygen vacancies in the semiconductor layer 108 are reduced. be able to.
- an insulating film which hardly diffuses oxygen and hydrogen is preferably used.
- a metal oxide film such as an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferably used.
- Aluminum oxide films, hafnium oxide films, hafnium aluminate films and the like have extremely high barrier properties even when the film thickness is thin. Therefore, the thickness can be 0.5 nm to 50 nm, preferably 1 nm to 40 nm, and more preferably 2 nm to 30 nm. In particular, since the aluminum oxide film has a high barrier property to hydrogen and the like, a sufficient effect can be obtained even if it is extremely thin (for example, 0.5 nm or more and 1.5 nm or less).
- Such a film can be formed by, for example, a film forming method such as sputtering or atomic layer deposition (ALD).
- the semiconductor layer 108 and the insulating layer 104 are each processed into an island shape.
- the outline of the insulating layer 104 is indicated by a broken line.
- the insulating layer 104 is provided so as to include at least the semiconductor layer 108 in plan view. In other words, the end portion of the insulating layer 104 is processed to be located outside the region overlapping with the semiconductor layer 108. Note that, as described later, the semiconductor layer 108 and the insulating layer 104 may be processed using the same etching mask, in which case the top surface shapes of the semiconductor layer 108 and the insulating layer 104 substantially match each other. .
- the insulating layer 103 and the insulating layer 116 are provided in contact with each other in a region outside the end portion of the insulating layer 104.
- the semiconductor layer 108, the insulating layer 104, and the like can be sealed by the insulating layer 103 and the insulating layer 116.
- the insulating layer 118 may contain hydrogen
- the insulating layer 104 including the oxide film in contact with the semiconductor layer 108 and the insulating layer 110 are not in contact with the insulating layer 118 due to the insulating layer 116. ing. Therefore, even when hydrogen is contained in the insulating layer 118, the hydrogen is diffused to the semiconductor layer 108 through the insulating layer 104 and the insulating layer 110 due to heat or the like applied to the manufacturing process of the transistor 100. You can prevent things effectively.
- Oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen is bonded to the oxygen vacancies and can be a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, a change in the electrical characteristics of the transistor 100, typically, a shift in threshold voltage occurs. Therefore, in the semiconductor layer 108, the less oxygen vacancies, the better.
- the insulating film in the vicinity of the semiconductor layer 108 specifically, the insulating layer 110 located above the semiconductor layer 108 and the insulating layer 104 located below include an oxide film. It is a structure. By transferring oxygen from the insulating layer 104 and the insulating layer 110 to the semiconductor layer 108 by heat or the like in the manufacturing process, oxygen vacancies in the semiconductor layer 108 can be reduced.
- the semiconductor layer 108 preferably includes a region in which the atomic ratio of In is larger than the atomic ratio of M. As the atomic ratio of In is larger, the field-effect mobility of the transistor can be improved.
- the bonding force between In and oxygen is weaker than the bonding force between Ga and oxygen, and therefore, when the atomic ratio of In is large, the metal oxide film There is a tendency for oxygen deficiency to form. In addition, the same tendency is obtained when the metal element indicated by M is used instead of Ga. When many oxygen vacancies are present in the metal oxide film, the electrical characteristics of the transistor and the reliability thereof are degraded.
- a very large amount of oxygen can be supplied to the semiconductor layer 108 including a metal oxide; therefore, a metal oxide material with a large atomic ratio of In can be used.
- a transistor having extremely high field effect mobility, stable electrical characteristics, and high reliability can be realized.
- a metal oxide in which the atomic ratio of In is at least 1.5 times, at least 2 times, at least 3 times, at least 3.5 times, or at least 4 times the atomic ratio of M It can be used suitably.
- a display device with a narrow frame width (also referred to as a narrow frame) can be provided.
- a source driver in particular, a demultiplexer connected to an output terminal of a shift register included in the source driver
- display with a small number of wirings connected to a display device An apparatus can be provided.
- the semiconductor layer 108 has a region in which the atomic ratio of In is larger than the atomic ratio of M, if the crystallinity of the semiconductor layer 108 is high, the field effect mobility may be low.
- the crystallinity of the semiconductor layer 108 can be analyzed, for example, by analysis using X-ray diffraction (XRD) or analysis using a transmission electron microscope (TEM). .
- impurities such as hydrogen or moisture mixed in the semiconductor layer 108 cause problems because they affect transistor characteristics. Therefore, in the semiconductor layer 108, it is preferable that the amount of impurities such as hydrogen or moisture be as low as possible.
- the use of a metal oxide film with a low impurity concentration and a low density of defect states is preferable because a transistor having excellent electrical characteristics can be manufactured.
- the carrier density in the film can be lowered by lowering the impurity concentration and lowering the density of defect states (reducing oxygen deficiency).
- an electrical characteristic also referred to as normally on
- a transistor using such a metal oxide film can have extremely low off-state characteristics.
- the semiconductor layer 108 may have a stacked structure of two or more layers.
- the semiconductor layer 108 in which two or more metal oxide films different in composition are stacked can be used.
- the semiconductor layer 108 in which two or more metal oxide films having different crystallinity are stacked can be used.
- the same oxide target is preferably used, and the film formation conditions are preferably different so that the oxide target is continuously formed without being exposed to the air.
- the oxygen flow ratio at the time of film formation of the first metal oxide film to be formed first is made smaller than the oxygen flow ratio at the time of film formation of the second metal oxide film to be formed later.
- oxygen is not flowed at the time of forming the first metal oxide film.
- oxygen can be effectively supplied at the time of film formation of the second metal oxide film.
- the first metal oxide film has lower crystallinity than the second metal oxide film, and can be a film having high electrical conductivity.
- the second metal oxide film provided on the upper side is a film having higher crystallinity than the first metal oxide film, damage is caused when the semiconductor layer 108 is processed or when the insulating layer 110 is formed. Can be suppressed.
- the oxygen flow ratio at the time of film formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, In fact, it is 10%.
- the oxygen flow rate ratio at the time of film formation of the second metal oxide film is 50% to 100%, preferably 60% to 100%, more preferably 80% to 100%, further preferably 90% or more 100% or less, typically 100%.
- conditions such as pressure, temperature, and electric power at the time of film formation may be different between the first metal oxide film and the second metal oxide film, conditions other than the oxygen flow ratio are the same. This is preferable because the time required for the film formation process can be shortened.
- the transistor 100 With such a configuration, the transistor 100 with excellent electrical characteristics and high reliability can be realized.
- FIGS. 2A and 2B show an example in which the insulating layer 104 and the semiconductor layer 108 are processed into an island shape by the same etching mask.
- the top surfaces of the insulating layer 104 and the semiconductor layer 108 substantially match in plan view.
- the insulating layer 104 and the semiconductor layer 108 have side surfaces continuous with each other at their end portions.
- the process for processing the insulating layer 104 can be omitted, so that the yield can be improved and the manufacturing cost can be reduced.
- FIG. 2C shows a cross section in the channel width direction.
- the modified example 1-1 and the modified example 1-2 have a configuration in which the area of the insulating layer 104 can be smaller than that of the first configuration example.
- FIG. 3A is a top view of the transistor 100A
- FIG. 3B is a cross-sectional view of the transistor 100A in the channel length direction
- FIG. 3C is a cross-sectional view of the transistor 100A in the channel width direction. .
- the transistor 100A is mainly different from Structural Example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 103.
- the conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112 with the insulating layer 104 and the insulating layer 103 interposed therebetween.
- the conductive layer 106 has a function as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 has a function as a second gate electrode (also referred to as a top gate electrode).
- part of the insulating layer 103 and the insulating layer 104 function as a first gate insulating layer, and part of the insulating layer 110 functions as a second gate insulating layer.
- a portion of the semiconductor layer 108 which overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that in the following, a portion overlapping with the conductive layer 112 of the semiconductor layer 108 may be referred to as a channel formation region for ease of description; A channel can be formed also in the portion (portion including the region 108 n).
- the conductive layer 106 is electrically connected to the conductive layer 112 through the opening 142 provided in the metal oxide layer 114, the insulating layer 110, the insulating layer 104, and the insulating layer 103. May be connected. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.
- the conductive layer 106 can be formed using the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b.
- the conductive layer 106 is preferably formed using a material containing copper because resistance can be reduced.
- the conductive layer 112 and the conductive layer 106 preferably protrude outward beyond the end portion of the semiconductor layer 108 in the channel width direction.
- the whole of the semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 with the insulating layer 110 and the insulating layer 104 interposed therebetween.
- the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes.
- the same potential is preferably applied to the conductive layer 106 and the conductive layer 112. Accordingly, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100A can be increased. Therefore, the transistor 100A can be miniaturized.
- the conductive layer 112 and the conductive layer 106 may not be connected to each other.
- a constant potential may be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be supplied to the other.
- the threshold voltage in driving the transistor 100A with the other electrode can also be controlled by the potential supplied to the one electrode.
- FIGS. 4A and 4B show an example in which the insulating layer 104 and the semiconductor layer 108 are processed into an island shape by the same etching mask.
- the conductive layer 112 and the conductive layer 106 are electrically connected to each other through the metal oxide layer 114, the insulating layer 110, and the opening 142 provided in the insulating layer 103. It is configured to be connected.
- the end portion of the insulating layer 104 is positioned outside the semiconductor layer 108, the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 and inside the conductive layer 106.
- the insulating layer 104 is processed as described above.
- FIGS. 5B and 5C the end of the insulating layer 104 is outside the semiconductor layer 108, and the conductive layer 112, the metal oxide layer 114, the insulating layer 110, and the conductive layer 106 are shown. It is an example in the case of being located inside rather than.
- FIG. 5B is an example in which the opening 142 is provided at a position where the insulating layer 104 does not exist.
- FIG. 5C shows an example in which the opening 142 is provided at the position where the insulating layer 104 is present.
- the end portion of the insulating layer 104 is closer to the channel width direction of the transistor.
- a portion of the outer conductive layer 112 is located below the semiconductor layer 108.
- FIG. 6A is a schematic top view of a display device in which a plurality of sub-pixels are arranged in a matrix.
- One subpixel includes at least the transistor 100 and the conductive layer 131 which is electrically connected to the transistor 100 and functions as a pixel electrode.
- the sub-pixel is shown here, another transistor, a capacitor, or the like can be provided as appropriate depending on a display element applied to the sub-pixel.
- the conductive layer 112 functions as a gate line (also referred to as a scan line)
- the conductive layer 120 a functions as a source line (also referred to as a signal line or a video signal line)
- the conductive layer 120 b is a transistor It functions as a wire electrically connecting the conductive layer 100 and the conductive layer 131.
- FIG. 6A shows an example in which one insulating layer 104 having an island shape is provided for one transistor. That is, it can be said that one insulating layer 104 overlaps with one semiconductor layer 108.
- 6B and 6C illustrate an example of a structure in which one insulating layer 104 overlaps with two or more semiconductor layers 108.
- FIG. 6B shows a portion including both ends in the extending direction of the gate line (conductive layer 112) in the display region 130 of the display device.
- the insulating layer 104 is processed so as to cross the display region 130.
- FIG. 6C shows a portion including the entire area of the display area 130 of the display device.
- one insulating layer 104 is processed so as to be provided over the entire display region 130.
- the insulating layer 104 is provided so as to overlap with all the semiconductor layers 108 provided in the display area 130.
- the configuration of the insulating layer 104 is not limited to the above, and one insulating layer 104 may be disposed for each pixel or for each block of several pixels. In the case where a plurality of transistors is included in one sub-pixel, one insulating layer may be provided for each sub-pixel.
- the transistor of one embodiment of the present invention can be applied to various circuits and devices as well as display devices.
- a display device to which various circuits such as an arithmetic circuit, a memory circuit, a driver circuit, and an interface circuit mounted in an electronic device or the like, a liquid crystal element or an organic EL element, or various sensor devices are applied. It can be suitably used for a drive circuit or the like.
- one insulating layer 104 is provided so as to include a block including one or more transistors 100 (eg, each circuit or each chip), and the insulating layer 116 and the insulating layer 103 are in contact with each other in the periphery
- the plurality of transistors 100 in the block can be sealed by the insulating layer 103 and the insulating layer 116. Accordingly, diffusion of hydrogen from the outside into the semiconductor layer 108 of the transistor 100 and diffusion of oxygen in the semiconductor layer 108 are effectively suppressed, and a highly reliable device can be realized.
- the material of the substrate 102 and the like are not particularly limited, but at least the heat resistance needs to be able to withstand the heat treatment to be performed later.
- a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate or the like is used as the substrate 102. It is also good.
- a substrate provided with a semiconductor element over these substrates may be used as the substrate 102.
- a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate.
- a peeling layer may be provided between the substrate 102 and the transistor 100 or the like. The release layer can be used for separation from the substrate 102 and reprinting onto another substrate after a semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 and the like can be transferred to a substrate with low heat resistance or a flexible substrate.
- the insulating layer 104 can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, or the like as appropriate.
- the insulating layer 104 can be formed, for example, as a single layer or a stack of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region in contact with the semiconductor layer 108 in the insulating layer 104 is preferably formed using an oxide insulating film.
- a film which releases oxygen by heating is preferably used for the insulating layer 104.
- the insulating layer 104 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used, and a single layer or stacked layers can be provided.
- the surface in contact with the semiconductor layer 108 is subjected to pretreatment such as oxygen plasma treatment; Preferably, or near the surface is oxidized.
- the conductive layer 112 and the conductive layer 106 which function as a gate electrode, the conductive layer 120 a which functions as one of a source electrode or a drain electrode, and the conductive layer 120 b which functions as the other include chromium, copper, aluminum, gold, silver, and zinc. Or a metal element selected from molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the above-described metal element as a component, or an alloy or the like combining the above-described metal elements be able to.
- an In-Sn oxide, an In-W oxide, an In-W-Zn oxide, an In-Ti oxide, an In-Ti, or the like can be used for the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b.
- An oxide conductor or metal oxide film such as -Sn oxide, In-Zn oxide, In-Sn-Si oxide, or In-Ga-Zn oxide can also be applied.
- oxide conductor Oxide Conductor
- OC Oxide Conductor
- a donor level is formed in the vicinity of the conduction band.
- the metal oxide becomes highly conductive and becomes conductive.
- a conductive metal oxide can be referred to as an oxide conductor.
- the conductive layer 112 or the like may have a stacked-layer structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy.
- the wiring resistance can be reduced by using a conductive film containing a metal or an alloy.
- a conductive film including an oxide conductor is preferably applied to the side in contact with the insulating layer which functions as a gate insulating film.
- the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b preferably include one or more selected from titanium, tungsten, tantalum, and molybdenum among the above-described metal elements. It is suitable. In particular, it is preferable to use a tantalum nitride film.
- the tantalum nitride film is a conductive film in contact with the semiconductor layer 108 because the tantalum nitride film has conductivity, high barrier properties against copper, oxygen, or hydrogen and little release of hydrogen from itself.
- the conductive film can be suitably used as a conductive film in the vicinity of the semiconductor layer 108.
- the insulating layer 110 functioning as a gate insulating film of the transistor 100 or the like can be formed by a PECVD method, a sputtering method, or the like.
- An insulating layer containing one or more of a film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used.
- the insulating layer 110 may have a stacked structure of two layers or a stacked structure of three or more layers.
- the insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition.
- the insulating layer 110 is an insulating film capable of releasing oxygen.
- the insulating layer 110 is formed in an oxygen atmosphere, heat treatment in an oxygen atmosphere, plasma treatment, or the like is performed on the insulating layer 110 after film formation, or over the insulating layer 110 in an oxygen atmosphere.
- Oxygen can also be supplied to the insulating layer 110 by forming an oxide film or the like.
- the insulating layer 110 a material such as hafnium oxide having a higher relative dielectric constant than silicon oxide or silicon oxynitride can be used.
- the film thickness of the insulating layer 110 can be increased to suppress the leak current due to the tunnel current.
- hafnium oxide having crystallinity is preferable because it has a high dielectric constant as compared to amorphous hafnium oxide.
- the sputtering target used to form the In-M-Zn oxide preferably has an atomic ratio of In greater than or equal to an atomic ratio of M.
- the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the above sputtering target.
- the atomic ratio of Ga is 1 or more and 3 or less, where the atomic ratio of In is 4.
- the atomic ratio of is 2 or more and 4 or less is included.
- the atomic ratio of Ga is larger than 0.1. It is 2 or less, and the case where the atomic ratio of Zn is 5 or more and 7 or less is included.
- the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more.
- the off-state current of the transistor can be reduced.
- the semiconductor layer 108 preferably has a non-single-crystal structure.
- the non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure described later.
- the amorphous structure has the highest density of defect states
- the CAAC structure has the lowest density of defect states.
- CAAC c-axis aligned crystal
- the CAAC structure is one of crystal structures such as a thin film having a plurality of nanocrystals (crystal regions having a maximum diameter of less than 10 nm), and each nanocrystal has c axis oriented in a specific direction and an a axis And b axes are crystal structures having a feature that nanocrystals are continuously connected without forming grain boundaries without having orientation.
- a thin film having a CAAC structure is characterized in that the c-axis of each nanocrystal is easily oriented in the thickness direction of the thin film, the normal direction of the formation surface, or the normal direction of the surface of the thin film.
- CAAC-OS Oxide Semiconductor
- CAAC-OS is an oxide semiconductor with high crystallinity.
- CAAC-OS can not confirm clear crystal grain boundaries, so that it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur.
- the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, generation of defects, or the like, so that the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, the oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is resistant to heat and has high reliability.
- crystallography it is general to take a unit cell with c-axis as a specific axis with respect to three axes (crystal axes) of a-axis, b-axis, and c-axis constituting the unit cell.
- crystal axes three axes
- b-axis a axis
- c-axis constituting the unit cell.
- two axes parallel to the plane direction of the layer are the a axis and b axis
- an axis intersecting the layer is the c axis.
- a typical example of a crystal having such a layered structure is graphite classified into a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane and the c-axis is orthogonal to the cleavage plane Do.
- a crystal of InGaZnO 4 having a layered crystal structure of YbFe 2 O 4 type can be classified into a hexagonal system, and the a-axis and b-axis of the unit cell are parallel to the plane direction of the layer and c-axis Is orthogonal to the layers (ie, the a and b axes).
- a metal oxide formed by sputtering at a substrate temperature of 100 ° C. to 130 ° C. using the above target has a crystal structure of nc (nano crystal) or CAAC, or a mixed structure thereof.
- nc nano crystal
- CAAC room temperature
- a metal oxide formed by a sputtering method with a substrate temperature of room temperature (RT) tends to have a nc crystal structure.
- RT room temperature
- the room temperature (R.T.) referred to here includes the temperature when the substrate is not intentionally heated.
- thin films insulating films, semiconductor films, conductive films, and the like that constitute a semiconductor device are formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulse laser deposition (PLD: Pulse Laser Deposition). ), Atomic layer deposition (ALD), or the like.
- CVD chemical vapor deposition
- PLA Pulse Laser Deposition
- ALD Atomic layer deposition
- CVD method include plasma enhanced chemical vapor deposition (PECVD), thermal CVD and the like.
- PECVD plasma enhanced chemical vapor deposition
- MOCVD metal organic chemical vapor deposition
- thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be spin-coated, dip, spray-coated, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain coat , Knife coating or the like.
- the thin film when processing a thin film forming the semiconductor device, can be processed using a photolithography method or the like.
- the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method or the like.
- the island-shaped thin film may be formed directly by a film formation method using a shielding mask such as a metal mask.
- the photolithography method there are typically the following two methods.
- One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and removing the resist mask.
- the other is a method of processing the thin film into a desired shape by forming a thin film having photosensitivity, followed by exposure and development.
- light used for exposure may be, for example, i-ray (wavelength 365 nm), g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these.
- ultraviolet light, KrF laser light, ArF laser light or the like can also be used.
- the exposure may be performed by the immersion exposure technique.
- extreme ultraviolet (EUV: Extreme Ultra-violet) or X-rays may be used.
- an electron beam can be used instead of light used for exposure. The use of extreme ultraviolet light, X-rays or electron beams is preferable because extremely fine processing is possible. In the case where exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.
- etching of the thin film a dry etching method, a wet etching method, a sand blast method, or the like can be used.
- a conductive film is formed over the substrate 102 and processed by etching to form a conductive layer 106 which functions as a gate electrode (FIG. 7A).
- the insulating layer 103 and the insulating layer 104 are stacked to cover the substrate 102 and the conductive layer 106 (FIG. 7B).
- the insulating layer 103 and the insulating layer 104 can each be formed by a PECVD method, an ALD method, a sputtering method, or the like.
- the insulating layer 103 can be formed by an ALD method or a sputtering method
- the insulating layer 104 can be formed by a PECVD method or a sputtering method.
- part of the insulating layer 104 is removed by etching and processed into an island shape (FIG. 7C).
- the metal oxide film is preferably formed by sputtering using a metal oxide target.
- an inert gas eg, helium gas, argon gas, xenon gas, or the like
- oxygen flow ratio the ratio of oxygen gas to the entire deposition gas at the time of depositing the metal oxide film
- Transistors can be realized.
- the oxygen flow ratio is lower, the crystallinity of the metal oxide film is lowered, and a transistor in which the on current is increased can be obtained.
- the substrate temperature may be higher than or equal to room temperature and lower than 200 ° C., preferably, the substrate temperature may be higher than or equal to room temperature and 140 ° C. or lower.
- productivity is preferably high.
- the crystallinity can be reduced by forming the metal oxide film while the substrate temperature is at room temperature or in a state in which the substrate temperature is not intentionally heated.
- treatment for desorbing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 104 and treatment for supplying oxygen to the insulating layer 104 may be performed.
- heat treatment can be performed at a temperature of 70 ° C to 200 ° C in a reduced pressure atmosphere.
- plasma treatment may be performed in an atmosphere containing oxygen.
- organic substances on the surface of the insulating layer 104 can be suitably removed. After such treatment, it is preferable to form a metal oxide film continuously without exposing the surface of the insulating layer 104 to the air.
- a wet etching method and a dry etching method may be used for processing of the metal oxide film.
- part of the insulating layer 104 which does not overlap with the semiconductor layer 108 may be etched and thinned.
- heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108.
- the temperature of the heat treatment is typically 150 ° C to less than the strain point of the substrate, or 250 ° C to 450 ° C, or 300 ° C to 450 ° C.
- the heat treatment can be performed under an atmosphere containing a rare gas or nitrogen. Alternatively, after heating under the atmosphere, heating may be performed under an atmosphere containing oxygen. Note that hydrogen, water, and the like are preferably not contained in the atmosphere of the heat treatment.
- an electric furnace, a rapid thermal annealing (RTA) apparatus, or the like can be used as the heat treatment. The heat treatment time can be shortened by using the RTA apparatus.
- an insulating film 110 f to be the insulating layer 110 and a metal oxide film 114 f to be the metal oxide layer 114 are stacked over the insulating layer 103, the insulating layer 104, and the semiconductor layer 108.
- an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma enhanced chemical vapor deposition apparatus (referred to as a PECVD apparatus or simply referred to as a plasma CVD apparatus). Alternatively, it may be formed by PECVD using microwaves.
- a plasma enhanced chemical vapor deposition apparatus referred to as a PECVD apparatus or simply referred to as a plasma CVD apparatus.
- it may be formed by PECVD using microwaves.
- the metal oxide film 114 f is preferably formed, for example, in an atmosphere containing oxygen.
- the film is preferably formed by sputtering in an atmosphere containing oxygen.
- oxygen can be supplied to the insulating film 110 f when the metal oxide film 114 f is formed.
- the metal oxide film 114f As a film formation condition of the metal oxide film 114f, it is preferable to form the metal oxide film by a reactive sputtering method using a metal target by using oxygen as a film formation gas.
- a metal target When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.
- the ratio of the oxygen flow rate to the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus (oxygen flow ratio) or the oxygen partial pressure in the film forming chamber is higher.
- the oxygen supplied into the membrane 110f can be increased.
- the oxygen flow ratio or oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow ratio to 100% and to bring the oxygen partial pressure as close as possible to 100%.
- oxygen is supplied to the insulating film 110f at the time of deposition of the metal oxide film 114f, and oxygen is supplied from the insulating film 110f. It is possible to prevent detachment. As a result, an extremely large amount of oxygen can be confined in the insulating film 110 f. Then, much heat can be supplied to the semiconductor layer 108 by heat treatment performed later. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.
- the metal oxide film 114f is formed, the metal oxide film 114f, the insulating film 110f, the insulating layer 104, and part of the insulating layer 103 are etched to form an opening which reaches the conductive layer 106. Accordingly, the conductive layer 112 and the conductive layer 106 which are to be formed later can be electrically connected to each other through the opening.
- FIG. 1 A schematic cross-sectional view at this stage corresponds to FIG.
- a conductive film to be the conductive layer 112 is formed over the metal oxide film 114 f.
- the conductive film is preferably formed by a sputtering method using a sputtering target of metal or alloy.
- part of the conductive film, the metal oxide film 114f, and the insulating film 110f is etched (FIG. 8C).
- the conductive film, the metal oxide film 114 f, and the insulating film 110 f are preferably processed using the same resist mask.
- the metal oxide film 114 f and the insulating film 110 f may be etched using the conductive layer 112 after etching as a hard mask.
- the island-shaped conductive layer 112, the metal oxide layer 114, and the insulating layer 110 whose top surface shapes are approximately the same can be formed.
- the semiconductor layer 108 which is not covered with the insulating layer 110 may be etched and thinned.
- the insulating layer 116 is formed to cover the insulating layer 104, the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, the conductive layer 112, and the like. At this time, a region where the insulating layer 103 and the insulating layer 116 are in contact with each other is formed outside the end portion of the insulating layer 104 (FIG. 9A).
- the insulating layer 116 is preferably formed by a reactive sputtering method using a sputtering target containing the above metal element and a mixed gas of nitrogen gas and a rare gas which is a dilution gas as a deposition gas.
- a reactive sputtering method using a sputtering target containing the above metal element and a mixed gas of nitrogen gas and a rare gas which is a dilution gas as a deposition gas.
- the flow rate of nitrogen gas is 30% to 100%, preferably 40% to 100% of the total flow rate of the deposition gas. It is preferable to set it as 50% or more and 100% or less more preferably below.
- a low-resistance region 108n is formed in a region in the vicinity of the interface of the semiconductor layer 108 in contact with the insulating layer 116.
- heat treatment is preferably performed.
- the heat treatment can further reduce the resistance of the region 108n of the semiconductor layer 108.
- the heat treatment is preferably performed under an inert gas atmosphere such as nitrogen or a rare gas.
- the temperature may be 120 ° C. to 500 ° C., preferably 150 ° C. to 450 ° C., more preferably 200 ° C. to 400 ° C., further preferably 250 ° C. to 400 ° C.
- semiconductor devices can be produced with high yield in a production facility using a large glass substrate.
- the heat treatment may be performed at any stage after the formation of the insulating layer 116.
- the heat treatment may be combined with another heat treatment.
- oxygen in the semiconductor layer 108 is extracted toward the insulating layer 116 by heat treatment, whereby oxygen vacancies are generated.
- the carrier concentration is increased by bonding of the oxygen vacancy and hydrogen contained in the semiconductor layer 108, so that a portion in contact with the insulating layer 116 can be lowered in resistance.
- the metal element contained in the semiconductor layer 108 is diffused toward the vicinity of the interface with the insulating layer 116 by heat treatment to form a region with a high concentration of the metal element, whereby a portion in contact with the insulating layer 116 is The resistance may be lowered.
- a region with a high indium concentration may be observed in the vicinity of the interface of the semiconductor layer 108 with the insulating layer 116.
- the region 108 n reduced in resistance by such a combined action becomes a very stable low resistance region.
- the region 108 n formed in this manner has a feature that it is difficult to increase the resistance again, for example, even when the process of supplying oxygen is performed in the later step.
- the insulating layer 118 is formed to cover the insulating layer 116.
- the insulating layer 118 can be formed by, for example, a PECVD method.
- Openings 141a and 141b [Formation of Openings 141a and 141b] Subsequently, part of the insulating layer 118 and the insulating layer 116 is etched to form an opening 141 a and an opening 141 b which reach the region 108 n.
- the transistor 100A can be manufactured.
- This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.
- FIG. 10A shows a top view of the display device 700.
- the display device 700 includes a first substrate 701 and a second substrate 705 which are attached by a sealant 712.
- the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are provided over the first substrate 701.
- Be The pixel portion 702 is provided with a plurality of display elements.
- an FPC terminal portion 708 to which an FPC 716 (FPC: Flexible Printed Circuit) is connected is provided in a portion of the first substrate 701 which does not overlap with the second substrate 705.
- FPC 716 Flexible Printed Circuit
- Various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC terminal portion 708 and the signal line 710 by the FPC 716.
- a plurality of gate driver circuit units 706 may be provided.
- the gate driver circuit unit 706 and the source driver circuit unit 704 may be separately formed on a semiconductor substrate or the like and may be in the form of an IC chip packaged.
- the IC chip can be mounted over the first substrate 701 or the FPC 716.
- the transistor which is the semiconductor device of one embodiment of the present invention can be applied to the transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.
- a liquid crystal element, a light emitting element, or the like can be given.
- a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, or the like can be used.
- a light emitting element self-luminous light emitting elements, such as LED (Light Emitting Diode), OLED (Organic LED), QLED (Quantum-dot LED), a semiconductor laser, are mentioned.
- a shutter type or a light interference type MEMS (Micro Electro Mechanical Systems) element a display element to which a microcapsule type, an electrophoresis type, an electrowetting type, an electronic powder fluid (registered trademark) type, or the like is applied is used. It can also be done.
- MEMS Micro Electro Mechanical Systems
- the display device 700A illustrated in FIG. 10B is a display device which can be suitably used for an electronic device having a large screen.
- the display device 700A can be suitably used, for example, for a television device, a monitor device, a personal computer (including a notebook computer or desktop computer), a tablet terminal, digital signage, and the like.
- the display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuit portions 722.
- the plurality of source driver ICs 721 are attached to the FPC 723 respectively.
- one terminal is connected to the first substrate 701, and the other terminal is connected to the printed substrate 724.
- the printed substrate 724 can be provided on the back side of the pixel portion 702 and mounted on the electronic device, and space saving of the electronic device can be achieved.
- the gate driver circuit portion 722 is formed on the first substrate 701. Thereby, an electronic device with a narrow frame can be realized.
- a large-sized and high-resolution display device can be realized.
- the present invention can also be applied to a display having a screen size of 30 inches or more, 40 inches, 50 inches, or 60 inches or more.
- a display device with extremely high resolution such as full high definition, 4K2K, or 8K4K can be realized.
- FIGS. 11 to 13 are cross-sectional views taken along the alternate long and short dash line Q-R shown in FIG. 10A, respectively.
- 11 and 12 each show a configuration using a liquid crystal element as a display element
- FIG. 13 shows a configuration using an EL element.
- the display device 700 illustrated in FIGS. 11 to 13 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708.
- the routing wiring portion 711 has a signal line 710.
- the pixel portion 702 includes a transistor 750 and a capacitor 790.
- the source driver circuit unit 704 includes a transistor 752.
- the transistors described in Embodiment 1 can be applied to the transistors 750 and 752.
- the transistor used in this embodiment has the oxide semiconductor film which is highly purified and in which the formation of oxygen vacancies is suppressed.
- the transistor can reduce off current. Therefore, the holding time of the electric signal such as the image signal can be lengthened, and the writing interval of the image signal etc can be set long. Thus, the frequency of the refresh operation can be reduced, which leads to an effect of reducing power consumption.
- the transistor used in this embodiment can be driven at high speed because relatively high field-effect mobility can be obtained.
- the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of components of the display device can be reduced.
- a transistor which can be driven at high speed also in the pixel portion an image with high quality can be provided.
- the capacitor 790 is formed by processing the same film as the semiconductor layer in the transistor 750, and is formed by processing the lower electrode whose resistance is reduced and the same conductive film as the source or drain electrode. And. In addition, a two-layer insulating film covering the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is held between a pair of electrodes.
- a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
- the transistor 750 in the pixel portion 702 and the transistor 752 in the source driver circuit portion 704 may have different structures. For example, a top gate transistor may be applied to one of the two and a bottom gate transistor may be applied to the other. Note that the above source driver circuit unit 704 may be read as a gate driver circuit unit.
- the signal line 710 is formed using the same conductive film as the source electrode, the drain electrode, and the like of the transistors 750 and 752. At this time, it is preferable to use a low-resistance material such as a material containing a copper element because signal delay due to wiring resistance and the like can be reduced and display on a large screen can be performed.
- the FPC terminal portion 708 includes a wiring 760 whose part functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716.
- the wiring 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film.
- the wiring 760 is formed using the same conductive film as the source electrode, the drain electrode, and the like of the transistors 750 and 752.
- first substrate 701 and the second substrate 705 for example, a flexible substrate such as a glass substrate or a plastic substrate can be used.
- a structure body 778 between the first substrate 701 and the second substrate 705 functions as a columnar spacer which controls a distance (cell gap) between the first substrate 701 and the second substrate 705.
- the structure body 778 may be formed on the second substrate 705 side or a spherical spacer may be used.
- a light shielding film 738, a coloring film 736, and an insulating film 734 in contact with these are provided.
- a display device 700 illustrated in FIG. 11 includes a liquid crystal element 775.
- the liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776 therebetween.
- the conductive film 774 is provided on the second substrate 705 side and has a function as a common electrode.
- the conductive film 772 is electrically connected to the source electrode or the drain electrode of the transistor 750.
- the conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode.
- a material which is translucent to visible light or a material which is reflective to visible light can be used.
- the light-transmitting material for example, an oxide material containing indium, zinc, tin, or the like may be used.
- the reflective material for example, a material containing aluminum, silver or the like may be used.
- the display device 700 is a reflective liquid crystal display device.
- a transmissive liquid crystal display device is obtained.
- a polarizing plate is provided on the viewing side.
- a transmissive liquid crystal display device a pair of polarizing plates is provided to sandwich a liquid crystal element.
- a display device 700 illustrated in FIG. 12 illustrates an example in which a liquid crystal element 775 in a horizontal electric field mode (for example, FFS mode) is used.
- a conductive film 774 functioning as a common electrode is provided over the conductive film 772 with the insulating film 773 interposed therebetween.
- an alignment film in contact with the liquid crystal layer 776 may be provided.
- an optical member optical substrate
- a polarization member such as a polarization member, a retardation member, and an anti-reflection member
- a light source such as a backlight and a side light
- thermotropic liquid crystal a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a polymer network liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like
- liquid crystal exhibiting a blue phase which does not use an alignment film may be used.
- TN Transmission Nematic
- VA Very Alignment
- IPS In-Plane-Switching
- FFS Ringe Field Switching
- ASM Analy Symmetrically Aligned Micro-cell
- OCB Optical Compensated Birefringence
- ECB Electro Mechanical Controlled Birefringence
- a display device 700 illustrated in FIG. 13 includes a light emitting element 782.
- the light-emitting element 782 includes the conductive film 772, the EL layer 786, and the conductive film 788.
- the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.
- Materials usable for the organic compound include fluorescent materials and phosphorescent materials.
- a material which can be used for a quantum dot a colloidal quantum dot material, an alloy type quantum dot material, a core-shell type quantum dot material, a core type quantum dot material, etc. are mentioned.
- an insulating film 730 which covers part of the conductive film 772 is provided over the planarization insulating film 770.
- the light emitting element 782 is a top emission type light emitting element having a light transmitting conductive film 788. Note that the light emitting element 782 may have a bottom emission structure in which light is emitted to the conductive film 772 side or a dual emission structure in which light is emitted to both the conductive film 772 side and the conductive film 788 side.
- the coloring film 736 is provided at a position overlapping with the light emitting element 782, and the light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704.
- the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. Further, a sealing film 732 is filled between the light emitting element 782 and the insulating film 734. Note that in the case where the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, in a case where the EL layer 786 is formed separately, the coloring film 736 may not be provided.
- the display device 700 illustrated in FIGS. 11 to 13 may be provided with an input device.
- an input device a touch sensor etc. are mentioned, for example.
- FIG. 14 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG. 12, and FIG. 15 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG.
- the touch panel 791 illustrated in FIGS. 14 and 15 is provided between the second substrate 705 and the coloring film 736.
- the touch panel 791 may be formed on the second substrate 705 side before the colored film 736 is formed.
- the touch panel 791 is provided between the second substrate 705 and the first substrate 701, and thus can be referred to as an in-cell touch panel.
- the touch panel 791 includes an electrode 793, an electrode 794, an insulating film 795, and an electrode 796 between the insulating film 792 covering the light shielding film 738 and the insulating layer 797. For example, it is possible to detect a change in capacitance between the electrode 793 and the electrode 794 that may occur when a detected object such as a finger or a stylus approaches.
- a crossing portion of the electrode 793 and the electrode 794 is shown.
- the electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795.
- the intersection may be formed, for example, in the lead wiring portion 711 or the like.
- the electrode 793 and the electrode 794 are preferably provided in a region which does not overlap with the light emitting element 782 or the liquid crystal element 775, for example, a portion overlapping with the light shielding film 738.
- the electrode 793 and the electrode 794 can have a mesh shape. Accordingly, the light emitted from the light emitting element 782 or the light transmitted through the liquid crystal element 775 can not be blocked, and the decrease in luminance due to the disposition of the touch panel 791 is suppressed, and the visibility is high and the consumption is high. A display device with reduced power can be realized. Further, at this time, a low-resistance metal material can be used for the electrodes 793 and 794. Therefore, the sensor sensitivity of the touch panel can be improved as compared with the case of using a translucent conductive material.
- the configuration of the touch panel is not limited to the in-cell type, and may be a so-called on-cell type touch panel in which the input device is formed on the display device 700 or a so-called out-cell type touch panel using the input device bonded to the display device 700. Good.
- This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.
- the display device illustrated in FIG. 16A includes a pixel portion 502, a driver circuit portion 504, a protective circuit 506, and a terminal portion 507. Note that the protective circuit 506 may not be provided.
- the transistor of one embodiment of the present invention can be applied to the transistor included in the pixel portion 502 and the driver circuit portion 504.
- the transistor of one embodiment of the present invention may be applied to the protective circuit 506.
- the pixel portion 502 includes a plurality of pixel circuits 501 for driving a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).
- the driver circuit portion 504 includes driver circuits such as a gate driver 504a which outputs a scan signal to the gate lines GL_1 to GL_X, and a source driver 504b which supplies a data signal to the data lines DL_1 to DL_Y.
- the gate driver 504a may be configured to have at least a shift register.
- the source driver 504 b is configured using, for example, a plurality of analog switches. Alternatively, the source driver 504 b may be configured using a shift register or the like.
- a terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.
- the protective circuit 506 is a circuit which brings a wiring and another wiring into conduction when the wiring to which the protection circuit 506 is connected is supplied with a potential outside the predetermined range.
- the protective circuit 506 illustrated in FIG. 16A is, for example, a scanning line GL which is a wiring between the gate driver 504 a and the pixel circuit 501 or a data line DL which is a wiring between the source driver 504 b and the pixel circuit 501. It is connected to various wiring.
- the gate driver 504 a and the source driver 504 b may be provided over the same substrate as the pixel portion 502, or a substrate in which a gate driver circuit or a source driver circuit is separately formed (for example, a single crystal semiconductor film or a plurality of substrates).
- the driver circuit substrate formed of a crystalline semiconductor film may be mounted on the substrate by COG or TAB (Tape Automated Bonding).
- FIG. 17 shows a configuration different from that of FIG.
- a pair of source lines for example, source line DLa1 and source line DLb1 are arranged so as to sandwich a plurality of pixels arranged in the source line direction.
- two adjacent gate lines for example, the gate line GL_1 and the gate line GL_2 are electrically connected.
- the pixels connected to the gate line GL_1 are connected to one of the source lines (the source line DLa1, the source line DLa2, etc.), and the pixels connected to the gate line GL_2 are the other source line (the source line DLb1, the source Are connected to line DLb2 etc.).
- the plurality of pixel circuits 501 illustrated in FIGS. 16A and 17 can have a configuration illustrated in FIG. 16B, for example.
- the pixel circuit 501 illustrated in FIG. 16B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. Further, to the pixel circuit 501, a data line DL_n, a scanning line GL_m, a potential supply line VL, and the like are connected.
- the potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set in accordance with the specification of the pixel circuit 501.
- the alignment state of the liquid crystal element 570 is set by the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.
- the pixel circuit 501 illustrated in FIG. 16C includes transistors 552 and 554, a capacitor 562, and a light emitting element 572. Further, to the pixel circuit 501, a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a power supply line VL_b, and the like are connected.
- the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.
- This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.
- Embodiment 4 In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.
- a display module 6000 illustrated in FIG. 18A includes a display device 6006 to which an FPC 6005 is connected, a frame 6009, a printed substrate 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.
- the display device manufactured using one embodiment of the present invention can be used for the display device 6006.
- the display device 6006 can realize a display module with extremely low power consumption.
- the shape and size of the upper cover 6001 and the lower cover 6002 can be appropriately changed in accordance with the size of the display device 6006.
- the display device 6006 may have a function as a touch panel.
- the frame 6009 may have a protective function of the display device 6006, a function of blocking an electromagnetic wave generated by the operation of the printed substrate 6010, a function as a heat sink, and the like.
- the printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.
- FIG. 18B is a schematic cross-sectional view of a display module 6000 including an optical touch sensor.
- the display module 6000 includes a light emitting unit 6015 and a light receiving unit 6016 provided on the printed circuit board 6010.
- a pair of light guide portions (light guide portions 6017 a and 6017 b) is provided in a region surrounded by the upper cover 6001 and the lower cover 6002.
- the display device 6006 is provided to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween.
- the display device 6006 and the frame 6009 are fixed to the light guide unit 6017 a and the light guide unit 6017 b.
- the light 6018 emitted from the light emitting unit 6015 passes through the upper portion of the display device 6006 by the light guiding unit 6017 a, passes through the light guiding unit 6017 b, and reaches the light receiving unit 6016. For example, when the light 6018 is blocked by a detection target such as a finger or a stylus, a touch operation can be detected.
- a detection target such as a finger or a stylus
- a plurality of light emitting units 6015 are provided along two adjacent sides of the display device 6006.
- a plurality of light receiving units 6016 are provided at positions facing the light emitting units 6015. Thereby, information on the position where the touch operation has been performed can be acquired.
- the light emitting unit 6015 can use, for example, a light source such as an LED element, and in particular, it is preferable to use a light source that emits infrared light.
- the light receiving unit 6016 can use a photoelectric element that receives light emitted by the light emitting unit 6015 and converts the light into an electric signal.
- a photodiode capable of receiving infrared light can be used.
- the light emitting unit 6015 and the light receiving unit 6016 can be disposed below the display device 6006 by the light guiding unit 6017a and the light guiding unit 6017b that transmit the light 6018, and outside light reaches the light receiving unit 6016 and the touch sensor Can be suppressed from malfunctioning.
- malfunction of the touch sensor can be more effectively suppressed.
- This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.
- FIG. 19A is a view showing the appearance of the camera 8000 in a state where the finder 8100 is attached.
- the camera 8000 includes a housing 8001, a display portion 8002, an operation button 8003, a shutter button 8004, and the like. Further, a detachable lens 8006 is attached to the camera 8000.
- the lens 8006 and the housing may be integrated.
- the camera 8000 can capture an image by pressing the shutter button 8004 or touching the display portion 8002 functioning as a touch panel.
- the housing 8001 has a mount having an electrode, and can be connected to a strobe device or the like in addition to the finder 8100.
- the finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
- the housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000.
- the finder 8100 can display an image or the like received from the camera 8000 on the display unit 8102.
- the button 8103 has a function as a power button or the like.
- the display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
- the camera may be a camera 8000 with a built-in finder.
- FIG. 19B is a view showing the appearance of the head mounted display 8200.
- the head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205 and the like.
- a battery 8206 is incorporated in the mounting portion 8201.
- the cable 8205 supplies power from the battery 8206 to the main body 8203.
- the main body 8203 includes a wireless receiver and the like, and can cause the display portion 8204 to display received video information.
- the main body 8203 includes a camera, and information on the movement of the user's eyeballs and eyelids can be used as an input unit.
- the mounting portion 8201 may be provided with a plurality of electrodes capable of detecting the current flowing along with the movement of the eyeball of the user at a position where the user touches the user, and may have a function of recognizing the sight line. Moreover, you may have a function which monitors a user's pulse by the electric current which flows into the said electrode.
- the mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and has a function of displaying biological information of the user on the display unit 8204 and movement of the head of the user. It may have a function of changing the image displayed on the display portion 8204 in accordance with the above.
- the display device of one embodiment of the present invention can be applied to the display portion 8204.
- FIG. 19C, 19D, and 19E show the appearance of the head mounted display 8300.
- FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-like fixing tool 8304, and a pair of lenses 8305.
- the user can view the display on the display portion 8302 through the lens 8305.
- the display portion 8302 is preferably arranged to be curved because a user can feel high reality. Further, by visually recognizing another image displayed in a different region of the display portion 8302 through the lens 8305, three-dimensional display or the like using parallax can be performed. Note that the present invention is not limited to the configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided and one display portion may be provided for one eye of the user.
- the display device in one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when enlarged using the lens 8305 as illustrated in FIG. More realistic images can be displayed.
- the electronic devices illustrated in FIGS. 20A to 20G include a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (power , Displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration , Including a function of measuring odor or infrared), a microphone 9008, and the like.
- the electronic devices illustrated in FIGS. 20A to 20G have various functions. For example, a function of displaying various information (still image, moving image, text image, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of controlling processing by various software (programs), A wireless communication function, a function of reading and processing a program or data recorded in a recording medium, and the like can be provided. Note that the functions of the electronic device are not limited to these, and can have various functions.
- the electronic device may have a plurality of display portions.
- a camera or the like is provided in the electronic device, and still images and moving images are taken and stored in a recording medium (externally or built in the camera), a function to display the taken image on the display unit, etc. Good.
- FIGS. 20A to 20G The details of the electronic devices illustrated in FIGS. 20A to 20G will be described below.
- FIG. 20A is a perspective view of the television set 9100.
- the television set 9100 can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.
- FIG. 20B is a perspective view showing the portable information terminal 9101.
- the portable information terminal 9101 can be used, for example, as a smartphone.
- the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
- the portable information terminal 9101 can display text and image information on the plurality of surfaces.
- FIG. 20B shows an example in which three icons 9050 are displayed. Further, information 9051 indicated by a dashed-line rectangle can also be displayed on another surface of the display portion 9001.
- Examples of the information 9051 include e-mail, SNS message, notification of arrival of a call etc., title or sender name of e-mail or SNS message, date / time, time of remaining battery, strength of antenna reception, etc.
- an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
- FIG. 20C is a perspective view showing the portable information terminal 9102.
- the portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001.
- the information 9052, the information 9053, and the information 9054 are displayed on different sides.
- the user can check the information 9053 displayed at a position where it can be observed from the upper side of the portable information terminal 9102 while the portable information terminal 9102 is stored in the chest pocket of the clothes.
- the user can confirm the display without taking out the portable information terminal 9102 from the pocket, and can determine, for example, whether or not to receive a call.
- FIG. 20D is a perspective view showing a wristwatch-type portable information terminal 9200.
- the portable information terminal 9200 can be used as, for example, a smart watch.
- the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
- the portable information terminal 9200 can perform mutual data transmission with another information terminal or charge the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding.
- FIG. 20E, 20F, and 20G are perspective views showing the foldable portable information terminal 9201.
- FIG. 20E shows a state in which the portable information terminal 9201 is expanded
- FIG. 20G shows a folded state
- FIG. 20F shows a change from one of FIG. 20E and FIG. 20G to the other. It is a perspective view of the state on the way.
- the portable information terminal 9201 is excellent in portability in the folded state, and excellent in viewability of display due to a wide seamless display area in the expanded state.
- a display portion 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
- the display portion 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.
- the electronic devices described below each include the display device of one embodiment of the present invention in a display portion. Therefore, it is an electronic device in which high resolution is realized. In addition, an electronic device in which a high resolution and a large screen are compatible can be provided.
- the display portion of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.
- Examples of the electronic devices include electronic devices having a relatively large screen such as a television device, a laptop personal computer, a monitor device, a digital signage, a pachinko machine, a game machine, a digital camera, a digital video camera, a digital photo A frame, a portable telephone, a portable game machine, a portable information terminal, a sound reproduction apparatus, etc. are mentioned.
- the electronic device or lighting device to which one embodiment of the present invention is applied can be incorporated along a flat surface or a curved surface of an inner or outer wall of a house or a building, an interior or exterior of a car, or the like.
- FIG. 21A shows an example of a television set.
- a display portion 7500 is incorporated in a housing 7101.
- a structure in which the housing 7101 is supported by the stand 7103 is shown.
- the television set 7100 illustrated in FIG. 21A can be operated by an operation switch of the housing 7101 or a separate remote controller 7111.
- the television device 7100 may be operated by applying a touch panel to the display portion 7500 and touching it.
- the remote controller 7111 may have a display portion in addition to the operation button.
- the television set 7100 may have a television broadcast receiver or a communication device for network connection.
- a notebook personal computer 7200 is shown in FIG.
- the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
- the display portion 7500 is incorporated in the housing 7211.
- 21C and 21D show an example of digital signage (digital signage).
- a digital signage 7300 illustrated in FIG. 21C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.
- FIG. 21D shows a digital signage 7400 attached to a cylindrical column 7401.
- the digital signage 7400 has a display 7500 provided along the curved surface of the column 7401.
- the display portion 7500 is wider, the amount of information that can be provided at one time can be increased, and since it is easy to be seen by people, for example, an effect of enhancing the advertising effect of an advertisement is achieved.
- a touch panel be applied to the display portion 7500 so that the user can operate it.
- it can be used not only for advertising applications but also for applications for providing information required by users, such as route information, traffic information, and guide information of commercial facilities.
- digital signage 7300 or digital signage 7400 can cooperate with an information terminal 7311 such as a smartphone possessed by a user by wireless communication.
- the display of the display unit 7500 can be switched by displaying the information of the advertisement displayed on the display unit 7500 on the screen of the information terminal 7311 or operating the information terminal 7311.
- the digital signage 7300 or the digital signage 7400 can execute a game using the information terminal 7311 as an operation means (controller).
- an unspecified number of users can simultaneously participate in and enjoy the game.
- the display device in one embodiment of the present invention can be applied to the display portion 7500 in FIGS.
- the electronic device of this embodiment has a display portion
- one embodiment of the present invention can be applied to an electronic device which does not have a display portion.
- This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.
Abstract
Description
本実施の形態では、本発明の一態様の半導体装置、表示装置、及びその作製方法について説明する。
図1(A)は、トランジスタ100の上面図であり、図1(B)は、図1(A)に示す一点鎖線A1−A2における切断面の断面図に相当し、図1(C)は、図1(A)に示す一点鎖線B1−B2における切断面の断面図に相当する。なお、図1(A)において、トランジスタ100の構成要素の一部(ゲート絶縁層等)を省略して図示している。また、一点鎖線A1−A2方向をチャネル長方向、一点鎖線B1−B2方向をチャネル幅方向と呼称する場合がある。また、トランジスタの上面図においては、以降の図面においても図1(A)と同様に、構成要素の一部を省略して図示する場合がある。
以下では、上記構成例1の変形例について説明する。
図2(A)、(B)では、絶縁層104と半導体層108とを、同じエッチングマスクにより島状に加工した場合の例を示している。言い換えると、絶縁層104と半導体層108とは、平面視における上面形状が概略一致しているとも言える。また、絶縁層104と半導体層108とは、それぞれの端部における側面が連続している、とも言うことができる。
図2(C)は、絶縁層104の端部が、半導体層108よりも外側であって、且つ導電層112、金属酸化物層114、及び絶縁層110の端部よりも内側に位置するように、絶縁層104を加工した場合の例である。図2(C)には、チャネル幅方向の断面を示している。
以下では、上記構成例1と一部の構成が異なるトランジスタの構成例について説明する。なお、以下では、上記構成例1と重複する部分は説明を省略する場合がある。また、以下で示す図面において、上記構成例と同様の機能を有する部分についてはハッチングパターンを同じくし、符号を付さない場合もある。
以下では、上記構成例2の変形例について説明する。
図4(A)、(B)は、絶縁層104と半導体層108とを、同じエッチングマスクにより島状に加工した場合の例を示している。
図5(A)は、絶縁層104の端部が、半導体層108、導電層112、金属酸化物層114、及び絶縁層110よりも外側であって、且つ、導電層106よりも内側に位置するように、絶縁層104を加工した場合の例である。
図5(B)、(C)はそれぞれ、絶縁層104の端部が、半導体層108よりも外側であって、且つ、導電層112、金属酸化物層114、絶縁層110、及び導電層106よりも内側に位置する場合の例である。
以下では、上記トランジスタを表示装置の画素に適用する場合の例について説明する。
次に、本実施の形態の半導体装置に含まれる構成要素について、詳細に説明する。
基板102の材質などに大きな制限はないが、少なくとも、後の熱処理に耐えうる程度の耐熱性を有している必要がある。例えば、シリコンや炭化シリコンを材料とした単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、SOI基板、ガラス基板、セラミック基板、石英基板、サファイア基板等を、基板102として用いてもよい。また、これらの基板上に半導体素子が設けられたものを、基板102として用いてもよい。
絶縁層104としては、スパッタリング法、CVD法、蒸着法、パルスレーザー堆積(PLD)法等を適宜用いて形成することができる。また、絶縁層104としては、例えば、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、半導体層108との界面特性を向上させるため、絶縁層104において少なくとも半導体層108と接する領域は酸化物絶縁膜で形成することが好ましい。また、絶縁層104には、加熱により酸素を放出する膜を用いることが好ましい。
ゲート電極として機能する導電層112及び導電層106、並びにソース電極またはドレイン電極の一方として機能する導電層120a、及び他方として機能する導電層120bとしては、クロム、銅、アルミニウム、金、銀、亜鉛、モリブデン、タンタル、チタン、タングステン、マンガン、ニッケル、鉄、コバルトから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いてそれぞれ形成することができる。
トランジスタ100等のゲート絶縁膜として機能する絶縁層110は、PECVD法、スパッタリング法等により形成できる。絶縁層110としては、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜、酸化イットリウム膜、酸化ジルコニウム膜、酸化ガリウム膜、酸化タンタル膜、酸化マグネシウム膜、酸化ランタン膜、酸化セリウム膜および酸化ネオジム膜を一種以上含む絶縁層を用いることができる。なお、絶縁層110を、2層の積層構造または3層以上の積層構造としてもよい。
半導体層108がIn−M−Zn酸化物の場合、In−M−Zn酸化物を成膜するために用いるスパッタリングターゲットは、Inの原子数比がMの原子数比以上であることが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、In:M:Zn=1:1:1、In:M:Zn=1:1:1.2、In:M:Zn=2:1:3、In:M:Zn=3:1:2、In:M:Zn=4:2:4.1、In:M:Zn=5:1:6、In:M:Zn=5:1:7、In:M:Zn=5:1:8、In:M:Zn=6:1:6、In:M:Zn=5:2:5等が挙げられる。
以下では、本発明の一態様のトランジスタの作製方法の例について説明する。ここでは、構成例2で例示したトランジスタ100Aを例に挙げて説明する。
基板102上に導電膜を成膜し、これをエッチングにより加工して、ゲート電極として機能する導電層106を形成する(図7(A))。
続いて、基板102及び導電層106を覆って、絶縁層103と絶縁層104を積層して形成する(図7(B))。絶縁層103及び絶縁層104はそれぞれ、PECVD法、ALD法、スパッタリング法などを用いて形成することができる。
続いて、絶縁層104及び絶縁層103上に金属酸化物膜を成膜し、これを加工することにより半導体層108を形成する。
続いて、絶縁層103、絶縁層104、及び半導体層108を覆って、絶縁層110となる絶縁膜110fと、金属酸化物層114となる金属酸化物膜114fを積層して成膜する。
続いて、金属酸化物膜114f上に、導電層112となる導電膜を成膜する。当該導電膜は、金属または合金のスパッタリングターゲットを用いたスパッタリング法により成膜することが好ましい。
続いて、絶縁層104、半導体層108、絶縁層110の側面、金属酸化物層114の側面、及び導電層112等を覆って、絶縁層116を形成する。またこのとき、絶縁層104の端部よりも外側において、絶縁層103と絶縁層116とが接する領域が形成される(図9(A))。
続いて、加熱処理を行うことが好ましい。加熱処理により、半導体層108の領域108nの低抵抗化をより促進させることができる。
続いて、絶縁層116を覆って絶縁層118を形成する。絶縁層118は、例えばPECVD法により形成することができる。
続いて、絶縁層118及び絶縁層116の一部をエッチングすることで、領域108nに達する開口部141a、開口部141bを形成する。
続いて、開口部141a、開口部141bを覆うように、絶縁層118上に導電膜を成膜し、当該導電膜を所望の形状に加工することで、導電層120a、導電層120bを形成する(図9(B))。
本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について説明を行う。
図10(A)に、表示装置700の上面図を示す。表示装置700は、シール材712により貼りあわされた第1の基板701と第2の基板705を有する。また第1の基板701、第2の基板705、及びシール材712で封止される領域において、第1の基板701上に画素部702、ソースドライバ回路部704、及びゲートドライバ回路部706が設けられる。また画素部702には、複数の表示素子が設けられる。
以下では、表示素子として液晶素子及びEL素子を用いる構成について、図11乃至図13を用いて説明する。なお、図11乃至図13は、それぞれ図10(A)に示す一点鎖線Q−Rにおける断面図である。図11及び図12は、表示素子として液晶素子を用いた構成であり、図13は、EL素子を用いた構成である。
図11乃至図13に示す表示装置700は、引き回し配線部711と、画素部702と、ソースドライバ回路部704と、FPC端子部708と、を有する。引き回し配線部711は、信号線710を有する。画素部702は、トランジスタ750及び容量素子790を有する。ソースドライバ回路部704は、トランジスタ752を有する。
図11に示す表示装置700は、液晶素子775を有する。液晶素子775は、導電膜772、導電膜774、及びこれらの間に液晶層776を有する。導電膜774は、第2の基板705側に設けられ、共通電極としての機能を有する。また、導電膜772は、トランジスタ750が有するソース電極またはドレイン電極と電気的に接続される。導電膜772は、平坦化絶縁膜770上に形成され、画素電極として機能する。
図13に示す表示装置700は、発光素子782を有する。発光素子782は、導電膜772、EL層786、及び導電膜788を有する。EL層786は、有機化合物、または量子ドットなどの無機化合物を有する。
また、図11乃至図13に示す表示装置700に入力装置を設けてもよい。当該入力装置としては、例えば、タッチセンサ等が挙げられる。
本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図16を用いて説明を行う。
本実施の形態では、本発明の一態様を用いて作製することができる表示モジュールについて説明する。
本実施の形態では、本発明の一態様を用いて作製された表示装置を備える電子機器について説明する。
Claims (9)
- 第1の絶縁層と、第2の絶縁層と、第3の絶縁層と、第4の絶縁層と、半導体層と、第1の導電層と、を有し、
前記第2の絶縁層は、前記第1の絶縁層上に位置し、
前記半導体層は、前記第2の絶縁層上に位置し、且つ島状の形状を有し、
前記第3の絶縁層及び前記第1の導電層は、前記半導体層上に積層して設けられ、
前記第2の絶縁層は、前記半導体層と重なる領域よりも外側に端部を有する島状の形状を有し、
前記第4の絶縁層は、前記第2の絶縁層、前記半導体層、前記第3の絶縁層、及び前記第1の導電層を覆い、且つ、前記半導体層の上面の一部と接し、且つ、前記第2の絶縁層の前記端部よりも外側において前記第1の絶縁層と接し、
前記半導体層は、金属酸化物を含み、
前記第2の絶縁層及び前記第3の絶縁層は、酸化物を含み、
前記第1の絶縁層は、金属酸化物、または窒化物を含み、
前記第4の絶縁層は、金属窒化物を含む、
半導体装置。 - 請求項1において、
前記第4の絶縁層は、アルミニウムを含む、
半導体装置。 - 請求項1または請求項2において、
前記第1の絶縁層は、アルミニウム及びハフニウムの少なくとも一方と、酸素と、を有する、
半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記第2の絶縁層と、前記半導体層とは、上面形状が概略一致する、
半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第2の絶縁層は、前記端部が、前記第1の導電層と重なる領域よりも外側に位置する部分を有する、
半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第2の絶縁層は、前記端部が、前記第1の導電層と重なる領域に位置する部分を有する、
半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第1の絶縁層よりも下に第2の導電層を有し、
前記第2の導電層は、前記半導体層及び前記第1の導電層の両方と重なる領域を有する、
半導体装置。 - 請求項7において、
前記第2の絶縁層は、前記端部が、前記第2の導電層と重なる領域よりも外側に位置する部分を有する、
半導体装置。 - 請求項7において、
前記第2の絶縁層は、前記端部が、前記第2の導電層と重なる領域に位置する部分を有する、
半導体装置。
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WO2023238746A1 (ja) * | 2022-06-07 | 2023-12-14 | 株式会社ジャパンディスプレイ | 半導体装置及び半導体装置の製造方法 |
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KR102350465B1 (ko) | 2021-04-29 | 2022-01-13 | (주)티에이치엔 | 확장 가능한 그로멧 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016201518A (ja) * | 2015-04-14 | 2016-12-01 | 株式会社半導体エネルギー研究所 | 導電体および半導体装置の作製方法 |
JP2017191934A (ja) * | 2016-04-08 | 2017-10-19 | 株式会社半導体エネルギー研究所 | トランジスタ、およびその作製方法 |
Family Cites Families (12)
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JP5708910B2 (ja) | 2010-03-30 | 2015-04-30 | ソニー株式会社 | 薄膜トランジスタおよびその製造方法、並びに表示装置 |
US8748240B2 (en) | 2011-12-22 | 2014-06-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
CN104380473B (zh) | 2012-05-31 | 2017-10-13 | 株式会社半导体能源研究所 | 半导体装置 |
JP5951442B2 (ja) | 2012-10-17 | 2016-07-13 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP6322503B2 (ja) * | 2013-07-16 | 2018-05-09 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9590111B2 (en) * | 2013-11-06 | 2017-03-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device including the semiconductor device |
US9929279B2 (en) * | 2014-02-05 | 2018-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10043913B2 (en) | 2014-04-30 | 2018-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor film, semiconductor device, display device, module, and electronic device |
JP6486712B2 (ja) * | 2014-04-30 | 2019-03-20 | 株式会社半導体エネルギー研究所 | 酸化物半導体膜 |
US10192995B2 (en) | 2015-04-28 | 2019-01-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9847406B2 (en) * | 2015-08-27 | 2017-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, storage device, resistor circuit, display device, and electronic device |
US9905657B2 (en) | 2016-01-20 | 2018-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
-
2018
- 2018-10-23 US US16/758,091 patent/US11424334B2/en active Active
- 2018-10-23 JP JP2019549673A patent/JPWO2019087002A1/ja not_active Withdrawn
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016201518A (ja) * | 2015-04-14 | 2016-12-01 | 株式会社半導体エネルギー研究所 | 導電体および半導体装置の作製方法 |
JP2017191934A (ja) * | 2016-04-08 | 2017-10-19 | 株式会社半導体エネルギー研究所 | トランジスタ、およびその作製方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023189493A1 (ja) * | 2022-03-30 | 2023-10-05 | 株式会社ジャパンディスプレイ | 半導体装置 |
WO2023238746A1 (ja) * | 2022-06-07 | 2023-12-14 | 株式会社ジャパンディスプレイ | 半導体装置及び半導体装置の製造方法 |
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US20220359691A1 (en) | 2022-11-10 |
JP2023106446A (ja) | 2023-08-01 |
KR20200077532A (ko) | 2020-06-30 |
CN111357086A (zh) | 2020-06-30 |
US11424334B2 (en) | 2022-08-23 |
JPWO2019087002A1 (ja) | 2020-12-10 |
US11929412B2 (en) | 2024-03-12 |
US20200328282A1 (en) | 2020-10-15 |
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