WO2019085374A1 - 光敏探测器、采用其构成的成像芯片以及探测方法 - Google Patents

光敏探测器、采用其构成的成像芯片以及探测方法 Download PDF

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WO2019085374A1
WO2019085374A1 PCT/CN2018/080182 CN2018080182W WO2019085374A1 WO 2019085374 A1 WO2019085374 A1 WO 2019085374A1 CN 2018080182 W CN2018080182 W CN 2018080182W WO 2019085374 A1 WO2019085374 A1 WO 2019085374A1
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transistor
control gate
charge
charge storage
phototransistor
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PCT/CN2018/080182
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English (en)
French (fr)
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闫锋
黄枝建
施毅
马浩文
李煜乾
卜晓峰
孔祥顺
毛成
杨程
张丽敏
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南京大学
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Priority to US16/652,870 priority Critical patent/US11342367B2/en
Publication of WO2019085374A1 publication Critical patent/WO2019085374A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
    • G03B7/08—Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
    • G03B7/091—Digital circuits
    • G03B7/093—Digital circuits for control of exposure time
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith

Definitions

  • This invention relates to an imaging device, and more particularly to a structure, a working mechanism, and a readout of an imaging detector member for use in visible light and infrared band detection, and the present invention is applicable to global exposure imaging.
  • Imaging devices have a wide range of applications in various fields. The most important imaging devices are CCD and CMOS-APS.
  • the CCD appears earlier, and the basic structure is formed by connecting MOS capacitors in series. After the gate is pulse-biased, a depletion region is formed to collect photoelectrons. Then, the pulse timing reads the photoelectrons in the form of charge packets.
  • the CCD is sensitive and resolved. The rate and imaging quality are superior to CMOS sensors, but there are disadvantages such as complicated process, high cost, and high power consumption.
  • CMOS image sensor is compatible with CMOS technology, so its cost and power consumption are lower than CCD, CMOS- APS is sensitive by diodes, and each detection unit includes several transistors for signal amplification and reading, addressing by peripheral decoding circuit and signal readout, because each detection unit contains A number of transistors cause CMOS-APS with small fill factor, low sensitivity, and high noise.
  • the patent CN201210442007 proposes a two-transistor photosensitive detector based on composite dielectric gate MOSFET, which makes up for the complicated CCD readout mode and small CMOS-APS fill factor.
  • the disadvantage of the size is difficult to reduce, the detector contains two transistors for sensing and reading, respectively, but in order to keep the number of photoelectrons in the detector from being affected by the order of reading time, the imaging chip using the detector array must The use of a mechanical shutter, so it does not have a global exposure function, which greatly limits its application range, so a new structure of the detector is needed to overcome this shortcoming, thereby achieving the global exposure of the imaging chip.
  • the present invention combines the principle of CCD charge transfer, and proposes an improved novel imaging device based on the functions of sensitization, photoelectron collection, reading and resetting of the original device.
  • the addition of photoelectron transfer and storage functions enables global exposure and further increases the fill factor and quantum efficiency of the pixels.
  • a global exposure photosensitive detector based on a composite dielectric gate MOSFET includes an array of a plurality of detecting units, each of which includes a photo transistor, a charge storage transistor, and a read transistor, and a phototransistor, a charge storage transistor, and a read transistor are formed Above the same P-type semiconductor substrate; the phototransistor is used to realize the photosensitive function of the photosensitive detector, and has a structure in which an underlying insulating dielectric layer and a charge coupling are sequentially arranged from bottom to top over the P-type semiconductor substrate.
  • a layer, a top dielectric dielectric layer and a control gate, or an underlying insulating dielectric layer and a control gate are sequentially disposed from bottom to top above the P-type semiconductor substrate;
  • the charge storage transistor is configured to realize storage of photogenerated charges,
  • the structure is: an underlying insulating dielectric layer, a charge coupling layer, a top insulating dielectric layer and a control gate are sequentially arranged from bottom to top above the P-type semiconductor substrate; the read transistor is used for reading signals
  • the structure is: an underlying insulating dielectric layer, a charge coupled layer, and a bottom layer of the P-type semiconductor substrate are arranged from bottom to top.
  • an N-type source is formed by ion implantation on a side of the P-type semiconductor substrate close to the underlying insulating medium, and the P-type semiconductor substrate is adjacent to the underlying insulating medium and the N
  • the opposite side of the source is formed by ion implantation to form an N-type drain
  • the charge storage transistor and the read transistor are separated in the substrate by a shallow trench isolation region;
  • the charge coupled layer of the phototransistor and the charge storage transistor The charge coupled layers are not connected, the control gate of the phototransistor is not connected to the control gate of the charge storage transistor;
  • the charge coupled layer of the charge storage transistor is connected to the charge coupled layer of the read transistor, and the control gate of the charge storage transistor Connected to the control gate of the read transistor.
  • a charge transfer transistor is disposed between the phototransistor and the charge storage transistor for controlling transfer of photo-generated charges; a charge transfer transistor is formed over the P-type semiconductor substrate, and an underlying insulation is sequentially provided from bottom to top a dielectric layer, a charge coupled layer, a top insulating dielectric layer, and a control gate; the charge coupled layer of the charge transfer transistor is not connected to the charge coupled layer of the phototransistor and the charge coupled layer of the charge storage transistor, and the control gate of the charge transfer transistor The pole is not connected to the control gate of the phototransistor and the control gate of the charge storage transistor.
  • control gates of the phototransistors of all the detecting units are interconnected to form a word line WL1; the control gates of the charge transfer transistors of all the detecting units are interconnected to form a word line WL2; and reading of each row of detecting units
  • An imaging chip comprising the above-mentioned global exposure photosensitive detector, comprising the detector array, a word line decoding and addressing circuit, a source line/drain line decoding and addressing circuit, an analog to digital conversion circuit and an interface circuit; a word line decoding addressing circuit for generating different bias signals for each word line during the exposure, transfer, read and reset phases of the detector according to the reading order; the source line/drain line decoding site selection a circuit for gating the source and drain of the detector read transistor in a read order; said analog to digital conversion circuit for converting an optoelectronic signal in the photodetector into a digital signal; said interface The circuit is used under the control of the clock signal to transmit the converted digital signal to the outside of the imaging chip.
  • a method for detecting a global exposure photosensitive detector based on a composite dielectric gate MOSFET comprising the following steps:
  • Photoelectron collection a positive bias is applied to the control gate of the phototransistor, a negative bias is applied to the substrate, a depletion region is formed on the P-type substrate to collect photoelectrons; and a control gate of the charge storage transistor is damaged. Applying a zero bias or a positive bias; the source and drain of the read transistor are grounded;
  • Another method for detecting a global exposure photosensitive detector based on the above composite dielectric gate MOSFET includes the following steps:
  • Photoelectron collection a positive bias is applied to the control gate of the phototransistor, a negative bias is applied to the substrate, and a depletion region is formed on the P-type substrate to collect photoelectrons; on the control gate of the charge transfer transistor Applying a negative bias voltage, applying a zero bias or a positive bias to the control gate of the charge storage transistor; the source and drain of the read transistor are grounded;
  • a negative bias equal to the bias voltage applied to the substrate is applied to the control gate of the phototransistor, the control gate of the charge transfer transistor, and the control gate of the charge storage transistor, and the source of the read transistor is read. And the drain is grounded, and the photoelectrons disappear by recombination with the holes.
  • the present invention can read the signal of each detecting unit through the row and column decoding unit. This method is different from the method of reading the signal by the mobile charge packet used by the CCD.
  • the photoelectron transfer process exists after each exposure, the photoelectron transfer is performed simultaneously, and the photoelectron transfer can be read immediately after completion. Its reading speed is faster than CCD;
  • the array composed of the detecting unit of the present invention has high integration with peripheral circuits, can greatly reduce the chip volume, and contributes to power consumption reduction, and the failure of any one pixel does not affect the normal operation of the entire imaging array.
  • 1 is a layout of a global exposure photosensitive detector device based on a composite dielectric gate MOSFET composed of three transistors;
  • 2 is a layout of a global exposure photosensitive detector device based on a composite dielectric gate MOSFET composed of four transistors;
  • Figure 3 is a cross-sectional view of Figure 1 taken along the aa' direction;
  • Figure 4 is a cross-sectional view of Figure 1 taken along the bb' direction;
  • Figure 5 is a cross-sectional view taken along line aa' of Figure 2;
  • Figure 6 is a cross-sectional view of Figure 2 taken along the bb' direction;
  • FIG. 7 is a schematic diagram of photoelectron transfer of a three-transistor global exposure photosensitive detector
  • FIG. 8 is a schematic diagram of photoelectron transfer of a four-transistor global exposure photosensitive detector
  • FIG. 9 is a schematic diagram showing changes in threshold voltage of a read transistor after photoelectron transfer
  • Figure 10 is an equivalent capacitance model of the structure of the signal reading portion of the global exposure photosensitive detector
  • 11 is a timing chart of operation of a three-transistor global exposure photosensitive detector unit
  • FIG. 13 is a schematic diagram of a three-transistor global exposure photosensitive detector array interconnection structure
  • FIG. 14 is a schematic diagram of a four-transistor global exposure photosensitive detector array interconnection structure
  • Figure 15 is a schematic diagram of a 3D imaging chip constructed by a global exposure photosensitive detector.
  • the global exposure photosensitive detector of this embodiment provides two basic structures, and the detecting unit uses three transistors and four transistors, respectively.
  • the structure of the three transistors includes a photo transistor 1, a charge storage transistor 2 and a read transistor 3.
  • the photo transistor 1 is used to realize the photoreceptive function of the photodetector, and the charge storage transistor 2 is used to store the photogenerated charge.
  • the structure of the four transistors includes a phototransistor 1, a charge transfer transistor 4, a charge storage transistor 2, and a read transistor 3.
  • the charge transfer transistor 4 controls the transfer of photogenerated electrons, and the charge storage transistor 2 is responsible for storing the transferred photoelectrons. Described as follows:
  • This embodiment is based on a three-crystal (3T) tube global exposure photosensitive detector of a composite dielectric gate MOSFET, the layout of which is shown in Figure 1, and the cross sections in the aa' and bb' directions are shown in Figures 3 and 4, respectively.
  • 3T three-crystal
  • the unit is configured by sequentially arranging the photo transistor 1, the charge storage transistor 2, and the read transistor 3 on the P-type semiconductor substrate 5; and providing an underlying insulating dielectric layer 6 from the bottom to the top of the P-type semiconductor substrate 5, a charge coupled layer 7, a top insulating dielectric layer 8 and a control gate 9; the global exposure photosensitive detector, the charge coupled layer 7 of the phototransistor 1 and the charge storage transistor 2 and the control gate 9 are etched by an etching process; The charge storage transistor 2 of the global exposure photosensitive detector and the charge coupling layer 7 and the control gate 9 of the read transistor 3 are connected, and the photoelectron signal stored by the charge storage transistor 2 is read by charge coupling; the charge storage transistor 2 and the P-type semiconductor substrate 5 under the read transistor 3 is separated by a shallow trench isolation (STI) 10; for the read transistor 3, a side of the P-type semiconductor substrate 5 close to the underlying insulating medium 6 is formed by ion implantation.
  • STI shallow trench isolation
  • the N-type source 11a forms an N-type drain 11b by ion implantation on the other side of the P-type semiconductor substrate 5 opposite to the underlying insulating medium 6 and the N-type source 11a; the phototransistor 1 and the charge storage transistor 2
  • the area may be the same or different, and the P-type semiconductor substrate 5 under the charge storage transistor 2 is P+ ion-implanted to form the P-type heavily doped region 12 to increase its full-charge capacity and reduce the area of the charge storage transistor 2.
  • the pixel fill factor is increased while isolating electrons collected from the photo transistor 1 and the P-type semiconductor substrate 5.
  • This embodiment is based on a four-crystal (4T) tube global exposure photosensitive detector of a composite dielectric gate MOSFET, the layout of which is shown in Figure 2, and the cross sections in the aa' and bb' directions are shown in Figures 5 and 6, respectively.
  • the unit is configured by sequentially arranging the photo transistor 1, the charge transfer transistor 4, the charge storage transistor 2, and the read transistor 3 on the P-type semiconductor substrate 5; and providing the bottom layer from the bottom to the top of the P-type semiconductor substrate 5 Insulating dielectric layer 6, charge coupling layer 7, top insulating dielectric layer 8 and control gate 9; said global exposure photosensitive detector, its phototransistor 1, charge transfer transistor 4 and charge storage layer 2 charge coupled layer 7 and control
  • the gate electrode 9 is etched by an etching process; the charge storage transistor 2 of the global exposure photosensitive detector and the charge coupling layer 7 of the read transistor 3 and the control gate 9 are connected, and the charge storage transistor 2 is read by charge coupling.
  • the stored photoelectron signal; the charge storage transistor 2 and the P-type semiconductor substrate 5 under the read transistor 3 are separated by a shallow trench isolation (STI) 10; for the read transistor 3, the P-type semiconductor substrate 5 is close to One side of the layer insulating medium 6 is formed by ion implantation to form an N-type source 11a, and on the side of the read transistor 3, the P-type semiconductor substrate 5 is adjacent to the other side of the underlying insulating dielectric layer 6 opposite to the N-type source 11a.
  • STI shallow trench isolation
  • the N-type drain 11b is formed by ion implantation; the areas of the phototransistor 1 and the charge storage transistor 2 may be the same or different, and P-type ion implantation is performed on the P-type semiconductor substrate under the charge storage transistor 2 to form a P-type heavily doped region. 12 to increase its full well charge capacity, reduce the area of the charge storage transistor 2, increase the cell fill factor, and isolate electrons collected from the photo transistor 1 and the P-type semiconductor substrate 5.
  • the bottom insulating dielectric layer 6 of the global exposure photosensitive detector is made of silicon oxide, SiON or other high dielectric constant medium, and has a thickness of about 10 nm; and the top insulating dielectric layer 8 is made of silicon nitride/silicon oxide/silicon nitride or silicon oxide.
  • control The gate 9 is made of polysilicon or other transparent conductive material; at least one of the dielectric layers on the substrate or the substrate of the phototransistor 1 is a transparent or translucent window for the wavelength of the detected light. In this embodiment, the upper insulating dielectric layer 6 is upward. To the control grid 9, a window that is transparent or translucent to the detector detection wavelength is provided.
  • the top insulating dielectric 8 and the charge coupled layer 7 above the phototransistor can be removed, and the control gate 9 is formed directly over the underlying insulating dielectric layer 6.
  • another method is to remove the top insulating dielectric layer 8 and the charge coupling layer 7 above the substrate of the phototransistor 1, and directly form the control gate 9 over the underlying insulating dielectric layer 6. It is to reduce the proportion of incident light absorbed by the medium above the substrate, especially the short wavelength components in the incident light.
  • the present embodiment is based on a preparation process of a global exposure photosensitive detector array of a composite dielectric gate MOSFET: first, active region definition and shallow trench isolation (STI) 10, one pixel includes two active regions, respectively, read transistors An active region of 3, and an active region of the phototransistor 1, the charge transfer transistor 4, and the charge storage transistor 2, which are isolated by shallow trench isolation (STI) 10; then the MOSFET cell is constructed Mainly forming the underlying insulating dielectric layer 6, the charge coupling layer 7, the top insulating dielectric layer 8, the control gate 9 and the source and drain regions (11a, 11b) of the transistor; the final process includes the fabrication and passivation of the metal interconnect lines. The layer is fabricated and the wafer surface is flattened.
  • STI shallow trench isolation
  • a suitable positive bias pulse is applied between the control gate of the phototransistor 1 and the substrate, and a depletion region is formed on the surface of the P-type semiconductor substrate 5.
  • the depth of the depletion region can be adjusted by the magnitude of the positive bias pulse;
  • the energy of the incident photon is greater than the forbidden band width of the semiconductor material (silicon)
  • the incident light is excited in the P-type semiconductor to generate an electron-hole pair, and the electron-hole pair in the depletion region acts under the electric field in the depletion region. Separating, photoelectrons are collected at the interface of the P-type semiconductor substrate and the underlying insulating dielectric layer, and holes are repelled into the substrate;
  • a positive bias voltage (2-5V) greater than the voltage applied to the control gate of the phototransistor 1 is applied to the control gate of the charge storage transistor 2, in the depletion region of the phototransistor 1
  • the photoelectrons are transferred to the depletion region of the charge storage transistor 2 under the action of thermal diffusion, self-induced drift and edge electric field.
  • a control and a P-type are added to the control gate of the phototransistor 1.
  • the negative bias voltage applied to the substrate is the same, the depletion region of the phototransistor 1 disappears, and the collection of photoelectrons is stopped.
  • a positive bias is applied to the control gate of the charge storage transistor 2 by a voltage greater than the voltage applied to the control gate of the phototransistor 1 (2-5 V), and a positive is applied to the charge transfer transistor 4.
  • the bias voltage lowers the barrier height of the semiconductor substrate underneath, thereby lowering the electron potential in the semiconductor substrate under the photosensitive transistor 1, the charge transfer transistor 4 and the charge storage transistor 2, and transferring the photoelectron from the photo transistor 1 to the charge storage
  • the method for reading the photoelectron signal based on the global exposure photosensitive detector of the composite dielectric gate MOSFET is as follows:
  • the threshold voltage of the read transistor in the dark state is scanned by adding a negative bias voltage (-5V-0V) to the substrate, the source 11a of the read transistor 3 is grounded, and the drain 11b is connected to a positive bias voltage ( 0.1V-0.2V), above the read transistor 3 control gate (shared with the charge storage transistor 2) plus a scan voltage from 0V to 7V, the voltage applied to the control gate when the source and drain are turned on is regarded as read Taking the threshold voltage V th1 of the transistor 3, the value should be a fixed value;
  • the photoelectrons stored in the depletion region of the charge storage transistor 2 are collected, and the potential of the charge coupled layer is affected by the mechanism of charge coupling.
  • the control gate above the charge storage transistor 2 is positively biased (2V). -7V), when reading, the source 11a of the read transistor 3 is grounded, and the drain 11b is connected to a positive bias (0.1V-0.2V), at which time the source and drain of the read transistor 3 are not turned on, and then
  • the control gate (shared with the read transistor) above the charge storage transistor 2 is applied with a ramp voltage, and the start value of the ramp voltage is equal to the positive bias value previously applied to the charge storage transistor 2, and the range of the ramp voltage is varied.
  • the specific value of (1V-2V) is determined by the sensitivity of the device. During the ramp-up voltage rise, the source and drain of the read transistor 3 gradually start to conduct, and the value of the ramp voltage when turned on is regarded as The threshold voltage V th2 of the transistor 3 is read after exposure.
  • the threshold voltage of the read transistor 3 after exposure is subtracted from the threshold voltage of the read transistor 3 in the dark state, that is, the change value ⁇ V th of the threshold voltage, as shown in FIG. 9, by which the charge storage transistor 2 can be obtained by calculation.
  • the number of photoelectrons stored in the area is not limited.
  • one method is to increase the fill factor of the pixel, increase the fill factor without increasing the pixel area, and increase the light-receiving surface area of the phototransistor 1 while reducing
  • the charge storage transistor 2 area in order to prevent incomplete charge transfer, needs to ensure that the full well charge capacity of the charge storage transistor 2 is greater than or equal to the full well charge capacity of the photo transistor 1, and the full charge of the charge storage transistor 2 can be increased by the following method.
  • P+ region 12 is formed by P+ ion implantation in the P-type semiconductor substrate 5 of the charge storage transistor 2, which can further increase the area of the phototransistor 1; it is noted that since the photodetector is charge coupled Acting to read the number of photoelectrons stored in the depletion region of the charge storage transistor 2, which means that reducing the area of the charge storage transistor 2 causes the sensitivity of the device to deteriorate because the amount of change in the threshold voltage of the device read transistor 3 depends on the capacitance C.
  • Three-transistor (3T) global exposure photosensitive detector photoelectric conversion process is the device operation timing diagram, during the exposure process, add a (-5-0V) negative bias pulse on the P-type semiconductor substrate 5.
  • the control gate cg_exp of the phototransistor 1 is added with a positive bias pulse of (0-2V), so that the substrate of the phototransistor 1 forms a depletion region, and when the incident photon reaches the depletion region, if the photon energy hv> semiconductor forbidden band Width E g , incident photons are absorbed by the semiconductor and excited to generate an electron hole pair, and an electric field directed to the P-type semiconductor substrate 5 at the interface between the P-type semiconductor substrate 5 and the underlying insulating dielectric layer 6 exists in the depletion region.
  • the electron-hole pairs are separated, electrons are collected at the interface while holes are repelled into the substrate, and as the photoelectrons are concentrated, the depth of the depletion region is reduced.
  • the device has a charge transfer transistor 2 due to its absence of charge transfer transistor 4, as shown in the timing diagram of FIG. 11, the charge storage transistor 2
  • the control gate cg_sto is added with a positive bias greater than cg_exp, so that the potential of the photoelectrons in the potential of the charge storage transistor 2 is lower than the potential of the photoelectrons of the phototransistor 1, and the photoelectrons will be under the action of thermal diffusion, self-induced drift and edge electric field.
  • the charge storage transistor 2 is transferred and stored in the depletion region.
  • FIG. 12 is the device operation timing diagram, during the exposure process, add a (-5-0V) negative bias pulse on the P-type semiconductor substrate 5.
  • the control gate cg_exp of the phototransistor 1 is added with a positive bias pulse of (0-2V), so that a depletion region is formed under the substrate of the phototransistor 1, and when the incident photon reaches the depletion region, if the photon energy hv> semiconductor is banned
  • the width E g the incident photons are absorbed by the semiconductor and excited to generate an electron hole pair, and an electric field directed to the P-type semiconductor substrate 5 at the interface between the P-type semiconductor substrate 5 and the underlying insulating dielectric layer 6 exists in the depletion region.
  • the electron-hole pairs are separated, electrons are collected at the interface while holes are repelled into the substrate, and as the photoelectrons are concentrated, the depth of the depletion region is reduced.
  • Photoelectron reading process After the photoelectron transfer of the photosensitive detector is completed, it is not necessary to transfer the charge packets like the CCD, but the CMOS-APS signal reading method is used to read the optical signal; a detecting unit is selected. Since photoelectrons are collected in the depletion region of the charge storage transistor 2, this partial charge affects the threshold voltage of the read transistor 3 by changing the surface potential, since a 10 nm thick underlying dielectric layer 6 is used in the design, and the gate liner is used. The bias difference between them is controlled within 8 V, and photoelectrons are negligible by tunneling into the charge coupled layer 7, so that the charge coupled layer 7 is always electrically neutral throughout the operation.
  • the charge coupled layer 7 of the charge storage transistor 2 has a potential V f
  • the surface potential of the substrate is V s
  • the bias voltage applied to the control gate is V cg
  • the surface of the charge coupled layer 7 and the charge storage transistor 2 The capacitance between them is C 1
  • the charge of the charge storage transistor 2 is C d
  • the capacitance between the charge coupled layer 7 and the control gate 9 is C 2
  • the capacitance above the STI region 10 is C STI
  • the charge coupled layer 7 and the read Taking the transistor 3 channel capacitance as C ch , for the charge coupling layer 7 node, ignoring the influence of electron injection, the charge amount in the charge coupled layer 7 is a constant Q f , then:
  • the above formula establishes the relationship between the potential change amount of the charge storage transistor 2 and the read transistor 3 charge coupling layer 7 and the number of photoelectrons in the depletion region of the charge storage transistor 2.
  • C This requires increasing C 1 or decreasing C 2 , C STI , C ch , C d .
  • Increasing C 1 can be achieved by reducing the thickness of the underlying insulating dielectric layer 6 of the charge storage transistor 2, increasing the area of the charge storage transistor 2 or using a dielectric material having a larger dielectric constant, but increasing the area of the charge storage transistor 2
  • the cost is a reduction of the pixel fill factor, so the device sensitivity cannot be increased by simply increasing the area of the charge storage transistor 2;
  • reducing Cch can increase the thickness or decrease of the underlying dielectric layer above the read transistor 3.
  • the area of the gate of the transistor 3 is read to achieve;
  • reducing C 2 can increase the thickness of the top insulating dielectric layer 8.
  • the change value ⁇ V f of the potential of the charge storage transistor 2 and the charge coupled layer 7 of the read transistor 3 is obtained, since the voltage change is considered from the viewpoint of the charge coupled layer 7, but the threshold voltage of the device is measured at the charge storage transistor 2 and A voltage is applied to the control gate of the read transistor 3, so it is necessary to convert the potential change of the charge coupled layer 7 into a change in the bias voltage on the control gate, and the conversion formula is Equation (7).
  • the number of photoelectrons can be estimated by measuring ⁇ V cg ; in order to obtain ⁇ V cg , the threshold voltage of the read transistor 3 under dark conditions is first obtained by direct scanning, which is denoted as V cg1 ; after exposure by oblique wave voltage scanning
  • the threshold voltage of the transistor 3 is read as follows: since V cg2 is already added to the control gate in advance, the ramp voltage start value is set to V cg2 , and it should be noted that the voltage value cannot be greater than that of the read transistor 3
  • the threshold voltage (the read transistor and the charge storage transistor share the control gate), the ramp voltage gradually increases from V cg2 , and when V cg2 + ⁇ V is reached, the read transistor 3 is turned on, then V cg2 + ⁇ V - V cg1 is the exposure
  • the change value ⁇ V cg of the threshold voltage of the transistor 3 is read before and after.
  • Reset process when the control gate of the phototransistor 1, the charge transfer transistor 4, and the charge control transistor 2 is added with a suitable negative bias (same as or slightly smaller than the negative bias applied to the substrate), the read transistor The source 11a and the drain 11b are grounded, and the photoelectrons accumulated in the depletion region are gradually reduced until they disappear by the recombination.
  • the above plurality of detecting units form an array to form an architecture of the detector array:
  • Figure 13 shows an equivalent circuit diagram of a three-transistor (3T) global exposure photosensitive detector array, the dashed box shows a detection unit, the control gate of each photodetector of each detection unit in the detection array is interconnected to form a word line WL1;
  • Figure 14 shows an equivalent circuit diagram of a four-transistor (4T) global exposure photosensitive detector array, the dashed box shows a detection unit, the control gate of each photodetector of each detection unit in the detection array is interconnected to form a word line WL1;
  • a four-transistor global exposure photosensitive detector array is taken as an example to provide an exposure imaging method.
  • the specific steps are as follows:
  • Photoelectron collection the substrate of the photosensitive detector array is negatively biased, the word line WL1 is positively biased, and the word line WL2 is negatively biased.
  • the bias signal is different from the reset phase, and the bias signal can be provided on-chip or off-chip.
  • the source/drain decoding addressing circuit is responsible for selecting the source and drain terminals of the photodetector reading transistor according to the reading order.
  • the analog-to-digital conversion circuit is responsible for converting the optoelectronic signal in the photosensitive detector into a digital signal;
  • the interface circuit is responsible for transmitting the converted digital signal to the clock signal under control of the clock signal The outside of the imaging chip.
  • the imaging chip can form a stacked imaging chip by a 3D stacking process, and the imaging chip is divided into three layers, as shown in FIG. 15, the top layer is a photosensitive array composed of photosensitive detectors, the middle layer is a word line decoding selection circuit, and the bottom layer is
  • the system includes an analog-to-digital conversion circuit, a source/drain decoding selection circuit, and an interface circuit, and the layers are interconnected by an interconnection process.

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Abstract

一种基于复合介质栅MOSFET的全局曝光光敏探测器、采用该光敏探测器构成的成像芯片以及探测方法，该光敏探测器包括由多个探测单元构成的阵列，每个探测单元包括感光晶体管（1）、电荷存储晶体管（2）和读取晶体管（3），或者包括感光晶体管、电荷转移晶体管（4）、电荷存储晶体管和读取晶体管；其中，感光晶体管用以实现光敏探测器的感光功能，电荷存储晶体管用以实现光生电荷的存储，读取晶体管用以实现信号的读取，电荷转移晶体管用以控制光生电荷的转移。该光敏探测器可实现全局曝光与快速读取，与现有浮栅CMOS工艺兼容，且任何一个像素的失效不会影响整个成像阵列的正常工作。

Description

[根据细则37.2由ISA制定的发明名称]　光敏探测器、采用其构成的成像芯片以及探测方法 技术领域
本发明涉及成像器件，尤其涉及一种应用于可见光和红外波段探测的成像探测器件的结构、工作机制和信号的读出，本发明可用于全局曝光成像。
背景技术
成像器件在各个领域都有很大的应用范围，当前最主要的成像器件是CCD和CMOS-APS。CCD较早出现，基本结构由MOS电容串联而成，在栅极加脉冲偏压后形成耗尽区用于收集光电子，随后脉冲时序将光电子以电荷包的形式读出，CCD虽然在灵敏度、分辨率、成像质量等方面都优于CMOS传感器，却存在着工艺复杂、成本高昂、功耗大等缺点，而CMOS图像传感器则与CMOS工艺兼容，因此其成本和功耗均较CCD低，CMOS-APS是通过二极管感光的，且每个探测单元都包括数个晶体管用于信号的放大和读取，通过外围译码电路进行寻址并且实现信号的读出，正因为每个探测单元中都包含若干个晶体管，造成CMOS-APS的填充系数较小，灵敏度不高，噪声较大等问题。
通过上述比较发现CCD和CMOS各有优缺点，鉴于此，已有专利CN201210442007中提出了一种基于复合介质栅MOSFET的双晶体管光敏探测器，弥补了CCD读出方式复杂以及CMOS-APS填充系数小、尺寸难以缩小的缺点，该探测器包含两个分别用于感光和读取的晶体管，但为了保持探测器中光电子数目不受读取时间前后顺序的影响，使用该探测器阵列的成像芯片必须使用机械快门，因而其不具备全局曝光功能，这就大大限制了它的应用范围，因此需要一种新结构的探测器来克服这一缺点，从而实现成像芯片全局曝光的功能。
发明内容
为了克服现有技术中存在的不足，本发明结合CCD电荷转移的原理，提出了一种改进后的新型成像器件，该器件在实现原有器件感光、光电子收集、读取和复位功能的基础上，新增了光电子转移和存储功能，可实现全局曝光，且可进一步提高像元的填充系数和量子效率。
为实现上述发明目的，本发明采用的技术方案如下：
基于复合介质栅MOSFET的全局曝光光敏探测器，包括由多个探测单元构成的阵列，每个探测单元包括感光晶体管、电荷存储晶体管和读取晶体管，感光晶体管、电荷存储晶体管和读取晶体管都形成在同一P型半导体衬底上方；所述感光晶体管用以实现光敏探测器的感光功能，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，或者在所述P型半导体衬底上方自下而上依次设有底层绝缘介质 层和控制栅极；所述电荷存储晶体管用以实现光生电荷的存储，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极；所述读取晶体管用以实现信号的读取，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，在所述P型半导体衬底靠近底层绝缘介质的一侧通过离子注入形成N型源极，在所述P型半导体衬底靠近底层绝缘介质与所述的N型源极相对的另一侧通过离子注入形成N型漏极；所述电荷存储晶体管和读取晶体管在衬底中通过浅槽隔离区隔开；所述感光晶体管的电荷耦合层和电荷存储晶体管的电荷耦合层不相连，感光晶体管的控制栅极和电荷存储晶体管的控制栅极不相连；所述电荷存储晶体管的电荷耦合层和读取晶体管的电荷耦合层相连，电荷存储晶体管的控制栅极和读取晶体管的控制栅极相连。
进一步地，在所述感光晶体管和电荷存储晶体管之间设置有电荷转移晶体管用以控制光生电荷的转移；电荷转移晶体管形成在所述P型半导体衬底上方，自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极；所述电荷转移晶体管的电荷耦合层与感光晶体管的电荷耦合层和电荷存储晶体管的电荷耦合层均不相连，电荷转移晶体管的控制栅极与感光晶体管的控制栅极和电荷存储晶体管的控制栅极均不相连。
在由多个探测单元构成的阵列中，一种方案为：所有探测单元的感光晶体管的控制栅极互连，形成字线WL1；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X；每一列探测单元的读取晶体管的源极互连，形成源线SL_X；每一列探测单元的读取晶体管的漏极互连，形成漏线DL_X，其中，X＝0、1、2、3···N。另一种方案为：所有探测单元的感光晶体管的控制栅极互连，形成字线WL1；所有探测单元的电荷转移晶体管的控制栅极互连，形成字线WL2；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X；每一列探测单元的读取晶体管的源极互连，形成源线SL_X；每一列探测单元的读取晶体管的漏极互连，形成漏线DL_X，其中，X＝0、1、2、3···N。
一种由上述全局曝光光敏探测器构成的成像芯片，包括所述探测器阵列、字线译码选址电路、源线/漏线译码选址电路、模数转换电路和接口电路；所述字线译码选址电路，按照读取顺序，用于产生每条字线在探测器的曝光、转移、读取和复位阶段的不同偏压信号；所述源线/漏线译码选址电路，按照读取顺序，用于对探测器读取晶体管的源极和漏极的选通；所述模数转换电路，用于将光敏探测器中的光电子信号转换成数字信号；所述接口电路，在时钟信号控制下用于将转换完成的数字信号传输到成像芯片外部。
一种利用上述基于复合介质栅MOSFET的全局曝光光敏探测器的探测方法，包括如下步骤：
(1)光电子收集：在感光晶体管的控制栅极上加正偏压，衬底加上负偏压，在P型衬底上形成耗尽区以收集光电子；在电荷存储晶体管的控制栅极伤加零偏压或正偏压；读取晶体管的源极和漏极接地；
(2)光电子的转移和存储：保持感光晶体管的控制栅极上所加的正偏压，在电荷存储晶体管的控制栅极上加一个正偏压，且该正偏压大于感光晶体管的控制栅极上所加的正偏压，使感光晶体管的耗尽区中收集的光电子完全转移到电荷存储晶体管的耗尽区中；光电子转移完成后，在感光晶体管的控制栅极上加与衬底相同的负偏压，这时感光晶体管中不再存在耗尽区，也不收集光电子；
(3)光电子读取：将读取晶体管的源极接地，漏极接合适的正偏压，通过在读取晶体管的控制栅极上加斜波电压，根据读取晶体管导通时斜波电压的变化值，计算得到感光晶体管收集到的光电子的数目；
(4)复位：在感光晶体管的控制栅极和电荷存储晶体管的控制栅极上加与衬底所加偏压大小一样的负偏压，读取晶体管的源极和漏极接地，光电子通过与空穴复合消失。
另一种利用上述基于复合介质栅MOSFET的全局曝光光敏探测器的探测方法，包括如下步骤：
(1)光电子收集：在感光晶体管的控制栅极上加正偏压，衬底加上负偏压，在P型衬底上形成耗尽区以收集光电子；在电荷转移晶体管的控制栅极上加负偏压，在电荷存储晶体管的控制栅极加零偏压或正偏压；读取晶体管的源极和漏极接地；
(2)光电子的转移和存储：保持感光晶体管的控制栅极上所加的正偏压，在电荷转移晶体管的控制栅极加正偏压，在电荷存储晶体管的控制栅极上加正偏压，使感光晶体管、电荷转移晶体管和电荷存储晶体管下方衬底中的电子电势逐级降低，使感光晶体管的耗尽区中收集的光电子完全转移到电荷存储晶体管的耗尽区中；光电子转移完成后，电荷转移晶体管的控制栅极加负偏压，在感光晶体管的控制栅极上加与衬底相同的负偏压，这时感光晶体管中不再存在耗尽区，也不收集光电子；
(3)光电子读取：将读取晶体管的源极接地，漏极接合适的正偏压，通过在读取晶体管的控制栅极上加斜波电压，根据读取晶体管导通时斜波电压的变化值，计算得到感光晶体管收 集到的光电子的数目；
(4)复位：在感光晶体管的控制栅极、电荷转移晶体管的控制栅极和电荷存储晶体管的控制栅极上加与衬底所加偏压大小一样的负偏压，读取晶体管的源极和漏极接地，光电子通过与空穴复合消失。
本发明的复合介质栅MOSFET光敏探测器具有下列显著优点：
(1)无需机械快门，可实现全局曝光与快速读取的功能；
(2)与现有浮栅CMOS工艺兼容，制造技术成熟，易于实现；
(3)与CCD和CMOS-APS技术相比，兼具CCD和COMS-APS的诸多优点，但又克服了它们很多缺点，例如：本发明可以通过行列译码单元读取每个探测单元的信号，这种方式区别于CCD所使用的移动电荷包进行信号读取的方式，虽然每一次曝光后都存在光电子转移过程，但光电子转移是同时进行的，且光电子转移完成后立即可以读取，因此其读取速度较CCD快；
(4)本发明由探测单元构成的阵列与周边电路整合性高，可以大幅缩小芯片体积，有助于功耗的降低，此外任何一个像素的失效不会影响整个成像阵列的正常工作。
附图说明
图1为由三个晶体管构成的基于复合介质栅MOSFET的全局曝光光敏探测器器件版图；
图2为由四个晶体管构成的基于复合介质栅MOSFET的全局曝光光敏探测器器件版图；
图3为图1沿aa’方向的剖面图；
图4为图1沿bb’方向的剖面图；
图5为图2沿aa’方向的剖面图；
图6为图2沿bb’方向的剖面图；
图7为三晶体管全局曝光光敏探测器光电子转移示意图；
图8为四晶体管全局曝光光敏探测器光电子转移示意图；
图9为光电子转移后读取晶体管阈值电压变化的示意图；
图10为全局曝光光敏探测器信号读取部分结构的等效电容模型；
图11为三晶体管全局曝光光敏探测器单元工作时序图；
图12为四晶体管全局曝光光敏探测器单元工作时序图；
图13为三晶体管全局曝光光敏探测器阵列互联结构示意图；
图14为四晶体管全局曝光光敏探测器阵列互联结构示意图；
图15为全局曝光光敏探测器构成的3D成像芯片示意图。
具体实施方式
本实施例的全局曝光光敏探测器提供两种基本结构，探测单元分别采用三个晶体管和四个晶体管。三个晶体管的结构包括感光晶体管1、电荷存储晶体管2和读取晶体管3，感光晶体管1用以实现光敏探测器的感光功能，电荷存储晶体管2用以实现光生电荷的存储，读取晶体管3用以实现信号的读取。四个晶体管的结构包括感光晶体管1、电荷转移晶体管4、电荷存储晶体管2和读取晶体管3，电荷转移晶体管4控制光生电子的转移，电荷存储晶体管2负责存储转移过来的光电子，现将具体结构描述如下：
本实施例基于复合介质栅MOSFET的三晶体(3T)管全局曝光光敏探测器，其版图如图1所示，aa’和bb’方向的截面分别如图3和4所示，每个探测器单元的构成是：在P型半导体衬底5上依次排列感光晶体管1、电荷存储晶体管2和读取晶体管3；在P型半导体衬底5上方自下而上依次设有底层绝缘介质层6、电荷耦合层7、顶层绝缘介质层8和控制栅极9；所述全局曝光光敏探测器，其感光晶体管1和电荷存储晶体管2的电荷耦合层7和控制栅极9通过刻蚀工艺刻开；所述全局曝光光敏探测器的电荷存储晶体管2和读取晶体管3的电荷耦合层7和控制栅极9均相连，通过电荷耦合方式读取电荷存储晶体管2存储的光电子信号；所述电荷存储晶体管2和读取晶体管3下方P型半导体衬底5使用浅槽隔离(STI)10隔开；对于读取晶体管3，在P型半导体衬底5靠近底层绝缘介质6的一侧通过离子注入形成N型源极11a，在P型半导体衬底5靠近底层绝缘介质6与所述的N型源极11a相对的另一侧通过离子注入形成N型漏极11b；感光晶体管1和电荷存储晶体管2的面积可以相同，也可以不相同，在电荷存储晶体管2下方P型半导体衬底5做P+离子注入形成P型重掺杂区12以增大其满阱电荷容量，减小电荷存储晶体管2面积，提高像元填充系数，同时隔离来自感光晶体管1和P型半导体衬底5中收集的电子。
本实施例基于复合介质栅MOSFET的四晶体(4T)管全局曝光光敏探测器，其版图如图2所示，aa’和bb’方向的截面分别如图5和6所示，每个探测器单元的构成是：在P型半导体衬底5上依次排列感光晶体管1、电荷转移晶体管4、电荷存储晶体管2和读取晶体管3；在P型半导体衬底5上方自下而上依次设有底层绝缘介质层6、电荷耦合层7、顶层绝缘介质层8和控制栅极9；所述全局曝光光敏探测器，其感光晶体管1，电荷转移晶体管4和电荷存储晶 体管2的电荷耦合层7和控制栅极9通过刻蚀工艺刻开；所述全局曝光光敏探测器的电荷存储晶体管2和读取晶体管3的电荷耦合层7和控制栅极9均相连，通过电荷耦合方式读取电荷存储晶体管2存储的光电子信号；所述电荷存储晶体管2和读取晶体管3下方P型半导体衬底5使用浅槽隔离(STI)10隔开；对于读取晶体管3，在P型半导体衬底5靠近底层绝缘介质6的一侧通过离子注入形成N型源极11a，在读取晶体管3一侧P型半导体衬底5靠近底层绝缘介质层6与所述的N型源极11a相对的另一侧通过离子注入形成N型漏极11b；感光晶体管1和电荷存储晶体管2的面积可以相同，也可以不相同，在电荷存储晶体管2下方P型半导体衬底做P+离子注入形成P型重掺杂区12以增大其满阱电荷容量，减小电荷存储晶体管2面积，提高像元填充系数，同时隔离来自感光晶体管1和P型半导体衬底5中收集的电子。
所述全局曝光光敏探测器的底层绝缘介质层6采用氧化硅、SiON或其它高介电常数介质，厚度为10nm左右；顶层绝缘介质层8采用氮化硅/氧化硅/氮化硅、氧化硅/氧化铝/氧化硅、氧化硅、氧化铝或其它高介电常数介质，等效氧化硅厚度为10nm-15nm；电荷耦合层7采用多晶硅、金属或其它导电材料，多晶硅厚度一般为100nm；控制栅极9采用多晶硅或其它透明导电材料；感光晶体管1衬底或衬底上方介质层至少有一处为对所探测光波长透明或半透明的窗口，本实施例中，从底层绝缘介质层6向上到控制栅极9，设为对探测器探测光波长透明或半透明的窗口。为了提高探测器量子效率，感光晶体管上方顶层绝缘介质8和电荷耦合层7可以去掉，直接在底层绝缘介质层6上方制作控制栅极9。为了提高光敏探测器的量子效率，另一种方法是去除感光晶体管1衬底上方顶层绝缘介质层8和电荷耦合层7，直接在底层绝缘介质层6上方制作控制栅极9，这样做的目的是减少入射光在衬底上方被介质吸收的比例，尤其是入射光中的短波长成份。
本实施例基于复合介质栅MOSFET的全局曝光光敏探测器阵列的制备工艺流程：首先进行有源区定义和浅槽隔离(STI)10，一个像元包含两个有源区，分别为读取晶体管3的有源区，以及感光晶体管1、电荷转移晶体管4、电荷存储晶体管2的有源区，这两个有源区之间用浅槽隔离(STI)10进行隔离；然后进行MOSFET单元的构造，主要形成底层绝缘介质层6、电荷耦合层7、顶层绝缘介质层8、控制栅极9和晶体管的源漏区(11a、11b)；最后进行的工艺包括金属互连线的制作、钝化层的制作并进行晶圆表面平坦化处理。
本实施例基于复合介质栅MOSFET的全局曝光光敏探测器对光信号的探测、光电子的收集、光电子的转移和存储的流程如下：
光电子收集：
在感光晶体管1的控制栅极和衬底之间加一合适的正偏压脉冲，在P型半导体衬底5表面会形成耗尽区，耗尽区的深度可由正偏压脉冲大小来调节；当入射光子的能量大于半导体材料(硅)的禁带宽度，入射光在P型半导体中激发产生电子-空穴对，位于耗尽区的电子-空穴对在耗尽区中电场的作用下分离，光电子被收集在P型半导体衬底和底层绝缘介质层的界面处，空穴被排斥到衬底中；
光电子转移和存储：
对于三晶体管(3T)全局曝光光敏探测器：在电荷存储晶体管2的控制栅极加一大于感光晶体管1控制栅极所加电压(2-5V)的正偏压，感光晶体管1耗尽区中的光电子在热扩散、自感应漂移和边缘电场等机制的作用下向电荷存储晶体管2耗尽区转移，如图7所示，转移完成后，在感光晶体管1的控制栅极加一与P型衬底所加电压相同的负偏压，感光晶体管1耗尽区消失，停止光电子的收集。
对于四晶体管(4T)全局曝光光敏探测器：在电荷存储晶体管2控制栅加一个大于感光晶体管1控制栅极所加电压(2-5V)的正偏压，在电荷转移晶体管4上加一个正偏压，使其下方半导体衬底的势垒高度降低，从而使感光晶体管1、电荷转移晶体管4和电荷存储晶体管2下方半导体衬底中电子电势逐级降低，光电子从感光晶体管1转移到电荷存储晶体管2，如图8所示，转移完成后，降低电荷转移晶体管4控制栅所加的偏压，从而拉高电荷转移晶体管4下方衬底的电子电势，此时感光晶体管1可以进行下一帧曝光；
本实施例基于复合介质栅MOSFET的全局曝光光敏探测器对光电子信号的读取方法如下：
首先扫描得到黑暗情况下读取晶体管的阈值电压，方法为：在衬底加一负偏压(-5V-0V)，读取晶体管3的源极11a接地，漏极11b接一正偏压(0.1V-0.2V)，在读取晶体管3上方控制栅极(与电荷存储晶体管2共用)加一从0V到7V的扫描电压，源漏导通时控制栅极所加的电压即视为读取晶体管3的阈值电压V th1，该值应为一固定值；
收集存储在电荷存储晶体管2耗尽区中的光电子，通过电荷耦合的机理影响电荷耦合层的电势，为了保持耗尽区中的光电子，电荷存储晶体管2上方的控制栅加有正偏压(2V-7V)，读取时，读取晶体管3源极11a接地，漏极11b接一正偏压(0.1V-0.2V)，此时读取晶体管3源极和漏极不导通，接着在电荷存储晶体管2上方的控制栅极(与读取晶体管共用)加一斜波电压，斜波电压的起始值等于之前加在电荷存储晶体管2上的正偏压值，斜波电压的变化范围为(1V-2V)具体值由器件的灵敏度来决定，在斜波电压上升的过程中，读取晶体管3的 源极和漏极逐渐开始导通，导通时的斜波电压的值视为曝光后读取晶体管3的阈值电压V th2。
将曝光后读取晶体管3的阈值电压减去黑暗条件下读取晶体管3的阈值电压即为阈值电压的变化值ΔV th，如图9所示，由该值通过计算可以得到电荷存储晶体管2耗尽区中存储的光电子数目。
为了提高光敏探测器的量子效率，一种方法是增大像元的填充系数，在不增大像元面积的前提下增大填充系数，需要增大感光晶体管1的受光面面积，同时减小电荷存储晶体管2面积，为了防止电荷转移不完全，需要保证电荷存储晶体管2的满阱电荷容量大于或等于感光晶体管1的满阱电荷容量，可以通过以下方法增大电荷存储晶体管2的满阱电荷容量：在电荷存储晶体管2的P型半导体衬底5中通过P+离子注入形成P+区12，这样可以进一步增大感光晶体管1的面积；需要注意的是，由于该光敏探测器是通过电荷耦合的作用来读取电荷存储晶体管2耗尽区中存储的光电子数，这意味缩小电荷存储晶体管2的面积，会导致器件的灵敏度变差，因为器件读取晶体管3阈值电压的变化量取决于电容C 1、C 2和C ch，随着电荷存储晶体管2的面积减小，C 1和C ch减小，造成阈值电压随V s的变化减小，其中C 1表示电荷存储晶体管氧化层电容，C 2表示电荷存储晶体管及读取晶体管电荷存储层与控制栅之间的电容，C ch表示读取晶体管氧化层电容，读取部分结构的等效电容如图10所示。
三晶体管(3T)全局曝光光敏探测器光电转换过程：如图11所示的是器件工作时序图，曝光过程中，在P型半导体衬底5加一个(-5-0V)的负偏压脉冲，感光晶体管1的控制栅极cg_exp加一个(0-2V)的正偏压脉冲，这样感光晶体管1衬底形成耗尽区，当入射光子到达耗尽区后，若光子能量hv>半导体禁带宽度E g，入射光子被半导体吸收并激发产生一个电子空穴对，由于耗尽区中存在着由P型半导体衬底5与底层绝缘介质层6界面处指向P型半导体衬底5的电场，电子空穴对被分离，电子被收集在界面处同时空穴被排斥到衬底中，随着光电子的聚集，耗尽区深度减小。
三晶体管(3T)全局曝光光敏探测器光电子转移和存储过程：该器件由于其没有电荷转移晶体管4，电荷存储晶体管2将发挥电荷转移的作用，结合图11的时序图可知，电荷存储晶体管2的控制栅cg_sto加一大于cg_exp的正偏压，使电荷存储晶体管2势阱中光电子的电势低于感光晶体管1光电子的电势，光电子将在热扩散、自感应漂移和边缘电场等机制的作用下向电荷存储晶体管2耗尽区中转移并存储。
四晶体管(4T)全局曝光光敏探测器光电子收集过程：如图12所示的是器件工作时序图，曝光过程中，在P型半导体衬底5加一个(-5-0V)的负偏压脉冲，感光晶体管1的控制栅极 cg_exp加一个(0-2V)的正偏压脉冲，这样感光晶体管1衬底下面形成耗尽区，当入射光子到达耗尽区后，若光子能量hv>半导体禁带宽度E g，入射光子被半导体吸收并激发产生一个电子空穴对，由于耗尽区中存在着由P型半导体衬底5与底层绝缘介质层6界面处指向P型半导体衬底5的电场，电子空穴对被分离，电子被收集在界面处同时空穴被排斥到衬底中，随着光电子的聚集，耗尽区深度减小。
四晶体管(4T)全局曝光光敏探测器光电子转移过程：由于增加了电荷转移晶体管4，器件曝光和信号读取过程可以同时进行，光电子转移时，电荷转移晶体管4的控制栅极cg_tra加一正偏压，电荷存储晶体管2的控制栅cg_sto加一大于cg_tra所加的正偏压，感光晶体管1、电荷转移晶体管4和电荷存储晶体管2下方衬底产生阶梯状降低的电子电势，如图8所示，光电子向电荷存储晶体管2侧的耗尽区转移，转移完成后，电荷转移晶体管4的控制栅极cg_tra加与衬底相同的负偏压，拉高电荷转移晶体管4下方电子电势，此时，可以对信号进行读取。
光电子读取过程：光敏探测器光电子转移完成后，并不需要像CCD那样再将电荷包挨个转移出去，而是采用类似CMOS-APS信号读出的方式来读取光信号；选中一个探测单元，由于光电子被收集在电荷存储晶体管2的耗尽区中，这部分电荷通过改变表面电势来影响读取晶体管3的阈值电压，由于设计中采用了10nm厚的底层绝缘介质层6，且栅衬之间的偏压差控制在8V以内，光电子通过隧穿注入到电荷耦合层7是可被忽略的，因而整个工作过程中电荷耦合层7始终是呈电中性的。
如图10所示，假设电荷存储晶体管2的电荷耦合层7电势为V f，衬底表面电势为V s，控制栅极所加偏压为V cg，电荷耦合层7与电荷存储晶体管2表面之间电容为C 1，电荷存储晶体管2耗尽区电容为C d，电荷耦合层7与控制栅极9之间电容为C 2，STI区10上方电容为C STI，电荷耦合层7与读取晶体管3沟道电容为C ch，针对电荷耦合层7节点，忽略电子注入的影响，电荷耦合层7中的电荷量为常数Q f，则有：
(V f-V s)C 1+(V f-V cg)C 2+(V f-V g)(C STI+C ch)＝Q f      (1)
由于曝光时V cg和V g为常数，对上式左右两边求导得：
Figure PCTCN2018080182-appb-000001
针对V s所在节点，假设其存储光电子的数量为Q，则有：
C d(V s-V g)+C 1(V s-V f)＝Q      (3)
上式两边求导得：
ΔQ＝(C d+C 1)ΔV s-C 1ΔV f       (4)
将式(4)代入式(2)可得：
Figure PCTCN2018080182-appb-000002
令
Figure PCTCN2018080182-appb-000003
则：
Figure PCTCN2018080182-appb-000004
上式建立起了电荷存储晶体管2和读取晶体管3电荷耦合层7电势改变量与电荷存储晶体管2耗尽区中光电子数目的关系，为了提高器件工作的灵敏度，需要减小C的值，为此需要增大C 1或者减小C 2、C STI、C ch、C d。增大C 1可以通过减小电荷存储晶体管2底层绝缘介质层6的厚度，增大电荷存储晶体管2的面积或使用更大介电常数的介质材料来实现，但由于增大电荷存储晶体管2面积的代价是像元填充系数的减小，因此不能通过一味增大电荷存储晶体管2的面积来提高器件灵敏度；减小C ch可以通过增大读取晶体管3上方底层绝缘介质层的厚度或减小读取晶体管3栅极的面积来实现；减小C 2可以增大顶层绝缘介质层8的厚度。
得到了电荷存储晶体管2和读取晶体管3电荷耦合层7电势的变化值ΔV f，由于该电压变化是从电荷耦合层7的角度考虑的，但测量器件阈值电压时是在电荷存储晶体管2和读取晶体管3的控制栅极上施加电压，因此需要将电荷耦合层7电势变化转换成控制栅极上偏压的变化，转换公式为式(7)。
Figure PCTCN2018080182-appb-000005
由上所述可以通过测量ΔV cg来推算光电子数目；为了得到ΔV cg，先通过直接扫描的方式得到黑暗条件下读取晶体管3的阈值电压，记为V cg1；通过斜波电压扫描得到曝光后读取晶体管3的阈值电压，方法如下：由于事先已经在控制栅极加有V cg2，因此斜波电压起始值设为V cg2，需要注意的是，该电压值不能大于读取晶体管3的阈值电压(读取晶体管和电荷存储晶体管共用控制栅极)，斜波电压从V cg2逐渐增大，当达到V cg2+ΔV后读取晶体管3导通，则V cg2+ΔV–V cg1为曝光前后读取晶体管3阈值电压的变化值ΔV cg。
复位过程：当感光晶体管1、电荷转移晶体管4、电荷控制晶体管2的控制栅极加上适当的负偏压(与衬底所加一样或稍小于衬底所加负偏压)，读取晶体管3源极11a和漏极11b接 地，积累在耗尽区中的光电子通过复合作用逐渐减少直至消失。
上述多个探测单元组成阵列形成探测器阵列的架构：
图13给出了三晶体管(3T)全局曝光光敏探测器阵列的等效电路图，虚线框表示一个探测单元，探测阵列中每个探测单元的感光晶体管的控制栅极互连，形成字线WL1；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X(X＝0、1、2、3···N)；每一列探测单元读取晶体管的源极互连，形成源线SL_X(X＝0、1、2、3···N)；每一列探测单元读取晶体管的漏极互连，形成漏线DL_X(X＝0、1、2、3···N)。
图14给出了四晶体管(4T)全局曝光光敏探测器阵列的等效电路图，虚线框表示一个探测单元，探测阵列中每个探测单元的感光晶体管的控制栅极互连，形成字线WL1；每个探测单元的电荷转移晶体管的控制栅极互连，形成字线WL2；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X(X＝0、1、2、3···N)；每一列探测单元读取晶体管的源极互连，形成源线SL_X(X＝0、1、2、3···N)；每一列探测单元读取晶体管的漏极互连，形成漏线DL_X(X＝0、1、2、3···N)。
本实施例以四晶体管的全局曝光光敏探测器阵列为例，提供一种曝光成像方法，具体步骤为：
光电子收集：光敏探测器阵列的衬底加负偏压，字线WL1加正电偏压，字线WL2加负偏压，每一行的字线WL3_X(X＝0、1、2、3···N)加零偏压或正偏压，所有源线SL_X(X＝0、1、2、3···N)和漏线DL_X(X＝0、1、2、3···N)接地；
光电子转移和存储：字线WL2和每一行的字线WL3_X(X＝0、1、2、3···N)加正偏压，光电子转移完成后，字线WL1和字线WL2加负偏压，所有源线SL_X(X＝0、1、2、3···N)和漏线DL_X(X＝0、1、2、3···N)接地；
光电子读取：保持衬底、字线WL1和字线WL2所加的偏压，被选中读取的探测器所在列的源线SL_X(X＝0、1、2、3···N)接地，漏线DL_X(X＝0、1、2、3···N)加正偏压，在被选中读取的探测器所在行的字线WL3_X(X＝0、1、2、3···N)加斜波电压；
复位：字线WL1和字线WL2加与衬底相同的负偏压，每一行的字线WL3_X(X＝0、1、2、3···N)加与衬底相同的负偏压，所有源线SL_X(X＝0、1、2、3···N)和漏线DL_X(X＝0、1、2、3···N)接地；
本实施例还提供一种成像芯片架构：
成像芯片包括基于复合介质栅MOSFET的全局曝光光敏探测器阵列(以四晶体管的结构为例)、字线译码选址电路，源线/漏线译码选址电路，模数转换电路和接口电路；字线译码选址电路，按照读取顺序，负责产生字线WL1，字线WL2和字线WL3_X(X＝0、1、2、3···N)在曝光、转移、读取和复位阶段不同的偏压信号，偏压信号可以片上提供也可以片外提供；源线/漏线译码选址电路，按照读取顺序，负责光敏探测器读取晶体管源端和漏端的选通，以便后续模数转换电路对光电子信号进行转换；模数转换电路，负责将光敏探测器中的光电子信号转换成数字信号；接口电路，在时钟信号控制下负责将转换完成的数字信号传输到成像芯片外部。
该成像芯片可以通过3D堆叠工艺形成堆栈式成像芯片，成像芯片分为三层结构，如图15所示，顶层为由光敏探测器构成的感光阵列，中间层为字线译码选择电路，底层包括模数转换电路、源/漏译码选择电路和接口电路，层与层之间通过互连工艺互连。

Claims (10)

  1. 基于复合介质栅MOSFET的全局曝光光敏探测器，包括由多个探测单元构成的阵列，其特征在于：每个探测单元包括感光晶体管、电荷存储晶体管和读取晶体管，感光晶体管、电荷存储晶体管和读取晶体管都形成在同一P型半导体衬底上方；
    所述感光晶体管用以实现光敏探测器的感光功能，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，或者在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层和控制栅极；
    所述电荷存储晶体管用以实现光生电荷的存储，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极；
    所述读取晶体管用以实现信号的读取，其结构为：在所述P型半导体衬底上方自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，在所述P型半导体衬底靠近底层绝缘介质的一侧通过离子注入形成N型源极，在所述P型半导体衬底靠近底层绝缘介质与所述的N型源极相对的另一侧通过离子注入形成N型漏极；
    所述电荷存储晶体管和读取晶体管在衬底中通过浅槽隔离区隔开；
    所述感光晶体管的电荷耦合层和电荷存储晶体管的电荷耦合层不相连，感光晶体管的控制栅极和电荷存储晶体管的控制栅极不相连；
    所述电荷存储晶体管的电荷耦合层和读取晶体管的电荷耦合层相连，电荷存储晶体管的控制栅极和读取晶体管的控制栅极相连。
  2. 根据权利要求1所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征在于，在所述感光晶体管和电荷存储晶体管之间设置有电荷转移晶体管用以控制光生电荷的转移；电荷转移晶体管形成在所述P型半导体衬底上方，自下而上依次设有底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极；所述电荷转移晶体管的电荷耦合层与感光晶体管的电荷耦合层和电荷存储晶体管的电荷耦合层均不相连，电荷转移晶体管的控制栅极与感光晶体管的控制栅极和电荷存储晶体管的控制栅极均不相连。
  3. 根据权利要求1或2所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征在于，所述感光晶体管控制栅极面和衬底至少有一处为探测器所探测光波长透明或半透明窗口。
  4. 根据权利要求1或2所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征在于，所述电荷存储晶体管的衬底通过离子注入掺杂形成P+区。
  5. 根据权利要求1或2所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征是，所述电荷耦合层采用多晶硅、金属或半导体材料；所述控制栅极采用多晶硅、金属或透明的导电电极；所述底层绝缘介质层的材料采用氧化硅或SiON；所述顶层绝缘介质层的材料采用氮化硅/氧化硅/氮化硅、氧化硅/氧化铝/氧化硅、氧化硅或氧化铝。
  6. 根据权利要求1所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征在于，由多个探测单元构成的阵列中，所有探测单元的感光晶体管的控制栅极互连，形成字线WL1；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X；每一列探测单元的读取晶体管的源极互连，形成源线SL_X；每一列探测单元的读取晶体管的漏极互连，形成漏线DL_X，其中，X＝0、1、2、3···N。
  7. 根据权利要求2所述的基于复合介质栅MOSFET的全局曝光光敏探测器，其特征在于，由多个探测单元构成的阵列中，所有探测单元的感光晶体管的控制栅极互连，形成字线WL1；所有探测单元的电荷转移晶体管的控制栅极互连，形成字线WL2；每一行探测单元的读取晶体管和电荷存储晶体管共用的控制栅极互连，形成字线WL3_X；每一列探测单元的读取晶体管的源极互连，形成源线SL_X；每一列探测单元的读取晶体管的漏极互连，形成漏线DL_X，其中，X＝0、1、2、3···N。
  8. 如权利要求6或7所述的基于复合介质栅MOSFET的全局曝光光敏探测器构成的成像芯片，其特征在于，成像芯片包括所述探测器阵列、字线译码选址电路、源线/漏线译码选址电路、模数转换电路和接口电路；
    所述字线译码选址电路，按照读取顺序，用于产生每条字线在探测器的曝光、转移、读取和复位阶段的不同偏压信号；
    所述源线/漏线译码选址电路，按照读取顺序，用于对探测器读取晶体管的源极和漏极的选通；
    所述模数转换电路，用于将光敏探测器中的光电子信号转换成数字信号；
    所述接口电路，在时钟信号控制下用于将转换完成的数字信号传输到成像芯片外部。
  9. 如权利要求1所述的基于复合介质栅MOSFET的全局曝光光敏探测器的探测方法，其特征在于，包括如下步骤：
    (1)光电子收集：在感光晶体管的控制栅极上加正偏压，衬底加上负偏压，在P型衬底上形成耗尽区以收集光电子；在电荷存储晶体管的控制栅极伤加零偏压或正偏压；读取晶体管 的源极和漏极接地；
    (2)光电子的转移和存储：保持感光晶体管的控制栅极上所加的正偏压，在电荷存储晶体管的控制栅极上加一个正偏压，且该正偏压大于感光晶体管的控制栅极上所加的正偏压，使感光晶体管的耗尽区中收集的光电子完全转移到电荷存储晶体管的耗尽区中；光电子转移完成后，在感光晶体管的控制栅极上加与衬底相同的负偏压，这时感光晶体管中不再存在耗尽区，也不收集光电子；
    (3)光电子读取：将读取晶体管的源极接地，漏极接合适的正偏压，通过在读取晶体管的控制栅极上加斜波电压，根据读取晶体管导通时斜波电压的变化值，计算得到感光晶体管收集到的光电子的数目；
    (4)复位：在感光晶体管的控制栅极和电荷存储晶体管的控制栅极上加与衬底所加偏压大小一样的负偏压，读取晶体管的源极和漏极接地，光电子通过与空穴复合消失。
  10. 如权利要求2所述的基于复合介质栅MOSFET的全局曝光光敏探测器的探测方法，其特征在于，包括如下步骤：
    (1)光电子收集：在感光晶体管的控制栅极上加正偏压，衬底加上负偏压，在P型衬底上形成耗尽区以收集光电子；在电荷转移晶体管的控制栅极上加负偏压，在电荷存储晶体管的控制栅极加零偏压或正偏压；读取晶体管的源极和漏极接地；
    (2)光电子的转移和存储：保持感光晶体管的控制栅极上所加的正偏压，在电荷转移晶体管的控制栅极加正偏压，在电荷存储晶体管的控制栅极上加正偏压，使感光晶体管、电荷转移晶体管和电荷存储晶体管下方衬底中的电子电势逐级降低，使感光晶体管的耗尽区中收集的光电子完全转移到电荷存储晶体管的耗尽区中；光电子转移完成后，电荷转移晶体管的控制栅极加负偏压，在感光晶体管的控制栅极上加与衬底相同的负偏压，这时感光晶体管中不再存在耗尽区，也不收集光电子；
    (3)光电子读取：将读取晶体管的源极接地，漏极接合适的正偏压，通过在读取晶体管的控制栅极上加斜波电压，根据读取晶体管导通时斜波电压的变化值，计算得到感光晶体管收集到的光电子的数目；
    (4)复位：在感光晶体管的控制栅极、电荷转移晶体管的控制栅极和电荷存储晶体管的控制栅极上加与衬底所加偏压大小一样的负偏压，读取晶体管的源极和漏极接地，光电子通过与空穴复合消失。
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CN110677604B (zh) * 2019-10-12 2024-02-20 南京威派视半导体技术有限公司 电压域全局曝光图像传感器的像素单元及其控制方法
CN110707116B (zh) * 2019-10-17 2021-08-24 德淮半导体有限公司 图像传感器单元
CN111147772B (zh) * 2019-12-10 2022-04-22 南京威派视半导体技术有限公司 基于复合介质栅双晶体管光敏探测器的曝光方法及其电路
CN111540759B (zh) * 2020-05-09 2023-05-05 南京大学 基于复合介质栅双晶体管光敏探测器的积分泄放电路
CN111540758B (zh) * 2020-05-09 2023-06-06 南京大学 基于复合介质栅横向耗尽的光敏探测器及其方法
CN111554699B (zh) * 2020-05-13 2023-05-09 南京大学 基于复合介质栅结构的光敏探测单元、探测器及其方法
CN113990890B (zh) * 2021-10-25 2024-04-09 南京大学 基于复合介质栅pn结的全局快门光敏探测器及工作方法
CN114071034B (zh) * 2021-11-10 2022-08-19 南京大学 基于开关电容的复合介质栅双晶体管像素读出电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102938409A (zh) * 2012-11-07 2013-02-20 南京大学 基于复合介质栅mosfet的双晶体管光敏探测器及其信号读取办法
CN104091813A (zh) * 2014-06-13 2014-10-08 南京大学 一种基于闪存工艺的三维图像传感器及其操作方法
CN104900667A (zh) * 2015-05-06 2015-09-09 南京大学 一种基于复合介质栅mosfet的多模态双晶体管光敏探测器
CN107180844A (zh) * 2017-06-26 2017-09-19 南京大学 一种复合介质栅电容耦合变增益光敏探测器及其工作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834387B2 (en) * 2008-04-10 2010-11-16 International Business Machines Corporation Metal gate compatible flash memory gate stack
US8698061B2 (en) * 2009-12-10 2014-04-15 Luxima Technology LLC Image sensors, methods, and pixels with storage and transfer gates
CN102544039B (zh) * 2012-01-09 2013-10-02 南京大学 基于复合介质栅mosfet光敏探测器源漏浮空编程方法
CN102916025B (zh) * 2012-10-12 2014-12-10 南京邮电大学 一种固态成像探测器
CN103227184B (zh) * 2013-04-11 2015-09-23 南京大学 基于复合介质栅结构像素单元的成像阵列及其曝光操作方法
JP6362527B2 (ja) * 2014-12-05 2018-07-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9859422B2 (en) * 2015-05-28 2018-01-02 Sandisk Technologies Llc Field effect transistor with elevated active regions and methods of manufacturing the same
CN105742296B (zh) * 2016-03-31 2019-05-07 上海天马有机发光显示技术有限公司 一种阵列基板及其制备方法、显示面板和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102938409A (zh) * 2012-11-07 2013-02-20 南京大学 基于复合介质栅mosfet的双晶体管光敏探测器及其信号读取办法
CN104091813A (zh) * 2014-06-13 2014-10-08 南京大学 一种基于闪存工艺的三维图像传感器及其操作方法
CN104900667A (zh) * 2015-05-06 2015-09-09 南京大学 一种基于复合介质栅mosfet的多模态双晶体管光敏探测器
CN107180844A (zh) * 2017-06-26 2017-09-19 南京大学 一种复合介质栅电容耦合变增益光敏探测器及其工作方法

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