WO2018018762A1 - 基于复合介质栅的双器件光敏探测单元、探测器及其方法 - Google Patents

基于复合介质栅的双器件光敏探测单元、探测器及其方法 Download PDF

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WO2018018762A1
WO2018018762A1 PCT/CN2016/102679 CN2016102679W WO2018018762A1 WO 2018018762 A1 WO2018018762 A1 WO 2018018762A1 CN 2016102679 W CN2016102679 W CN 2016102679W WO 2018018762 A1 WO2018018762 A1 WO 2018018762A1
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gate
composite dielectric
control gate
semiconductor substrate
layer
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PCT/CN2016/102679
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English (en)
French (fr)
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马浩文
闫锋
卜晓峰
沈忱
张丽敏
杨程
毛成
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南京大学
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Priority to US16/320,908 priority Critical patent/US10868075B2/en
Publication of WO2018018762A1 publication Critical patent/WO2018018762A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses

Definitions

  • the invention relates to an imaging detector device, in particular to a structure, a working mechanism and a signal reading of an imaging detector device in the infrared, visible light to ultraviolet bands, and is a dual device photosensitive detecting unit and detector based on a composite dielectric grid. Its signal reading method.
  • Imaging detectors have great applications in various fields such as military and civilian use.
  • the main imaging detectors currently developed are CCD and CMOS-APS.
  • CCD appeared earlier, the technology is relatively mature, its basic structure is a series of MOS capacitors in series, through the voltage pulse timing on the capacitor to control the generation and change of the semiconductor surface potential well, thereby realizing the storage and transfer readout of the photogenerated charge signal, also positive Because of this signal transfer characteristic, the charge transfer speed is very limited, so the imaging speed is not high, and because the capacitor is connected in series, a capacitor has problems affecting the transmission of the entire line of signals, so the process requirements are extremely high, and the yield and cost are insufficient. ideal.
  • Each pixel of CMOS-APS is composed of a diode and a transistor.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS-APS consists of multiple transistors and one photodiode (including amplifier and A/D conversion circuit), so that the photosensitive area of each pixel occupies only a small surface area of the pixel itself, and the sensitivity and resolution are relatively small.
  • CMOS-APS has achieved rapid development along with the continuous progress of CMOS technology in recent years, and has shown great prospects.
  • An imaging detector based on a CMOS process and capable of overcoming the shortcomings of conventional CMOS-APS is of great significance.
  • An ideal imaging device can be an array architecture consisting of a CCD pixel + CMOS-APS. This architecture has been considered for storage devices.
  • the floating gate memory device structure currently envisaged is to add a gate between the control gate and the channel of the conventional MOS structure, which is surrounded by a dense oxide and is not connected to the outside, and is called a floating gate.
  • Chinese patent CN96122772.9 "Semiconductor memory device and its manufacturing method” discloses a memory device using a floating gate structure, which is provided with a control gate on the floating gate, and uses a tunneling effect of electrons under a certain electric field. Electrons are injected into the floating gate in the dense oxide layer. The imaging device can be fabricated directly using this effect, see patent WO2010/094233.
  • Chinese patent CN201210442007.X proposes a two-transistor scheme to solve the crosstalk problem between optoelectronic signals, but in fact, the imaging principle of the imaging device still utilizes the tunneling effect of electrons. The problem of low low light response, significant saturation effect and low detection efficiency cannot be solved.
  • the object of the present invention is to propose a dual device photosensitive detector based on a composite dielectric grid.
  • Each detecting unit of the detector comprises a composite dielectric gate MOS-C portion and a composite dielectric gate MOSFET portion, which is sensitized by the composite dielectric gate MOS-C portion, and the optical signal obtained by the MOS-C partial photosensitive is coupled by charge coupling.
  • the composite dielectric gate MOSFET portion is thus read.
  • Another object of the present invention is to provide a method of detecting the photosensitive detector.
  • the photosensitive detector is sensitized and read using two different devices, which can well detect the optical signal, so that it has better low light response and linearity, and there is no obvious saturation phenomenon. Dynamic range and relatively high quantum efficiency.
  • a dual device photosensitive detecting unit based on a composite dielectric gate includes a composite dielectric gate MOS-C portion having a photosensitive function and a composite dielectric gate MOSFET portion having a read information function, and the two portions are formed over the same P-type semiconductor substrate
  • the composite dielectric gate MOS-C portion includes a charge coupled layer, a first top dielectric layer, and a first control gate sequentially stacked over the P-type semiconductor substrate, wherein the charge coupled in the P-type semiconductor substrate An N-type implant layer is disposed under the layer;
  • the composite dielectric gate MOSFET portion includes an underlying dielectric layer sequentially stacked over the P-type semiconductor substrate, a charge coupled layer, a second top dielectric layer and a second control gate, wherein an N-type source region and an N-type drain region are provided on a side of the P-type semiconductor substrate and adjacent to the underlying dielectric layer, a threshold adjustment implantation region is disposed in the P-type semiconductor substrate and under the underlying dielectric layer; wherein the
  • the composite dielectric gate MOS-C portion further includes a first underlying dielectric layer disposed over the P-type semiconductor substrate and below the charge coupled layer.
  • the first underlying dielectric layer is connected to the underlying dielectric layer of the composite dielectric gate MOSFET portion as a unitary structure or as two separate portions, the first top dielectric layer and the second top dielectric layer being connected as a unitary structure or Two parts that are independent of each other.
  • the first control gate and the second control gate are connected in a single structure. Or the first control gate and the second control gate are side-by-side dual gate structures, wherein the first control gate is a photosensitive control gate, and the second control gate is a read control gate.
  • the area of the P-type semiconductor substrate and the charge coupled layer of the composite dielectric gate MOS-C portion is larger than the area of the P-type semiconductor substrate and the charge coupled layer of the composite dielectric gate MOSFET portion.
  • the material of the charge coupling layer is one of polysilicon, metal or other electronic conductor; the material of the first control gate or the second control gate is one of polysilicon, metal or transparent conductive electrode;
  • the material of the underlying dielectric layer is one of silicon oxide, SiON or other high dielectric constant medium;
  • the material of the first top dielectric layer or the second top dielectric layer is silicon oxide/silicon nitride/silicon oxide, silicon oxide / Alumina / silicon oxide, silicon oxide, aluminum oxide or other high dielectric constant dielectric material.
  • the dual device photosensitive detector based on the composite dielectric grid is formed by arraying a plurality of the two-device photosensitive detecting units on the same P-type semiconductor substrate, wherein the composite dielectric gate is disposed between the MOS-C portions a deep trench isolation region and a P+ implant region for separating the respective photosensitive detecting units; the composite dielectric gate MOSFET portion is interconnected by a NOR architecture of the flash memory, and the second control gate is connected and the N-type drain region is connected The wires are used perpendicular to each other for address reading of XY values, and the common N-type source region is grounded during exposure.
  • the invention utilizes a detection method of a dual device photosensitive detector to collect, store and read photosensitive photoelectrons through the composite dielectric gate MOS-C portion and the composite dielectric gate MOSFET portion, and the composite dielectric gate MOS-C portion is exposed during the exposure process.
  • the potential variation of the charge coupled layer brought in can be measured by the composite dielectric gate MOSFET portion; the P-type semiconductor substrate of the composite dielectric gate MOS-C portion is photosensitive, and then photoelectrons are coupled to the charge coupled layer, the photoelectron signal Reading is performed through the composite dielectric gate MOSFET portion.
  • the invention realizes photosensitive detection by using two components of the composite dielectric gate MOS-C part and the MOSFET part respectively
  • the sensitization and reading functions of the photodetector separate the sensitizing and reading functions of the photodetector. Its features and advantages include:
  • the sensitization working principle of the detector is similar to CCD, which eliminates the tunneling process and avoids the loss of electrons during tunneling.
  • the MOS-C portion of the composite dielectric gate and the substrate of the MOSFET portion are separated by shallow trench isolation and P+ type implantation, which can prevent the photocharge collected by the MOS-C portion from the source in the MOSFET portion.
  • the region and drain region are missing. Photoelectrons generated by photons entering the depletion region are almost entirely collected at the channel, and thus have high quantum efficiency.
  • FIG. 1 is a schematic structural view of a portion of a detector photosensitive MOS-C
  • FIG. 2 is a schematic structural view of a portion of another detector photosensitive MOS-C;
  • FIG. 3 is a schematic structural view of a portion of a detector read MOSFET
  • FIG. 4 is a schematic diagram of a pixel structure of a detector unit
  • Figure 5 is a block diagram of another detector unit
  • Figure 6 is a pixel layout of the detector unit
  • FIG. 7 is a schematic diagram 1 of a pixel structure of a detector double gate structure unit
  • FIG. 8 is a schematic diagram 2 of a pixel structure of a detector double gate structure unit
  • Figure 10 is a layout of the detector array
  • Figure 11 is a schematic diagram of isolation between photosensitive MOS-C portions
  • Figure 12 is a schematic diagram 2 of the isolation between the photosensitive MOS-C portions
  • FIG. 13 is a schematic view showing a color filter and a microlens disposed on a unit pixel
  • FIG. 14 is a schematic diagram of photoelectron voltage application for collecting and storing pixels of a detector unit
  • Figure 15 is an equivalent circuit diagram 1 of the detector unit pixel
  • Figure 16 is an equivalent circuit diagram 2 of the detector unit pixel
  • 17 is an equivalent circuit diagram 1 of a pixel of a detector double gate structure unit
  • Figure 18 is a second embodiment of a pixel double gate structure unit pixel equivalent circuit
  • Figure 19 is a circuit diagram of the detector readout amplification method one
  • Figure 20 is a circuit diagram of the second method of detector readout amplification.
  • each detector unit pixel is composed of a composite dielectric gate MOS-C portion for sensitization and a
  • the composite dielectric gate MOSFET portion for reading is realized by using the composite dielectric gate MOS-C portion to realize the photosensitive function, and the composite dielectric gate MOSFET portion is used for the reading function, and the composite dielectric gate MOS-C portion and the MOSFET portion are formed on the same substrate.
  • the composite dielectric gate MOS-C portion and the MOSFET portion are formed on the same substrate.
  • the P-type semiconductor material Above the P-type semiconductor material.
  • the structure of the composite dielectric gate MOS-C portion for sensing is as shown in FIG. 1 and includes:
  • an N-type implant may be formed by ion implantation doping to lower the photocharge storage position away from the interface between the P-type semiconductor substrate and the top dielectric layer.
  • FIG. 2 Another structure of the composite dielectric gate MOS-C portion for sensitization is shown in FIG. 2, and includes:
  • a P-type semiconductor substrate is sequentially provided with a charge coupling layer, a top dielectric layer and a control gate;
  • an N-type implant may be formed by ion implantation doping to lower the photocharge storage position away from the interface between the P-type semiconductor substrate and the top dielectric layer.
  • the structure of the composite dielectric gate MOSFET portion for reading is as shown in FIG. 3, and includes:
  • an N-type source region and an N-type drain region are formed by ion implantation doping to realize reading of the photosensitive detector signal;
  • a threshold adjustment implant formed by ion implantation doping to adjust the threshold voltage of the composite dielectric gate MOSFET portion.
  • connection method of the MOS-C portion of the composite dielectric gate and the MOSFET partial charge-coupled photodetector is as shown in FIG. 4 and FIG. 5, and the MOS-C portion of the composite dielectric gate and the MOSFET portion are connected through the same charge-coupling layer and the substrate, thereby The number of photocharges obtained by sensitization in the MOS-C portion can be read by the MOSFET portion read.
  • the MOS-C portion of the composite dielectric gate and the underlying dielectric layer of the MOSFET portion and the control gate are respectively connected to form a monolithic structure.
  • the MOS-C portion of the composite dielectric gate and the substrate of the MOSFET portion are separated by shallow trench isolation and a deeper P+ implant under shallow trench isolation to prevent photocharges collected by the MOS-C portion from the MOSFET portion.
  • the source and drain regions are missing, and the depth of the shallow trench isolation and the P+ implant preferably exceeds the width of the depletion region to maximize the protection of the photocharge collected by the MOS-C portion.
  • the unit pixel layout of the composite dielectric gate MOS-C portion and the MOSFET partial charge-coupled photosensitive detector is shown in Fig. 6, wherein the area of the photosensitive MOS-C portion is much larger than the portion of the MOSFET for reading to enhance the photosensitive detector unit. Pixel photosensitive area.
  • the detector can also adopt a side-by-side double-gate structure, as shown in Figures 7 and 8.
  • the photosensitive control gate is used for operation, and the read control gate is used for reading, without changing the photosensitive control gate.
  • the sensitivity of the photosensitive detector unit pixels can be greatly increased without reducing the full well charge.
  • the charge coupling layer of the detector is polysilicon, metal or other electronic conductor. Only the conductor can well couple the photocharge induced by the photosensitive MOS-C part to read the light collected by the MOSFET part of the photosensitive MOS-C part. Charge.
  • the control gate is a polysilicon, metal or transparent conductive electrode to apply the exposed and read voltages. At least one of the control gate or the P-type semiconductor substrate of the composite dielectric gate MOS-C portion for sensing is a transparent or translucent window for detecting the wavelength of the detector, so that light can be incident on the depletion region. Detection of light.
  • the underlying dielectric material may be silicon oxide, SiON or other high dielectric constant dielectric.
  • the material of the top dielectric may be silicon oxide/silicon nitride/silicon oxide, silicon oxide/aluminum oxide/silicon oxide, silicon oxide, aluminum oxide or other high.
  • the dielectric constant medium, the MOS-C portion of the composite dielectric gate and the underlying dielectric layer and the top dielectric layer of the MOSFET portion may be the same material or different materials.
  • the insulating medium of the underlying dielectric layer and the top dielectric layer needs to be thick enough to effectively prevent electron tunneling of the control gate and the substrate into the charge coupling layer to affect the function of the charge coupled layer.
  • the composite dielectric gate MOS-C portion and the MOSFET partial charge coupled photosensitive detector unit can form a detector array.
  • the composite dielectric gate MOSFET portion used for reading in the detector array is interconnected by a NOR architecture of the flash memory to facilitate XY address reading through the connection lines of the mutually perpendicular control gates and the drain terminals. Grounding the common source region of the read transistor during the exposure process can effectively prevent the common source read transistor from affecting the exposure.
  • FIG. 9 is a schematic diagram of interconnection of detector arrays, wherein a large dotted frame shows a pixel unit, and the MOSFET portions for reading are interconnected by a flash NOR architecture, and the MOS-C portions for sensing are independent.
  • Figure 10 is a layout of the detector array. In the detector array, the composite dielectric gate MOS-C portions for sensing are separated by deep trench isolation and P+ implant to prevent crosstalk between the cell pixels, as shown in FIGS. 11 and 12.
  • the color filter and the microlens may be sequentially superimposed on the pixel of the detector unit, and the color image is restored in the array by an arrangement such as a Bell pattern.
  • Figure 14 is a schematic diagram of the applied voltage of the photodetector collecting and storing photoelectrons, in the MOS-C part or the control gate of the MOSFET part
  • Zero bias or small positive bias pulse such as 0 ⁇ 1V
  • P-type semiconductor substrate plus negative bias pulse such as -5V ⁇ 0V
  • a depletion layer in the P-type semiconductor when the photon reaches the consumption In the region, if the photon energy photon hv>semiconductor Eg (or Eg+ ⁇ Ec), the photons are absorbed by the semiconductor and excite an electron-hole pair.
  • the photoelectrons are moved by the gate voltage to the interface of the P-type semiconductor substrate and the underlying dielectric layer or the interface of the P-type semiconductor substrate and the N-type implant, and the storage of the photoelectrons at the interface causes the potential at the interface to change.
  • the change of the potential changes the potential of the charge-coupling layer by the action of charge coupling, so that the threshold of the threshold voltage is generated in the composite dielectric gate MOSFET portion for reading, and the threshold voltage of the composite dielectric gate MOSFET is changed before and after the exposure.
  • the measurement determines the number of photoelectrons collected in the channel; in the stage of collecting photoelectrons, the source and drain regions of the composite dielectric gate MOSFET are connected to zero bias, so that the composite dielectric gate MOSFET portion does not affect the collection of photoelectrons.
  • the composite dielectric gate MOS-C portion for sensing and the composite dielectric gate MOSFET portion for reading share a charge coupling layer, the potential variation of the charge coupled layer brought about by the composite dielectric gate MOS-C portion during exposure can be The composite dielectric gate MOSFET is partially measured.
  • 15 and 16 are equivalent circuit diagrams of a composite dielectric gate MOS-C portion and a MOSFET partial charge coupled photosensitive detector.
  • the photodetector photosensitive MOS-C part of the substrate is equivalent to a photodiode
  • C CGtotal is the sum of the capacitance between the control gate of the MOS-C part and the control gate of the MOSFET part and the charge coupled layer
  • C FG is The capacitance between the partial dielectric MOS-C substrate and the charge coupled layer.
  • ⁇ V G is the change in threshold voltage before exposure to exposure
  • q is the amount of charge of electrons
  • N is the number of collected photoelectrons.
  • the sensitivity of the reading can be improved by using a photosensitive gate and a read control gate using a dual gate structure as shown in FIGS. 17 and 18.
  • the equivalent circuit diagram of the photodetector with double gate structure is shown in Fig. 9.
  • V G1 is the voltage of the photosensitive control gate
  • V G2 is the voltage of the read control gate
  • C CG1 is the capacitance between the photosensitive control gate and the charge coupled layer
  • C CG2 is the capacitance between the read control gate and the charge coupled layer.
  • the voltage is applied to the read control gate, and the threshold voltage of the MOSFET portion can be read by reading the control gate.
  • the relationship between the change in threshold voltage and the collection of photoelectrons is:
  • ⁇ V G2 is the pre-exposure-exposure change of the threshold voltage of the MOSFET portion read by the read control gate
  • C CGtotal C CG1 + C CG2 .
  • ⁇ V S is the maximum change that can be produced by the MOS-C partial channel surface potential.
  • Photoelectron readout amplification method 1 The source region of the composite dielectric gate MOSFET is connected to zero bias, the voltage of the P-type semiconductor substrate is the same as the voltage of the P-type semiconductor substrate during photoelectron collection and storage, and the drain region is connected to a suitable positive voltage. (such as 0.1V or more), give a gradual ramp voltage (such as 1-3V ramp voltage) on the photosensitive control gate or read control gate, measure the current in the drain region, record the drain The magnitude of the gate voltage when the zone current reaches a given current value (eg, 1 ⁇ A).
  • Fig. 19 is a circuit diagram showing the read amplification method.
  • the actual situation is that the current in the drain region is compared by the current comparison circuit to obtain the time when the current reaches a given current value (for example, 1 ⁇ A).
  • the time and the slope of the control gate ramp voltage can be used to obtain the given current value.
  • the resulting gate voltage is the threshold voltage of the composite dielectric gate MOSFET portion.
  • the current comparison circuit works by first charging Cread through PrechN, then adding a small to large ramp voltage on WL, and the counter counter starts counting.
  • the readout circuit is The read capacitor Cread starts to discharge, the comparator controls the counter to stop counting, and the value of the counter is equal to the pixel unit. Threshold voltage.
  • ⁇ V G is the amount of voltage change of the control gate where the drain region current reaches a given value before exposure - after exposure
  • q is the charge amount of electrons
  • N is the number of collected photoelectrons
  • C CGtotal is part of MOS-C
  • C CG is the capacitance between the control gate of the MOS-C portion or the control gate of the MOSFET portion and the charge coupled layer
  • C FG It is the capacitance between the partial dielectric MOS-C substrate and the charge coupled layer.
  • Photoelectron readout amplification method 2 Connect the drain of the composite dielectric gate MOSFET to the power supply voltage (such as 3.3V), and connect the control gate of the MOS-C part or MOSFET part to a suitable positive voltage (such as 1-3.3V), P
  • the type of semiconductor substrate voltage is the same as the voltage of the P-type semiconductor substrate during photoelectron collection and storage, and the source region gives a constant current (eg, 1 ⁇ A) to measure the output voltage of the source region.
  • Fig. 20 is a circuit diagram showing the read amplification method. The relationship between the amount of change in the output voltage and the number of photoelectrons before and after exposure is as follows.
  • ⁇ V out is the amount of change in the output voltage before exposure-exposure
  • q is the charge of electrons
  • N is the number of photoelectrons collected
  • I is the source current
  • C CGtotal is the control gate of the MOS-C part
  • C CG is the capacitance between the control gate of the MOS-C portion or the control gate of the MOSFET portion and the charge coupled layer
  • C FG is the composite dielectric gate
  • ⁇ is the electron mobility
  • C ox is the equivalent capacitance of the control gate of the MOS-C portion or the control gate of the MOSFET portion to the P-type semiconductor substrate.
  • W is the gate width of the composite dielectric gate MOSFET portion
  • L is the gate length of the composite dielectric gate MOSFET portion.
  • Composite dielectric gate MOS-C portion and MOSFET partial charge-coupled photodetector reset method since electrons are collected into the channel during the photo-sensing process, the photodetector needs to be reset after exposure and reading, that is, collected in the channel The electronics are drained. The actual operation is to add a negative bias (such as -1V ⁇ -3V) to the control gate of the detector MOS-C part or MOSFET part, the P-type semiconductor substrate is connected to the zero bias, and the source region of the composite dielectric gate MOSFET part Grounded to the drain region. The electrons stored in the channel return to the substrate under the action of an electric field.
  • a negative bias such as -1V ⁇ -3V

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Abstract

本发明公开了一种基于复合介质栅的双器件光敏探测单元、探测器及其方法。其中，光敏探测单元包括复合介质栅MOS-C部分和复合介质栅MOSFET部分，这两部分形成在同一P型半导体衬底的上方，并共用电荷耦合层。多个上述光敏探测单元在同一P型半导体衬底上排成阵列形成探测器，探测器中相邻单元像素之间通过深槽隔离区以及隔离区下方的P+型注入区来实现隔离。探测时，复合介质栅MOS-C部分的P型半导体衬底感光，然后将光电子耦合到电荷耦合层，光电子信号通过复合介质栅MOSFET部分进行读取。本发明可以很好地实现光信号的探测，具有较好的弱光响应和线性度，同时没有明显的饱和现象，有比较大的动态范围和比较高的量子效率。

Description

基于复合介质栅的双器件光敏探测单元、探测器及其方法 技术领域
本发明涉及成像探测器件，尤其是关于红外、可见光波段至紫外波段的成像探测器件的结构、工作机制及其信号的读出，是一种基于复合介质栅的双器件光敏探测单元、探测器及其信号读取方法。
背景技术
成像探测器在军事民用等各个领域都有很大的应用，当前发展的主要成像探测器是CCD和CMOS-APS。CCD出现较早，技术相对比较成熟，它的基本结构是一列列MOS电容串联，通过电容上面电压脉冲时序控制半导体表面势阱产生和变化，进而实现光生电荷信号的存储和转移读出，也正是由于这个信号转移特点，电荷转移速度很受限制，所以成像速度不高，另外由于是电容串联，一个电容有问题会影响整行信号的传输，所以对工艺要求极高，成品率和成本不够理想。CMOS-APS每个像素采用二极管和晶体管组成，每个像素都是相互独立的，在整个信号传输过程中不需要串行移动电荷，某一个像素出现问题不影响其他像素性能，所以克服了CCD在此方面的缺点，也因此对工艺的要求不是那么苛刻。CMOS由于采用单点信号传输，通过简单的X-Y寻址技术，允许从整个排列、部分甚至单元来读出数据，从而提高寻址速度，实现更快的信号传输。不过CMOS-APS每个像素由多个晶体管与一个感光二极管构成(含放大器与A/D转换电路)，使得每个像素的感光区域只占据像素本身很小的表面积，灵敏度和分辨率相对较小。
通过比较发现上述两种传统成像探测技术各有优劣，CMOS-APS近年来伴随着CMOS工艺的不断进步取得了迅速的发展，并表现出巨大的前景。如能提出一种基于CMOS工艺并能够尽量克服传统CMOS-APS的缺点的成像探测器，意义是很大的。
理想的成像器件可以是由CCD的像素+CMOS-APS所组成的阵列架构。这种架构已被考虑用于存储器件。目前设想中的浮栅存储器件结构是在常规的MOS结构的控制栅和沟道之间加入一层栅，这层栅被致密的氧化物所包围，没有跟外界相连，被称之浮栅。
中国专利CN96122772.9、《半导体存储器件及其制造方法》中公开了一种利用浮栅架构的存储器件，在浮栅上设有控制栅，利用电子的隧道效应，在一定的电场作用下，电子被注入到致密的氧化层中的浮栅内。可以直接利用该效应制成成像器件，参考专利WO2010/094233。
但由于该种成像机理的成像效率与栅氧电场的关系非常密切，随着光强的逐渐增强会有明显的饱和效应。这种饱和效应是指，随着浮栅收集电子的量的增加，栅氧电场会逐渐降低，反 过来会降低浮栅收集电子的效率。浮栅收集电子的效率越来越低，到了一定程度，所述的栅氧电场达不到隧穿效应发生所需要的电场的大小，收集电子的动作就会停止。并且，在弱光下由于控制栅和衬底之间的电压降主要集中在耗尽区中，因此栅氧电场不足以发生隧道效应，因此没有很好的弱光探测效应。同时，在电子从沟道向浮栅转移的过程中无法做到百分百转移，因此会损失收集到的光电子而大幅降低探测效率。
此外，将所述的多个单个的浮栅探测单元集成起来，做成一个浮栅探测阵列时，在特定的架构下，会发生不同浮栅探测单元所采集的光电子信号之间的串扰问题。参见WO2010/094233中的图7，该图中示出了一个3*3的NOR架构的浮栅单元阵列，并且在其所采有的连接架构中，9个浮栅单元的源极区都接在公用源上，且由于该公用源在工作时没有被施加电压，致使所述的9个浮栅单元的源极区电压相同，且不是固定的。当一个浮栅探测单元被曝光后，会接收到光电子，并且它的源极区就会将一个表示所述光电子信息的信号通过所述的公用源平均地分配到所述的9个浮栅单元中。这样，当其中的任一个浮栅探测单元探测时，都会使得所有的探测单元上产生信号，而使得光敏探测器无法工作。
中国专利CN201210442007.X提出了一种双晶体管方案来解决光电子信号之间的串扰问题，但是实际上由于该成像器件工作原理仍旧利用电子的隧道效应。无法解决弱光响应低，饱和效应显著和探测效率低下的问题。
发明内容
本发明的目的是提出一种基于复合介质栅的双器件光敏探测器。该探测器的每个探测单元包括复合介质栅MOS-C部分和复合介质栅MOSFET部分，利用复合介质栅MOS-C部分进行感光，MOS-C部分感光得到的光信号通过电荷耦合的作用耦合到复合介质栅MOSFET部分上从而进行读取。本发明的另外一个目的是提供该光敏探测器的探测方法。将光敏探测器感光和读取使用两个不同器件来完成，可以很好地实现光信号的探测，使其有较好的弱光响应和线性度，同时没有明显的饱和现象，有比较大的动态范围和比较高的量子效率。
本发明采用的技术方案如下：
基于复合介质栅的双器件光敏探测单元，包括具有感光功能的复合介质栅MOS-C部分和具有读取信息功能的复合介质栅MOSFET部分，且这两部分形成在同一P型半导体衬底的上方；所述复合介质栅MOS-C部分包括在P型半导体衬底上方依次叠设的电荷耦合层、第一顶层介质层和第一控制栅极，其中，在P型半导体衬底中且电荷耦合层的下方设有N型注入层；所述复合介质栅MOSFET部分包括在所述P型半导体衬底上方依次叠设的底层介质层、所述 电荷耦合层、第二顶层介质层和第二控制栅极，其中，在所述P型半导体衬底中且靠近底层介质层的一侧设有N型源极区和N型漏极区，在所述P型半导体衬底中且底层介质层的下方设有阈值调节注入区；所述P型半导体衬底中，N型注入层与N型源极区、N型漏极区之间通过设置浅槽隔离区和P+型注入区隔开。
进一步地，所述复合介质栅MOS-C部分还包括第一底层介质层，所述第一底层介质层设置在P型半导体衬底上方且电荷耦合层的下方。
所述第一底层介质层与复合介质栅MOSFET部分的底层介质层相连为一整体结构或者为相互独立的两部分，所述第一顶层介质层和第二顶层介质层相连为一整体结构或者为相互独立的两部分。
所述第一控制栅极和第二控制栅极相连为一个整体结构。或者所述第一控制栅极和第二控制栅极为并排的双栅极结构，其中，第一控制栅极为感光控制栅，第二控制栅极为读取控制栅。
所述复合介质栅MOS-C部分的P型半导体衬底和电荷耦合层的面积大于复合介质栅MOSFET部分的P型半导体衬底和电荷耦合层的面积。
所述电荷耦合层的材料为多晶硅、金属或其它电子导体中的一种；所述第一控制栅极或第二控制栅极的材料为多晶硅、金属或透明导电电极中的一种；所述底层介质层的材料为氧化硅、SiON或其它高介电常数介质中的一种；所述第一顶层介质层或第二顶层介质层的材料为氧化硅/氮化硅/氧化硅、氧化硅/氧化铝/氧化硅、氧化硅、氧化铝或其它高介电常数介质材料中的一种。
本发明基于复合介质栅的双器件光敏探测器，由多个所述双器件光敏探测单元在同一P型半导体衬底上排成阵列形成，其中，所述复合介质栅MOS-C部分之间设置深槽隔离区和P+型注入区，用于隔开各个光敏探测单元；所述复合介质栅MOSFET部分之间采用闪存的NOR架构进行互联，第二控制栅极的连线和N型漏极区的连线相互垂直被用于X-Y值的选址读取，共有的N型源极区在曝光过程中被接地。
本发明利用双器件光敏探测器的探测方法，通过所述复合介质栅MOS-C部分与复合介质栅MOSFET部分来收集、储存和读取感光的光电子，并且复合介质栅MOS-C部分在曝光过程中带来的电荷耦合层的电位变化可以被复合介质栅MOSFET部分测量得到；所述复合介质栅MOS-C部分的P型半导体衬底感光，然后将光电子耦合到所述电荷耦合层，光电子信号通过复合介质栅MOSFET部分进行读取。
本发明通过使用复合介质栅MOS-C部分和MOSFET部分两个器件分别实现了光敏探测 器的感光和读取功能，使得光敏探测器的感光和读取功能分开，其特点和优越性包括：
(1)弱光响应：由于光敏探测器的复合介质栅MOS-C部分与MOSFET部分没有采用隧穿的工作机理，因此在弱光情况下，电压几乎全部集中在耗尽区，导致的很低的栅氧电场不会影响光敏探测器的探测效率。同时采用双栅结构可以极大的提高光敏探测器的探测灵敏度，对探测弱光有很大的益处。
(2)弱饱和效应：由于光敏探测器的复合介质栅MOS-C部分与MOSFET部分没有采用隧穿的工作机理，因此探测效率与电场强度不相关，所以随着电荷的收集导致的电场的下降不会很大的影响光敏探测器的探测效率，从而不会导致饱和效应的产生。
(3)感光单元之间无串扰：由于光敏探测器的感光部分没有源漏注入，晶体管之间无法导通，使得晶体管之间无法直接相互干扰。同时构成探测器阵列中的用以感光的MOS-C部分之间采用深槽隔离区和隔离区下方的P+注入区隔开，可以有效的防止MOS-C部分收集的光电荷互相产生干扰而影响成像品质。因此感光单元之间几乎没有串扰，光敏探测器读到的图像与真实的图像基本相同。
(4)量子效率高:探测器的感光工作原理类似CCD，摒弃了隧穿的过程，避免了隧穿过程中电子的损失。同时复合介质栅MOS-C部分和MOSFET部分的衬底(靠近叠层介质一侧)通过浅槽隔离和P+型注入隔开，可以防止MOS-C部分收集的光电荷从MOSFET部分中的源极区和漏极区漏掉。光子进入耗尽区产生的光电子几乎全部被收集到沟道处，因此有很高的量子效率。
附图说明
图1为探测器感光MOS-C部分结构示意图；
图2为另一种探测器感光MOS-C部分结构示意图；
图3为探测器读取MOSFET部分结构示意图；
图4为探测器单元像素结构示意图；
图5为另一种探测器单元像素结构图；
图6为探测器单元像素版图；
图7为探测器双栅结构单元像素结构示意图一；
图8为探测器双栅结构单元像素结构示意图二；
图9为探测器阵列互联示意图；
图10为探测器阵列版图；
图11为感光MOS-C部分之间隔离示意图一；
图12为感光MOS-C部分之间隔离示意图二；
图13为单元像素上设置滤色片和微透镜示意图；
图14为探测器单元像素收集、储存光电子电压施加示意图；
图15为探测器单元像素的等效电路图一；
图16为探测器单元像素的等效电路图二；
图17为探测器双栅结构单元像素的等效电路图一；
图18为探测器双栅结构单元像素等效电路图二；
图19为探测器读出放大方法一的电路图；
图20为探测器读出放大方法二的电路图。
具体实施方式
复合介质栅MOS-C部分与MOSFET部分电荷耦合光敏探测器单元像素结构如图1-图5所示，每个探测器单元像素都是由一个用以感光的复合介质栅MOS-C部分和一个用以读取的复合介质栅MOSFET部分构成，利用复合介质栅MOS-C部分实现感光功能，同时利用复合介质栅MOSFET部分实现读取功能，复合介质栅MOS-C部分和MOSFET部分形成在同一基底P型半导体材料上方。
其中用以感光的复合介质栅MOS-C部分的结构如图1所示，包括：
1)P型半导体衬底；
2)P型半导体衬底正上方依次设有底层介质层、电荷耦合层、顶层介质层和控制栅极；
3)P型半导体衬底中(叠层介质正下方)可以有通过离子注入掺杂形成N型注入，用以使得光电荷存储位置下移，离开P型半导体衬底和顶层介质层的界面处。
另一种用以感光的复合介质栅MOS-C部分的结构如图2所示，包括：
1)P型半导体衬底；
2)P型半导体衬底正上方依次设有电荷耦合层、顶层介质层和控制栅极；
3)P型半导体衬底中(叠层介质正下方)可以有通过离子注入掺杂形成N型注入，用以使得光电荷存储位置下移，离开P型半导体衬底和顶层介质层的界面处。
其中用以读取的复合介质栅MOSFET部分的结构如图3所示，包括：
1)P型半导体衬底；
2)P型半导体衬底正上方依次设有底层介质层、电荷耦合层、顶层介质层和控制栅极；
3)P型半导体衬底中(靠近叠层介质一侧)通过离子注入掺杂形成N型源极区和N型漏极区，用以实现光敏探测器信号的读取；
4)P型半导体衬底中(叠层介质正下方)可以有通过离子注入掺杂形成的阈值调节注入，用以调节复合介质栅MOSFET部分的阈值电压。
复合介质栅MOS-C部分和MOSFET部分电荷耦合光敏探测器的连接方法如图4和图5所示，复合介质栅MOS-C部分和MOSFET部分通过同一电荷耦合层以及衬底相连，从而使得用以读取的MOSFET部分可以读取到用以感光的MOS-C部分中感光得到的光电荷的数目。其中，复合介质栅MOS-C部分和MOSFET部分的底层介质层以及控制栅极都分别相连形成一整体结构。复合介质栅MOS-C部分和MOSFET部分的衬底(靠近叠层介质一侧)通过浅槽隔离以及浅槽隔离下方更深的P+型注入隔开以防止MOS-C部分收集的光电荷从MOSFET部分中的源极区和漏极区漏掉，其中浅槽隔离和P+型注入的深度最好要超过耗尽区的宽度才能最大程度上保护住MOS-C部分收集到的光电荷。复合介质栅MOS-C部分和MOSFET部分电荷耦合光敏探测器的单元像素版图如图6所示，其中用以感光MOS-C部分的面积远大于用以读取的MOSFET部分以提升光敏探测器单元像素感光面积。
另外，探测器还可以采用并排的双栅结构，如图7和8所示，感光的时候采用感光控制栅，进行操作，读取的时候采用读取控制栅进行操作，在不改变感光控制栅和读取控制栅总面积的条件下，减小读取控制栅的面积，可以在不减小满阱电荷的同时大大地增加光敏探测器单元像素的灵敏度。
探测器的电荷耦合层是多晶硅，金属或其它电子导体，只有导体才能很好的耦合感光MOS-C部分感应到的光电荷以便读取MOSFET部分读出感光MOS-C部分沟道中收集到的光电荷。控制栅极是多晶硅、金属或透明导电电极，以便施加曝光和读取的电压。用以感光的复合介质栅MOS-C部分的控制栅极或P型半导体衬底中的至少一个，为对探测器探测波长透明或半透明的窗口，才能使得光可以入射到耗尽区而实现对光的探测。底层介质材料可以采用氧化硅、SiON或其它高介电常数介质，顶层介质的材料可以采用氧化硅/氮化硅/氧化硅、氧化硅/氧化铝/氧化硅、氧化硅、氧化铝或其它高介电常数介质，复合介质栅MOS-C部分和MOSFET部分的底层介质层和顶层介质层可以采用相同的材料也可以为不同的材料。其中，底层介质层和顶层介质层这两层绝缘介质都需足够厚以有效地阻止控制栅极和衬底的电子隧穿进入电荷耦合层而影响电荷耦合层的功能。
复合介质栅MOS-C部分与MOSFET部分电荷耦合光敏探测器单元能够构成探测器阵列。 探测器阵列中用以读取的复合介质栅MOSFET部分之间采用闪存的NOR架构进行互联以便于通过相互垂直的控制栅极的连线和漏端的连线进行X-Y的选址读取，同时在曝光过程中将读取晶体管的共有的源极区接地，可以有效的防止共源的读取晶体管对曝光产生影响。图9为探测器阵列的互联示意图，其中大虚线框所示为一个像素单元，用以读取的MOSFET部分以闪存NOR架构互联，用以感光的MOS-C部分各自独立。图10为探测器阵列的版图。在探测器阵列中，用以感光的复合介质栅MOS-C部分之间通过深槽隔离和P+型注入隔开以防止单元像素之间发生串扰，如图11和12所示。
探测器单元像素上方可以依次叠加滤色片和微透镜，在阵列中通过如贝尔图案的排列方式实现彩色图像的还原。
复合介质栅MOS-C部分与MOSFET部分电荷耦合光敏探测器光电子收集、储存的步骤：图14为该光敏探测器收集储存光电子的施加电压示意图，在MOS-C部分或者MOSFET部分的控制栅极加零偏压或很小的正偏压脉冲(如0～1V)，P型半导体衬底加负偏压脉冲(如-5V～0V)，在P型半导体中形成耗尽层，当光子到达耗尽区，如果光子能量光子hv>半导体Eg(或Eg+ΔEc)，光子被半导体吸收并激发一个电子空穴对。光电子在栅极电压的驱使下移动到P型半导体衬底和底层介质层的界面处或P型半导体衬底和N型注入的界面处，上述界面处存储光电子后会使得界面处电位发生改变，该电位的改变会通过电荷耦合的作用使得电荷耦合层的电位发生改变，从而使得用以读取的复合介质栅MOSFET部分产生阈值电压的漂移，通过对曝光前后复合介质栅MOSFET部分阈值电压变化的测量确定出沟道中收集到的光电子的数目；在搜集光电子的阶段，复合介质栅MOSFET部分源极区和漏极区接零偏压，使得复合介质栅MOSFET部分不会影响到光电子的收集。
由于用以感光的复合介质栅MOS-C部分和用以读取的复合介质栅MOSFET部分共用电荷耦合层，复合介质栅MOS-C部分在曝光过程中带来的电荷耦合层的电位变化可以被复合介质栅MOSFET部分测量得到。图15和16为复合介质栅MOS-C部分与MOSFET部分电荷耦合光敏探测器的等效电路图。其中光敏探测器感光MOS-C部分衬底等效成一个光电二极管，CCGtotal为MOS-C部分的控制栅极和MOSFET部分的控制栅极与电荷耦合层之间的电容之和，CFG为复合介质栅MOS-C部分衬底与电荷耦合层之间的电容。可以得出读取MOSFET部分阈值电压的变化与光电子收集的关系为：
Figure PCTCN2016102679-appb-000001
其中ΔVG为曝光前-曝光后阈值电压的变化，q为电子的电荷量，N为收集到的光电子的数目。
可以采用如图17和图18所示的双栅结构使用感光控制栅和读取控制栅来提升读取的灵敏度。双栅结构的光敏探测器的等效电路图如图9所示。其中VG1为感光控制栅的电压，VG2为读取控制栅的电压，CCG1为感光控制栅与电荷耦合层之间的电容，CCG2为读取控制栅与电荷耦合层之间的电容。本实施例中，在读取控制栅上加压，通过读取控制栅可以读取到MOSFET部分的阈值电压。该阈值电压的变化与光电子的收集关系为：
Figure PCTCN2016102679-appb-000002
其中ΔVG2为读取控制栅读取到的MOSFET部分的阈值电压曝光前-曝光后的变化，CCGtotal＝CCG1+CCG2。
而满阱电荷为：
Figure PCTCN2016102679-appb-000003
其中ΔVS为MOS-C部分沟道表面势可以产生的最大的变化值。
由上述公式可以看出在不改变感光控制栅和读取控制栅总面积的情况下减小读取控制栅的面积(即在不改变CCGtotal的情况下减小CCG2)可以不减小满阱电荷的情况下增大读取的灵敏度。
光电子读出放大方法一：将复合介质栅MOSFET部分的源极区接零偏压，P型半导体衬底电压与光电子收集和储存过程中P型半导体衬底电压相同，漏极区接合适正电压(如0.1V以上即可)，在感光控制栅极或读取控制栅极上给出一个渐变的斜坡电压(如1-3V的斜坡电压)，在漏极区对电流进行测量，记录漏极区电流到达给定电流值(如1μA)时的栅极电压的大小。图19为该读出放大方法的电路示意图。实际情况是通过电流比较电路对漏极区的电流进行比较得到电流到达给定电流值(如1μA)时的时间，通过该时间和控制栅极斜坡电压的斜率即可得出到达给定电流值是控制栅极的电压大小。得到的栅极电压即为复合介质栅MOSFET部分的阈值电压。
电流比较电路的工作过程为：先通过PrechN对Cread进行充电，然后在WL上加从小到大的斜波电压，同时计数器Counter开始计数，当WL电压等于像素单元的阈值电压时，读出电路中的读出电容Cread开始放电，比较器控制计数器停止计数，计数器的值就等于像素单元 的阈值电压。
曝光前-曝光后该阈值电压的变化量与光电子数目的关系如下，
Figure PCTCN2016102679-appb-000004
其中ΔVG为曝光前-曝光后漏极区电流到达给定值的控制栅极的电压变化量，q为电子的电荷量，N为收集到的光电子的数目，CCGtotal为MOS-C部分的控制栅极和MOSFET部分的控制栅极与电荷耦合层之间的电容之和，CCG为MOS-C部分的控制栅极或者MOSFET部分的控制栅极与电荷耦合层之间的电容，CFG为复合介质栅MOS-C部分衬底与电荷耦合层之间的电容。
光电子的读出放大方法二：将复合介质栅MOSFET部分漏极区接电源电压(如3.3V)，MOS-C部分或者MOSFET部分的控制栅极接合适正电压(如1-3.3V)，P型半导体衬底电压与光电子收集和储存过程中P型半导体衬底电压相同，源极区给一个恒定的电流(如1μA)，测量源极区的输出电压。图20为该读出放大方法的电路示意图。曝光前-曝光后该输出电压的变化量与光电子数目的关系如下，
Figure PCTCN2016102679-appb-000005
其中ΔVout为曝光前-曝光后输出电压的变化量，q为电子的电荷量，N为收集到的光电子的数目，I为源极区电流，CCGtotal为MOS-C部分的控制栅极和MOSFET部分的控制栅极与电荷耦合层之间的电容之和，CCG为MOS-C部分的控制栅极或MOSFET部分的控制栅极与电荷耦合层之间的电容，CFG为复合介质栅MOS-C部分衬底与电荷耦合层之间的电容，μ为电子迁移率，Cox为MOS-C部分的控制栅极或MOSFET部分的控制栅极到P型半导体衬底的等效电容，W为复合介质栅MOSFET部分的栅宽，L为复合介质栅MOSFET部分的栅长。
复合介质栅MOS-C部分与MOSFET部分电荷耦合光敏探测器复位方法：由于在感光过程中电子被收集到沟道中，在曝光和读取完成后需要将光敏探测器进行复位，即将收集到沟道中的电子排走。实际操作是在探测器MOS-C部分或者MOSFET部分的控制栅极上加负偏压(如-1V～-3V)，P型半导体衬底接零偏压，复合介质栅MOSFET部分的源极区和漏极区接地。存储在沟道中的电子即在电场的作用下回到衬底中。

Claims (16)

  1. 基于复合介质栅的双器件光敏探测单元，其特征在于，包括具有感光功能的复合介质栅MOS-C部分和具有读取信息功能的复合介质栅MOSFET部分，且这两部分形成在同一P型半导体衬底的上方；
    所述复合介质栅MOS-C部分包括在P型半导体衬底上方依次叠设的电荷耦合层、第一顶层介质层和第一控制栅极，其中，在P型半导体衬底中且电荷耦合层的下方设有N型注入层；
    所述复合介质栅MOSFET部分包括在所述P型半导体衬底上方依次叠设的底层介质层、所述电荷耦合层、第二顶层介质层和第二控制栅极，其中，在所述P型半导体衬底中且靠近底层介质层的一侧设有N型源极区和N型漏极区，在所述P型半导体衬底中且底层介质层的下方设有阈值调节注入区；
    所述P型半导体衬底中，N型注入层与N型源极区、N型漏极区之间通过设置浅槽隔离区和P+型注入区隔开。
  2. 根据权利要求1所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述复合介质栅MOS-C部分还包括第一底层介质层，所述第一底层介质层设置在P型半导体衬底上方且电荷耦合层的下方。
  3. 根据权利要求2所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述第一底层介质层与复合介质栅MOSFET部分的底层介质层相连为一整体结构或者为相互独立的两部分，所述第一顶层介质层和第二顶层介质层相连为一整体结构或者为相互独立的两部分。
  4. 根据权利要求1、2或3所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述第一控制栅极和第二控制栅极相连为一个整体结构。
  5. 根据权利要求1、2或3所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述第一控制栅极和第二控制栅极为并排的双栅极结构，其中，第一控制栅极为感光控制栅，第二控制栅极为读取控制栅。
  6. 根据权利要求1、2或3所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述复合介质栅MOS-C部分的P型半导体衬底和电荷耦合层的面积大于复合介质栅MOSFET部分的P型半导体衬底和电荷耦合层的面积。
  7. 根据权利要求1、2或3所述的基于复合介质栅的双器件光敏探测单元，其特征在于，所述电荷耦合层的材料为多晶硅、金属或其它电子导体中的一种；所述第一控制栅极或第二控制栅极的材料为多晶硅、金属或透明导电电极中的一种；所述底层介质层的材料为氧化硅、SiON或其它高介电常数介质中的一种；所述第一顶层介质层或第二顶层介质层的材料为氧化 硅/氮化硅/氧化硅、氧化硅/氧化铝/氧化硅、氧化硅、氧化铝或其它高介电常数介质材料中的一种。
  8. 利用如权利要求1所述基于复合介质栅的双器件光敏探测单元的探测器，其特征在于，多个所述双器件光敏探测单元在同一P型半导体衬底上排成阵列形成探测器，其中，所述复合介质栅MOS-C部分之间设置深槽隔离区和P+型注入区，用于隔开各个光敏探测单元；所述复合介质栅MOSFET部分之间采用闪存的NOR架构进行互联，第二控制栅极的连线和N型漏极区的连线相互垂直被用于X-Y值的选址读取，共有的N型源极区在曝光过程中被接地。
  9. 根据权利要求8所述的探测器，其特征在于，所述探测器的每个光敏探测单元上贴合有滤光片层，每个滤光片层上贴合有微透镜。
  10. 根据权利要求8或9所述的探测器，其特征在于，所述复合介质栅MOS-C部分的P型半导体衬底和第一控制栅极中的至少一个，具有探测器用于探测光的透明或半透明窗口。
  11. 如权利要求8所述探测器的探测方法，其特征在于，利用所述复合介质栅MOS-C部分与复合介质栅MOSFET部分来收集、储存和读取感光的光电子，并且复合介质栅MOS-C部分在曝光过程中带来的电荷耦合层的电位变化可以被复合介质栅MOSFET部分测量得到；所述复合介质栅MOS-C部分的P型半导体衬底感光，然后将光电子耦合到所述电荷耦合层，光电子信号通过复合介质栅MOSFET部分进行读取。
  12. 根据权利要求11所述的探测方法，其特征在于，所述第一控制栅极和第二控制栅极相连为一个整体结构；或者所述第一控制栅极和第二控制栅极为并排的双栅极结构，其中，第一控制栅极为感光控制栅，用来感光，第二控制栅极为读取控制栅，用来读取光电子信号。
  13. 根据权利要求11所述的探测方法，其特征在于，光电子收集时，所述第一控制栅极或第二控制栅极加零偏压或很小的正偏压脉冲，P型半导体衬底加负偏压脉冲，在P型半导体衬底中形成耗尽层；当光入射到耗尽层中光子被半导体吸收时，产生光电子，光电子在栅极电压的驱使下移动到P型半导体衬底的上表面，或者移动到P型半导体衬底和N型注入层的界面处，界面处存储光电子后会使得界面处电位发生改变，该电位的改变会通过电荷耦合的作用使得电荷耦合层的电位发生改变，从而使得用以读取的复合介质栅MOSFET部分产生阈值电压的漂移，通过对曝光前后复合介质栅MOSFET部分阈值电压变化的测量，确定出沟道中收集到的光电子的数目；在搜集光电子的阶段，复合介质栅MOSFET部分的N型源极区和N型漏极区接零偏压，使得复合介质栅MOSFET部分不会影响到光电子的收集。
  14. 根据权利要求11所述的探测方法，其特征在于，读取光电子信号时，将复合介质栅 MOSFET部分的N型源极区接零偏压，P型半导体衬底电压与光电子收集和储存过程中的P型半导体衬底的电压相同，N型漏极区接正电压，在第一控制栅极或第二控制栅极上给出一个渐变的斜坡电压，在N型漏极区对电流进行测量，记录N型漏极区电流到达给定电流值时的栅极电压的大小，该栅极电压即为复合介质栅MOSFET部分的阈值电压，曝光前至曝光后该阈值电压的变化量与光电子数目的关系如下，
    Figure PCTCN2016102679-appb-100001
    其中ΔVG为曝光前至曝光后漏极区电流到达给定值的第一控制栅极或者第二控制栅极的电压变化量，q为电子的电荷量，N为收集到的光电子的数目，CCG为第一控制栅极或者第二控制栅极与电荷耦合层之间的电容，CCGtotal为第一控制栅极和第二控制栅极与电荷耦合层之间的电容之和，CFG为复合介质栅MOS-C部分的P型半导体衬底与电荷耦合层之间的电容。
  15. 根据权利要求11所述的探测方法，其特征在于，读取光电子信号时，将复合介质栅MOSFET部分的N型漏极区接电源电压，第一控制栅极或者第二控制栅极接正电压，P型半导体衬底电压与光电子收集和储存过程中的P型半导体衬底的电压相同，N型源极区给一个恒定的电流，测量N型源极区的输出电压，曝光前至曝光后该输出电压的变化量与光电子数目的关系如下，
    Figure PCTCN2016102679-appb-100002
    其中ΔVout为曝光前至曝光后输出电压的变化量，q为电子的电荷量，N为收集到的光电子的数目，I为源极区电流，CCG为第一控制栅极或者第二控制栅极与电荷耦合层之间的电容，CCGtotal为第一控制栅极和第二控制栅极与电荷耦合层之间的电容之和，CFG为复合介质栅MOS-C部分的P型半导体衬底与电荷耦合层之间的电容，μ为电子迁移率，Cox为第一控制栅极或者第二控制栅极到P型半导体衬底的等效电容，W为复合介质栅MOSFET部分的栅宽，L为复合介质栅MOSFET部分的栅长。
  16. 根据权利要求11至15之一所述的探测方法，其特征在于，所述光电子信号读取完成后，将感光得到的光电子进行复位：在探测器的第一控制栅极或第二控制栅极上加负偏压，P 型半导体衬底接零偏压，复合介质栅MOSFET部分的N型源极区和N型漏极区接地，使存储在沟道中的电子即在电场的作用下回到衬底中。
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