WO2019085138A1 - 显示装置、及阵列基板与 ic 芯片的绑定方法 - Google Patents

显示装置、及阵列基板与 ic 芯片的绑定方法 Download PDF

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WO2019085138A1
WO2019085138A1 PCT/CN2017/114521 CN2017114521W WO2019085138A1 WO 2019085138 A1 WO2019085138 A1 WO 2019085138A1 CN 2017114521 W CN2017114521 W CN 2017114521W WO 2019085138 A1 WO2019085138 A1 WO 2019085138A1
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conductive particles
metal terminal
chip
array substrate
metal
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PCT/CN2017/114521
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English (en)
French (fr)
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李成
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武汉华星光电半导体显示技术有限公司
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Priority to US15/735,963 priority Critical patent/US10411218B2/en
Publication of WO2019085138A1 publication Critical patent/WO2019085138A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour

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  • the present invention relates to the field of display technologies, and in particular, to a display device, and a method for binding an array substrate and an IC chip.
  • the display panel needs to bind the IC chip to the substrate in the module process.
  • the current binding method is mainly an anisotropic conductive adhesive ( ACF). Attached to the bump (metal protrusion) on the end to be bonded, the other end of the bump is crimped on the ACF and cured to complete the bonding process.
  • ACF anisotropic conductive adhesive
  • the conductive particles in the anisotropic conductive film are evenly distributed in the resin.
  • the fluidity of the resin increases due to the temperature rise, and the binding pressure causes bump to be bump.
  • the conductive particles at the contact are squeezed into the gap, making the density of the conductive particles at the gap higher than the flux At the place, causing a short circuit.
  • the current method for improving the utilization rate of conductive particles is mainly to add inorganic insulating particles to the anisotropic conductive paste to reduce the fluidity of the conductive paste, but this method also reduces the percentage of the resin and the conductive particles, which may cause pressure.
  • the prior art display panel is bound to the IC
  • the conductive particles distributed at the resin setting position are displaced due to the fluidity of the resin, which causes a short circuit between the leads, thereby affecting the quality of the display panel.
  • the present invention provides a display device in which a quasi-crystal conductive particle is disposed in a package region of a display device
  • the flowability of the conductive particles in the resin can be reduced to solve the positional shift of the conductive particles distributed in the resin set position in the process of binding the IC chip in the prior art display panel, which is affected by the fluidity of the resin.
  • the present invention provides a display device, the display device comprising:
  • An array substrate the surface of the array substrate is provided with a binding area, and at least three first metal terminals are disposed in the binding area;
  • An anisotropic conductive film disposed on a surface of the bonding region, the anisotropic conductive film including a resin layer;
  • IC a chip
  • one side of the IC chip is provided with at least three second metal terminals corresponding to the first metal terminal, the IC chip is aligned with the binding region, and the second metal terminal is The first metal terminal is in a pair, and the IC chip is bound to the array substrate.
  • the IC chip is combined with the bonding region of the array substrate by a hot pressing process to heat fluidize the anisotropic conductive film, and the first metal terminal and the The second metal terminal is further contacted such that the first metal terminal and the second metal terminal are electrically connected to the array substrate through the quasi-crystalline conductive particles.
  • the conductive particles are used to make the surface of the array substrate after the array substrate and the IC chip are pressure-bonded by a conductive adhesive.
  • the conductive particles are used to reduce the fluidity of the conductive particles in the conductive paste during the crimping process.
  • the present invention provides a display device, the display device comprising:
  • An array substrate the surface of the array substrate is provided with a binding area, and at least three first metal terminals are disposed in the binding area;
  • An anisotropic conductive film disposed on a surface of the bonding region, the anisotropic conductive film including a resin layer;
  • Conductive particles are distributed in the resin layer, the conductive particles are correspondingly distributed over the first metal terminal, and the conductive particles are quasi-crystalline conductive particles;
  • IC a chip
  • one side of the IC chip is provided with at least three second metal terminals corresponding to the first metal terminal, the IC chip is aligned with the binding region, and the second metal terminal is The first metal terminal is in a pair, and the IC chip is bound to the array substrate.
  • the IC chip is combined with the bonding region of the array substrate by a hot pressing process to heat fluidize the anisotropic conductive film, and the first metal terminal and the The second metal terminal is further contacted such that the first metal terminal and the second metal terminal are electrically connected to the array substrate through the quasi-crystalline conductive particles.
  • the conductive particles are used to make the first metal terminal on the surface of the array substrate and the second surface of the IC chip after the array substrate and the IC chip are bonded by the conductive adhesive. Electrical connection between metal terminals;
  • the conductive particles are used to reduce the fluidity of the conductive particles in the conductive paste during the crimping process.
  • a method for binding an array substrate to an IC chip includes:
  • step S10 an array substrate is provided, and a binding area is disposed on the surface of the array substrate, and at least three first metal terminals are spaced apart in the binding area;
  • Step S20 an anisotropic conductive film is disposed on a surface of the binding region, the anisotropic conductive film includes a resin layer, and conductive particles distributed in the resin layer, wherein the conductive particles are correspondingly distributed in the first a metal terminal; the conductive particles using quasi-crystalline conductive particles;
  • Step S30 providing an IC chip, one side of the IC chip is provided with at least three second metal terminals corresponding to the first metal terminal, and the IC chip is aligned with the binding area, and The second metal terminal is in a pair with the first metal terminal;
  • Step S40 the bonding region of the IC chip and the array substrate is further combined by a hot pressing process, and the anisotropic conductive film is fluidized by heat, so that the first metal terminal and the second metal terminal Further, the first metal terminal and the second metal terminal are electrically connected by the quasi-crystalline conductive particles to complete bonding of the array substrate and the IC chip.
  • the surface of the first metal terminal is a concave surface.
  • inorganic insulating particles are disposed between two adjacent first metal terminals.
  • the pitch of the adjacent two first metal terminals is 5-10 times the particle diameter of the quasi-crystalline conductive particles.
  • the quasi-crystalline conductive particles have a particle diameter of 6 to 9 ⁇ m.
  • the anisotropic conductive film is pretreated by heat, laser or ultraviolet light irradiation.
  • the array substrate is a flexible OLED substrate.
  • the beneficial effects of the present invention are: compared to existing display devices
  • the conductive particles in the package structure, the conductive particles provided by the present invention are quasi-crystalline conductive particles, and because of the shape of the plurality of planes, the flow of the conductive particles in the resin can be restricted, thereby preventing the conductive particles from being displaced and causing the conductive particles to be distributed. Uneven, which in turn causes a short circuit between the metal terminals on the same side;
  • the conductive particles distributed in the resin set position are displaced due to the fluidity of the resin, thereby causing bump The phenomenon of short circuit, which in turn affects the quality of the display panel.
  • FIG. 1 is a schematic structural view of a display device provided by the present invention.
  • FIG. 2 is a schematic structural view of a quasi-crystalline conductive particle provided by the present invention.
  • FIG. 3 is a schematic view showing an outer circular cut surface of a quasi-crystalline conductive particle provided by the present invention.
  • FIG. 4 is a schematic view showing a contact surface of a quasi-crystalline conductive particle provided by the present invention.
  • Figure 5 is a schematic view showing the outer circular cut surface of the quasi-crystalline conductive particles provided by the present invention.
  • FIG. 6 is a flow chart of a method for binding an array substrate and an IC chip according to the present invention.
  • the present invention is directed to a prior art display panel in a binding IC
  • the conductive particles distributed at the resin set position are displaced by the influence of the fluidity of the resin, thereby causing a short circuit between the bumps, thereby affecting the quality of the display panel.
  • This embodiment can solve the defect. .
  • the present invention provides a display device including an array substrate 101.
  • the surface of the array substrate 101 is provided with a binding region 102, and at least three first metal terminals 103 are disposed in the binding region 102.
  • An anisotropic conductive film disposed on a surface of the bonding region 102, the anisotropic conductive film including a resin layer 104; conductive particles 105, the conductive particles 105 being distributed over the resin In the layer 104, the conductive particles 105 are correspondingly distributed over the first metal terminal 103, the conductive particles 105 are quasi-crystalline conductive particles, and the IC chip 106 is provided with at least three sides of the IC chip 106.
  • the second metal terminal 107 corresponding to the first metal terminal 103, the IC chip 106 is aligned with the binding region 102, and the second metal terminal 107 is paired with the first metal terminal 103.
  • the IC chip 106 is bound to the array substrate 101.
  • the IC chip 106 is combined with the bonding region 102 of the array substrate 101 by a hot pressing process to heat fluidize the anisotropic conductive film, and the first metal terminal 103 and the second metal are The terminal 107 is further in contact such that the first metal terminal 103 and the second metal terminal 107 are electrically connected to the array substrate 101 through the quasi-crystalline conductive particles.
  • the conductive particles 105 are used to make the first metal terminal 103 on the surface of the array substrate 101 and the second metal terminal on the surface of the IC chip 106 after the array substrate 101 and the IC chip 106 are bonded by the conductive adhesive. Electrical connection between 107; at least three of the conductive particles 105 are distributed between the first metal terminal 103 and the second metal terminal 107; the conductive particles 105 are used to reduce the crimping process The fluidity of the conductive particles 105 in the conductive paste.
  • the conductive particles are provided for the first metal terminal on the surface of the array substrate and the surface of the IC chip after the array substrate and the IC chip are pressure-bonded by a conductive adhesive.
  • Quasicrystals also known as 'quasicrystals' or 'crystals', are solid structures between crystalline and amorphous; in quasicrystal arrangements, the structure is long-range ordered, and The crystals are similar; however, the quasicrystals do not have translational symmetry, which is different from crystals. Ordinary crystals have a second, third, fourth or sixth rotational symmetry, but the quasicrystal Bragg diffraction pattern has other symmetry, such as five symmetry or higher six or more symmetry. Therefore, the quasicrystal has a multi-faceted symmetrical structure.
  • the quasi-crystalline conductive particles provided by the present invention have a shape of a regular pentagonal dodecahedron in a Palladium solid, and a horizontal bevel inclination angle ⁇ of each plane of the conductive particles. 120°; the outer circular section of the quasi-crystalline conductive particle includes a quasi-crystal side surface 301 and a quasi-crystal side edge a, between the center of the outer circular section and the connection point of any adjacent two quasi-crystal side edges a
  • the contact surface between two adjacent quasi-crystalline conductive particles is a pentagonal plane, and the area of the pentagon plane:
  • S quasicrystal a 2 ⁇ ( 1 + cos 72 ° ) ⁇ sin 72 ° ⁇ a 2 ⁇ ( 1 + 2 cos 72 ° ) ⁇ 0.3
  • a is the side length of the pentagonal plane.
  • the outer circular section of the quasi-crystalline conductive particle includes a quasi-crystal side surface 501 and a quasi-crystal side edge a.
  • the deformation rate is 60%.
  • a is the quasi-crystal side edge length .
  • the quasi-crystalline conductive particles After the quasi-crystalline conductive particles are compressively deformed, a deformation angle 402 is generated, the quasi-crystalline conductive particles have a horizontal bevel angle, and the lateral length of the quasi-crystalline conductive particles is long, thereby increasing the quasi-crystalline conductive particles.
  • the support area reduces the rolling inertia.
  • a method for binding an array substrate and an IC chip includes the following steps:
  • step S10 an array substrate is provided, and a binding area is disposed on the surface of the array substrate, and at least three first metal terminals are disposed at intervals in the binding area.
  • Step S20 an anisotropic conductive film is disposed on a surface of the binding region, the anisotropic conductive film includes a resin layer, and conductive particles distributed in the resin layer, wherein the conductive particles are correspondingly distributed in the first Above a metal terminal; the conductive particles are quasi-crystalline conductive particles.
  • Step S30 providing an IC chip, one side of the IC chip is provided with at least three second metal terminals corresponding to the first metal terminal, and the IC chip is aligned with the binding area, and The second metal terminal is in a pair with the first metal terminal.
  • Step S40 the bonding region of the IC chip and the array substrate is further combined by a hot pressing process, and the anisotropic conductive film is fluidized by heat, so that the first metal terminal and the second metal terminal Further, the first metal terminal and the second metal terminal are electrically connected by the quasi-crystalline conductive particles to complete bonding of the array substrate and the IC chip.
  • the surface of the first metal terminal is a concave surface; both sides of the concave surface have a slope, and the movement of the quasi-crystalline conductive particles located on the surface of the first metal terminal can be restricted to avoid the deviation thereof. Moving and gathering between adjacent first metal terminals.
  • inorganic insulating particles are disposed between the two adjacent first metal terminals, and the inorganic insulating particles are used to insulate between the two adjacent first metal terminals, thereby further avoiding a short circuit between the first metal terminals caused by a shift of the quasi-crystalline conductive particles; further, a stack height of the inorganic insulating particles is greater than a height of the first metal terminal.
  • the pitch of the adjacent two first metal terminals is 5-10 times the particle diameter of the quasi-crystalline conductive particles; by increasing the pitch of the adjacent two first metal terminals, the pitch is decreased. The possibility of a short circuit between the first metal terminals.
  • the quasi-crystalline conductive particles have a particle diameter of 6 to 9 ⁇ m.
  • the anisotropic conductive film is pretreated by heating, laser or ultraviolet light irradiation.
  • the beneficial effects of the present invention are: compared to existing
  • the conductive particles provided by the present invention are quasi-crystalline conductive particles. Since the outer shape has a plurality of planes, the flow of the conductive particles in the resin can be restricted, thereby preventing the uneven distribution of the conductive particles caused by the deviation of the conductive particles; Up In the prior art display panel, in the process of binding the IC chip, the conductive particles distributed in the resin set position are displaced due to the fluidity of the resin, thereby causing bump The phenomenon of short circuit, which in turn affects the quality of the display panel.

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Abstract

一种显示装置，其封装区域的导电粒子（105），用于实现阵列基板（101）与IC芯片（106）通过导电胶压接贴合之后，所述阵列基板（101）表面的第一金属端子（103）与所述IC芯片（106）表面的第二金属端子（107）之间的电性连接；所述第一金属端子（103）与所述第二金属端子（107）之间分布有至少三个所述导电粒子（105）；其中，所述导电粒子（105）采用准晶体导电粒子（201）。

Description

显示装置、及阵列基板与 IC 芯片的绑定方法 技术领域
本发明涉及 显示技术领域，尤其涉及显示装置、及阵列基板与IC芯片的绑定方法 。
背景技术
显示面板在模组制程中，需要对 IC 芯片与基板进行绑定。目前的绑定方法主要是将各向异性导电胶（ ACF ）贴在要绑定一端的 bump （金属突起）上，将另一端的 bump 热压接的在 ACF 上，固化后完成绑定制程。
IC 芯片与基板压接之前，各向异性导电膜中的导电粒子均匀分布在树脂中，热压的过程中因温度上升树脂的流动性增大，绑定的压力使 bump 接触处的导电粒子被挤压至空隙中，使空隙处导电粒子密度高于 bump 处，造成短路现象。目前的提高导电粒子利用率的方法主要为在各向异性导电胶中添加无机绝缘粒子，减小导电胶的流动性，但这种方法同时会降低树脂和导电粒子的百分含量，可能造成压接后粘合力减小，压接两端剥离的情况。
综上所述，现有技术的显示面板在绑定 IC 芯片的制程中，分布在树脂设定位置的导电粒子，受树脂流动性影响导致位置偏移，进而造成 bump 间短路的现象，进而影响显示面板的品质 。
 技术问题
本发明提供一种显示装置，在显示装置的封装区域设置准晶体 导电粒子 ，能够减小导电粒子在树脂中的流动性，以解决 现有技术的显示面板在绑定 IC 芯片的制程中，分布在树脂设定位置的导电粒子，受树脂流动性影响导致位置偏移，进而造成 bump 间短路的现象，进而影响显示面板的品质的技术问题。
技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种显示装置，所述显示装置包括：
阵列基板，所述阵列基板表面设置有绑定区域，所述绑定区域内间隔设置有至少三个第一金属端子；
各向异性导电膜，所述各向异性导电膜设置在所述绑定区域表面，所述各向异性导电膜包括树脂层；
导电粒子，所述导电粒子分布于所述树脂层内，所述导电粒子对应分布于所述第一金属端子上方，所述导电粒子为准晶体导电粒子；所述导电粒子形状为正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°；
IC 芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位，所述IC芯片与所述阵列基板绑定。
根据本发明一优选实施例，所述IC芯片通过热压工艺与所述阵列基板的绑定区域结合，以使所述各向异性导电膜受热流化，并使得所述第一金属端子与所述第二金属端子进一步接触，从而使得所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子导通来与所述阵列基板进行绑定。
根据本发明一优选实施例，所述导电粒子用于在实现阵列基板与IC芯片通过导电胶压接贴合之后，使得所述阵列基板表面的
第一金属端子与所述IC芯片表面的第二金属端子之间的电性连接；
所述第一金属端子与所述第二金属端子之间分布有至少三个所述导电粒子；
所述导电粒子用于减小压接过程中所述导电粒子在所述导电胶中的流动性。
本发明提供一种显示装置，所述显示装置包括：
阵列基板，所述阵列基板表面设置有绑定区域，所述绑定区域内间隔设置有至少三个第一金属端子；
各向异性导电膜，所述各向异性导电膜设置在所述绑定区域表面，所述各向异性导电膜包括树脂层；
导电粒子，所述导电粒子分布于所述树脂层内，所述导电粒子对应分布于所述第一金属端子上方，所述导电粒子为准晶体导电粒子；
IC 芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位，所述IC芯片与所述阵列基板绑定。
根据本发明一优选实施例，所述IC芯片通过热压工艺与所述阵列基板的绑定区域结合，以使所述各向异性导电膜受热流化，并使得所述第一金属端子与所述第二金属端子进一步接触，从而使得所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子导通来与所述阵列基板进行绑定。
根据本发明一优选实施例，所述导电粒子用于在实现阵列基板与IC芯片通过导电胶压接贴合之后，使得所述阵列基板表面的第一金属端子与所述IC芯片表面的第二金属端子之间的电性连接；
所述第一金属端子与所述第二金属端子之间分布有至少三个所述导电粒子；
所述导电粒子用于减小压接过程中所述导电粒子在所述导电胶中的流动性。
依据本发明的上述目的，提供一种阵列基板与IC芯片的绑定方法，所述方法包括：
步骤S10，提供一阵列基板，在所述阵列基板表面设置绑定区域，在所述绑定区域内间隔设置至少三个第一金属端子；
步骤S20，在所述绑定区域表面设置各向异性导电膜，所述各向异性导电膜包括树脂层，以及分布于所述树脂层内的导电粒子，所述导电粒子对应分布于所述第一金属端子上方；所述导电粒子采用准晶体导电粒子；
步骤S30，提供一IC芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，将所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位；
步骤S40，通过热压工艺，使所述IC芯片与所述阵列基板的绑定区域进一步结合，所述各向异性导电膜受热流化，使得所述第一金属端子与所述第二金属端子进一步接触，所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子实现导通，完成所述阵列基板与所述IC芯片的绑定。
根据本发明一优选实施例，所述导电粒子形状为正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°。
根据本发明一优选实施例，在所述步骤S10中，所述第一金属端子的表面为凹面。
根据本发明一优选实施例，在所述步骤S10中，相邻两所述第一金属端子之间设置有无机绝缘粒子。
根据本发明一优选实施例，在所述步骤S10中，相邻两所述第一金属端子的间距为所述准晶体导电粒子的粒径的5-10倍。
根据本发明一优选实施例，在所述步骤S20中，所述准晶体导电粒子的粒径为6-9微米。
根据本发明一优选实施例，通过加热、镭射或紫外光照射的方法对所述各向异性导电膜进行预处理。
根据本发明一优选实施例，所述阵列基板为柔性OLED基板。
 有益效果
本发明的有益效果为： 相较于现有显示装置 的封装结构中的导电粒子，本发明所提供的导电粒子，为准晶体导电粒子，因其外形具备多个平面，能够限制导电粒子在树脂中的流动，进而避免导电粒子偏移导致导电粒子分布不均，进而导致位于同一侧的金属端子间短路的问题；解决了 现有技术的显示面板在绑定 IC 芯片的制程中，分布在树脂设定位置的导电粒子，受树脂流动性影响导致位置偏移，进而造成 bump 间短路的现象，进而影响显示面板的品质的技术问题 。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图 1 为本发明提供的显示装置结构示意图；
图 2 为本发明提供的 准晶体导电粒子结构示意图 ；
图 3 为本发明提供的 准晶体导电粒子外圆切面示意图；
图 4 为本发明提供的 准晶体导电粒子 接触面示意图；
图 5 为本发明提供的 准晶体导电粒子形变后外圆切面示意图；
图 6 为本发明提供的阵列基板与 IC 芯片的绑定方法流程图 。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如 [ 上 ] 、 [ 下 ] 、 [ 前 ] 、 [ 后 ] 、 [ 左 ] 、 [ 右 ] 、 [ 内 ] 、 [ 外 ] 、 [ 侧面 ] 等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对 现有技术的显示面板在绑定 IC 芯片的制程中，分布在树脂设定位置的导电粒子，受树脂流动性影响导致位置偏移，进而造成 bump 间短路的现象，进而影响显示面板的品质 ，本实施例能够解决该缺陷 。
如图1所示，本发明提供一种显示装置，包括阵列基板101，所述阵列基板101表面设置有绑定区域102，所述绑定区域102内间隔设置有至少三个第一金属端子103；各向异性导电膜，所述各向异性导电膜设置在所述绑定区域102表面，所述各向异性导电膜包括树脂层104；导电粒子105，所述导电粒子105分布于所述树脂层104内，所述导电粒子105对应分布于所述第一金属端子103上方，所述导电粒子105为准晶体导电粒子；IC芯片106，所述IC芯片106的一侧设置有至少三个与所述第一金属端子103相对应的第二金属端子107，所述IC芯片106与所述绑定区域102对位，且所述第二金属端子107与所述第一金属端子103一一对位，所述IC芯片106与所述阵列基板101绑定。
所述IC芯片106通过热压工艺与所述阵列基板101的绑定区域102结合，以使所述各向异性导电膜受热流化，并使得所述第一金属端子103与所述第二金属端子107进一步接触，从而使得所述第一金属端子103与所述第二金属端子107通过所述准晶体导电粒子导通来与所述阵列基板101进行绑定。
所述导电粒子105用于在实现阵列基板101与IC芯片106通过导电胶压接贴合之后，使得所述阵列基板101表面的第一金属端子103与所述IC芯片106表面的第二金属端子107之间的电性连接；所述第一金属端子103与所述第二金属端子107之间分布有至少三个所述导电粒子105；所述导电粒子105用于减小压接过程中所述导电粒子105在所述导电胶中的流动性。
如图2所示，本发明提供的导电粒子，所述导电粒子用于实现阵列基板与IC芯片通过导电胶压接贴合之后，所述阵列基板表面的第一金属端子与所述IC芯片表面的第二金属端子之间的电性连接；现有技术的导电粒子均为球体，球体表面圆滑，缺少稳固的支撑部位，导电粒子在压缩之后，易于向压迫方向的两侧移动，树脂在高温加热后呈流态，树脂受压迫之后会向周围流动，更加促进球形导电粒子向两侧偏移；而本发明提供的导电粒子采用准晶体导电粒子201。
准晶体，亦称为'准晶'或'拟晶'，是一种介于晶体和非晶体之间的固体结构；在准晶的原子排列中，其结构是长程有序的，这一点和晶体相似；但是准晶不具备平移对称性，这一点又和晶体不同。普通晶体具有的是二次、三次、四次或六次旋转对称性，但是准晶的布拉格衍射图具有其他的对称性，例如五次对称性或者更高的六次以上对称性。因此，准晶体具有多面对称结构。
如图3所示，本发明提供的准晶体导电粒子，所述准晶体导电粒子的外形为帕拉图立体中的正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°；所述准晶体导电粒子的外圆切面中，包括准晶体侧面301及准晶体侧棱a，外圆切面的中心与任意相邻两所述准晶体侧棱a的连接点之间的距离为所述准晶体导电粒子的半径r，其中，半径 r=(31/2+151/2) / 4 × a ，a为所述准晶体侧棱的长度。
如图4所示，相邻两所述准晶体导电粒子之间的接触面为五边形平面，该五边形平面的面积：
S 准晶体 = a 2 ×( 1+cos72° ) × sin72° × a 2 ×( 1+2cos72° ) × 0.3 ，a为五边形平面的边长。
相邻两所述准晶体导电粒子的接触面越大，导电粒子间的吸引力越大，多个所述准晶体导电粒子结合在一起则更加稳固，不易受外力影响至偏移。
如图5所示，所述准晶体导电粒子的外圆切面中，包括准晶体侧面501及准晶体侧棱a，当所述准晶体导电粒子受应力压缩发生形变，其形变率为60%～80%，在其形变率均值70%的理想形变下接触面积 S 形变球体 = 0.91 ×π×r 2 = (9+3 × 51/2 ) / 8 × a 2 ，a为准晶体侧棱长度。
量化后 S 准晶体 = 1.73 × a 2 ＜ 1.963 × a 2 = S 形变球体 ，a为准晶体侧棱长度。准晶体结构较为稳定，但因原材的性质存在一定的形变率，将此形变率最大化为80%时，准晶体水平斜面最大倾角θ= 162° ＜ 180° ，且保持较大的反应率。
当所述准晶体导电粒子压缩形变之后，产生形变角402，所述准晶体导电粒子水平斜面倾角减小，且所述准晶体导电粒子的横向长度边长，从而增加了所述准晶体导电粒子的支撑面积，减小滚动惯性。
依据本发明的上述目的，如图6所示，提供一种阵列基板与IC芯片的绑定方法，所述方法包括以下步骤：
步骤S10，提供一阵列基板，在所述阵列基板表面设置绑定区域，在所述绑定区域内间隔设置至少三个第一金属端子。
步骤S20，在所述绑定区域表面设置各向异性导电膜，所述各向异性导电膜包括树脂层，以及分布于所述树脂层内的导电粒子，所述导电粒子对应分布于所述第一金属端子上方；所述导电粒子采用准晶体导电粒子。
步骤S30，提供一IC芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，将所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位。
步骤S40，通过热压工艺，使所述IC芯片与所述阵列基板的绑定区域进一步结合，所述各向异性导电膜受热流化，使得所述第一金属端子与所述第二金属端子进一步接触，所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子实现导通，完成所述阵列基板与所述IC芯片的绑定。
所述导电粒子形状为正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°。
在所述步骤S10中，所述第一金属端子的表面为凹面；所述凹面的两侧具有坡度，能够对位于所述第一金属端子表面的准晶体导电粒子的移动进行限制，避免其偏移并聚集在相邻所述第一金属端子之间。
在所述步骤S10中，相邻两所述第一金属端子之间设置有无机绝缘粒子，所述无机绝缘粒子用以使得相邻两所述第一金属端子之间绝缘，进一步避免因所述准晶体导电粒子的偏移导致的所述第一金属端子间的短路；进一步，所述无机绝缘粒子的堆叠高度大于所述第一金属端子的高度。
在所述步骤S10中，相邻两所述第一金属端子的间距为所述准晶体导电粒子的粒径的5-10倍；通过增加相邻两所述第一金属端子的间距，减小所述第一金属端子间短路的可能性。
在所述步骤S20中，所述准晶体导电粒子的粒径为6-9微米。
通过加热、镭射或紫外光照射的方法对所述各向异性导电膜进行预处理。
本发明的有益效果为： 相较于现有 的导电粒子，本发明所提供的导电粒子，为准晶体导电粒子，因其外形具备多个平面，能够限制导电粒子在树脂中的流动，进而避免导电粒子偏移导致导电粒子分布不均；解决了 现有技术的显示面板在绑定 IC 芯片的制程中，分布在树脂设定位置的导电粒子，受树脂流动性影响导致位置偏移，进而造成 bump 间短路的现象，进而影响显示面板的品质的技术问题 。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准 。

Claims (12)

  1. 一种显示装置，其中，所述显示装置包括：
    阵列基板，所述阵列基板表面设置有绑定区域，所述绑定区域内间隔设置有至少三个第一金属端子；
    各向异性导电膜，所述各向异性导电膜设置在所述绑定区域表面，所述各向异性导电膜包括树脂层；
    导电粒子，所述导电粒子分布于所述树脂层内，所述导电粒子对应分布于所述第一金属端子上方，所述导电粒子为准晶体导电粒子；所述导电粒子形状为正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°；
    IC芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位，所述IC芯片与所述阵列基板绑定。
  2. 根据权利要求1所述的显示装置，其中，所述IC芯片通过热压工艺与所述阵列基板的绑定区域结合，以使所述各向异性导电膜受热流化，并使得所述第一金属端子与所述第二金属端子进一步接触，从而使得所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子导通来与所述阵列基板进行绑定。
  3. 根据权利要求1所述的显示装置，其中，所述导电粒子用于在实现阵列基板与IC芯片通过导电胶压接贴合之后，使得所述阵列基板表面的第一金属端子与所述IC芯片表面的第二金属端子之间的电性连接；
    所述第一金属端子与所述第二金属端子之间分布有至少三个所述导电粒子；
    所述导电粒子用于减小压接过程中所述导电粒子在所述导电胶中的流动性。
  4. 一种显示装置，其中，所述显示装置包括：
    阵列基板，所述阵列基板表面设置有绑定区域，所述绑定区域内间隔设置有至少三个第一金属端子；
    各向异性导电膜，所述各向异性导电膜设置在所述绑定区域表面，所述各向异性导电膜包括树脂层；
    导电粒子，所述导电粒子分布于所述树脂层内，所述导电粒子对应分布于所述第一金属端子上方，所述导电粒子为准晶体导电粒子；
    IC芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位，所述IC芯片与所述阵列基板绑定。
  5. 根据权利要求4所述的显示装置，其中，所述IC芯片通过热压工艺与所述阵列基板的绑定区域结合，以使所述各向异性导电膜受热流化，并使得所述第一金属端子与所述第二金属端子进一步接触，从而使得所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子导通来与所述阵列基板进行绑定。
  6. 根据权利要求4所述的显示装置，其中，所述导电粒子用于在实现阵列基板与IC芯片通过导电胶压接贴合之后，使得所述阵列基板表面的第一金属端子与所述IC芯片表面的第二金属端子之间的电性连接；
    所述第一金属端子与所述第二金属端子之间分布有至少三个所述导电粒子；
    所述导电粒子用于减小压接过程中所述导电粒子在所述导电胶中的流动性。
  7. 一种阵列基板与IC芯片的绑定方法，其中，所述方法包括：
    步骤S10，提供一阵列基板，在所述阵列基板表面设置绑定区域，在所述绑定区域内间隔设置至少三个第一金属端子；
    步骤S20，在所述绑定区域表面设置各向异性导电膜，所述各向异性导电膜包括树脂层，以及分布于所述树脂层内的导电粒子，所述导电粒子对应分布于所述第一金属端子上方；所述导电粒子采用准晶体导电粒子；
    步骤S30，提供一IC芯片，所述IC芯片的一侧设置有至少三个与所述第一金属端子相对应的第二金属端子，将所述IC芯片与所述绑定区域对位，且所述第二金属端子与所述第一金属端子一一对位；
    步骤S40，通过热压工艺，使所述IC芯片与所述阵列基板的绑定区域进一步结合，所述各向异性导电膜受热流化，使得所述第一金属端子与所述第二金属端子进一步接触，所述第一金属端子与所述第二金属端子通过所述准晶体导电粒子实现导通，完成所述阵列基板与所述IC芯片的绑定。
  8. 根据权利要求7所述的绑定方法，其中，所述导电粒子形状为正五角十二面体，所述导电粒子的每一平面的水平斜面倾角θ=120°。
  9. 根据权利要求7所述的绑定方法，其中，在所述步骤S10中，所述第一金属端子的表面为凹面。
  10. 根据权利要求7所述的绑定方法，其中，在所述步骤S10中，相邻两所述第一金属端子之间设置有无机绝缘粒子。
  11. 根据权利要求7所述的绑定方法，其中，在所述步骤S10中，相邻两所述第一金属端子的间距为所述准晶体导电粒子的粒径的5-10倍。
  12. 根据权利要求11所述的绑定方法，其中，在所述步骤S20中，所述准晶体导电粒子的粒径为6-9微米。
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