WO2019064369A1 - Dispositif codeur, émetteur, dispositif décodeur et récepteur - Google Patents

Dispositif codeur, émetteur, dispositif décodeur et récepteur Download PDF

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Publication number
WO2019064369A1
WO2019064369A1 PCT/JP2017/034928 JP2017034928W WO2019064369A1 WO 2019064369 A1 WO2019064369 A1 WO 2019064369A1 JP 2017034928 W JP2017034928 W JP 2017034928W WO 2019064369 A1 WO2019064369 A1 WO 2019064369A1
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Prior art keywords
error correction
data
code
encoding
parity
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PCT/JP2017/034928
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English (en)
Japanese (ja)
Inventor
吉田　英夫
慎也 平栗
俊之 久世
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US16/648,841 priority Critical patent/US11115058B2/en
Priority to EP17927721.5A priority patent/EP3691131A4/fr
Priority to EP23163725.7A priority patent/EP4220967A1/fr
Priority to PCT/JP2017/034928 priority patent/WO2019064369A1/fr
Priority to EP23163733.1A priority patent/EP4220968A1/fr
Priority to JP2019545441A priority patent/JP6921216B2/ja
Publication of WO2019064369A1 publication Critical patent/WO2019064369A1/fr
Priority to JP2021098935A priority patent/JP7199474B2/ja

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1575—Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2921—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes wherein error correction coding involves a diagonal direction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2945—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using at least three error correction codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present invention relates to an encoding device, a transmitter, a decoding device and a receiver.
  • error correction codes are generally applied as an effective method for achieving high transmission capacity and long distance transmission.
  • the error correction code is a technology used in a wired communication system, a wireless communication system, a storage device, and the like.
  • the error correction code is a technology that makes it possible to correct an error even if an error occurs in received data by adding redundant bits to digital data sent out on the transmission side.
  • Non-Patent Document 1 an error correction code of a concatenated code scheme in which an LDPC code is an inner code and a BCH code is an outer code is adopted.
  • DVD-S2 is an abbreviation for DVB system for Satellite broadcasting and unicasting, 2nd generation.
  • DVD is an abbreviation for Digital Video Broadcasting.
  • LDPC is an abbreviation for Low Density Parity Check.
  • BCH is an abbreviation for Bose-Chaudhuri-Hocquenghem.
  • Non-Patent Document 2 shows a satellite transmission scheme using the DVB-S2 scheme.
  • the DVB-S2 BB frame is configured of an 80-bit fixed length BB header including control information, user data, and padding for adjusting the frame length.
  • BB is an abbreviation of BaseBand.
  • BCH coding is performed on BB frames. As a result, parity of BCH code is generated. The parity of the BCH code is added to the BB frame. This yields a BCH coded block.
  • LDPC encoding is performed. As a result, parity of the LDPC code is generated. The parity of the LDPC code is added to the BCH code block. Thereby, an LDPC coded block is obtained.
  • An LDPC coded block is modulated and transmitted after bit interleaving according to a modulation mode.
  • an LDPC coded block is obtained from the received and demodulated signal after bit deinterleaving according to the modulation mode.
  • the LDPC coded block is decoded by an LDPC code which is an inner code.
  • an error-corrected BCH coded block is obtained with an LDPC code.
  • decoding is performed using a BCH code which is an outer code. As a result, a BB frame in which an error that could not be corrected by the LDPC code is corrected is output.
  • a plurality of LDPC coding rates are prepared.
  • the BB frame length and the BCH parity bit length differ depending on the coding rate.
  • the BB frame length is a length divisible by 8 bits. Eight bits correspond to one octet.
  • An LDPC code is known as a code having a high correction capability. However, it is also known that an error floor occurs.
  • the error floor is a phenomenon in which the BER can not be improved even if the transmission power is increased.
  • "BER" is an abbreviation for Bit Error Rate.
  • a BCH code which is a type of block code, is used for the outer code.
  • Non-Patent Document 3 in the case of DVB-S2, when the SNR becomes higher than a predetermined level, a phenomenon occurs in which the correction effect by the concatenated code becomes loose. That is, in DVB-S2, an error floor still occurs.
  • SNR is an abbreviation for Signal to Noise Ratio. For further high speed transmission, more reliable correction capability and burst correction capability are required.
  • Patent Document 1 shows a configuration in which an interleave circuit is inserted between a coding circuit of a BCH code, which is an outer code, and a coding circuit of an LDPC code, which is an inner code, in order to avoid the occurrence of an error floor. ing.
  • Patent Document 2 data protected by an error correction code of MPE-FEC, which is prepared independently of DVB-S2, is divided into a plurality of packets to which a CRC is added, and then transmitted by a BB frame. There is shown a method of detecting an error remaining after decoding of -S2 by CRC.
  • MPE is an abbreviation for Multi-Protocol Encapsulation.
  • FEC is an abbreviation for Forward Error Correction.
  • CRC Cyclic Redundancy Check.
  • An object of the present invention is to make it possible to exhibit reliable correction capability and burst-correction capability even in high-speed transmission.
  • An encoding apparatus is The parity of the first error correction code is generated by encoding each first data sequence existing along a direction different from the row direction of the input data, which is regarded as one matrix, using a first error correction code, A first encoding unit that generates encoded data by adding the parity of the first error correction code to each first data sequence, and extends the matrix as a result; Generating parity of the second error correction code by encoding each second data sequence existing along the row direction of the encoded data generated by the first encoding unit using a second error correction code; And a second encoding unit that generates a plurality of frames including one data sequence existing along the row direction of the encoded data and one corresponding parity of the second error correction code per frame.
  • the decoding device is A plurality of frames including one data sequence existing along the row direction of the encoded data, which is regarded as one matrix per frame, and the parity of the corresponding second error correction code are obtained, and in the row direction of the encoded data A second error correction unit that performs error correction using the parity of the second error correction code on each second data sequence existing along the second data sequence; The parity of the first error correction code added to each first data sequence existing along the direction different from the row direction of the encoded data subjected to the error correction by the second error correction unit is obtained, And a first error correction unit that performs error correction on the first data sequence using the parity of the first error correction code.
  • the present invention by applying the first error correction code in a direction different from that of the second error correction code, even in high-speed transmission, it is possible to exhibit highly reliable correction capability and burst correction capability. Become.
  • FIG. 1 is a block diagram showing the configuration of a communication system according to Embodiment 1;
  • FIG. 2 is a block diagram showing an exemplary configuration of a part of the encoding apparatus according to Embodiment 1.
  • FIG. 2 is a block diagram showing an exemplary configuration of a part of the decoding apparatus according to Embodiment 1.
  • FIG. 6 is a diagram showing a flow of processing performed by the coding apparatus according to Embodiment 1 and a configuration of an obtained frame.
  • FIG. 7 is a diagram showing an example of assignment of encoded data to a frame according to the first embodiment.
  • FIG. 7 is a block diagram showing the configuration of a communication system according to a modification of the first embodiment.
  • FIG. 7 is a diagram showing the flow of processing performed by the coding apparatus according to Embodiment 2 and the configuration of an obtained frame.
  • FIG. 14 is a block diagram showing an example of a configuration of a part of the decoding apparatus according to Embodiment 3.
  • 16 is a flowchart showing a flow of processing performed by the decoding device according to the third embodiment.
  • FIG. 16 is a diagram showing the flow of processing performed by the coding apparatus according to Embodiment 4 and the configuration of an obtained frame.
  • FIG. 16 is a diagram showing an example of allocation of coded data to a frame according to a fourth embodiment.
  • FIG. 16 is a diagram showing the flow of processing performed by the coding apparatus according to Embodiment 5 and the configuration of an obtained frame;
  • FIG. 18 is a diagram showing an example of allocation of coded data to a frame according to a fifth embodiment.
  • FIG. 18 is a diagram showing the configuration of a header area of a frame according to a fifth embodiment.
  • FIG. 16 is a block diagram showing the configuration of a communication system according to a sixth embodiment.
  • FIG. 18 is a diagram showing an example of allocation of coded data to a frame according to a sixth embodiment.
  • Embodiment 1 The present embodiment will be described with reference to FIGS. 1 to 5.
  • the communication system 10 comprises a transmitter 11 and a receiver 12.
  • the transmitter 11 comprises an encoding device 20.
  • the transmitter 11 may be any device as long as it transmits a plurality of frames obtained from the encoding device 20 to the outside, but in the present embodiment it is a satellite station.
  • the receiver 12 comprises a decoding device 30.
  • the receiver 12 may be any device as long as it receives a plurality of frames from the outside and provides the plurality of frames to the decoding device 30, but in the present embodiment it is a ground station.
  • the frame transmitted / received between the transmitter 11 and the receiver 12 is the DVB-S2 frame 13 in this embodiment, but it may be a DVB-S2X frame which is an evolution system of DVB-S2, or DVB-T2 Or, it may be a frame of another transmission method such as ISDB-S3.
  • DVB-S2X is an abbreviation of DVB-S2 Extensions.
  • DVD-T2 is an abbreviation of DVB system for Terrestrial broadcasting, 2nd generation.
  • ISDB-S3 is an abbreviation for Integrated Services Digital Broadcasting for Satellite, 3rd generation.
  • the communication system 10 is not only communication between the ground station and the satellite station, but also data transmission for satellite communication such as between the satellite communication portable terminal (ground terminal) and the satellite station or between the satellite station and the satellite station.
  • the receiver 12 is a satellite communication portable terminal or a satellite station.
  • the encoding device 20 of the transmitter 11 includes a first encoding unit 21, a second encoding unit 22, and an insertion unit 23.
  • the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 are realized by hardware.
  • the encoding device 20 includes hardware such as an electronic circuit 24.
  • the electronic circuit 24 is dedicated hardware that implements the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23.
  • the electronic circuit 24 is, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, a logic IC, a GA, an FPGA or an ASIC.
  • IC is an abbreviation for Integrated Circuit.
  • GA is an abbreviation of Gate Array.
  • FPGA is an abbreviation of Field-Programmable Gate Array.
  • ASIC is an abbreviation for Application Specific Integrated Circuit.
  • the encoding device 20 may include a plurality of electronic circuits that replace the electronic circuit 24.
  • the plurality of electronic circuits implement the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 as a whole.
  • Each electronic circuit is, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, a logic IC, a GA, an FPGA or an ASIC.
  • the decoding device 30 of the receiver 12 includes a first error correction unit 31, a second error correction unit 32, and a detection unit 33.
  • the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 are realized by hardware.
  • the decoding device 30 includes hardware such as an electronic circuit 34.
  • the electronic circuit 34 is dedicated hardware that implements the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33.
  • the electronic circuit 34 is, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, a logic IC, a GA, an FPGA or an ASIC.
  • the decoding device 30 may include a plurality of electronic circuits that replace the electronic circuit 34.
  • the plurality of electronic circuits realize the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 as a whole.
  • Each electronic circuit is, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, a logic IC, a GA, an FPGA or an ASIC.
  • the first encoding unit 21 has an input terminal 41 of input data 61, an RS encoding circuit 42 that performs RS encoding, an input terminal 43 and an output terminal 44 of the RS encoding circuit 42, and an output terminal.
  • a connection terminal 45 connected to the connection terminal 44, a connection terminal 46 connected to the input terminal 41, and a connection terminal 47 selectively connected to the connection terminal 45 and the connection terminal 46 are provided.
  • "RS" is an abbreviation of Reed-Solomon.
  • the number of RS encoding circuits 42 is K. Therefore, the number of input terminals 43 and output terminals 44 is also K.
  • the connection terminal 47 corresponds to the selector 63.
  • the insertion unit 23 includes an ASM generation circuit 48 that generates an ASM, and an output terminal 49 of the ASM generation circuit 48.
  • ASM is an abbreviation for Attached Synchronization Marker.
  • the first encoding unit 21 further includes an output terminal 50 selectively connected to the connection terminal 47 and the output terminal 49.
  • the detection unit 33 includes an ASM detection circuit 51 that detects an ASM from the DVB-S2 frame 13.
  • the first error correction unit 31 has an input terminal 52 of data to be decoded, an RS decoding circuit 53 corresponding to the RS encoding circuit 42, an input terminal 54 and an output terminal 55 of the RS decoding circuit 53, and an output terminal 55. And an output terminal 56 connected thereto.
  • the number of RS decoding circuits 53 is K. Therefore, the number of input terminals 54 and output terminals 55 is also K.
  • an RS code is used as the first error correction code
  • a concatenated code is used as the second error correction code.
  • the concatenated code a combination of a BCH code which is an outer code and an LDPC code which is an inner code is used according to DVB-S2.
  • the first error correction code may be an error correction code other than the RS code, such as an extended RS code.
  • the second error correction code may be an error correction code other than the combination of the BCH code and the LDPC code, as long as the transmission method used between the transmitter 11 and the receiver 12 is other than DVB-S2, It may be an error correction code.
  • the first error correction code is an RS code with a code length of 255 symbols and an information length of 253 symbols that can be corrected by one symbol, where one octet is one symbol. That is, the first error correction code is an RS code with a code length of 255 octets and an information length of 253 octets.
  • the length of the user data area 67 "DATA FIELD" of the DVB-S2 frame 13 is K octets.
  • the code length and information length of the RS code may be changed as appropriate.
  • the input data 61 is encoded in block units of 253 ⁇ K octets.
  • the RS encoding circuit 42 provided in parallel in K generates parity of RS code each time one block of input data 61 is encoded.
  • the selector 63 selects and outputs the input data 61 and the parity of the RS code.
  • interleaved encoded data 64 of 255 ⁇ K octets is obtained.
  • an identifier 65 which is a synchronization signal for identifying the beginning of the encoded data 64, is added.
  • the identifier 65 is ASM shown by the nonpatent literature 2 in this embodiment.
  • the encoded data 64 to which the identifier 65 is added is inserted into the user data area 67 "DATA FIELD" of the DVB-S2 frame 13 in K octet units.
  • a header area 66 "BBHEADER” containing control information As data elements constituting the DVB-S2 frame 13, a header area 66 "BBHEADER” containing control information, a user data area 67 "DATA FIELD” of K octets, and a parity area of BCH code which is an outer code
  • the input data 61 is input to the encoded data 64 through the selector 63 in octet units, and is input to the RS encoding circuit 42 that generates the parity of K RS codes in K octet cycles. Be done.
  • the storage element of parity of one RS code is at most 2 octets.
  • an ASM is added as an identifier 65 serving as a delimiter of the encoded data 64.
  • the length of the ASM is preferably a multiple of octets, such as 4 octets, since the RS code is 1 symbol and 1 octet.
  • ASM and encoded data 64 are allocated to the user data area 67 “DATA FIELD” of K octets of the DVB-S2 frame 13.
  • K RS code sequences that is, four code sequences can not be allocated to one DVB-S2 frame 13 because ASM is 4 octets, since ASM is also inserted.
  • these four code sequences are assigned to the next DVB-S2 frame 13, so there is no problem.
  • the insertion of information in the header area 66 to construct the DVB-S2 frame 13, the generation of the parity of the BCH code, and the generation of the LDPC code parity are conventional.
  • FIG. 5 shows an example of allocation of the encoded data 64 to the DVB-S2 frame 13.
  • the encoded data 64 is regarded as a small block 70 in units of one octet except for the ASM.
  • the upper stage is the block number of the encoded data 64
  • the middle stage is the RS code sequence number
  • the lower stage is the RS code input number.
  • the small block 70 at the top of the encoded data 64 identified by “BL1” is “1” in which the upper row indicates “BL1”, the middle row indicates the first RS code sequence, and the lower row indicates the first symbol. It is 1 ".
  • the last small block 70 of the encoded data 64 identified by "BL1" is "K” in which the upper row is “BL1”, the middle row is the K-th RS code sequence, and "255" in which the lower row is the 255th symbol. It is.
  • the 254th and 255th symbols are parity symbols of the RS code.
  • the ASM is inserted in the user data area 67 “DATA FIELD” of the top DVB-S2 frame 13. Therefore, up to the leading symbol of the K-4th RS code sequence is input to the user data area 67 "DATA FIELD” of K octets.
  • the leading symbol of the K-3rd RS code sequence is assigned to the beginning of the user data area 67 “DATA FIELD” of the next DVB-S2 frame 13.
  • each RS code sequence is assigned only one symbol or less. Therefore, even if an error remains in the whole of one DVB-S2 frame 13, it is an error of at most one symbol, that is, an error of one octet, from the viewpoint of the RS code sequence.
  • the input data 61 of 253 ⁇ K octets is input to the input terminal 41 in octet units. Since an RS code with a code length of 255 octets and an information length of 253 octets is used, the RS encoding circuit 42 only needs a storage circuit for parity operation of 2 octets each.
  • the data input from the input terminal 41 is input from the input terminal 43 of one of the RS encoding circuits 42, and through the connection terminal 46, the connection terminal 47 and the output terminal 50, the user data area 67 of the DVB-S2 frame 13. It is output to "DATA FIELD".
  • the ASM generation circuit 48 outputs the ASM to the user data area 67 "DATA FIELD" of the DVB-S2 frame 13 through the connection terminal 47 and the output terminal 50 in octet units through the output terminal 49.
  • DATA FIELD DATA FIELD
  • the ASM a unique number having regularity, such as an increment pattern or the like, capable of ARQ for each block of the input data 61 may be partially included.
  • ARQ is an abbreviation for Automatic Repeat Request.
  • the output terminal 44 of the RS encoding circuit 42 is switched for each octet output and connected to the connection terminal 45, and further through the connection terminal 47 and the output terminal 50 Parity is output sequentially in octet units.
  • the input data 61 can be output to the DVB-S2 frame 13 without having to be temporarily stored, and the RS encoding circuit 42 has a storage circuit for storing a slight parity of the RS code. Good. If the input is performed in the same unit as the RS code symbol, it is possible to share the operation circuit and perform the operation and output while toggling the primary holding memory of the parity of the RS code.
  • a plurality of RS symbols may be simultaneously input instead of the input in octet units corresponding to the RS code symbols. If the number of symbols to be input is a divisor of K, it is possible to share arithmetic circuits for the input symbols and perform arithmetic and output while toggling the primary retention memory of the parity of the RS code.
  • the first encoding unit 21 distributes the input data 61 into a plurality of first data sequences in units of one symbol or less.
  • the first encoding unit 21 generates parity of the RS code for each first data sequence by encoding each first data sequence using an RS code.
  • the second encoding unit 22 divides the encoded data 64 including the input data 61 and the parity generated by the first encoding unit 21 into a plurality of second data sequences in units of data transmission.
  • the second encoding unit 22 generates the parity of the BCH code and the LDPC code for each second data sequence by encoding each second data sequence with the BCH code and the LDPC code.
  • the second encoding unit 22 outputs a plurality of DVB-S2 frames 13 including one second data sequence and a corresponding parity per DVB-S2 frame 13.
  • the first encoding unit 21 distributes the input data 61 into K first data sequences in symbol units. At the time of the distribution, the first encoding unit 21 distributes, to the common first data sequence, a symbol group included in the input data 61 and to which the relative position in each second data sequence matches. The first encoding unit 21 compares the parity corresponding to each first data sequence with the parity corresponding to each first data sequence and the symbol group allocated to each first data sequence in each second data sequence.
  • the encoded data 64 is generated by linking to the input data 61 in the order in which the positions will match.
  • the first encoding unit 21 generates parity of a plurality of symbols as parity of RS code for each first data sequence.
  • the first encoding unit 21 distributes the parity corresponding to each first data sequence to a plurality of parity sequences in symbol units.
  • the first encoding unit 21 generates a data block by concatenating the plurality of parity sequences with the input data 61.
  • the number of parity symbols of the RS code may be any number, but is two in the present embodiment.
  • the inserting unit 23 adds an identifier 65 for identifying the block head of the input data 61 to the head of the encoded data 64.
  • the second encoding unit 22 divides the encoded data 64 including the identifier 65 inserted by the insertion unit 23 into a plurality of second data sequences.
  • the first encoding unit 21 sets each of the first data sequences existing along a direction different from the row direction of the input data 61 which is captured as one matrix.
  • the parity of the RS code is generated by encoding with the RS code.
  • the first encoding unit 21 generates encoded data 64 by adding the parity of the RS code to each first data sequence, and expands the matrix as a result.
  • the second encoding unit 22 encodes each second data sequence existing along the row direction of the encoded data 64 generated by the first encoding unit 21 with the BCH code and the LDPC code, thereby generating the BCH code and the BCH code. Generate parity of LDPC code.
  • the second encoding unit 22 generates a plurality of DVB-S2 frames including one data sequence existing along the row direction of the encoded data 64 per one DVB-S2 frame 13 and the corresponding BCH code and parity of the LDPC code. Generate 13.
  • the data elements present in each row of each first data series have a data length of 1 symbol or less. Specifically, data elements present in each row of each first data sequence have a data length of one symbol.
  • Each first data series exists along the column direction of the input data 61.
  • the first encoding unit 21 generates the encoded data 64 and, as a result, expands the matrix in the column direction.
  • the matrix of 253 rows and K columns is expanded to 255 rows and K columns.
  • the insertion unit 23 inserts an identifier 65 for identifying the beginning of the coded data 64 into the first row of the coded data 64, and shifts the matrix as a result.
  • each row of the matrix expanded to 255 rows and K columns is shifted to the right by 4 columns.
  • Each second data sequence is generated along the row direction of the encoded data 64 generated by the first encoding unit 21 and into which the identifier has been inserted by the insertion unit 23.
  • the first encoding unit 21 encodes RS code parity by encoding the first data sequence of the number according to the length of the user data area 67 of one DVB-S2 frame 13 using RS code parity. Generate The first encoding unit 21 inserts each data sequence existing along the row direction of the encoded data 64 into the user data area 67 of each DVB-S2 frame 13.
  • the operation of the decoding device 30 according to the present embodiment is the reverse of the operation of the coding device 20.
  • the operation of the decoding device 30 corresponds to the decoding method according to the present embodiment.
  • the ASM detection circuit 51 detects the ASM from the user data area 67 “DATA FIELD” of the DVB-S2 frame 13 to detect the beginning of the block of the input data 61 on the encoding side.
  • the ASM detection circuit 51 performs initialization of the connection from the input terminal 52 to the input terminals 54 of the K RS decoding circuits 53 by detecting the beginning of the block of the input data 61 and also performs input terminals 54 in octet units. It controls that the initialization of the input to the K RS decoding circuits 53, which are input more, is performed at each input timing.
  • the RS decoding circuit 53 outputs the decoded data corrected at the output timing in units of octets from the output terminal 55 as the user data 62 through the output terminal 56 due to a fixed processing delay.
  • the RS decoding circuit 53 adds the decoding processing delay from the syndrome to the code length of 255 symbols or the information length of 253 symbols necessary for syndrome operation. A delay memory and a storage circuit for 2 octet syndrome calculation are required. However, the processing delay is small because the 2-octet syndrome immediately obtains the maximum correction capability of the 1-octet error position and the magnitude of the error.
  • each RS decoding circuit 53 can obtain an error position and its size immediately after the syndrome operation, so that it is a relatively small delay memory in which the decoding processing delay is added to the code length or the information length. , Decoding and output. If the input is performed in the same unit as the RS code symbol, it is also possible to share the operation circuit and perform decoding and output while toggling the holding memory for syndrome operation.
  • a plurality of RS symbols may be simultaneously input instead of the input in octet units corresponding to the RS code symbols. If the number of symbols to be input is a divisor of K, a syndrome operation and a memory for input data for the processing delay are necessary, but the arithmetic circuit for decoding is shared, and the primary holding of the RS code syndrome is performed. It is also possible to decode and output while toggling memory.
  • the second error correction unit 32 includes one data sequence existing along the row direction of the encoded data 64 and the corresponding one, which are captured as one matrix per one DVB-S2 frame 13. A plurality of DVB-S2 frames 13 including BCH code and parity of LDPC code are obtained. The second error correction unit 32 performs error correction on each second data sequence existing along the row direction of the encoded data 64 using the parity of the BCH code and the LDPC code.
  • the first error correction unit 31 is a parity of the RS code added to each first data sequence existing along a direction different from the row direction of the encoded data 64 subjected to the error correction by the second error correction unit 32. Get The first error correction unit 31 performs error correction on each first data sequence using the parity of the RS code.
  • a plurality of RS code sequences with small redundant bits corresponding to the user data length of DVB-S2 are generated and dispersed into a plurality of DVB-S2 frames 13.
  • An ASM is inserted at the beginning of a block composed of a plurality of RS code sequences dispersed in a plurality of DVB-S2 frames 13.
  • the beginning of a block in which a plurality of RS code sequences are dispersed is recognized by ASM, and error correction is performed by the RS code.
  • the frame header and information bit sequence input to the BCH code which is the outer code of DVB-S2 is generated as it is, and a slight RS code parity is generated before BCH coding and added.
  • a slight RS code parity is generated before BCH coding and added.
  • the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 of the encoding device 20 are realized by hardware, but as a modification, the first encoding unit 21, The functions of the second encoding unit 22 and the insertion unit 23 may be realized by software.
  • the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 of the decoding device 30 are also realized by hardware, but as a similar modification, the first error correction unit 31
  • the functions of the second error correction unit 32 and the detection unit 33 may be realized by software. The difference between this modification and the present embodiment will be mainly described for such a modification.
  • the encoding device 20 is a computer.
  • the encoding device 20 includes hardware such as a processor 25 and a memory 26.
  • the processor 25 is connected to other hardware via a signal line to control the other hardware.
  • the processor 25 is a device that executes an encoding program.
  • the encoding program is a program for realizing the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23.
  • the processor 25 is, for example, a CPU or a DSP.
  • CPU is an abbreviation for Central Processing Unit.
  • DSP is an abbreviation of Digital Signal Processor.
  • the memory 26 is a device that stores an encoding program.
  • the memory 26 is, for example, a flash memory or a RAM.
  • RAM is an abbreviation for Random Access Memory.
  • the encoding program is read into the processor 25 and executed by the processor 25.
  • the memory 26 stores not only the encoding program but also the OS. "OS” is an abbreviation of Operating System.
  • the processor 25 executes the encoding program while executing the OS.
  • the encoding device 20 may include a plurality of processors that replace the processor 25.
  • the plurality of processors share the execution of the encoding program.
  • Each processor is, for example, a CPU or a DSP.
  • Data, information, signal values and variable values used, processed or output by the encoding program are stored in the memory 26 or in a register or cache memory in the processor 25.
  • the encoding program is a program that causes a computer to execute the processing performed by the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 as a first encoding process, a second encoding process, and an insertion process, respectively. .
  • the encoding program causes the computer to execute the procedures performed by the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 as a first encoding procedure, a second encoding procedure, and an insertion procedure, respectively. It is.
  • the encoding program may be recorded and provided on a computer readable medium, may be stored and provided on a recording medium, and may be provided as a program product.
  • the decryption device 30 is also a computer.
  • the decoding device 30 includes hardware such as a processor 35 and a memory 36.
  • the processor 35 is connected to other hardware via signal lines and controls the other hardware.
  • the processor 35 is a device that executes a decryption program.
  • the decoding program is a program for realizing the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33.
  • the processor 35 is, for example, a CPU or a DSP.
  • the memory 36 is a device that stores a decryption program.
  • the memory 36 is, for example, a flash memory or a RAM.
  • the decoding program is read into the processor 35 and executed by the processor 35.
  • the memory 36 stores not only the decryption program but also the OS.
  • the processor 35 executes the decryption program while executing the OS.
  • decryption program may be incorporated into the OS.
  • the decoding device 30 may include a plurality of processors that replace the processor 35.
  • the plurality of processors share the execution of the decoding program.
  • Each processor is, for example, a CPU or a DSP.
  • Data, information, signal values and variable values used, processed or output by the decoding program are stored in the memory 36 or in a register or cache memory in the processor 35.
  • the decoding program is a program that causes a computer to execute the processing performed by the first error correction unit 31, the second error correction unit 32, and the detection unit 33 as a first error correction process, a second error correction process, and a detection process, respectively.
  • the decoding program is a program that causes the computer to execute the procedures performed by the first error correction unit 31, the second error correction unit 32, and the detection unit 33 as the first error correction procedure, the second error correction procedure, and the detection procedure, respectively.
  • the decryption program may be recorded on a computer readable medium and provided, may be stored and provided on a recording medium, and may be provided as a program product.
  • the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 of the encoding device 20 may be realized by a combination of software and hardware. That is, part of the functions of the first encoding unit 21, the second encoding unit 22, and the insertion unit 23 may be realized by dedicated hardware, and the remaining may be realized by software.
  • the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 of the decoding device 30 may also be realized by a combination of software and hardware. That is, part of the functions of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 may be realized by dedicated hardware, and the rest may be realized by software.
  • the electronic circuit 24, the processor 25, the electronic circuit 34 and the processor 35 are all processing circuits. That is, even if the configuration of the encoding device 20 is the configuration shown in FIG. 1 or FIG. 6, the operations of the first encoding unit 21, the second encoding unit 22 and the insertion unit 23 It will be. Regardless of whether the configuration of the decoding device 30 is shown in FIG. 1 or FIG. 6, the operations of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 are performed by the processing circuit.
  • one symbol is an RS code of one octet
  • the number of dispersed codes matches the size K of the user data area 67 of the DVB-S2 frame 13 and an error is made in one DVB-S2 frame Even if it remains, correction is guaranteed.
  • As a method of correcting errors of the continuous DVB-S2 frame 13 in a larger range there is a method of performing dispersion with the number of code words larger than K.
  • the size K of the user data area 67 of the DVB-S2 frame 13 changes according to the coding rate of the LDPC code. Therefore, in consideration of the maximum user data length of the DVB-S2 frame 13, it is possible to set the number of code words to a fixed number L without being influenced by the coding rate of the LDPC code.
  • one symbol is an RS code of one octet and the maximum code length is 255 symbols
  • the user data area 67 of the DVB-S2 frame 13 has a data length in octet units, but there is no guarantee that it will fit in the user data area 67 at other symbol sizes.
  • padding 71 is inserted in the DVB-S2 frame 13 in the present embodiment. Therefore, even if the symbol of the RS code is not an octet, the data length of the user data area 67 can be adjusted to the size of the symbol of the RS code by adjusting the padding length.
  • the symbol size of the RS code is a divisor of ASM.
  • the first encoding unit 21 performs the first data sequence in a number larger than the number corresponding to the length of the user data area 67 of one DVB-S2 frame 13. Is generated by RS code to generate parity of RS code.
  • the first encoding unit 21 inserts each data sequence existing along the row direction of the encoded data 64 into the user data area 67 of each DVB-S2 frame 13, and the user data area 67 of each DVB-S2 frame 13. Fill the rest of the with 71 padding.
  • the decoding of the first error correction code is performed by the normal decoding for obtaining the error correction position and the size thereof, but in the present embodiment, the BCH code which is the outer code of the DVB-S2 frame 13 Perform erasure correction in cooperation with
  • FIG. 8 shows a configuration example of the first error correction unit 31, the second error correction unit 32, and the detection unit 33 of the decoding device 30.
  • the second error correction unit 32 includes a BCH decoding circuit 80, a descramble circuit 81, and a DATA FIELD extraction circuit 82 for extracting the user data area 67 of the DVB-S2 frame 13.
  • the output of the DATA FIELD extraction circuit 82 is an input to the ASM detection circuit 51 and the input terminal 52.
  • the second error correction unit 32 includes, as constituent elements for erasure correction, an erasure flag generation circuit 83, an output terminal 84 of the erasure flag generation circuit 83, and an erasure flag input terminal 85 of the RS decoding circuit 53.
  • the erasure flag generation circuit 83 performs erasure determination of the user data area 67 of the DVB-S2 frame 13 from the corrected bit number monitor and the uncorrectable flag for each DVB-S2 frame 13 obtained from the BCH decoding circuit 80.
  • the result of the erasure determination is input from the output terminal 84 to the erasure flag input terminal 85 as a erasure flag.
  • the RS decoding circuit 53 has an erasure correction processing function.
  • the erasure flag generation circuit 83 erases the symbol of the RS code relating to the user data area 67 based on the number of corrections or the non-correction flag in BCH decoding obtained from the BCH decoding circuit 80 in units of the user data area 67 Generate and output a flag.
  • the erasure flag generation circuit 83 may generate the erasure flag in response to the uncorrectable flag from the BCH decoding circuit 80.
  • the erasure flag may be set even when there is a detection of the number of correction bits around the correction bit, which is the maximum correction capability with a high probability of occurrence of erroneous correction.
  • the connection from the output terminal 84 to the erasure flag input terminal 85 of the RS decoding circuit 53 is performed in synchronization with the RS code symbol.
  • each RS code sequence is assigned only one symbol or less. Therefore, even if the erasure is determined for the user data area 67 of one DVB-S2 frame 13, it will be erasure of at most one symbol from the viewpoint of the RS code sequence.
  • the RS decoding circuit 53 specifies an erasure position together with a syndrome operation based on the input RS code symbol.
  • FIG. 9 shows an example of the erasure correction method in the RS decoding circuit 53.
  • ⁇ is a primitive element. In the case of this RS code, up to two erasure corrections are possible.
  • the syndrome calculation is the same as the conventional error correction method.
  • An element on the Galois field corresponding to the input order is also generated by the input erasure flag.
  • ⁇ i is an element on the Galois field indicating the vanishing position i.
  • ⁇ j is an element on the Galois field indicating the vanishing position j.
  • the first error correction unit 31 determines that there is no error if both S0 and S1 are zero.
  • S0 is the remainder of (X-1).
  • S1 is the remainder of (X- ⁇ ). From the viewpoint of each RS code sequence, the possibility of all being errors even if there are erasures is generally small, and in many cases symbols without errors are often input.
  • the first error correction unit 31 determines the number of erasure symbols, and corrects S0 as an error pattern at the erasure position in the case of one erasure symbol. If S0 is 0 and S1 is non-zero, or S0 is non-zero and S1 is 0, it can be determined as an uncorrectable error. Even if S1 / S0, that is, the result of the division on the Galois field does not match the element on the Galois field indicating the erasure position, it can be determined that correction is not possible in 1 erasure.
  • Ei is the disappearance pattern of the disappearance position i.
  • E j is an elimination pattern of the elimination position j.
  • the first error correction unit 31 performs the second error correction unit 32 as error correction using the parity of the RS code for each first data sequence. Perform erasure correction based on the result of error correction by
  • the first error correction unit 31 within the DVB-S2 frame 13 Determine the loss of the bit sequence of
  • ASM which is a synchronization pattern of the encoded data 64
  • ASMs which are synchronization patterns, are inserted at equal intervals at a short interval that does not increase the overhead much.
  • at least the beginning of the encoded data 64 must be recognized with certainty.
  • the block of the input data 61 is 253 ⁇ (K ⁇ L) octets, which is a block slightly smaller than that shown in FIG.
  • the RS encoding circuit 42 provided in parallel with (K ⁇ L) pieces generates parity of RS code each time one block of input data 61 is encoded.
  • the selector 63 selects and outputs the input data 61 and the parity of the RS code. This yields encoded data 64 of interleaved 255 ⁇ (K ⁇ L) octets.
  • the coded data 64 is divided into a plurality of coding blocks 73 in units of (K ⁇ L) octets.
  • An identifier 65 which is a synchronization signal for identifying the leading encoding block 73 of the encoded data 64, is added to the leading encoding block 73.
  • an identifier 72 which is a synchronization signal for identifying coding blocks 73 other than the beginning of the coded data 64, is added.
  • the identifier 72 is an ASM shown in Non-Patent Document 2, but has a pattern different from the identifier 65 at the head.
  • the identifier 72 is, for example, inverted data of the identifier 65.
  • the identifier 65 is added, and the encoded data 64 in which the identifier 72 is inserted between the encoding blocks 73 is inserted into the user data area 67 "DATA FIELD" of the DVB-S2 frame 13 in K octet units.
  • the operation up to the generation of the encoded data 64 is different from that of the first embodiment only in the parallel number of the RS encoding circuit 42, the block length of the input data 61 and the size of the encoded data 64. Is the same.
  • the identifier 72 By inserting the identifier 72, synchronization on the decoding side can be advanced. Since both the identifiers 65 and 72 are L octets in length and the length of the coding block 73 is (K ⁇ L) octets, the total length of the identifier 65 or the identifier 72 and the coding block 73 Are unified into K octets and have the same length as the user data area 67 of the DVB-S2 frame 13. Therefore, even if an error remains in the whole of one DVB-S2 frame 13, it is an error of at most one symbol, that is, an error of one octet, from the viewpoint of the RS code sequence.
  • FIG. 11 shows an example of allocation of the encoded data 64 to the DVB-S2 frame 13.
  • an ASM corresponding to the identifier 65 or the identifier 72 is disposed at the head of the user data area 67 of each DVB-S2 frame 13.
  • the erasure positions of the (K ⁇ L) RS code sequences are all the same. Therefore, partial processing such as Galois field transformation from the erasure position in the decoding processing can be shared.
  • a part of the ASM to be inserted has a different pattern, it is possible to identify, for each DVB-S2 frame 13, a frame assumed to have an error remaining after BCH decoding, so that frame by frame It is also possible to specify the erasure position or to request retransmission on a frame basis.
  • the insertion unit 23 encodes an identifier for identifying the head of the input data 61 other than the head in units of data transmission from the head of the coded data 64. Insert in 64 That is, the insertion unit 23 inserts an identifier for distinguishing other than the head and the head of the coded data 64 at the head of each line of the coded data 64.
  • the second encoding unit 22 divides the encoded data 64 including the identifier inserted by the insertion unit 23 into a plurality of second data sequences. Therefore, each second data sequence is generated along the row direction of the encoded data 64 generated by the first encoding unit 21 and having the identifier inserted by the insertion unit 23.
  • Embodiment 5 The difference between this embodiment and the fourth embodiment will be mainly described with reference to FIGS. 12 to 14.
  • ASM which is a synchronization signal
  • DATA FIELD user data area 67 “DATA FIELD” of each DVB-S2 frame 13.
  • information replacing the ASM is inserted into the header area 66 "BBHEADER" of each DVB-S2 frame 13.
  • the block of the input data 61 is 253 ⁇ K octets.
  • the RS encoding circuit 42 provided in parallel in K generates parity of RS code each time one block of input data 61 is encoded.
  • the selector 63 selects and outputs the input data 61 and the parity of the RS code.
  • interleaved encoded data 64 of 255 ⁇ K octets is obtained.
  • the encoded data 64 is divided into a plurality of encoding blocks 73 in units of K octets.
  • the encoded data 64 is inserted into the user data area 67 "DATA FIELD" of the DVB-S2 frame 13 in K octet units without addition or insertion of ASM.
  • each coding block 73 is always placed at the top of the user area 7 of each DVB-S2 frame.
  • An identifier 74 which is a synchronization signal indicating the beginning of the encoded data 64 and is information replacing the ASM, is inserted into a header area 66 "BBHEADER" which is an area for control information of DVB-S2.
  • FIG. 13 shows an example of allocation of the encoded data 64 to the DVB-S2 frame 13.
  • the same RS code sequence is placed at the same position in the user data area 67 of the DVB-S2 frame 13.
  • an RS code with a code length of 255 octets and an information length of 253 octets with one octet as one symbol is used, so the user data area 67 of the 254th and 255th DVB-S2 frames 13 It comprises only the parity of the RS code.
  • an RS code in which one symbol is larger than one octet can be used, and the code length of the RS code can be lengthened.
  • erasure correction may be performed as in the third embodiment.
  • a position into which the identifier 74 is to be inserted for example, “MATYPE-2” or “SYNCD” in the header area 66 “BBHEADER” shown in FIG. 14 is a candidate.
  • Non-Patent Document 1 shows that “MATYPE-2” is reserved in the case of single input. "MATYPE-2” is 8 bits. Therefore, in single input, the identifier 74 can be put in "MATYPE-2".
  • ARQ for each encoded data 64 is also possible.
  • the DVB-S2 frame 13 and the first error correction code are synchronized to form a frame, thereby efficiently reducing the overhead while reducing the DVB-S2 frame 13. High performance can be achieved by correcting the remaining error.
  • the insertion unit 23 uses an identifier 74 for identifying whether the beginning of the encoded data 64 is included in each DVB-S2 frame 13 as each DVB- The header area 66 of the S2 frame 13 is inserted.
  • FIG. 15 Sixth Embodiment The difference between this embodiment and the first embodiment will be mainly described with reference to FIGS. 15 and 16.
  • FIG. 15 Sixth Embodiment The difference between this embodiment and the first embodiment will be mainly described with reference to FIGS. 15 and 16.
  • FIG. 15 Sixth Embodiment The difference between this embodiment and the first embodiment will be mainly described with reference to FIGS. 15 and 16.
  • FIG. 15 Sixth Embodiment The difference between this embodiment and the first embodiment will be mainly described with reference to FIGS. 15 and 16.
  • a plurality of RS code sequences are made into one block of the encoded data 64, and a synchronization signal at least the beginning of the block can be added to it.
  • And are dispersed in the user data area 67 “DATA FIELD” of the DVB-S2 frame 13. Therefore, even if an error remains in the whole of one DVB-S2 frame 13, it is an error of at most one symbol, that is, an error of one octet, from the viewpoint of the RS code sequence.
  • the insertion unit 23 of the encoding device 20 can be omitted.
  • the detection unit 33 of the decoding device 30 can also be omitted.
  • an RS code with a code length of 255 octets and an information length of 253 octets is used, with one octet as one symbol.
  • the parity of the RS code, which is the first error correction code is concentrated in a specific DVB-S2 frame 13, but in the present embodiment, the parity of the RS code, which is the first error correction code, is It is assigned to each DVB-S2 frame 13.
  • FIG. 16 shows an example of allocation of the encoded data 64 to the DVB-S2 frame 13.
  • the user data area 67 "DATA FIELD" of K octets is divided into 255 small blocks 70 which are code lengths of RS codes.
  • the fraction not divisible by 255 which is the code length of the RS code is padding 71.
  • the RS code sequence is a series of small blocks 70 that are diagonally continuous in the DVB-S2 frame 13 transmitted sequentially, and the 255th frame In the last small block 70, the parity of the RS code sequence starting from the first small block 70 of the first frame is inserted.
  • the series of small blocks 70 may be composed of a plurality of RS code series.
  • the user data area 67 of the DVB-S2 frame 13 is divided into small blocks 70 whose number corresponds to the RS code length, and the RS code sequence is divided into small blocks 70 at different positions every DVB-S2 frame 13 By allocating, it is not necessary to add information that indicates the start position of the RS code sequence. In the present embodiment, even if errors remain in all of the user data area 67 of one DVB-S2 frame 13, they are dispersed into at most one symbol error, that is, one octet error from the viewpoint of the RS code sequence. be able to.
  • an RS code in which one symbol is larger than one octet can be used, and the code length of the RS code can be lengthened.
  • erasure correction may be performed as in the third embodiment.
  • each first data series exists along the diagonal direction of the input data 61.
  • the first encoding unit 21 generates RS code parity by encoding the first data sequence of the number according to the length of each first data sequence using an RS code.
  • the first encoding unit 21 generates encoded data 64 by adding the parity of the RS code to each first data sequence, and as a result expands the matrix in the diagonal direction.

Abstract

L'invention concerne un dispositif codeur (20) dans lequel une première unité de codage (21) code, à l'aide d'un code RS, chacune de premières séquences de données présentes dans une direction différente de la direction de rangée de données d'entrée, générant ainsi une parité de code RS, et ajoute la parité de code RS à chacune des premières séquences de données, générant ainsi des données codées, et élargissant par conséquent une matrice. Une seconde unité de codage (22) code, à l'aide d'un code BCH et d'un code LDPC, chacune de secondes séquences de données présentes dans la direction de rangée des données codées, générant ainsi des parités de code BCH et de code LDPC, et génère une pluralité de trames DVB-S2 (13) comprenant chacune une séquence de données présente dans la direction de rangée des données codées et les parités de code BCH et de code LDPC correspondantes.
PCT/JP2017/034928 2017-09-27 2017-09-27 Dispositif codeur, émetteur, dispositif décodeur et récepteur WO2019064369A1 (fr)

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US16/648,841 US11115058B2 (en) 2017-09-27 2017-09-27 Coding device, transmitter, decoding device, and receiver
EP17927721.5A EP3691131A4 (fr) 2017-09-27 2017-09-27 Dispositif codeur, émetteur, dispositif décodeur et récepteur
EP23163725.7A EP4220967A1 (fr) 2017-09-27 2017-09-27 Dispositif de codage et émetteur
PCT/JP2017/034928 WO2019064369A1 (fr) 2017-09-27 2017-09-27 Dispositif codeur, émetteur, dispositif décodeur et récepteur
EP23163733.1A EP4220968A1 (fr) 2017-09-27 2017-09-27 Dispositif de codage et émetteur
JP2019545441A JP6921216B2 (ja) 2017-09-27 2017-09-27 符号化装置、送信機、復号装置および受信機
JP2021098935A JP7199474B2 (ja) 2017-09-27 2021-06-14 符号化装置、送信機、復号装置および受信機

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US20200266835A1 (en) 2020-08-20
EP3691131A1 (fr) 2020-08-05
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EP3691131A4 (fr) 2020-10-07
JP7199474B2 (ja) 2023-01-05
JP6921216B2 (ja) 2021-08-18
EP4220968A1 (fr) 2023-08-02
JPWO2019064369A1 (ja) 2020-11-05
US11115058B2 (en) 2021-09-07

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