WO2019062260A1 - 薄膜晶体管及其制作方法、以及阵列基板与显示装置 - Google Patents

薄膜晶体管及其制作方法、以及阵列基板与显示装置 Download PDF

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WO2019062260A1
WO2019062260A1 PCT/CN2018/094790 CN2018094790W WO2019062260A1 WO 2019062260 A1 WO2019062260 A1 WO 2019062260A1 CN 2018094790 W CN2018094790 W CN 2018094790W WO 2019062260 A1 WO2019062260 A1 WO 2019062260A1
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gas
film transistor
layer
thin film
etching
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PCT/CN2018/094790
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English (en)
French (fr)
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铃木浩司
陈卓
张毅先
张帆
任思雨
苏君海
李建华
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信利（惠州）智能显示有限公司
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Priority to US16/648,248 priority Critical patent/US11227881B2/en
Publication of WO2019062260A1 publication Critical patent/WO2019062260A1/zh

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Definitions

  • the present invention relates to the field of semiconductor devices, and in particular to a thin film transistor and a method of fabricating the same, and an array substrate and a display device.
  • Thin film transistor liquid crystal display is the most important one in the field of flat panel display. It has many advantages, such as thin size, light weight, excellent picture quality, low power consumption, long life, digitization, etc. It spans all sizes of display technology and is used in a wide range of applications, covering almost every major electronic product in today's information society, such as televisions, monitors, laptops, cell phones, PDAs, GPS, in-vehicle displays, instrumentation, public displays and medical applications. Display and so on.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix/Organic Light Emitting Diode
  • each OLED scans an input current progressively through a TFT (Thin Film Transistor) switching circuit.
  • Gate materials of thin film transistors used in thin film transistor liquid crystal displays (TFT-LCDs) and AMOLEDs generally use molybdenum, tungsten or molybdenum tungsten alloys.
  • a two-step etching method is generally employed: the first step uses a gas containing SF 6 , such as SF. 6 and O 2 mixed gas as an etching gas, etching off part of the gate metal layer; the second step uses a gas containing Cl 2 , such as a mixed gas of Cl 2 and O 2 as an etching gas, and the remaining gate metal layer Etched off.
  • the reaction in the second step of the etching process, will MoCl 2 O 2, MoCl 4 O , MoCl 5 and other gases, and MoCl 2 O 2, MoCl 4 O , MoCl 5 and other reaction products due to low vapor pressure will Adhering again into the etching chamber, the chamber is easily dirty.
  • the reaction will MoF 6, MoF 4 O gas and the like, and MoF 6, MoF 4 O other reaction products due to high vapor pressure, does not pollute the chamber, while having a cleaning chamber Effect.
  • the etching process of the first step and the second step is repeated to prevent contamination of the chamber, but the contamination of the chamber cannot be completely prevented after the etching process of the second step.
  • the fluorine-containing gas is used to etch the gate insulating film of the lower layer of the gate metal layer, and Cl 2 and O 2 are used as the etching gas, the gate insulating film is not etched, so that the prior art cannot The gate is formed by the first etching described above, and the gate electrode must be formed by the etching processes of the first step and the second step described above, which inevitably causes contamination of the chamber.
  • a thin film transistor and a method of fabricating the same, and an array substrate and a display device are provided.
  • a method of fabricating a thin film transistor comprising:
  • ion implantation is performed on the active layer to form a source region and a drain region;
  • a passivation layer is deposited on the gate, and a via hole is formed in the gate insulating layer and the passivation layer, and a source and a drain are formed.
  • a thin film transistor is manufactured by the above-described fabrication method.
  • An array substrate includes a substrate, and gate lines, data lines, pixel electrodes, and the thin film transistor disposed on the substrate.
  • a display device comprising the above array substrate.
  • FIG. 1 is a schematic flow chart of a method of fabricating a thin film transistor of one embodiment
  • FIG. 2A-2G are schematic structural views respectively showing the steps of the thin film transistor shown in FIG. 1 in the manufacturing process.
  • a schematic flow diagram of a method for fabricating a thin film transistor includes: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer; patterning the polysilicon layer to form an active layer; Depositing a gate insulating layer on the source layer; depositing a gate metal layer on the gate insulating layer, and performing dry etching on the gate metal layer by using a gas containing CO as an etching gas by a patterning process a gate; a gate as a mask, ion implantation of the active layer to form a source region and a drain region; depositing a passivation layer on the gate, and the gate insulating layer and the passivation
  • the layers form vias and make source and drain.
  • a gas containing CO is used as an etching gas, and the vapor pressure of the reaction product generated is high, and Adhering into the etching chamber does not cause contamination of the chamber, and the CO gas as the main etching gas does not etch away the gate insulating film of the lower layer of the gate metal layer.
  • a method for fabricating a thin film transistor specifically includes the following steps:
  • Step 110 Form a buffer layer on the substrate.
  • a buffer layer 200 is formed on a clean substrate 100, which may be a glass substrate or a flexible substrate.
  • the buffer layer 200 formed can increase the degree of adhesion between the amorphous silicon layer to be formed and the substrate. At the same time, it is also possible to prevent metal ions in the substrate from diffusing to the active layer, reduce impurity defects, and reduce leakage current generation.
  • a buffer layer of a certain thickness is deposited on the glass substrate by plasma chemical vapor deposition (PECVD).
  • the deposition material may be a single-layer silicon oxide (SiO x ) film layer or a silicon nitride (SiN x ) film layer, or a laminate of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the reaction gas for forming the SiN x film layer may be a mixed gas of SiH 4 , NH 3 , and N 2 , or a mixed gas of SiH 2 Cl 2 , NH 3 , and N 2 ; and the reaction gas for forming the SiO x film layer may be SiH 4, a mixed gas of N2O, or a SiH 4, tetraethylorthosilicate (TEOS) mixed gas.
  • TEOS tetraethylorthosilicate
  • Step 120 depositing an amorphous silicon layer on the buffer layer, and performing a laser annealing process on the amorphous silicon layer to form a polysilicon layer.
  • an amorphous silicon layer is deposited on the buffer layer using a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the deposition temperature is generally controlled below 500 °C.
  • the amorphous silicon layer has a thickness of 40 nm to 60 nm.
  • the appropriate thickness can also be selected according to the specific process needs.
  • the thickness of the amorphous silicon layer is 42 nm to 55 nm, and the thickness of the amorphous silicon layer is 45 nm, 48 nm, 50 nm, 51 nm, 52 nm or 54 nm, for example.
  • excimer laser annealing is performed by laser annealing using an excimer laser such as xenon chloride (XeCl), krypton fluoride (KrF), or argon fluoride (ArF), for example, at a wavelength of 308 nm.
  • an excimer laser such as xenon chloride (XeCl), krypton fluoride (KrF), or argon fluoride (ArF), for example, at a wavelength of 308 nm.
  • the laser beam passes through the optical system and is a linear light source.
  • the pulse repetition rate of the excimer laser annealing is 300 Hz to 800 Hz, and the pulse repetition rate of the excimer laser annealing is 400 Hz to 600 Hz; for example, the scan pitch is 15 ⁇ m to 30 ⁇ m.
  • the laser energy density is 150-600 mJ/cm 2 , and, for example, the laser energy density is 350-500 mJ/cm 2 ;
  • the scanning rate is preferably 0.5 mm/s to 50 mm/s, and, for example, the scanning rate It is 0.5 mm/s to 50 mm/s 1 mm/s to 30 mm/s, and, for example, the scanning rate is 2 mm/s to 10 mm/s.
  • the amorphous silicon layer needs to be dehydrogenated to reduce the hydrogen content to less than 2% to prevent hydrogen explosion.
  • hydrogen is removed from the amorphous silicon layer by a thermal annealing treatment.
  • Step 130 Perform a patterning process on the polysilicon layer to form an active layer.
  • Step 1 forming a mask by a photolithography process, forming a pattern by a dry etching method, forming an active layer 300 including a source region, a drain region, and a channel region, and a cross section of the completed structure is shown in FIG. 2B.
  • Step 2 ion implantation is performed on the active layer to form channel doping.
  • the purpose of doping the channel is to adjust the threshold voltage of the device.
  • the threshold voltage of the thin film transistor is required to move in a positive direction
  • the active layer is doped with boron
  • the threshold voltage of the thin film transistor is required to move in a negative direction
  • the active layer is doped with phosphorus or The arsenic element is doped
  • ion implantation of the active layer is not required to achieve channel doping.
  • the injection medium is a boron-containing element or a phosphorus-containing element, depending on the threshold voltage of the thin film transistor.
  • a mixed gas of B 2 H 6 and H 2 is used as an injection medium, and, for example, a ratio of B 2 H 6 to H 2 is 1% to 30%, and an implantation energy range is 2 to A 50 KeV, more preferably an energy range of 4 to 10 KeV, and an implantation dose range of 0 to 5 ⁇ 10 13 atoms/cm 3 , preferably, the implantation dose ranges from 0 to 9 ⁇ 10 12 atoms/cm 3 .
  • a phosphorus-containing element such as a mixed gas of PH 3 and H 2 is used as an injection medium, for example, a ratio of PH 3 to H 2 is 1% to 30%; an implantation energy range is 5 to 50 KeV, and more preferably energy. The range is 7 to 20 KeV; the implantation dose ranges from 0 to 5 ⁇ 10 13 atoms/cm 3 , and preferably, the implantation dose ranges from 0 to 9 ⁇ 10 12 atoms/cm 3 .
  • Step 140 depositing a gate insulating layer 400 on the active layer 300, and a cross section of the completed structure is shown in FIG. 2C.
  • a gate insulating layer is formed on a substrate on which an active layer is formed by a chemical vapor deposition method.
  • the deposition temperature is generally controlled below 500 °C.
  • the thickness of the gate insulating layer may be 80-200 nm, and a suitable thickness may be selected according to specific process requirements.
  • the gate insulating layer is a single layer of silicon oxide, silicon nitride, or a combination of the two.
  • Step 150 depositing a gate metal layer on the gate insulating layer 400, and performing dry etching on the gate metal layer by using a gas containing CO as an etching gas to form a gate electrode 500. See Figure 2D for a section of the structure.
  • a gate metal layer is deposited by a method such as CVD, and then, by a patterning process, exposure, development, and etching are performed using a mask to pattern the gate metal layer to form a gate.
  • PECVD thermal evaporation or plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • ECR- A gate metal layer is deposited by a method such as CVD, and then, by a patterning process, exposure, development, and etching are performed using a mask to pattern the gate metal layer to form a gate.
  • the material of the gate metal layer is molybdenum, tungsten or a molybdenum-tungsten alloy, and, for example, a combination of several materials described above is used.
  • the thickness of the gate metal layer is 100-800 nm, for example, the thickness of the gate metal layer is 400 nm.
  • the thickness of the gate metal layer can also be selected according to the specific process requirements.
  • a gas containing CO is used as an etching gas, for example, dry etching by reactive ion etching; for example, dry etching by plasma etching, for example, inductive coupling
  • the plasma etching method performs dry etching.
  • the source power of the plasma source of the etching machine is 4000-6000 W
  • the power of the bias RF source (bias) Power) is 800-1200W.
  • the plasma power source of the etch machine has a source power of 5000W.
  • the bias power of the biased RF source is 1000W.
  • the gas pressure in the etching chamber is 4-6 Pa.
  • the gas pressure in the etching chamber is 5 Pa.
  • the flow rate of CO gas is 400-600 sccm.
  • the flow rate of CO gas is 500 sccm.
  • a gate metal layer on the gate insulating layer depositing a gate metal layer on the gate insulating layer, and dry etching the gate metal layer by a patterning process, for example, using CO gas as an etching gas; for example, using CO gas and O 2
  • the mixed gas of the gas is dry-etched as an etching gas to form a gate electrode; for example, a mixed gas of CO gas and an inert gas (such as gases such as He, Ar, and Ne) is used as an etching gas.
  • Drying the gate metal layer to form a gate for example, dry etching the gate metal layer using a mixed gas of CO gas and Cl 2 gas as an etching gas to form a gate;
  • the gate metal layer is dry etched using a mixed gas of at least one of O 2 gas, an inert gas, and a Cl 2 gas and CO as an etching gas to form a gate electrode.
  • the material of the gate metal layer is Mo
  • CO is used as a main etching gas to react to form Mo(CO) 6 .
  • the vapor pressure of Mo(CO) 6 is 1.0*(e 1 to e 2 )mmHg.
  • MOCl 2 O 2 is about 5.0* (e ⁇ 1 ⁇ e 0 ) ) mmHg
  • MOCl 4 O is about 5.0*(e -1 to e 0 )mmHg.
  • the vapor pressure of the reaction product of CO as the main etching gas is much higher than the vapor pressure of the reaction product of the mixed gas of Cl 2 and O 2 as the etching gas, and therefore, CO is used as the main engraving.
  • the vapor pressure of the etch gas reaction product is high and does not adhere to the etching chamber, thereby avoiding contamination of the chamber, and the CO gas as the main etching gas does not insulate the gate of the lower layer of the gate metal layer. The film is etched away.
  • the gate metal layer is dry etched using a gas containing CO as an etching gas to form a gate electrode. , also includes the steps:
  • the gate metal layer is subjected to preliminary dry etching using a gas containing SF 6 as an etching gas, and the gate metal layer of the first thickness is etched away, and the gate metal layer of the second thickness remains.
  • the two-step etching method is divided into a first etching and a second etching.
  • the first etching uses a gas containing SF 6 as an etching gas to perform preliminary dry etching on the gate metal layer, and etching away a first thickness of the gate metal layer, a second thickness of the gate metal layer, and a second etching using a CO-containing gas as an etching gas to dry-etch the remaining second thickness of the gate metal layer to form Gate.
  • the flow rate of the SF 6 gas is 400 to 600 sccm, and for example, the flow rate of the SF 6 gas is 500 sccm.
  • the gate metal layer is initially dry etched by using a gas containing SF 6 as an etching gas, and the gate metal layer of the first thickness is etched away, and the gate metal layer of the second thickness is left, for example, SF 6 gas is used.
  • a gas containing SF 6 as an etching gas
  • etching away the gate metal layer of the first thickness leaving a gate metal layer of a second thickness; for example, mixing of SF 6 gas and O 2 gas
  • the gas is used as an etching gas to perform preliminary dry etching on the gate metal layer, etching the gate metal layer of the first thickness, and remaining the gate metal layer of the second thickness; for example, using SF 6 gas and an inert gas (such as a mixed gas of He, Ar, and Ne) is used as an etching gas to perform preliminary dry etching of the gate metal layer, etching a gate metal layer of a first thickness, and remaining a gate metal layer of a second thickness; a mixed gas of SF 6 gas, CO
  • a preliminary dry etching of the gate metal layer is performed by using a mixed gas of SF6 gas and O2 gas as an etching gas, and the gate metal layer of the first thickness is etched away, and the gate metal layer of the second thickness remains,
  • the flow rate of the SF 6 gas is 400 to 600 sccm
  • the flow rate of the O 2 is 100 to 300 sccm.
  • the flow rate of the SF 6 gas is 500 sccm
  • the flow rate of the O 2 gas is 200 sccm.
  • the flow rate of the CO gas is 400-600 sccm.
  • the flow rate of CO gas is 500 sccm.
  • the first thickness of the gate metal layer is first etched by using the gas containing SF 6 as an etching gas, and the gas containing CO is used as the etching gas. Etching off the remaining second thickness of the gate metal layer prevents etching of the underlying gate insulating film, greatly reducing the time required for the gate metal layer to form the gate.
  • the ratio of the first thickness to the second thickness is (1 to 2): 1.
  • the ratio of the first thickness to the second thickness is 1.5:1.
  • the gate metal layer has a thickness of 250 nm, a first thickness of 150 nm, and a second thickness of 100 nm.
  • the SF 6- containing gas having a faster etching rate is used as an etching gas to etch away most of the gate metal layer
  • the CO-containing gas having a slow etching rate is used as an etching gas to etch a small portion.
  • the gate metal layer prevents etching of the underlying gate insulating film, further reducing the time for the gate metal layer to form a gate.
  • the second thickness is 50 to 150 nm.
  • the second thickness is 100 nm.
  • the gas containing CO which speeds up the entire etching process and reduces the formation of the gate metal layer. time.
  • Step 160 performing ion implantation on the active layer 300 by using the gate 500 as a mask to form a source region 310 and a drain region 320.
  • the gate 500 As a mask to form a source region 310 and a drain region 320.
  • the implanted medium is a boron-containing element and/or a phosphorus-containing element gas to form a P-type or N-type thin film transistor.
  • a boron-containing element such as a mixed gas of B 2 H 6 /H 2 is used as an injection medium, for example, a ratio of B 2 H 6 to H 2 is 1% to 30%; an implantation energy range is 5 to 50 KeV, and more The preferred energy range is 20 to 30 KeV; the implantation dose ranges from 1 ⁇ 10 13 to 1 ⁇ 10 17 atoms/cm 3 , preferably, the implantation dose ranges from 5 ⁇ 10 14 to 5 ⁇ 10 15 atoms/cm 3 ; A phosphorus-containing element such as a mixed gas of PH 3 /H 2 is used as an injection medium.
  • a mixed gas of PH 3 /H 2 is used as an injection medium, for example, a ratio of PH 3 to H 2 is 1% to 30%; an implantation energy range is 20 to 110 KeV, and a more preferable energy range is 50 to 70 KeV; The range is 1 ⁇ 10 13 to 1 ⁇ 10 17 atoms / cm 3 , and preferably, the implantation dose ranges from 5 ⁇ 10 14 to 5 ⁇ 10 15 atoms / cm 3 .
  • Step 170 depositing a passivation layer 600 on the gate electrode 500, and forming a via hole 610 in the gate insulating layer 400 and the passivation layer 600. See FIG. 2F for a cross section of the completed structure.
  • a passivation layer having a thickness of 200 nm to 800 nm may be deposited by a chemical vapor deposition process, for example, the passivation layer is an oxide, a nitride, or an oxynitride compound, and, for example, the passivation layer is a single layer structure or a multilayer structure.
  • the gas forming the passivation layer is SiH 4 , NH 3 , N 2 or SiH 4 , N 2 O.
  • a dry etching method is used to form a mask by a photolithography process, and via holes are formed on the passivation layer and the gate insulating layer to expose the source and drain regions.
  • a fluorine-containing element or a chlorine-containing gas such as SF 6 , CF 4 , CHF 3 , CCl 2 F 2 or a mixed gas of the foregoing gas and O 2 may be used as the etching medium.
  • Etching is performed by reactive ion etching, plasma etching or inductively coupled plasma etching.
  • Step 180 Manufacture the source 710 and the drain 720, and the completed cross section is shown in FIG. 2G.
  • a metal layer is formed over the passivation layer by sputtering, thermal evaporation or plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.
  • a photoresist mask is formed by photoresist using a photolithography process, and a pattern including a source and a drain is formed by wet etching or dry etching. Referring to FIG. 2G , the source 710 passes through the via 610 and is electrically connected to the source region 310 .
  • the drain 720 extends through the via 610 and is electrically connected to the drain region 320 .
  • the preparation of the thin film transistor including the gate, the source and the drain of the array substrate has been completed by the method, and the gate lines, the data lines and the pixel electrodes on the array substrate can be obtained according to a conventional process.
  • the display panel can be finally formed by a conventional process to further form a display device.
  • Another example is a thin film transistor which is prepared by the fabrication method described in any of the above embodiments.
  • an array substrate includes a substrate, and a thin film transistor, a gate line, a data line, and a pixel electrode disposed on the substrate, wherein the thin film transistor is prepared by the manufacturing method of any of the above embodiments. .
  • a display device is provided, and the display device includes the array substrate in any of the above embodiments.
  • the display device is a product or component having a display function; for example, the display device is a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

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Abstract

本发明公开了一种薄膜晶体管的制作方法、以及阵列基板与显示装置。上述薄膜晶体管的制作方法包括：在基板上形成缓冲层；在缓冲层上形成多晶硅层；对多晶硅层进行构图工艺，形成有源层；在有源层上沉积栅极绝缘层；在栅极绝缘层上沉积栅极金属层，通过构图工艺，采用含有CO的气体作为刻蚀气体对栅极金属层进行干法刻蚀，形成栅极；以栅极为掩膜，对有源层进行离子注入，形成源区和漏区；在栅极上沉积钝化层，并在栅极绝缘层及钝化层形成过孔，并制作源极及漏极。

Description

薄膜晶体管及其制作方法、以及阵列基板与显示装置
本申请要求于2017年9月28日提交中国专利局、申请号为201710898220.4、发明名称为“薄膜晶体管及其制作方法、以及阵列基板与显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件领域，特别是涉及一种薄膜晶体管及其制作方法、以及阵列基板与显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)是平板显示领域中最重要的一种，由于其具有众多优点，如体积薄、重量轻、画面品质优异、功耗低、寿命长、数字化等，而且也是唯一可跨越所有尺寸的显示技术，其应用领域非常广泛，几乎涵盖了当今信息社会的主要电子产品，如电视、监视器、便携式电脑、手机、PDA、GPS、车载显示、仪器仪表、公共显示和医用显示等。OLED(Organic Light Emitting Diode，有机发光二极管)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。在AMOLED(Active Matrix/Organic Light Emitting Diode，有源矩阵有机发光二极管)技术中，每个OLED均通过TFT(Thin Film Transistor，薄膜晶体管)开关电路逐行扫描输入电流。
薄膜晶体管液晶显示器(TFT-LCD)和AMOLED中使用的薄膜晶体管的栅极材料通常使用钼、钨或钼钨合金等。在栅极金属层通过构图工艺形成栅极的刻蚀过程中，例如，采用Mo作为栅极金属层的材料时，一般采用两步刻蚀法：第一步使用含有SF 6的气体，例如SF 6与O 2混合气体作为刻蚀气体， 刻蚀掉部分栅极金属层；第二步使用含有Cl 2的气体，例如Cl 2与O 2混合气体作为刻蚀气体，把剩余的栅极金属层刻蚀掉。其中，在第二步的刻蚀过程中，会反应生成MoCl 2O 2、MoCl 4O、MoCl 5等气体，而MoCl 2O 2、MoCl 4O、MoCl 5等反应生成物因蒸气压低，会再次粘附到刻蚀腔室内，易使腔室变脏。而在第一步的刻蚀过程中，会反应生成MoF 6、MoF 4O等气体，而MoF 6、MoF 4O等反应生成物因蒸气压高，不会污染腔室，同时具有清洁腔室的效果。因此现有技术通常是采用反复进行第一步和第二步的刻蚀过程来防止腔室污染，但是通过第二步的刻蚀过程之后并不能完全防止污染腔室。而由于使用含氟气体会把栅极金属层下层的栅极绝缘膜刻蚀掉，而Cl 2和O 2作为刻蚀气体不会把栅极绝缘膜刻蚀掉，因此现有技术中不能只采用上述第一步刻蚀就形成栅极，而必须采用上述第一步和第二步的刻蚀过程形成栅极，这样就不可避免将造成腔室的污染。
发明内容
根据本申请公开的各种实施例，提供一种薄膜晶体管及其制作方法、以及阵列基板与显示装置。
一种薄膜晶体管的制作方法，包括：
在基板上形成缓冲层；
在所述缓冲层上形成多晶硅层；
对所述多晶硅层进行构图工艺，形成有源层；
在所述有源层上沉积栅极绝缘层；
在所述栅极绝缘层上沉积栅极金属层，通过构图工艺，采用含有CO的气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；
以栅极为掩膜，对所述有源层进行离子注入，形成源区和漏区；以及
在所述栅极上沉积钝化层，并在所述栅极绝缘层及所述钝化层形成过孔，并制作源极及漏极。
一种薄膜晶体管，采用上述的制作方法制造得到。
一种阵列基板，包括基板，以及设置于所述基板上的栅线、数据线、像素电极及上述的薄膜晶体管。
一种显示装置，包括上述的阵列基板。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为一个实施例的薄膜晶体管的制作方法的流程示意图；
图2A-2G分别为图1所示的薄膜晶体管在制作过程中的各步骤所产生的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
例如，一种薄膜晶体管的制作方法的流程示意图，包括：在基板上形成缓冲层；在所述缓冲层上形成多晶硅层；对所述多晶硅层进行构图工艺，形 成有源层；在所述有源层上沉积栅极绝缘层；在所述栅极绝缘层上沉积栅极金属层，通过构图工艺，采用含有CO的气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；以栅极为掩膜，对所述有源层进行离子注入，形成源区和漏区；在所述栅极上沉积钝化层，并在所述栅极绝缘层及所述钝化层形成过孔，并制作源极及漏极。
本实施例的薄膜晶体管的制作方法，在将栅极金属层通过构图工艺形成栅极的刻蚀过程中，采用含有CO的气体作为刻蚀气体，生成的反应生成物的蒸气压高，不会粘附到刻蚀腔室内，不会造成腔室污染，且CO气体作为主要的刻蚀气体也不会把栅极金属层下层的栅极绝缘膜刻蚀掉。
例如，一种薄膜晶体管的制作方法，如图1所示，其具体包括如下步骤：
步骤110：在基板上形成缓冲层。
请参阅图2A，在干净的基板100上形成缓冲层200，基板100可为玻璃基板或柔性基板。形成的缓冲层200可以提高待形成的非晶硅层与基板之间的附着程度。同时，还可以防止基板中的金属离子扩散至有源层，降低杂质缺陷，并且可以减少漏电流的产生。
具体地，在玻璃基板上利用等离子体化学气相沉积法(PECVD)沉积一层一定厚度的缓冲层。沉积材料可以为单层的氧化硅(SiO x)膜层或氮化硅(SiN x)膜层，或者为氧化硅(SiO x)和氮化硅(SiN x)的叠层。
其中，形成SiN x膜层的反应气体可以为SiH 4、NH 3、N 2的混合气体，或者为SiH 2Cl 2、NH 3、N 2的混合气体；形成SiO x膜层的反应气体可以为SiH 4、N2O的混合气体，或者为SiH 4、硅酸乙酯(TEOS)的混合气体。
步骤120：在缓冲层上沉积非晶硅层，并对非晶硅层进行激光退火工艺，形成多晶硅层。
例如，采用等离子体增强化学气相沉积(PECVD)工艺在缓冲层上沉积非晶硅层。又如，沉积温度一般控制在500℃以下。
在本实施例中，非晶硅层的厚度为40nm～60nm。当然，也可根据具体的工艺需要选择合适的厚度。例如，非晶硅层的厚度为42nm～55nm，又如，非 晶硅层的厚度为45nm、48nm、50nm、51nm、52nm或54nm。
例如，采用氯化氙(XeCl)、氟化氪(KrF)、氟化氩(ArF)等准分子激光器进行激光退火，例如波长为308nm，来进行准分子激光退火。激光光束经过光学系统后为线性光源。
又如，准分子激光退火的脉冲重复率(pulse repetition ratio)为300Hz～800Hz，又如，准分子激光退火的脉冲重复率为400Hz～600Hz；又如，扫描间距(scan pitch)为15μm～30μm；又如，激光能量密度为150～600mJ/cm 2，又如，激光能量密度为350～500mJ/cm 2；又如，扫描速率优选为0.5mm/s～50mm/s，又如，扫描速率为0.5mm/s～50mm/s 1mm/s～30mm/s，又如，扫描速率为2mm/s～10mm/s。
优选地，在进行激光退火工艺之前，需要对非晶硅层进行去氢处理，使得氢含量降至2％以下，防止氢爆现象的产生。例如，采用热退火处理将氢从该非晶硅层中排除。
步骤130：对多晶硅层进行构图工艺，形成有源层。
例如，具体地，其包括以下步骤：
步骤一：利用光刻工艺形成掩膜，采用干法刻蚀方法形成图形，形成包括源区、漏区和沟道区的有源层300，其完成后的结构的截面请参阅图2B。
步骤二：对有源层进行离子注入，形成沟道掺杂。
对沟道进行掺杂的目的是为了调节器件的阈值电压。例如，当需要薄膜晶体管的阈值电压向正的方向移动时，对有源层进行硼元素掺杂；当需要薄膜晶体管的阈值电压向负的方向移动时，对有源层进行磷元素掺杂或砷元素掺杂；而根据工艺如果不需要调节阈值电压，则不需要对有源层进行离子注入实现沟道掺杂。
根据薄膜晶体管阈值电压的需要，注入介质为含硼元素或含磷元素的气体。例如，需要含硼元素注入时，如以B 2H 6与H 2的混合气体为注入介质，又如，B 2H 6与H 2的比例为1％～30％，注入能量范围为2～50KeV，更优选的能量范围为4～10KeV，注入剂量范围为0～5×10 13atoms/cm 3，优选地，注入剂 量范围为0～9×10 12atoms/cm 3。又如，采用含磷元素，如以PH 3与H 2的混合气体作为注入介质，例如，PH 3与H 2的比例为1％～30％；注入能量范围为5～50KeV，更优选的能量范围为7～20KeV；注入剂量范围为0～5×10 13atoms/cm 3，优选地，注入剂量范围为0～9×10 12atoms/cm 3。
步骤140：在有源层300上沉积栅极绝缘层400，其完成后的结构的截面请参阅图2C。
例如，采用化学气相沉积方法，在形成了有源层的基板上形成栅极绝缘层。又如，沉积温度一般控制在500℃以下。又如，栅极绝缘层的厚度可为80～200nm，也可根据具体工艺需要选择合适的厚度。又如，栅极绝缘层采用单层的氧化硅、氮化硅，或者二者的叠层。
步骤150：在栅极绝缘层400上沉积栅极金属层，通过构图工艺，采用含有CO的气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极500，其完成后的结构的截面请参阅图2D。
例如，采用溅射、热蒸发或等离子体增强化学气相沉积(PECVD)、低压力化学气相沉积(LPCVD)、常压化学气相淀积(APCVD)、电子回旋共振微波等离子体化学气相沉积(ECR-CVD)等方法沉积栅极金属层，然后，通过构图工艺，利用掩膜板(mask)进行曝光、显影和刻蚀，将栅极金属层图形化，形成栅极。
例如，栅极金属层的材料为钼、钨或钼钨合金，又如，使用上述几种材料的组合。在本实施例中，栅极金属层的厚度为100-800nm，例如，栅极金属层的厚度为400nm，当然，栅极金属层的厚度也可根据具体工艺需要选择合适的厚度。
干法刻蚀工艺中，采用含有CO的气体作为刻蚀气体，例如，采用反应离子刻蚀法进行干法刻蚀；例如，采用等离子体刻蚀法进行干法刻蚀，例如，采用电感耦合等离子体刻蚀法进行干法刻蚀。例如，采用含有CO的气体作为刻蚀气体对栅极金属层进行等离子体刻蚀中，刻蚀机的等离子体射频源的功率(source power)为4000-6000W，偏置射频源的功率(bias power)为 800-1200W。例如，刻蚀机的等离子体射频源的功率(source power)为5000W。例如，偏置射频源的功率(bias power)为1000W。例如，刻蚀腔内的气压为4-6Pa。例如，刻蚀腔内的气压为5Pa。例如，CO气体的流量为400-600sccm。例如，CO气体的流量为500sccm。
在栅极绝缘层上沉积栅极金属层，通过构图工艺，例如，采用CO气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；例如，采用CO气体和O 2气体的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；例如，采用CO气体和惰性气体(如He、Ar和Ne等气体)的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；例如，采用CO气体和Cl 2气体的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；例如，采用O2气体、惰性气体和Cl 2气体中的至少一种与CO的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极。
本实施例中，例如，栅极金属层的材料为Mo，采用CO作为主要的刻蚀气体，反应生成Mo(CO) 6，在80℃的工艺温度下，Mo(CO) 6的蒸气压为1.0*(e 1～e 2)mmHg。而如采用Cl 2与O 2混合气体作为刻蚀气体，反应生成MoCl 2O 2、MoCl 4O等，在80℃的工艺温度下，MOCl 2O 2约为5.0*(e -1～e 0)mmHg，MOCl 4O约为5.0*(e -1～e 0)mmHg。因此，由此可知，CO作为主要的刻蚀气体的反应生成物的蒸气压大大高于Cl 2与O 2混合气体作为刻蚀气体的反应生成物的蒸气压，因此，采用CO作为主要的刻蚀气体反应生成物的蒸气压高，不会粘附到刻蚀腔室内，从而能够避免造成腔室污染，且CO气体作为主要的刻蚀气体也不会把栅极金属层下层的栅极绝缘膜刻蚀掉。
为了减少栅极金属层形成栅极的过程的时间。例如，在构图工艺中，利用掩膜板(mask)进行曝光、显影后进入刻蚀过程时，在采用含有CO的气体作为刻蚀气体对栅极金属层进行干法刻蚀，形成栅极之前，还包括步骤：
采用含有SF 6的气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层。
即，采用两步刻蚀法，分为第一刻蚀和第二刻蚀，第一刻蚀采用含有SF 6 的气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层，第二刻蚀采用含有CO的气体作为刻蚀气体对剩余的第二厚度的栅极金属层进行干法刻蚀，形成栅极。例如，第一刻蚀中，SF 6气体的流量为400～600sccm，例如，SF 6气体的流量为500sccm。
采用含有SF 6的气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层，例如，采用SF 6气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层；例如，采用SF 6气体和O 2气体的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层；例如，采用SF 6气体和惰性气体(如He、Ar和Ne等气体)的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层；采用SF 6气体、CO气体和Cl2气体的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层；例如，采用O2气体、惰性气体、CO气体和Cl2气体中的至少一种与SF 6的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层。
例如，采用SF6气体和O2气体的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层，第一刻蚀中，SF 6气体的流量为400～600sccm，O 2的流量为100～300sccm。例如，SF 6气体的流量为500sccm，O 2气体的流量为200sccm。例如，第二刻蚀中，CO气体的流量为400-600sccm。例如，CO气体的流量为500sccm。
由于采用含有SF 6的气体作为刻蚀气体的刻蚀速率高，先采用含有SF 6的气体作为刻蚀气体先刻蚀掉第一厚度的栅极金属层，再采用含有CO的气体作为刻蚀气体刻蚀掉剩余第二厚度的栅极金属层防止将下层的栅极绝缘膜刻蚀掉，大大减少了栅极金属层形成栅极的过程的时间。
例如，第一厚度与第二厚度的比为(1～2)：1。例如，第一厚度与第二厚度的比为1.5：1。例如，栅极金属层的厚度为250nm，第一厚度为150nm，第二厚度为100nm。这样，刻蚀速率较快的含有SF 6的气体作为刻蚀气体刻蚀掉大部分的栅极金属层，再采用刻蚀速率较慢的含有CO的气体作为刻蚀气体刻蚀掉较小部分的栅极金属层以防止将下层的栅极绝缘膜刻蚀掉，进一步减少了栅极金属层形成栅极的过程的时间。例如，第二厚度为50～150nm。例如，第二厚度为100nm。这样，不管栅极金属层的厚度是多少，只保留小部分的栅极金属层通过含有CO的气体刻蚀，加快了整个刻蚀过程的速率，减少了栅极金属层形成栅极的过程的时间。
步骤160：以栅极500为掩膜，对有源层300进行离子注入，形成源区310及漏区320，其完成后的结构的截面请参阅图2E。
例如，在本实施例中采用具有质量分析仪的离子注入方式。又如，根据设计需要，注入介质为含硼元素和/或含磷元素的气体，以形成P型或N型薄膜晶体管。例如，采用含硼元素，如以B 2H 6/H 2的混合气体为注入介质，例如，B 2H 6与H 2的比例为1％～30％；注入能量范围为5～50KeV，更优选的能量范围为20～30KeV；注入剂量范围为1×10 13～1×10 17atoms/cm 3，优选地，注入剂量范围为5×10 14～5×10 15atoms/cm 3；又如，采用含磷元素，如以PH 3/H 2的混合气体作为注入介质。如以PH 3/H 2的混合气体为注入介质，例如，PH 3与H 2的比例为1％～30％；注入能量范围为20～110KeV，更优选的能量范围为50～70KeV；注入剂量范围为1×10 13～1×10 17atoms/cm 3，优选地，注入剂量范围为5×10 14～5×10 15atoms/cm 3。
步骤170：在栅极500上沉积钝化层600，并在栅极绝缘层400及钝化层600形成过孔610，其完成后的结构的截面请参阅图2F。
具体地，可以通过化学气相沉积工艺沉积厚度为200nm～800nm的钝化层，例如，钝化层为氧化物、氮化物或者氧氮化合物，又如，钝化层为单层结构或者多层结构，又如，形成钝化层的气体为SiH 4，NH 3，N 2或者SiH 4，N 2O。
例如，采用干法刻蚀的方法，以光刻工艺形成掩膜，在钝化层和栅极绝缘层上形成过孔以暴露源区和漏区。其中，干法刻蚀工艺中，可采用含氟元素或含氯元素的气体，如SF 6、CF 4、CHF 3、CCl 2F 2等气体或者前述气体与O 2的混合气体作为刻蚀介质，采用反应离子刻蚀法、等离子刻蚀法或电感耦合等离子体刻蚀法进行刻蚀。
步骤180：制作源极710及漏极720，其完成后的截面请参阅图2G。
具体地，在钝化层的上方采用溅射方式、热蒸发方式或等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成金属层。在金属层的上方，采用光刻工艺以光刻胶形成光阻掩模，并采用湿法刻蚀或干法刻蚀形成包括源极和漏极的图形。请参阅图2G，源极710贯穿过孔610并与源区310电连接，漏极720贯穿过孔610并与漏区320电连接。
至此，通过该方法即已完成阵列基板包含栅极、源极和漏极的薄膜晶体管的制备，而阵列基板上的栅线、数据线及像素电极可根据常规工艺得到。根据阵列基板的结构需求，可通过常规工艺最终形成显示面板，进一步形成显示装置。
又如，一种薄膜晶体管，其采用上述任一实施例所述制作方法制备得到。
又如，一种阵列基板，其包括基板，以及设置于所述基板上的薄膜晶体管、栅线、数据线及像素电极，其中，所述薄膜晶体管采用上述任一实施例所述制作方法制备得到。
本实施例中提供一显示装置，该显示装置包括上述任一实施例中的阵列基板。例如，该显示装置为具有显示功能的产品或部件；例如，该显示装置为液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或者导航仪。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这 些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种薄膜晶体管的制作方法，包括：
    在基板上形成缓冲层；
    在所述缓冲层上形成多晶硅层；
    对所述多晶硅层进行构图工艺，形成有源层；
    在所述有源层上沉积栅极绝缘层；
    在所述栅极绝缘层上沉积栅极金属层，通过构图工艺，采用含有CO的气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极；
    以栅极为掩膜，对所述有源层进行离子注入，形成源区和漏区；以及
    在所述栅极上沉积钝化层，并在所述栅极绝缘层及所述钝化层形成过孔，并制作源极及漏极。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述栅极金属层的材料为钼、钨或钼钨合金。
  3. 根据权利要求2所述的薄膜晶体管的制作方法，其特征在于，所述采用含有CO的气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极之前包括：
    采用含有SF 6的气体作为刻蚀气体对所述栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其特征在于，采用O 2气体、惰性气体、CO气体和Cl 2气体中的至少一种与SF 6的混合气体作为刻蚀气体对栅极金属层进行初步干法刻蚀，刻蚀掉第一厚度的栅极金属层，剩余第二厚度的栅极金属层。
  5. 根据权利要求3所述的薄膜晶体管的制作方法，其特征在于，SF 6气体的流量为400～600sccm。
  6. 根据权利要求3所述的薄膜晶体管的制作方法，其特征在于，所述第一厚度与所述第二厚度的比为1～2：1。
  7. 根据权利要求3所述的薄膜晶体管的制作方法，其特征在于，所述第 二厚度为50～150nm。
  8. 根据权利要求5所述的薄膜晶体管的制作方法，其特征在于，所述栅极金属层的厚度为100-800nm。
  9. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述钝化层的厚度为200nm～800nm。
  10. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，采用含有CO的气体作为刻蚀气体对栅极金属层进行等离子体刻蚀，形成栅极。
  11. 根据权利要求8所述的薄膜晶体管的制作方法，其特征在于，刻蚀机的等离子体射频源的功率为4000-6000W。
  12. 根据权利要求9所述的薄膜晶体管的制作方法，其特征在于，偏置射频源的功率为800-1200W。
  13. 根据权利要求10所述的薄膜晶体管的制作方法，其特征在于，刻蚀腔内的气压为4-6Pa。
  14. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，CO气体的流量为400-600sccm。
  15. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，采用CO气体和O 2气体的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极。
  16. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，采用CO气体和惰性气体的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极。
  17. 根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，采用CO气体和Cl 2气体的混合气体作为刻蚀气体对所述栅极金属层进行干法刻蚀，形成栅极。
  18. 一种薄膜晶体管，采用权利要求1所述的制作方法制造得到。
  19. 一种阵列基板，包括基板，以及设置于所述基板上的栅线、数据线、像素电极及权利要求18所述的薄膜晶体管。
  20. 一种显示装置，包括如权利要求19所述的阵列基板。
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