WO2019059561A1 - 다중 터널 정션 구조를 가지는 발광 다이오드 - Google Patents
다중 터널 정션 구조를 가지는 발광 다이오드 Download PDFInfo
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- WO2019059561A1 WO2019059561A1 PCT/KR2018/010245 KR2018010245W WO2019059561A1 WO 2019059561 A1 WO2019059561 A1 WO 2019059561A1 KR 2018010245 W KR2018010245 W KR 2018010245W WO 2019059561 A1 WO2019059561 A1 WO 2019059561A1
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- light emitting
- common electrode
- tunnel junction
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- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 230000000694 effects Effects 0.000 abstract description 4
- 239000003086 colorant Substances 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910019990 cerium-doped yttrium aluminum garnet Inorganic materials 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
- H01L33/0016—Devices characterised by their operation having p-n or hi-lo junctions having at least two p-n junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
Definitions
- the present invention relates to a light emitting diode field, and more particularly, to a light emitting diode including a multiple tunnel junction structure.
- a basic model of a light emitting diode includes an active region interposed between an n-type carrier layer and a p-type carrier layer.
- the active region has a thickness and the composition of the two carrier layers is different, a single or multiple quantum well structure is formed in the active region.
- the bias is applied, the n-type carrier layer and the p-type carrier layer carry the n-type carrier and the p-type carrier into the active region, respectively, .
- a light emitting diode In order for a light emitting diode to be used in an illumination device, white light similar to natural light should be emitted.
- a color conversion element such as a filter or a phosphor that converts the light emission color of the light emitting chip to white is used.
- an illumination device that emits white light by coupling a yellow phosphor to a nitride semiconductor light emitting chip that emits blue light, such as GaN, is widely used.
- the blue light emitting diode chip generates high heat during operation, and there is a problem that existing phosphors coupled for color conversion are affected by the heat.
- the present invention provides a light emitting diode including multiple tunnel junctions and multiple light emitting structures.
- the present invention provides a light emitting diode comprising: a common electrode layer; First and second tunnel junction layers disposed on the lower and upper surfaces of the common electrode layer, respectively; A first light emitting structure disposed on a lower surface of the first tunnel junction layer; And a second light emitting structure disposed on an upper surface of the second tunnel junction layer.
- the first light-emitting structure includes: a first n-type constraint layer and a first p-type constraint layer interposed between the first active region and the first p-type constraint layer is in contact with the first tunnel junction layer .
- the second light emitting structure includes: a second p-type confinement layer and a second n-type confinement layer interposed between the second active regions, and the second p-type confinement layer is in contact with the second tunnel junction layer .
- the common electrode layer may be an n-type semiconductor.
- a second mesa structure in which the upper layers of the common electrode layer are removed to expose a part of the upper surface of the common electrode layer and a positive metal contact formed on the upper surface of the common electrode layer exposed by the second mesa structure.
- RTI ID 0.0 > a < / RTI >
- the first light emitting structure may emit blue light
- the second light emitting structure may emit green light
- a light emitting diode having multiple tunnel junctions enable the construction of multiple light emitting structures.
- the light emitting diode of the present invention may be configured such that the first light emitting structure is a blue element, the second light emitting structure is a green element, and a red color converting element or a separate light emitting structure is applied to realize a white light emitting diode.
- a white diode can be implemented by itself.
- the light emitting diode having multiple tunnel junctions of the present invention can be preferably applied to the micro LED field. By applying an n-type semiconductor to the common electrode layer, the current spreading effect is enhanced and the luminous efficiency is improved. Furthermore, since the semiconductor layer exposed on the uppermost surface can be applied as an n-type semiconductor, it is possible to suppress damage in the subsequent process.
- FIG. 1 is a schematic view of a light emitting diode according to a preferred embodiment of the present invention.
- FIG. 2A to 2H are views showing a process of manufacturing the light emitting diode of FIG.
- FIG. 3 is a schematic view illustrating a light emitting diode according to another embodiment of the present invention.
- the present invention relates to a light emitting diode comprising multiple light emitting structures and multiple tunnel junctions.
- a preferred embodiment of the present invention provides a structure in which two light emitting structures are arranged on the upper and lower sides of the common electrode layer.
- the common electrode layer may be formed of, for example, an n-type semiconductor layer, and a first tunnel junction layer and a second tunnel junction layer are disposed on the lower surface and the upper surface of the common electrode, respectively.
- the first light emitting structure is arranged to be in contact with the lower surface of the first tunnel junction layer and the second light emitting structure is arranged in contact with the upper surface of the second tunnel junction layer.
- the first light emitting structure and the second light emitting structure are arranged such that the p-type constraint layer is in contact with the tunnel junction layer, and holes are injected into the active regions of the first and second light emitting structures through the common electrode layer.
- the multiple luminescent structure of the present invention not only improves the current spreading effect but also suppresses the exposure of the p-type semiconductor layer, thereby reducing the occurrence of damage relatively in various subsequent processes.
- the multiple LED of the present invention can constitute a combination of various luminescent colors such as blue and green, which widens the choice of applicable phosphors.
- a positive metal contact or a negative metal contact with respect to a metal contact is for distinguishing and designating the metal contact to be formed, and does not limit the kind of the metal to be applied.
- the n-type constraint layer may be selected from a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0? X? 1, 0? Y? 1, 0? X + y?
- a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0? X? 1, 0? Y? 1, 0? X + y?
- GaN, AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN an n-type dopant such as Si, Ge, or Sn can be doped.
- the p-type constraint layer may be selected from a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0? x? 1, 0? y? 1, 0? x + y? 1) AlN, AlGaN, InGaN, InN, InAlGaN, and AlInN, and a p-type dopant such as Mg, Zn, Ca, Sr, or Ba may be doped.
- the active region may be formed of a semiconductor material having a composition formula of In x Al y Ga 1-xy N (0? X? 1, 0? Y? 1, 0? X + y? 1) And a multi quantum well (MQW) structure.
- the tunnel junction layer can be formed such that the n-type dopant and the p-type dopant are contained at relatively higher concentrations, respectively.
- FIG. 1 is a schematic cross-sectional view of a light emitting diode according to a preferred embodiment of the present invention.
- a light emitting diode includes a first light emitting structure and a second light emitting structure disposed on the lower and upper sides of the common electrode layer 31, respectively.
- First and second tunnel junction layers 32 and 33 are disposed between the common electrode layer 31 and the first light emitting structure and between the common electrode layer 31 and the second light emitting structure, respectively.
- the first light-emitting structure and the second light-emitting structure may be, for example, blue and green light, respectively.
- the common electrode layer 31 may be an n-type semiconductor, for example, n-GaN, but is not limited thereto.
- the first tunnel junction layer 32 is disposed on the lower surface of the common electrode layer 31.
- the first tunnel junction layer 32 may have a structure in which an n ++ -GaN layer and a p ++ -GaN layer are sequentially stacked in a downward direction from the common electrode layer 31 side, for example.
- a first light emitting structure is disposed under the first tunnel junction layer 32.
- the first light emitting structure includes a first p-type constraint layer 13, a first active region 12, and a first n-type constraint layer 11, which are sequentially disposed downward from the first tunnel junction layer 32 .
- the second tunnel junction layer 33 is disposed on the upper surface of the common electrode layer 31.
- the second tunnel junction layer 33 may have a structure in which an n ++ -GaN layer and a p ++ -GaN layer are sequentially stacked in the upward direction from the common electrode layer 31 side, for example.
- a second light emitting structure is disposed on the second tunnel junction layer 33.
- the second light emitting structure includes a second p-type constraint layer 23, a second active region 22, and a second n-type constraint layer 21, which are sequentially disposed in the upward direction from the second tunnel junction layer 33 .
- the light emitting diode of the present invention may include a second mesa structure 52 for exposing a part of the upper surface of the common electrode layer 31.
- a positive metal contact 40 may be disposed on the top surface of the common electrode layer 31 exposed by the etched portion of the side surface of the second mesa structure 52.
- the light emitting diode may further include a first mesa structure 51 in which the upper layers of the first n-type constraint layer 11 are removed to expose a part of the upper surface of the first n-type constraint layer 11.
- the first negative metal contact 41 may be disposed on the upper surface of the first n-type constraint layer 11 exposed by the etched portion of the side surface of the first mesa structure 51.
- the common electrode layer 31 and the exposed portion of the first n-type constraint layer 11 in the above-described mesa etching are different from the illustrated example in that the common electrode layer 31 and the first n- The upper surface portion can be etched a little deeper.
- the light emitting diode may include a second negative metal contact 42 disposed on the upper surface of the second n-type constraint layer 21.
- Multiple quantum well structures may be disposed in the first active region 12 and the second active region.
- the first and second tunnel junction layers 32 and 33 are disposed on the lower surface and the upper surface of the common electrode layer 31 made of an n-type semiconductor such as n-GaN, Holes can be injected into the first active region 12 and the second active region 22, thereby realizing a light emitting diode in which two light emitting structures are stacked.
- the common electrode layer 31 for injecting holes can be formed of an n-type semiconductor, the light emitting diode structure of the present invention can provide a common electrode layer 31) is good, and the light emitting efficiency of the light emitting diode is good.
- the semiconductor layer disposed on the uppermost layer may be an n-type semiconductor layer.
- This structure has the effect that the damage of the semiconductor layer, which may occur during the process performed after the completion of the stacking of the entire structure, can be suppressed as compared with the conventional light emitting diode structure in which the p- . Further, since all of the metal contacts 40, 41, 42 are formed on the n-type semiconductor layer, the adhesive force is relatively good.
- the first light emitting structure may emit blue light and the second light emitting structure may emit green light.
- the white color light can be easily realized by applying the red color conversion element. Therefore, Ce3 +: YAG (cerium-doped yttrium aluminum garnet) which causes a discoloration problem applied to a gallium-based blue element to emit white light may not be applied to the diode of the present invention.
- the light emitting device according to the preferred embodiment of the present invention described above can be manufactured through the following process.
- FIGS. 2A to 2G are views illustrating a manufacturing process of a light emitting diode of the present invention.
- a laminated structure for a first light emitting structure is formed on a substrate s such as sapphire.
- a substrate s such as sapphire.
- This can be achieved by sequentially laminating a first n-type constraint layer 11, a layer 120 for the first active region, and a layer 130 for the first p-type constraint layer on the substrate s .
- the first n-type constraint layer 11 may be n-GaN, for example, and the layer 130 for the first p-type constraint layer may be p-GaN.
- a layer 320 for the first tunnel junction layer is formed on the first p-type constraint layer 130 having the structure formed in FIG. 2A.
- a structure in which a p ++ -GaN layer and an n ++ -GaN layer are stacked from bottom to top can be applied.
- a layer 310 for the common electrode layer is formed of n-GaN on the layer 320 for the first tunnel junction layer.
- a layer 330 for the second tunnel junction layer is formed on the layer 310 for the common electrode layer.
- a structure in which an n ++ -GaN layer and a p ++ -GaN layer are stacked from bottom to top on a layer 310 for a common electrode layer can be applied.
- a layer structure for the second light emitting structure is formed on the layer 330 for the second tunnel junction.
- a layer 230 for the second p-type confinement layer, a layer 220 for the second active region, and a layer for the second n-type confinement layer may be formed on the layer 330 for the second tunnel junction layer 210 are sequentially formed.
- the layer 230 for the second p-type confinement layer and the layer 210 for the second n-type confinement layer are formed of p-GaN and n-GaN, respectively.
- a first mesa structure 51 is formed.
- the first mesa structure may be formed by removing a portion of the upper layers so as to expose a part of the upper surface of the first n-type constraint layer 11.
- the first tunnel junction layer 32, and the common electrode layer 31 are completed.
- the second mesa structure 52 is formed so that a part of the upper surface of the common electrode layer 310 is exposed.
- the second mesa structure 52 includes a layer 330 for a second tunnel junction layer on the common electrode layer 31, a layer 230 for a second p-type confinement layer, a layer 220 for a second active region, And the layer 210 for the second n-type confinement layer are partially removed.
- the second n-type constraint layer 21, the second active region 22, the second p-type constraint layer 23 of the second light emitting structure are formed by forming the second mesa structure 52, And the second tunnel junction layer 33 are completed.
- the positive metal contact 40 and the first negative metal contact 30 are formed on the common electrode layer 31, the first n-type constraint layer 11 and the second n-type constraint layer 21, respectively, 41, and a second negative metal contact 42 are formed.
- FIG 3 is a cross-sectional view schematically illustrating a light emitting diode according to another embodiment of the present invention.
- FIG. 3 shows a configuration including three or more active regions 12, 22, 62.
- the second n-type constraint layer 21 disposed on the bottom surface of the third active region 62 is commonly used in the uppermost layer of the light emitting diode of the preferred embodiment of FIG.
- a third active region 62 is formed thereon, and a third p-type confinement layer 63 is disposed on the third active region 62.
- the third tunnel junction layer 34 may be disposed on the third p-type constraint layer 63, and the uppermost n-type semiconductor layer 61 may be disposed thereon. In this way, a plurality of light emitting structures can be continuously stacked in the upward direction.
- the light emitting diode of FIG. 3 may include a mesa structure 53 and a positive contact 43, and such a structure may implement a white diode by itself.
- the third tunnel junction layer 34 and the uppermost n-type semiconductor layer 61 may be removed in the structure of FIG.
- the light emitting diode of the present invention shown in FIGS. 2 and 3 can be driven separately for each light emitting structure, and in this case, it is possible to emit a desired color.
- first n-type constraint layer 12 first active region
- first p-type constraint layer 23 second p-type constraint layer
- n-type semiconductor layer 62 third active region
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Abstract
Description
Claims (7)
- 발광 다이오드로서:공통 전극층;상기 공통 전극층 하면과 상면에 각각 배치된 제1 및 제2 터널정션층;상기 제1 터널정션층의 하면에 배치된 제1 발광구조; 및상기 제2 터널정션층의 상면에 배치된 제2 발광구조;를 포함하는 발광 다이오드.
- 청구항 1에 있어서, 상기 제1 발광구조는:제1 활성영역을 사이에 개재한 제1 n형 구속층과 제1 p형 구속층을 포함하고, 상기 제1 p형 구속층이 상기 제1 터널정션층에 접하는 것인, 발광 다이오드.
- 청구항 1에 있어서, 상기 제2 발광구조는:제2 활성영역을 사이에 개재한 제2 p형 구속층과 제2 n형 구속층을 포함하고, 상기 제2 p형 구속층이 상기 제2 터널정션층에 접하는 것인, 발광 다이오드.
- 청구항 1에 있어서,상기 공통 전극층은 n형 반도체인, 발광 다이오드.
- 청구항 1 내지 4 중 어느 하나에 있어서,상기 공통 전극층의 상면의 일부를 노출하기 위하여 상기 공통 전극층의 상위층들을 제거한 제2 메사구조와,상기 제2 메사구조에 의해 노출된 상기 공통 전극층의 상면에 형성된 금속 콘택을 포함하는 것인, 발광 다이오드.
- 청구항 5에 있어서,상기 제1 n형 구속층의 상면의 일부를 노출하기 위하여 상기 제1 n형 구속층의 상위층들을 제거한 제1 메사구조와,상기 제1 메사구조에 의해 노출된 상기 제1 n형 구속층의 상면에 형성된 금속 콘택을 포함하는 것인, 발광 다이오드.
- 청구항 6에 있어서,상기 제2 n형 구속층의 상면에 형성된 금속 콘택을 더 포함하는 것인, 발광 다이오드.
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US16/648,662 US11152537B2 (en) | 2017-09-19 | 2018-09-04 | Light emitting diode with multiple tunnel junction structure |
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KR1020170120141A KR101931798B1 (ko) | 2017-09-19 | 2017-09-19 | 다중 터널 정션 구조를 가지는 발광 다이오드 |
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KR102170243B1 (ko) * | 2019-06-24 | 2020-10-26 | 주식회사 썬다이오드코리아 | 공융 금속-합금 본딩을 이용한 다중 접합 발광 다이오드 및 이의 제조방법 |
US20200411724A1 (en) * | 2019-06-27 | 2020-12-31 | Lumileds Llc | Nanocone arrays for enhancing light outcoupling and package efficiency |
KR102273917B1 (ko) * | 2019-10-15 | 2021-07-07 | 주식회사 썬다이오드코리아 | 마이크로 디스플레이의 화소 및 이의 제조방법 |
US11489089B2 (en) | 2020-06-19 | 2022-11-01 | Lextar Electronics Corporation | Light emitting device with two vertically-stacked light emitting cells |
US20230420607A1 (en) * | 2022-06-24 | 2023-12-28 | Lumileds Llc | High flux led with low operating voltage |
US20230420599A1 (en) * | 2022-06-24 | 2023-12-28 | Lumileds Llc | High flux led with low operating voltage utilizing two p-n junctions connected in parallel and having one tunnel junction |
US20230420627A1 (en) * | 2022-06-24 | 2023-12-28 | Lumileds Llc | Compact arrays of color-tunable pixels having two p-n junctions |
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Also Published As
Publication number | Publication date |
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US20200287080A1 (en) | 2020-09-10 |
KR101931798B1 (ko) | 2018-12-21 |
US11152537B2 (en) | 2021-10-19 |
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