WO2019056992A1 - 像素结构、阵列基板及显示装置 - Google Patents

像素结构、阵列基板及显示装置 Download PDF

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Publication number
WO2019056992A1
WO2019056992A1 PCT/CN2018/105738 CN2018105738W WO2019056992A1 WO 2019056992 A1 WO2019056992 A1 WO 2019056992A1 CN 2018105738 W CN2018105738 W CN 2018105738W WO 2019056992 A1 WO2019056992 A1 WO 2019056992A1
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Prior art keywords
strip electrode
electrode
strip
pixel structure
thin film
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PCT/CN2018/105738
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English (en)
French (fr)
Inventor
王小元
杨妮
方琰
许亨艺
李云泽
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18857955.1A priority Critical patent/EP3686665B1/en
Priority to US16/473,970 priority patent/US10921655B2/en
Publication of WO2019056992A1 publication Critical patent/WO2019056992A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel structure, an array substrate, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD can be classified into two types, a vertical electric field type and a horizontal electric field type, depending on the direction of the electric field driving the liquid crystal.
  • the vertical electric field type needs to form a pixel electrode on the array substrate, and form a common electrode on a color filter substrate (CF substrate), such as a commonly used TN (Twist Nematic) mode; and a horizontal electric field type It is necessary to simultaneously form a pixel electrode and a common electrode on the array substrate, such as an ADS mode (Advanced Super Dimensional Switching).
  • CF substrate color filter substrate
  • ADS mode Advanced Super Dimensional Switching
  • a pixel structure including: a plate electrode, an interlayer insulating layer, and a strip electrode configured to be sequentially disposed on a substrate;
  • the strip electrode includes a first strip electrode, a second strip electrode, and a third strip electrode
  • the first strip electrode is disposed opposite to the plate electrode such that an orthographic projection of the first strip electrode on the substrate at least partially overlaps with an orthographic projection of the plate electrode on the substrate;
  • the first strip electrode and the plate electrode are configured to apply different voltages.
  • the second strip electrode and the third strip electrode are alternately and spaced apart;
  • the second strip electrode and the third strip electrode are configured to apply different voltages.
  • the first strip electrode and the third strip electrode are configured to apply the same voltage when displayed, and the plate electrode and the second strip electrode are configured as Apply the same voltage.
  • an orthographic projection of the plate electrode on the substrate covers an orthographic projection of the first strip electrode on the substrate.
  • the first strip electrode is located in an intermediate region of the pixel structure, and the second strip electrode and the third strip electrode are both located in a peripheral region of the pixel structure.
  • the first strip electrode is coupled to the third strip electrode.
  • the first strip electrode is spaced apart from the second strip electrode to be insulated, and the third strip electrode is spaced apart from the second strip electrode to be insulated.
  • one of the pixel structures forms a sub-pixel, and one of the sub-pixels displays a color.
  • the second strip electrode and the plate electrode are connected by a via hole penetrating the interlayer insulating layer.
  • the pixel structure further includes a thin film transistor.
  • the interlayer insulating layer includes: a gate insulating layer and a passivation layer disposed away from the substrate in sequence; wherein
  • a gate of the thin film transistor is located on a surface of the substrate, and a gate of the thin film transistor is disposed in the same layer as the plate electrode;
  • the gate insulating layer is located on a side surface of the gate away from the substrate;
  • An active layer of the thin film transistor is located on a side surface of the gate insulating layer away from the gate;
  • the source and the drain of the thin film transistor are both located on a side surface of the active layer away from the gate insulating layer;
  • the passivation layer is located on a side surface of the source and the drain away from the active layer;
  • the first strip electrode, the second strip electrode, and the third strip electrode are all located on a side surface of the passivation layer away from the source and the drain; a strip electrode is connected to the plate electrode through a via hole penetrating the gate insulating layer and the passivation layer, and the second strip electrode further passes through a via hole penetrating the passivation layer The drain of the thin film transistor is connected.
  • the second strip electrode and the plate electrode together form a pixel electrode; the first strip electrode and the third strip electrode are connected to form a common electrode.
  • the interlayer insulating layer includes: a gate insulating layer and a passivation layer disposed away from the substrate in sequence; wherein
  • a gate of the thin film transistor is located on a surface of the substrate, and a gate of the thin film transistor is disposed in the same layer as the plate electrode;
  • the gate insulating layer is located on a side surface of the gate away from the substrate;
  • An active layer of the thin film transistor is located on a side surface of the gate insulating layer away from the gate;
  • the source and the drain of the thin film transistor are both located on a side surface of the active layer away from the gate insulating layer;
  • the passivation layer is located on a side surface of the source and the drain away from the active layer;
  • the first strip electrode, the second strip electrode, and the third strip electrode are all located on a side surface of the passivation layer away from the source and the drain; a strip electrode is connected to the plate electrode through a via hole penetrating the gate insulating layer and the passivation layer; the third strip electrode passes through a via hole penetrating the passivation layer and the thin film transistor The drain connection.
  • the first strip electrode and the third strip electrode are connected to form a pixel electrode; the second strip electrode and the plate electrode together form a common electrode.
  • the interlayer insulating layer includes a gate insulating layer and a passivation layer disposed away from the substrate in sequence;
  • a gate of the thin film transistor is located on a surface of the substrate
  • An active layer of the thin film transistor is located on a side surface of the gate insulating layer away from the gate, and an active layer of the thin film transistor is disposed in the same layer as the plate electrode;
  • the source and the drain of the thin film transistor are both located on a side surface of the active layer away from the gate insulating layer, and the drain of the thin film transistor is directly connected to the plate electrode;
  • the passivation layer is located on a side surface of the thin film transistor whose source and drain are away from the active layer;
  • the first strip electrode, the second strip electrode, and the third strip electrode are all located on a side surface of the passivation layer away from the source and the drain, and the The two strip electrodes are connected to the plate electrode through a via hole penetrating the passivation layer.
  • the first strip electrode and the third strip electrode are connected to form a common electrode; the second strip electrode and the plate electrode together form a pixel electrode.
  • an array substrate comprising the pixel structure of any of the above.
  • a display device including the array substrate.
  • FIG. 1 is a top plan view of a pixel structure in an array substrate according to an exemplary embodiment of the present disclosure
  • Figure 2 is a cross-sectional view taken along line A-A' of Figure 1;
  • FIG. 3 is a top plan view of a pixel structure according to some embodiments of the present disclosure.
  • FIG. 4 is a cross-sectional view taken along line A-A' when the pixel structure illustrated in FIG. 3 (which is configured to be disposed on a substrate indicated by a broken line) in an ADS display mode;
  • FIG. 5 is a cross-sectional view taken along line BB' when the pixel structure illustrated in FIG. 3 (which is configured to be disposed on a substrate indicated by a broken line) in an ADS display mode;
  • FIG. 6 is a top plan view of still another pixel structure according to some embodiments of the present disclosure.
  • Figure 7 is a cross-sectional view of the pixel structure of Figure 6 (which is configured to be disposed on a substrate indicated by a dashed line) in the CC' direction;
  • FIG. 8 is a top plan view of another pixel structure according to some embodiments of the present disclosure.
  • Figure 9 is a cross-sectional view of the pixel structure of Figure 8 (which is configured to be disposed on a substrate indicated by a dashed line) in the CC' direction;
  • Figure 10 is a cross-sectional view taken along line A-A' when the pixel structure illustrated in Figure 3 (which is configured to be disposed on a substrate indicated by a dashed line) in the HADS display mode;
  • Figure 11 is a cross-sectional view taken along line BB' when the pixel structure illustrated in Figure 3 (which is configured to be disposed on a substrate indicated by a dashed line) in the HADS display mode;
  • FIG. 12 is a top plan view of still another pixel structure according to some embodiments of the present disclosure.
  • Figure 13 is a cross-sectional view of the pixel structure of Figure 12 (which is configured to be disposed on a substrate indicated by a dashed line) in the CC' direction;
  • FIG. 14 is a schematic diagram of an electric field comparison between a pixel structure and a conventional pixel structure according to some embodiments of the present disclosure.
  • ADS refers to a planar electric field wide viewing angle core technology-Advanced Super Dimension Switch, whose core technical characteristics can be described as: passing through the edge of the strip electrode 2 in the same plane.
  • a large-size high-resolution thin film transistor liquid crystal display (TFT-LCD) product especially a display product having a GOA (Gate Driver on Array) structure, is a TV (Television). , TV) product development direction.
  • TFT-LCD thin film transistor liquid crystal display
  • UHD Normal products refer to conventional ultra-clear products, that is, one line of pixels of the display is controlled by one gate line;
  • UHD Dual Gate products refer to ultra-high-definition products with dual gates (gate lines), that is, displays The row of pixels is controlled by two gate lines; the 1H charging time is only about 7.4 ⁇ s, which means that each row (ie, 1H, H is the first letter of the Chinese alphabet of "row"), the gate line is turned on (ie, the charging time) ) is 7.4 ⁇ s.
  • the charging rate is generally satisfied by increasing the W/L value of the thin film transistor (TFT) (using SSM/MSM), increasing the line width of the trace, and reducing the resistance.
  • TFT thin film transistor
  • increasing the TFT size and line width further reduces the originally smaller pixel aperture ratio, thereby affecting the transmittance of the display panel and increasing the backlight power consumption.
  • the distance between the source and the drain of the TFT is referred to as the channel length (L), and the vertical L direction is the width of the source and the drain (W); the W/L value refers to the width and length of the channel ratio.
  • SSM is a preparation technology of TFT, which is the abbreviation of Single Slit Mask, which is to prepare TFT by using single slit mask; MSM is another preparation technology of TFT, which is short for Modified Single Slit Mask, that is, using improved single The slit mask is used to prepare the TFT.
  • the lateral capacitance and the overlapping capacitance formed between the two electrodes (the strip electrode 2 and the plate electrode 1) on the array substrate constitute a storage capacitor.
  • Storage Capacitance (Csc) is an important factor affecting the charging rate.
  • some embodiments of the present disclosure provide a pixel structure, including: a plate electrode 1, an interlayer insulating layer 5, and a strip electrode configured to be sequentially disposed on the substrate 10;
  • the electrode 20 includes a first strip electrode 21, a second strip electrode 22, and a third strip electrode 23; the first strip electrode 21 is disposed opposite to the plate electrode 1 such that the first strip electrode 21 is on the substrate 10.
  • the orthographic projection at least partially overlaps the orthographic projection of the plate electrode 1 on the substrate 10; in display, the first strip electrode 21 and the plate electrode 1 are configured to apply different voltages.
  • first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 is not limited, that is, the first strip electrode 21 is at least one strip and the second strip is At least one of the electrodes 22 and at least one of the third strip electrodes 23 are provided.
  • the first strip electrode 21 is disposed opposite to the plate electrode 1, such that the orthographic projection of the first strip electrode 21 on the substrate 10 at least partially overlaps with the orthographic projection of the plate electrode 1 on the substrate 10, in the first strip A storage capacitor is formed between the portion of the electrode 21 that overlaps with the orthographic projection of the plate electrode 1.
  • the first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 are disposed in the same layer, and the plate electrode 1 is only in the strip electrode 20
  • the first strip electrodes 21 are oppositely disposed. Therefore, an overlap capacitance is formed only between the first strip electrodes 21 and the plate electrodes 1, which greatly reduces the strip electrodes 20 and the plate electrodes 1 compared to the conventional pixel structure.
  • the area of the overlapping capacitance formed between, that is, the capacitance of the storage capacitor formed between the strip electrode 20 and the plate electrode 1 is reduced, thereby increasing the charging rate of the pixel structure.
  • the above-described embodiments provided by the present disclosure can satisfy the charging rate requirement by, for example, increasing the TFT size and/or the line width by reducing the capacitance of the storage capacitor. Therefore, there is no influence on the aperture ratio of the originally smaller pixel, so that the pixel aperture ratio can be prevented from being lowered.
  • the orthographic projection of the plate electrode 1 on the substrate 10 may cover the orthographic projection of the first strip electrode 21 on the substrate 10.
  • the second strip electrode 22 and the third strip electrode 23 are alternately and spaced apart; when displayed, the second strip electrode 22 and the third strip electrode 23 are configured to apply different voltages.
  • a horizontal electric field can be formed between the second strip electrode 22 and the third strip electrode 23; when the pixel structure is applied to a liquid crystal display device, the horizontal electric field can be used to increase the control of the deflection of the liquid crystal molecules.
  • the first strip electrode 21 and the third strip electrode 23 are configured to apply the same voltage
  • the plate electrode 1 and the second strip electrode 22 are configured to apply the same voltage
  • the first strip electrode 21 is disposed in an intermediate portion of the pixel structure, and since the plate electrode 1 is disposed opposite to the first strip electrode 21 of the strip electrode 20, Therefore, the plate electrode 1 is also disposed in the intermediate portion of the pixel structure; both the second strip electrode 22 and the third strip electrode 23 are disposed in the peripheral region of the pixel structure.
  • the first strip electrode 21 and the third strip electrode 23 are connected so that the first strip electrode 21 and the third strip electrode 23 have the same potential when displayed;
  • the second strip electrode 22 is The plate electrode 1 is connected to the via hole penetrating the interlayer insulating layer so that the second strip electrode 22 and the plate electrode 1 have the same potential at the time of display.
  • the first strip electrode 21 is spaced apart from the second strip electrode 22 to be insulated, and the third strip electrode 23 is spaced apart from the second strip electrode 22 to be insulated.
  • the first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 are disposed in the same layer, that is, both are disposed on the same surface of the interlayer insulating layer 5.
  • connection between the first strip electrode 21 and the third strip electrode 23 may be exemplified by the first strip shape by the lateral electrode 21a disposed at an angle with the strip direction.
  • the electrode 21 is connected to the third strip electrode 23.
  • one of the above pixel structures forms a sub-pixel, and one sub-pixel corresponds to one color.
  • the pixel structure in some embodiments of the present disclosure may be an ADS display mode or a HADS (ie, high transmittance ADS) display mode.
  • ADS ADS display mode
  • HADS high transmittance ADS
  • the pixel structure of the ADS display mode in some embodiments of the present disclosure includes: a strip electrode 20, a plate electrode 1 and a thin film transistor 6 (restricted by the cross-sectional direction, FIG. The thin film transistor 6) is not illustrated in both 4 and 5.
  • the interlayer insulating layer 5 located between the plate electrode 1 and the strip electrode 20 includes a gate insulating layer 3 and a passivation layer 4 which are disposed away from the substrate 10 in sequence; wherein, as shown in FIGS. 6 and 7, the thin film transistor 6
  • the gate G is located on the surface of the substrate 10, and the gate G of the thin film transistor 6 is disposed in the same layer as the plate electrode 1;
  • the gate insulating layer 3 is located on the side of the layer where the gate G is located away from the substrate 10;
  • the active layer L of 6 is located on a side surface of the gate insulating layer 3 away from the gate G;
  • the source S and the drain D of the thin film transistor 6 are both located on a side surface of the active layer L away from the gate insulating layer 3.
  • the passivation layer 4 is located on a side surface of the source S and the drain D away from the active layer L; the first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 are all located on the passivation layer 4 Upper (here, the first strip electrode 21 and the third strip electrode 23 are shown in FIG. 4); the second strip electrode 22 passes through the via hole V 1 and the plate electrode penetrating the gate insulating layer 3 and the passivation layer 4 1 is connected, and the second strip electrode 22 is also connected to the drain D of the thin film transistor 6 through a via V 2 penetrating through the passivation layer 4.
  • the first strip electrode 21 and the third strip electrode 23 are both common electrodes; the second strip electrode 22 and the plate electrode 1 are both pixel electrodes. That is, the second strip electrode 22 and the plate electrode 1 together form a pixel electrode; the first strip electrode 21 and the third strip electrode 23 are connected to form a common electrode.
  • the third strip electrode 23 passes through the via hole penetrating the passivation layer.
  • the first strip electrode 21 and the third strip electrode 23 are pixel electrodes; the second strip electrode 22 and the plate electrode 1 are common electrodes.
  • the above structure is exemplified by: the pixel structure further includes a thin film transistor 6; the interlayer insulating layer 5 includes: a gate insulating layer disposed in turn away from the substrate 10 3 and a passivation layer 4; wherein, as shown in FIGS.
  • the gate G of the thin film transistor 6 is located on the surface of the substrate 10, and the gate G of the thin film transistor 6 is disposed in the same layer as the plate electrode 1;
  • the pole insulating layer 3 is located on a side surface of the gate G away from the substrate 10;
  • the active layer L of the thin film transistor 6 is located on a side surface of the gate insulating layer 3 away from the gate G;
  • the poles D are all located on a side surface of the active layer L away from the gate insulating layer 3;
  • the passivation layer 4 is located on a side surface of the source S and the drain D away from the active layer L;
  • the second strip electrode 22 and the third strip electrode 23 are both located on a side surface of the passivation layer 4 away from the source S and the drain D;
  • the second strip electrode 22 passes through the gate insulating layer 3 and the passivation layer.
  • vias V 1 1 is connected to the plate electrode 4;
  • the first strip electrode 21 and the third strip electrode 23 are connected to form a pixel electrode; the second strip electrode 22 and the plate electrode 1 together form a common electrode.
  • the pixel structure as the HADS display mode in the present embodiment includes: a strip electrode 20, a plate electrode 1 and a thin film transistor 6 (limited by the cross-sectional direction, FIG. 10 and The thin film transistor 6) is not illustrated in FIG.
  • the interlayer insulating layer 5 between the plate electrode 1 and the strip electrode 20 includes a passivation layer 4; wherein the gate G of the thin film transistor 6 is located on the surface of the substrate 10; gate insulating is provided on the gate G Layer 3; the active layer L of the thin film transistor 6 is located on the side of the gate insulating layer 3 away from the gate G, and the active layer L of the thin film transistor 6 is disposed in the same layer as the plate electrode 1; the source of the thin film transistor 6 The terminal S and the drain D are both located on a side surface of the active layer L away from the gate insulating layer 3, and the drain D of the thin film transistor 6 is directly connected to the plate electrode 1; the passivation layer 4 is located at the source of the thin film transistor 6.
  • the first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 are all located on a side surface of the passivation layer 4 away from the source S and the drain D ( Here, the first strip electrode 21 and the third strip electrode 23 are shown in FIG. 4), and the second strip electrode 22 is connected to the plate electrode 1 through the via hole V penetrating the passivation layer 4; the first strip electrode 21 is connected to the third strip electrode 23 (see Fig. 3 here).
  • the first strip electrode and the third strip electrode are common electrodes; the second strip electrode and the plate electrode are pixel electrodes.
  • the materials of the first strip electrode 21, the second strip electrode 22, and the third strip electrode 23 all include a transparent conductive material or both include a metal material, specifically It is an indium tin oxide or MoTi (molybdenum titanium) alloy.
  • the material of the plate electrode 1 is a transparent conductive material, and the transparent conductive material may be Indium Tin Oxide (ITO). Of course, the transparent conductive material may also adopt other transparent conductive materials.
  • ITO Indium Tin Oxide
  • FIG. 14 a schematic diagram of electric field comparison between the above pixel structure and a conventional pixel structure provided by some embodiments of the present disclosure, as can be seen from FIG. 14 , in the conventional pixel structure, due to the strip electrode 2 and the plate electrode 1 almost completely overlaps, the storage capacity formed between the two is relatively large, and only a fringe electric field can be formed between the two, and the Op (Operation Voltage) is large, thereby causing a large logic power consumption of the product. .
  • the board is reduced.
  • the relative area between the electrode 1 and the strip electrode 20 is such that the storage capacity formed therebetween is small.
  • first strip electrode 21 and the plate electrode 1 are disposed in the intermediate portion of the pixel structure, the first strip electrode 21 and the plate electrode 1 are configured to have different potentials when displayed; and the first strip electrode 21
  • the second strip electrode 22 and the third strip electrode 23 disposed in the same layer are both disposed in the peripheral region of the pixel structure (ie, the left and right sides in FIG. 14), and the second strip electrode 22 and the third strip electrode 23 are displayed. It is also configured to have different potentials.
  • the edge electric field formed between the plate electrode 1 and the first strip electrode 21 disposed oppositely can be used to control the deflection of the liquid crystal molecules; and the second strip electrode 22 and the third strip disposed in the same layer on the left and right sides are utilized.
  • the horizontal electric field formed between the electrodes 23 controls the deflection of the liquid crystal molecules.
  • the horizontal electric field on the left and right sides is lower than the Vop in the middle edge electric field, thereby reducing the logic power consumption of the product.
  • some embodiments of the present disclosure also provide an array substrate and a display device, wherein the array substrate includes the above pixel structure.
  • the display device includes the array substrate.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of the embodiment may further include other conventional structures such as a power supply unit, a display driving unit, and the like.

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Abstract

一种像素结构、阵列基板及显示装置，属于显示技术领域。像素结构包括：配置为适于依次设置在基底(10)上的板状电极(1)、层间绝缘层(5)、条状电极(20)；其中，条状电极(20)包括第一条状电极(21)、第二条状电极(22)、第三条状电极(23)；第一条状电极(21)与板状电极(1)相对设置，使第一条状电极(21)在基底(10)上的正投影与板状电极(1)在基底(10)上的正投影至少部分重叠；在显示时，第一条状电极(21)与板状电极(1)配置为施加不同电压。

Description

像素结构、阵列基板及显示装置
本申请要求于2017年09月22日提交中国专利局、申请号为201710867032.5、发明名称为“像素结构、阵列基板及显示装置”的中国专利申请的优先权和权益，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种像素结构、阵列基板及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)是一种重要的显示设备。根据驱动液晶的电场方向的不同，可以将TFT-LCD分为垂直电场型和水平电场型这两种类型。其中，垂直电场型需要在阵列基板上形成像素电极，在彩膜基板(Color Filter，简称CF基板)上形成公共电极，如常用的TN(Twist Nematic，扭曲向列型)模式；而水平电场型则需要在阵列基板上同时形成像素电极和公共电极，如ADS模式(Advanced Super Dimensional Switching，高级超维场转换模式)。
发明内容
在本公开实施例的一个方面，提供一种像素结构，包括：配置为适于依次设置在基底上的板状电极、层间绝缘层、条状电极；其中，
所述条状电极包括第一条状电极、第二条状电极、第三条状电极；
所述第一条状电极与所述板状电极相对设置，使所述第一条状电极在所述基底上的正投影与所述板状电极在所述基底上的正投影至少部分重叠；
在显示时，所述第一条状电极与所述板状电极配置为施加不同电压。
在本公开的一些实施例中，所述第二条状电极与所述第三条状电极交替且间隔设置；
在显示时，所述第二条状电极与所述第三条状电极配置为施加不同电压。
在本公开的一些实施例中，在显示时，所述第一条状电极据与所述第三条状电极配置为施加相同电压，所述板状电极与所述第二条状电极配置 为施加相同电压。
在本公开的一些实施例中，所述板状电极在所述基底上的正投影覆盖所述第一条状电极在所述基底上的正投影。
在本公开的一些实施例中，所述第一条状电极位于所述像素结构的中间区域，所述第二条状电极和第三条状电极均位于所述像素结构的周边区域。
在本公开的一些实施例中，所述第一条状电极与所述第三条状电极连接。
在本公开的一些实施例中，所述第一条状电极与所述第二条状电极间隔以绝缘，所述第三条状电极与所述第二条状电极间隔以绝缘。
在本公开的一些实施例中，一个所述像素结构形成一个亚像素，一个所述亚像素对应显示一种颜色。
在本公开的一些实施例中，所述第二条状电极与所述板状电极通过贯穿所述层间绝缘层的过孔连接。
在本公开的一些实施例中，所述像素结构还包括薄膜晶体管。
在本公开的一些实施例中，所述层间绝缘层包括：依次远离所述基底设置的栅极绝缘层和钝化层；其中，
所述薄膜晶体管的栅极位于所述基底的表面上，且所述薄膜晶体管的栅极与所述板状电极同层设置；
所述栅极绝缘层位于所述栅极远离所述基底的一侧表面上；
所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上；
所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上；
所述钝化层位于所述源极和所述漏极远离所述有源层的一侧表面上；
所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上；所述第二条状电极通过贯穿所述栅极绝缘层和所述钝化层的过孔与所述板状电极连接，且所述第二条状电极还通过贯穿所述钝化层的过孔与所述薄膜晶体管的漏极连接。
在本公开的一些实施例中，所述第二条状电极和所述板状电极共同形成像素电极；所述第一条状电极和所述第三条状电极连接后共同形成公共电极。
在本公开的一些实施例中，所述层间绝缘层包括：依次远离所述基底设置的栅极绝缘层和钝化层；其中，
所述薄膜晶体管的栅极位于所述基底的表面上，且所述薄膜晶体管的栅极与所述板状电极同层设置；
所述栅极绝缘层位于所述栅极远离所述基底的一侧表面上；
所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上；
所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上；
所述钝化层位于所述源极和所述漏极远离所述有源层的一侧表面上；
所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上；所述第二条状电极通过贯穿所述栅极绝缘层和所述钝化层的过孔与所述板状电极连接；所述第三条状电极通过贯穿所述钝化层的过孔与所述薄膜晶体管的漏极连接。
在本公开的一些实施例中，所述第一条状电极和所述第三条状电极连接后共同形成像素电极；所述第二条状电极和所述板状电极共同形成公共电极。
在本公开的一些实施例中，所述层间绝缘层包括依次远离所述基底设置的栅极绝缘层和钝化层；其中，
所述薄膜晶体管的栅极位于所述基底的表面上；
在所述栅极上设置有栅极绝缘层；
所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上，且所述薄膜晶体管的有源层与所述板状电极同层设置；
所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上，且所述薄膜晶体管的漏极直接与所述板状电极连接；
所述钝化层位于所述薄膜晶体管的源极和漏极远离所述有源层的一侧表面上；
所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上，且所述第二条状电极通过贯穿所述钝化层的过孔与所述板状电极连接。
在本公开的一些实施例中，所述第一条状电极和所述第三条状电极连接后共同形成公共电极；所述第二条状电极和所述板状电极共同形成像素 电极。
在本公开实施例的再一个方面，提供一种阵列基板，其中，包括上述任一项所述的像素结构。
在本公开实施例的又一个方面，提供一种显示装置，其中，包括所述的阵列基板。
附图说明
图1为本公开示例性实施例提供的一种阵列基板中的像素结构的俯视图；
图2为图1中沿A-A＇方向的剖视图；
图3为本公开一些实施例提供的一种像素结构的俯视图；
图4为当图3中示意出的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)为ADS显示模式时沿A-A＇方向的剖视图；
图5为当图3中示意出的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)为ADS显示模式时沿B-B＇方向的剖视图；
图6为本公开一些实施例提供的再一种像素结构的俯视图；
图7为图6中的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)沿C-C＇方向的剖视图；
图8为本公开一些实施例提供的另一种像素结构的俯视图；
图9为图8中的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)沿C-C＇方向的剖视图；
图10为当图3中示意出的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)为HADS显示模式时沿A-A＇方向的剖视图；
图11为当图3中示意出的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)为HADS显示模式时沿B-B＇方向的剖视图；
图12为本公开一些实施例提供的又一种像素结构的俯视图；
图13为图12中的像素结构(该像素结构配置为适于设置在以虚线表示的基底上)沿C-C＇方向的剖视图；
图14为本公开一些实施例提供的一种像素结构与常规像素结构形成的电场对比示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
结合图1和2所示，ADS是指平面电场宽视角核心技术-高级超维场转换技术(Advanced Super Dimension Switch)，其核心技术特性可以被描述为：通过同一平面内条状电极2边缘所产生的电场，以及该条状电极2所在的层与板状电极1所在的层之间产生的电场，从而形成多维电场，使液晶盒内位于该条状电极2之间、该条状电极2正上方的所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率、并增大了透光效率。
目前，大尺寸高分辨率薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)产品，尤其是具有GOA(Gate Driver on Array，阵列基板行驱动)结构的显示产品，是TV(Television，电视)产品的重点开发方向。
例如UHD(Ultra High Definition，超高清，分辨率例如为3840*2160)GOA产品，因充电时间短(60Hz下，UD Normal产品1H充电时间仅约为7.4μs，而UHD Dual Gate产品1H充电时间更是减半)，加之GOA驱动能力限制，充电不足是一大难题。
其中，UD(UHD的简写)Normal产品是指常规超清产品，即显示器的一行像素由一条栅极线控制；UHD Dual Gate产品是指具有双Gate(栅极线)的超高清产品，即显示器的一行像素由二条栅极线控制；1H充电时间仅约为7.4μs是指每一行(即1H，H为“行”的中文拼音的第一个字母)栅极线打开的时间(即充电时间)为7.4μs。
为了满足充电率，一般通过采用增大薄膜晶体管(TFT，Thin Film Transistor)的W/L值(采用SSM/MSM)、增加走线的线宽从而减小电阻等方法来满足充电率的要求。然而，增大TFT尺寸和线宽会使原本就较小的像素开口率进一步下降，从而影响显示面板的透过率，增加背光功耗。
其中，TFT的源极和漏极之间的间距称为沟道长(L)，垂直L方向的是源极和漏极的宽度(W)；W/L值即指：沟道的宽长比。
SSM是TFT的一种制备技术，是Single Slit Mask的简称，即利用单狭缝掩膜板制备TFT；MSM是TFT的另一种制备技术，是Modified Single Slit Mask的简称，即利用改良的单狭缝掩膜板制备TFT。
在ADS模式下，阵列基板上两层电极(条状电极2和板状电极1)之间形成的侧向电容和交叠电容构成存储电容。对于ADS显示模式而言，存储电容(Storage Capacitance，简称Csc)大是影响充电率的重要因素。
结合图3-13所示，本公开一些实施例提供一种像素结构，包括：配置 为适于依次设置在基底10上的板状电极1、层间绝缘层5、条状电极；其中，条状电极20包括第一条状电极21、第二条状电极22、第三条状电极23；第一条状电极21与板状电极1相对设置，使第一条状电极21在基底10上的正投影与板状电极1在基底10上的正投影至少部分重叠；在显示时，第一条状电极21与板状电极1配置为施加不同电压。
需要说明的是，本公开对第一条状电极21、第二条状电极22、第三条状电极23的具体数量不作限定，即，第一条状电极21至少为一条，第二条状电极22至少为一条，第三条状电极23至少为一条。
上述的第一条状电极21与板状电极1相对设置，使第一条状电极21在基底10上的正投影与板状电极1在基底10上的正投影至少部分重叠，在第一条状电极21与板状电极1的正投影有重叠的部分之间形成存储电容。
由于在本公开一些实施例提供的像素结构中，第一条状电极21、第二条状电极22、第三条状电极23同层设置，且板状电极1仅与条状电极20中的第一条状电极21相对设置，因此，仅在第一条状电极21与板状电极1之间形成交叠电容，较常规像素结构而言大大减小了条状电极20与板状电极1之间形成的交叠电容的面积，即减少了条状电极20与板状电极1之间形成的存储电容的电容量，从而提高了像素结构的充电速率。
这样一来，本公开提供的上述实施例通过减少存储电容的电容量，可以不需要通过例如增大TFT尺寸和/或走线线宽的方式来满足充电率的要求。故，对原本就较小的像素的开口率不会产生影响，从而可避免降低像素开口率。
在本公开一些实施例中，板状电极1在基底10上的正投影可以覆盖第一条状电极21在基底10上的正投影。
在本公开一些实施例中，第二条状电极22与第三条状电极23交替且间隔设置；在显示时，第二条状电极22与第三条状电极23配置为施加不同电压。这样，第二条状电极22与第三条状电极23之间能够形成水平电场；当该像素结构应用于液晶显示装置中时，能够利用该水平电场增加对液晶分子偏转的控制。
示例的，在显示时，第一条状电极21与第三条状电极23配置为施加相同电压，板状电极1与第二条状电极22配置为施加相同电压。
其中，如图3和图4所示，示例的，将第一条状电极21设置在像素结构的中间区域，由于板状电极1与条状电极20中的第一条状电极21相对 设置，因此，板状电极1也是设置在像素结构的中间区域；将第二条状电极22和第三条状电极23均设置在像素结构的周边区域。
为便于清楚地示意，中间区域和周边区域仅在图4中示意出，并分别标记为S0和S1。
该种设置方式，便于将第一条状电极21与第三条状电极23连接，以使第一条状电极21和第三条状电极23在显示时同电位；将第二条状电极22与板状电极1通过贯穿层间绝缘层的过孔连接，以使第二条状电极22和板状电极1在显示时同电位。
在本公开一些实施例中，第一条状电极21与第二条状电极22间隔以绝缘，第三条状电极23与第二条状电极22间隔以绝缘。
第一条状电极21、第二条状电极22、第三条状电极23同层设置，即均设置在层间绝缘层5的同一表面上。
其中，如图3所示，第一条状电极21与第三条状电极23之间的连接的方式示例的可以为通过与条状方向呈一定夹角设置的横向电极21a将第一条状电极21与第三条状电极23连接在一起。
也可以将所有的第二条状电极22和第三条状电极23均设置在像素结构中的同一侧，将第一条状电极21设置在像素结构中相对于第二条状电极22和第三条状电极23的另一侧。
这样一来，无需增加单独用于控制第二条状电极22的控制信号，同样的，也无需单独增加用于控制第三条状电极23的控制信号，从而可降低生产成本。
在本公开一些实施例中，上述一个像素结构形成一个亚像素(即sub-pixel)，一个亚像素对应显示一种颜色。
其中，本公开一些实施例中的像素结构可以是ADS显示模式，也可以是HADS(即高透过率的ADS)显示模式。以下分别对ADS显示模式的像素结构和HADS的像素结构进行说明。
示例的，如图4和5所示，作为本公开一些实施例中的ADS显示模式的像素结构，包括：条状电极20、板状电极1和薄膜晶体管6(受限于剖视方向，图4和图5中均未示意出薄膜晶体管6)。
位于板状电极1和条状电极20之间的层间绝缘层5包括依次远离基底10设置的栅极绝缘层3和钝化层4；其中，如图6和图7所示，薄膜晶体管6的栅极G位于基底10的表面上，且薄膜晶体管6的栅极G与板状 电极1同层设置；栅极绝缘层3位于栅极G所在层远离基底10的一侧表面上；薄膜晶体管6的有源层L位于栅极绝缘层3远离栅极G的一侧表面上；薄膜晶体管6的源极S和漏极D均位于有源层L远离栅极绝缘层3的一侧表面上；钝化层4位于源极S和漏极D远离有源层L的一侧表面上；第一条状电极21、第二条状电极22、第三条状电极23均位于钝化层4上(此处第一条状电极21和第三条状电极23请参见图4)；第二条状电极22通过贯穿栅极绝缘层3和钝化层4的过孔V 1与板状电极1连接，且第二条状电极22还通过贯穿钝化层4的过孔V 2与薄膜晶体管6的漏极D连接。
在此情况下，第一条状电极21和第三条状电极23均为公共电极；第二条状电极22和板状电极1均为像素电极。即，第二条状电极22和板状电极1共同形成像素电极；第一条状电极21和第三条状电极23连接后共同形成公共电极。
示例的，如果第二条状电极22不与薄膜晶体管的漏极连接，而是第一条状电极21和第三条状电极23连接，第三条状电极23通过贯穿钝化层的过孔与薄膜晶体管的漏极连接，在此情况下，第一条状电极21和第三条状电极23为像素电极；第二条状电极22和板状电极1为公共电极。
作为本公开一些实施例中的ADS显示模式的另一种像素结构，上述结构示例的为：该像素结构还包括薄膜晶体管6；层间绝缘层5包括：依次远离基底10设置的栅极绝缘层3和钝化层4；其中，如图8和图9所示，薄膜晶体管6的栅极G位于基底10的表面上，且薄膜晶体管6的栅极G与板状电极1同层设置；栅极绝缘层3位于栅极G远离基底10的一侧表面上；薄膜晶体管6的有源层L位于栅极绝缘层3远离栅极G的一侧表面上；薄膜晶体管6的源极S和漏极D均位于有源层L远离栅极绝缘层3的一侧表面上；钝化层4位于源极S和漏极D远离有源层L的一侧表面上；第一条状电极21、第二条状电极22、第三条状电极23均位于钝化层4远离源极S、漏极D的一侧表面上；第二条状电极22通过贯穿栅极绝缘层3和钝化层4的过孔V 1与板状电极1连接；第三条状电极23通过贯穿钝化层4的过孔V 2与薄膜晶体管6的漏极D连接。
即，第一条状电极21和第三条状电极23连接后共同形成像素电极；第二条状电极22和板状电极1共同形成公共电极。示例的，如图10和图11所示，作为本实施例中的HADS显示模式的像素结构包括：条状电极 20、板状电极1和薄膜晶体管6(受限于剖视方向，图10和图11中均未示意出薄膜晶体管6)。
位于板状电极1和条状电极20之间的层间绝缘层5包括钝化层4；其中，薄膜晶体管6的栅极G位于基底10的表面上；在栅极G上设置有栅极绝缘层3；薄膜晶体管6的有源层L位于栅极绝缘层3远离栅极G的一侧表面上，且薄膜晶体管6的有源层L与板状电极1同层设置；薄膜晶体管6的源极S和漏极D均位于有源层L远离栅极绝缘层3的一侧表面上，且薄膜晶体管6的漏极D直接与板状电极1连接；钝化层4位于薄膜晶体管6的源极S和漏极D上；第一条状电极21、所述第二条状电极22、第三条状电极23均位于钝化层4远离源极S、漏极D的一侧表面上(此处第一条状电极21和第三条状电极23请参见图4)，且第二条状电极22通过贯穿钝化层4的过孔V与板状电极1连接；第一条状电极21和第三条状电极23连接(此处请参见图3)。
在此情况下，第一条状电极和第三条状电极为公共电极；第二条状电极和板状电极为像素电极。
其中，在本公开提供的一些实施例的像素结构中，第一条状电极21、第二条状电极22、第三条状电极23的材料均包括透明导电材料或者均包括金属材料，具体可以是氧化铟锡或者MoTi(钼钛)合金。
板状电极1的材料为透明导电材料，该透明导电材料可以是氧化铟锡(Indium Tin Oxide，简称ITO)。当然，该透明导电材料也可以采用其他透明导电材料。
如图14所示，为本公开一些实施例提供的上述像素结构与常规像素结构的电场对比示意图，从该图14中可以看出，在常规像素结构中，由于条状电极2和板状电极1几乎完全重叠，二者之间形成的存储电容量较大，并且，二者之间只能形成边缘电场，Vop(Operation Voltage，即工作电压)较大，从而造成产品的逻辑功耗较大。
而在本公开一些实施例提供的上述像素结构中，通过将下方的板状电极1内缩，使该板状电极1仅与条状电极中的第一条状电极21相对设置，减少了板状电极1与条状电极20之间的相对面积，从而使得二者之间形成的存储电容量较小。
并且，由于第一条状电极21、板状电极1设置在像素结构的中间区域，第一条状电极21和板状电极1在显示时配置为具有不同电位；而与第一条 状电极21同层设置的第二条状电极22和第三条状电极23均设置在像素结构的周边区域(即图14中的左右侧)，第二条状电极22和第三条状电极23在显示时也配置为具有不同电位。
这样一来，可以利用板状电极1和相对设置的第一条状电极21之间形成的边缘电场控制液晶分子偏转；而利用左右侧的同层设置的第二条状电极22和第三条状电极23之间形成的水平电场控制液晶分子偏转。左右侧的水平电场相比于中间的边缘电场的Vop更低，从而可减少产品的逻辑功耗。
相应的，本公开一些实施例还提供了一种阵列基板和显示装置，其中阵列基板包括上述的像素结构。显示装置包括该阵列基板。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种像素结构，包括：配置为适于依次设置在基底上的板状电极、层间绝缘层、条状电极；其中，
    所述条状电极包括第一条状电极、第二条状电极、第三条状电极；
    所述第一条状电极与所述板状电极相对设置，使所述第一条状电极在所述基底上的正投影与所述板状电极在所述基底上的正投影至少部分重叠；
    在显示时，所述第一条状电极与所述板状电极配置为施加不同电压。
  2. 根据权利要求1所述的像素结构，其中，所述第二条状电极与所述第三条状电极交替且间隔设置；
    在显示时，所述第二条状电极与所述第三条状电极配置为施加不同电压。
  3. 根据权利要求2所述的像素结构，其中，在显示时，所述第一条状电极据与所述第三条状电极配置为施加相同电压，所述板状电极与所述第二条状电极配置为施加相同电压。
  4. 根据权利要求1所述的像素结构，其中，所述板状电极在所述基底上的正投影覆盖所述第一条状电极在所述基底上的正投影。
  5. 根据权利要求1所述的像素结构，其中，所述第一条状电极位于所述像素结构的中间区域，所述第二条状电极和第三条状电极均位于所述像素结构的周边区域。
  6. 根据权利要求1所述的像素结构，其中，所述第一条状电极与所述第三条状电极连接。
  7. 根据权利要求1所述的像素结构，其中，所述第一条状电极与所述第二条状电极间隔以绝缘，所述第三条状电极与所述第二条状电极间隔以绝缘。
  8. 根据权利要求1所述的像素结构，其中，一个所述像素结构形成一个亚像素，一个所述亚像素对应显示一种颜色。
  9. 根据权利要求1所述的像素结构，其中，所述第二条状电极与所述板状电极通过贯穿所述层间绝缘层的过孔连接。
  10. 根据权利要求1所述的像素结构，其中，所述像素结构还包括薄膜晶体管。
  11. 根据权利要求10所述的像素结构，其中，所述层间绝缘层包括：依次远离所述基底设置的栅极绝缘层和钝化层；其中，
    所述薄膜晶体管的栅极位于所述基底的表面上，且所述薄膜晶体管的栅极与所述板状电极同层设置；
    所述栅极绝缘层位于所述栅极远离所述基底的一侧表面上；
    所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上；
    所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上；
    所述钝化层位于所述源极和所述漏极远离所述有源层的一侧表面上；
    所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上；所述第二条状电极通过贯穿所述栅极绝缘层和所述钝化层的过孔与所述板状电极连接，且所述第二条状电极还通过贯穿所述钝化层的过孔与所述薄膜晶体管的漏极连接。
  12. 根据权利要求11所述的像素结构，其中，
    所述第二条状电极和所述板状电极共同形成像素电极；
    所述第一条状电极和所述第三条状电极连接后共同形成公共电极。
  13. 根据权利要求10所述的像素结构，其中，所述层间绝缘层包括：依次远离所述基底设置的栅极绝缘层和钝化层；其中，
    所述薄膜晶体管的栅极位于所述基底的表面上，且所述薄膜晶体管的栅极与所述板状电极同层设置；
    所述栅极绝缘层位于所述栅极远离所述基底的一侧表面上；
    所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上；
    所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上；
    所述钝化层位于所述源极和所述漏极远离所述有源层的一侧表面上；
    所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上；所述第二条状电极通过贯穿所述栅极绝缘层和所述钝化层的过孔与所述板状电极连接；所述第三条状电极通过贯穿所述钝化层的过孔与所述薄膜晶体管的漏极连接。
  14. 根据权利要求13所述的像素结构，其中，
    所述第一条状电极和所述第三条状电极连接后共同形成像素电极；
    所述第二条状电极和所述板状电极共同形成公共电极。
  15. 根据权利要求10所述的像素结构，其中，所述层间绝缘层包括依次远离所述基底设置的栅极绝缘层和钝化层；其中，
    所述薄膜晶体管的栅极位于所述基底的表面上；
    在所述栅极上设置有栅极绝缘层；
    所述薄膜晶体管的有源层位于所述栅极绝缘层远离所述栅极的一侧表面上，且所述薄膜晶体管的有源层与所述板状电极同层设置；
    所述薄膜晶体管的源极和漏极均位于所述有源层远离所述栅极绝缘层的一侧表面上，且所述薄膜晶体管的漏极直接与所述板状电极连接；
    所述钝化层位于所述薄膜晶体管的源极和漏极远离所述有源层的一侧表面上；
    所述第一条状电极、所述第二条状电极、所述第三条状电极均位于所述钝化层远离所述源极、所述漏极的一侧表面上，且所述第二条状电极通过贯穿所述钝化层的过孔与所述板状电极连接。
  16. 根据权利要求15所述的像素结构，其中，
    所述第一条状电极和所述第三条状电极连接后共同形成公共电极；
    所述第二条状电极和所述板状电极共同形成像素电极。
  17. 一种阵列基板，其中，包括权利要求1-16中任一项所述的像素结构。
  18. 一种显示装置，其中，包括权利要求17所述的阵列基板。
PCT/CN2018/105738 2017-09-22 2018-09-14 像素结构、阵列基板及显示装置 WO2019056992A1 (zh)

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