WO2019041894A1 - 一种柔性薄膜晶体管及其制备方法 - Google Patents

一种柔性薄膜晶体管及其制备方法 Download PDF

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WO2019041894A1
WO2019041894A1 PCT/CN2018/087309 CN2018087309W WO2019041894A1 WO 2019041894 A1 WO2019041894 A1 WO 2019041894A1 CN 2018087309 W CN2018087309 W CN 2018087309W WO 2019041894 A1 WO2019041894 A1 WO 2019041894A1
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insulating layer
film transistor
layer
thin film
flexible thin
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PCT/CN2018/087309
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English (en)
French (fr)
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来春荣
宗记文
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昆山国显光电有限公司
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Publication of WO2019041894A1 publication Critical patent/WO2019041894A1/zh
Priority to US16/540,403 priority Critical patent/US20190371827A1/en

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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a Thin Film Transistor (TFT) and a method for fabricating the same.
  • TFT Thin Film Transistor
  • the thin film transistor includes a substrate 100, a buffer layer 101 formed on the substrate 100, and an active layer 102 formed on the buffer layer 101, formed on the buffer layer 101 and electrically connected to the active layer 102.
  • a first interlayer dielectric layer 106 and a second interlayer dielectric layer 107 are formed on the capacitive insulating layer 105.
  • the thicknesses of the gate insulating layer 103 and the capacitive insulating layer 105 are respectively 120 nm, and the overall thickness of the first interlayer dielectric layer 106 and the second interlayer dielectric layer 107 is about 500 nm.
  • the first interlayer dielectric layer 106 and the second interlayer dielectric layer 107 are mainly used for interlayer insulation in the prior art, and the overall thickness of the two layers is thicker than that of other insulating layers, to some extent, It affects the degree of bending of the thin film transistor.
  • the gate insulating layer 103, the capacitive insulating layer 105, the first interlayer dielectric layer 106, and the second interlayer dielectric layer 107 are all inorganic insulating layers, and the material thereof is an inorganic material having relatively poor elasticity and flexibility, and thus To a certain extent, it also affects the degree of bending of the thin film transistor.
  • embodiments of the present invention provide a flexible thin film transistor and a method for fabricating the same, which are used to improve the bendability of a flexible display screen.
  • One aspect of the present invention provides a flexible thin film transistor including: a substrate; an active layer formed over the substrate; a gate formed over the active layer; and an organic insulating layer formed over the gate.
  • the flexible thin film transistor further includes: an inorganic insulating layer formed on the organic insulating layer.
  • the material of the organic insulating layer is an organic glue or a polyimide.
  • the organic insulating layer is also doped with an inorganic material.
  • the inorganic insulating layer has a thickness in the range of 45 nm to 55 nm.
  • the inorganic insulating layer has a thickness of 50 nm.
  • the thickness of the organic insulating layer is in the range of 300 nm to 450 nm.
  • the organic insulating layer has a thickness of 350 nm.
  • the flexible thin film transistor further includes: a buffer layer formed between the substrate and the active layer; a gate insulating layer formed between the active layer and the gate; and a capacitive insulating layer, Formed between the gate and the organic insulating layer.
  • Another aspect of the present invention provides a method of fabricating a flexible thin film transistor, comprising: forming an active layer over a substrate; forming a gate over the active layer; and forming an organic insulating layer over the gate.
  • the method of fabricating the flexible thin film transistor further comprises: forming an inorganic insulating layer on the organic insulating layer.
  • the forming an inorganic insulating layer on the organic insulating layer comprises: depositing a thin inorganic insulating layer on the organic insulating layer by chemical vapor deposition or film formation, and The inorganic insulating layer is exposed, developed, etched, and then deposited by physical vapor deposition onto the organic insulating layer.
  • forming the active layer over the substrate includes forming at least one buffer layer over the substrate and disposing the active layer on at least one buffer layer.
  • the forming an organic insulating layer over the gate includes:
  • An organic insulating layer is formed on the capacitor metal.
  • the embodiment of the present invention by replacing the interlayer dielectric layer of the prior art with an organic insulating layer, the stress of the interlayer dielectric layer is reduced, and the overall thickness of the interlayer dielectric layer is reduced, thereby improving The degree of flexibility of the flexible display.
  • FIG. 1 is a schematic view showing the structure of a thin film transistor of the prior art.
  • FIG. 2 is a schematic structural diagram of a flexible thin film transistor according to an exemplary embodiment of the invention.
  • FIG. 3 is a schematic structural diagram of a flexible thin film transistor according to another exemplary embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of fabricating a flexible thin film transistor according to an exemplary embodiment of the invention.
  • FIG. 5 is a schematic flow chart of a method of fabricating a flexible thin film transistor according to another exemplary embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a flexible thin film transistor according to an exemplary embodiment of the invention.
  • the flexible thin film transistor includes: a substrate 200; an active layer 202 formed over the substrate 200; a gate 204 formed over the active layer 202; and an organic insulating layer 206 formed over the gate 204 .
  • the substrate 200 is generally a transparent glass substrate, and may be another transparent substrate, such as a transparent plastic substrate, which is not limited in the present invention.
  • the material of the active layer 202 may be polysilicon (p-Si) or amorphous silicon (a-Si).
  • polysilicon is preferred because the electron migration rate of the polysilicon is faster and the stability is higher, which can reduce the area of the thin film circuit and improve the resolution of the display screen.
  • the thickness of the active layer 202 is usually in the range of 20 nm to 50 nm, preferably 45 nm.
  • the material of the gate electrode 204 may be a combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and silver (Ag).
  • the thickness of the gate 206 is typically in the range of 200 nm to 300 nm, preferably 250 nm.
  • the thickness of the organic insulating layer 206 may range from 300 nm to 450 nm, preferably 350 nm.
  • the embodiment of the present invention by replacing the interlayer dielectric layer of the prior art with an organic insulating layer, the stress of the interlayer dielectric layer is reduced, and the overall thickness of the interlayer dielectric layer is reduced, thereby improving The degree of flexibility of the flexible display.
  • the flexible thin film transistor further includes an inorganic insulating layer (not shown) formed on the organic insulating layer 206.
  • the material of the inorganic insulating layer may be one of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
  • the inorganic insulating layer is very thin and has a thickness in the range of 45 nm to 55 nm, preferably 50 nm. In the embodiment of the present invention, considering that the insulating property of the organic insulating layer is far less than the insulating property of the inorganic insulating layer, the thin film transistor can be more effectively improved by arranging a thin inorganic insulating layer on the organic insulating layer 206.
  • the inorganic insulating layer is only 50 nm thick and very thin, it does not have a large influence on the overall thickness of the thin film transistor.
  • the organic insulating layer 206 and the inorganic insulating layer of the embodiment of the present invention have an overall thickness ranging from 345 nm to 505 nm, preferably 400 nm, which is significantly thinner than the prior art first interlayer dielectric layer 106 and the second layer.
  • the overall thickness of the dielectric layer 107 (shown in FIG. 1) is 500 nm, thus saving the manufacturing cost of the thin film transistor.
  • the material of the organic insulating layer 206 is an organic glue or a polyimide.
  • the material of the organic insulating layer 206 may be an organic glue or polyimide (PI) having high electrical resistivity, high strength, high toughness, high insulation, abrasion resistance, high temperature resistance, and corrosion resistance. Since the organic rubber or polyimide has high electrical resistivity, high toughness, and high insulation, the stress of the interlayer dielectric layer is reduced, thereby improving the flexibility of the flexible display panel.
  • PI organic glue or polyimide
  • the organic insulating layer 206 is also doped with an inorganic material.
  • the inorganic material for example, silicon oxide, silicon nitride, etc.
  • the inorganic material particles/pellets may be doped in the organic glue or polyimide of the organic insulating layer 206, or may be disposed on the organic glue or polyimide.
  • the invention is not limited thereto.
  • by doping the inorganic insulating material in the organic insulating layer 206 the insulating property of the organic insulating layer 206 can be further improved, and thus the inorganic insulating layer disposed on the organic insulating layer 206 can be omitted, thereby saving the thin film transistor. Production costs.
  • the flexible thin film transistor further includes: a buffer layer 201 formed between the substrate 200 and the active layer 202; and a gate insulating layer 203 formed on the active layer 202 and the gate 204 And a capacitor insulating layer 205 formed between the gate 204 and the organic insulating layer 206.
  • the material of the buffer layer 201 may be one of silicon oxide, silicon nitride, or a combination thereof.
  • the thickness of the buffer layer 201 is usually in the range of 200 nm to 300 nm, preferably 250 nm. It should be noted that the number of layers of the buffer layer 201 can be set according to actual needs, for example, two layers, three layers, and the like, which is not limited in the present invention.
  • the material of the gate insulating layer 203 may be one of silicon oxide, silicon nitride, or a combination thereof, and may have a thickness in the range of 100 nm to 150 nm, preferably 120 nm.
  • a capacitive insulating layer 205 may be formed between the gate 204 and the organic insulating layer 206, and may have a thickness in the range of 100 nm to 150 nm, preferably 120 nm.
  • a source 207 and a drain 208 are formed on the buffer layer 201 and electrically connected to the active layer 202, respectively.
  • the material of the source 207 and the drain 208 may be a combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and silver (Ag).
  • the thickness of the gate electrode 206 is usually in the range of 200 nm to 300 nm, preferably 250 nm.
  • FIG. 3 is a schematic structural diagram of a flexible thin film transistor according to another exemplary embodiment of the present invention.
  • the flexible thin film transistor includes: a substrate 300; a first buffer layer 301 formed on the substrate 300; a second buffer layer 302 formed on the first buffer layer 301; and an active layer 303 formed in the a second buffer layer 302; a gate insulating layer 304 formed on the active layer 303; a gate 305 formed on the gate insulating 304; a capacitive insulating layer 306 formed on the gate 305; and an organic insulating layer 307 formed On the capacitive insulating layer 306; and the inorganic insulating layer 308, an organic insulating layer 307 is formed.
  • the first buffer layer 301 and the second buffer layer 302 may be sequentially formed on the substrate 300, and the materials of the first buffer layer 301 and the second buffer layer 302 may be one of silicon oxide and silicon nitride. kind or a combination thereof.
  • the material of the first buffer layer 301 is silicon nitride, and its thickness is usually in the range of 45 nm to 55 nm, preferably 50 nm.
  • the material of the second buffer layer 302 is silicon oxide, and its thickness is usually in the range of 200 nm to 300 nm, preferably 250 nm.
  • the materials of the first buffer layer 301 and the second buffer layer 302 may also be organic glue or polyimide, or organic glue or polyimide doped with inorganic materials, that is, in order to improve For the degree of bending of the thin film transistor, any one or two of the first buffer layer 301 and the second buffer layer 302 may be prepared as an organic insulating layer.
  • the material of the gate insulating layer 304 may be one of silicon oxide, silicon nitride, or a combination thereof. It should be noted that the material of the gate insulating layer 304 may also be organic glue or polyimide, or an organic glue or polyimide doped with an inorganic material, that is, in order to improve the bendability of the thin film transistor. To the extent, the gate insulating layer 304 can also be prepared as an organic insulating layer.
  • the material of the capacitive insulating layer 306 may be one of silicon oxide, silicon nitride, or a combination thereof. It should be noted that the material of the capacitor insulating layer 306 may also be organic glue or polyimide, or an organic glue or polyimide doped with an inorganic material, that is, in order to improve the bendability of the thin film transistor.
  • the capacitor insulating layer 306 can also be prepared as an organic insulating layer.
  • the material of the inorganic insulating layer 308 may be one of silicon oxide, silicon nitride, or a combination thereof. Further, the inorganic insulating layer 308 is very thin and has a thickness in the range of 45 nm to 55 nm, preferably 50 nm. In the embodiment of the present invention, in consideration of the fact that the insulating property of the organic insulating layer is far less than the insulating property of the inorganic insulating layer, the thin film can be more effectively improved by arranging a thin inorganic insulating layer 308 on the organic insulating layer 307.
  • the inorganic insulating layer 308 has a thickness of only 50 nm, it is very thin, and therefore does not have a large influence on the overall thickness of the thin film transistor.
  • the organic insulating layer 307 and the inorganic insulating layer 308 of the embodiment of the present invention have an overall thickness in the range of 345 nm to 505 nm, preferably 400 nm, which is significantly thinner than the first interlayer dielectric layer 106 and the second layer of the prior art.
  • the overall thickness of the dielectric layer 107 (shown in FIG. 1) is 500 nm, thereby saving the manufacturing cost of the thin film transistor.
  • the embodiment of the present invention by replacing the interlayer dielectric layer of the prior art by using an organic insulating layer and a thin inorganic insulating layer, the overall stress of the interlayer dielectric layer is reduced, and the flexible display is improved. The degree of bending of the screen.
  • FIG. 4 is a schematic flow chart of a method of fabricating a flexible thin film transistor according to an exemplary embodiment of the invention. As shown in FIG. 4, the method for preparing the flexible thin film transistor includes:
  • the embodiment of the present invention by replacing the interlayer dielectric layer of the prior art with an organic insulating layer, the stress of the interlayer dielectric layer is reduced, and the overall thickness of the interlayer dielectric layer is reduced, thereby improving The degree of flexibility of the flexible display.
  • the method of fabricating the flexible thin film transistor further includes: forming an inorganic insulating layer on the organic insulating layer.
  • the method for fabricating the flexible thin film transistor further includes: forming a buffer layer between the substrate and the active layer; forming a gate insulating layer between the active layer and the gate; and A capacitive insulating layer is formed between the pole and the organic insulating layer.
  • FIG. 5 is a schematic flow chart of a method of fabricating a flexible thin film transistor according to another exemplary embodiment of the present invention. As shown in FIG. 5, the method for preparing the flexible thin film transistor includes:
  • 510 forming a first buffer layer and a second buffer layer on the substrate.
  • the first buffer layer and the second buffer layer are sequentially formed on the cleaned glass substrate or the plastic substrate by a chemical vapor deposition (CVD) method.
  • the first buffer layer and the second buffer layer may be a silicon oxide layer, a silicon nitride layer, or a composite layer of a silicon oxide layer and a silicon nitride layer.
  • the first buffer layer is a silicon nitride layer and the second buffer layer is a silicon oxide layer.
  • an active layer is formed on the second buffer layer by a chemical vapor deposition method, and the material of the active layer is amorphous silicon.
  • the amorphous silicon is converted into polycrystalline silicon by an Excimer Laser Anneal (ELA) process.
  • ELA Excimer Laser Anneal
  • 530 forming a gate insulating layer on the active layer.
  • a gate insulating layer is formed on the active layer by a plasma enhanced chemical vapor deposition (PECVD) method, and the gate insulating layer covers the second buffer layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate electrode directly above the active layer that is, the first metal M1 is formed on the gate insulating layer by a physical vapor deposition (PVD) method. Further, boron ions are implanted into both ends of the active layer to form a source and a drain.
  • PVD physical vapor deposition
  • a capacitive insulating layer is formed on the gate by chemical vapor deposition or film formation, the capacitive insulating layer covering the gate insulating layer.
  • a capacitor metal that is, a second metal M2 is formed on the capacitor insulating layer by physical vapor deposition or film formation.
  • an organic insulating layer is formed on the capacitor metal by applying an organic glue or polyimide, and the organic insulating layer is exposed and developed.
  • a thin inorganic insulating layer is deposited on the organic insulating layer by chemical vapor deposition or film formation, and the inorganic insulating layer is exposed, developed, and etched. Further, a third metal M3 is deposited on the organic insulating layer by physical vapor deposition.
  • the glass substrate or the plastic substrate and the thin film transistor are separated.
  • the material of the first metal M1, the second metal M2, and the third metal M3 may be a combination of one or more of molybdenum, titanium, aluminum, copper, gold, and silver.
  • the embodiment of the present invention by replacing the interlayer dielectric layer of the prior art by using an organic insulating layer and a thin inorganic insulating layer, the overall stress of the interlayer dielectric layer is reduced, and the flexible display is improved. The degree of bending of the screen.
  • the flexible thin film transistor of the present invention and the preparation method thereof reduce the stress of the interlayer dielectric layer and reduce the overall thickness of the interlayer dielectric layer by replacing the interlayer dielectric layer of the prior art with an organic insulating layer, thereby further reducing the overall thickness of the interlayer dielectric layer, and further Increases the flexibility of the flexible display.

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Abstract

本发明公开了一种柔性薄膜晶体管及其制备方法。该柔性薄膜晶体管包括：基板；有源层，形成在基板上方；栅极，形成在有源层上方；以及有机绝缘层，形成在栅极上方。本发明减小了层间介电层的应力，降低了层间介电层的整体厚度，进而提升柔性显示屏的可弯折程度。

Description

一种柔性薄膜晶体管及其制备方法
本发明是要求由申请人提出的，申请日为2017年8月31日，申请号为CN201710776518.8，名称为“一种柔性薄膜晶体管及其制备方法”的申请的优先权。以上申请的全部内容通过整体引用结合于此。
技术领域
本发明涉及显示技术领域，尤其涉及一种柔性薄膜晶体管(Thin Film Transistor，TFT)及其制备方法。
发明背景
随着柔性显示技术的发展，显示屏已经可以制作成可弯曲、可折叠、可卷起的形式。可变型、可弯折的柔性显示屏能够给用户带来颠覆性的使用体验。但目前的柔性显示技术还不够成熟，可弯折仍是技术难点。这是因为柔性显示屏的像素区的无机绝缘层较多，且无机绝缘层的厚度较厚，使得在柔性显示屏发生形变时会产生较大应力，直接影响了柔性显示屏的可弯折程度，进而造成显示不良。
图1是现有技术的薄膜晶体管的结构示意图。如图1所示，该薄膜晶体管包括：基板100、形成在基板100上的缓冲层101、形成在缓冲层101上的有源层102、形成在缓冲层101上且与有源层102电连接的源极108和漏极109、形成在有源层102上的栅极绝缘层103、形成在栅极绝缘层103上的栅极104、形成在栅极104上的电容绝缘层105、以及依次形成在电容绝缘层105上的第一层间介电层106和第二层间介电层107。栅极绝缘层103和电容绝缘层105的厚度分别为120nm，第一层间介电层106和第二层间介电层107的整体厚度约为500nm。
由于现有技术中第一层间介电层106和第二层间介电层107主要用于层间绝缘，且二者的整体厚度比其他绝缘层的厚度更厚，因此，在一定程度上影响了薄膜晶体管的可弯折程度。另外，栅极绝缘层103、电容绝缘层105、第一层间介电 层106和第二层间介电层107均为无机绝缘层，其材料为弹性和柔韧性相对差的无机材料，因此，在一定程度上也影响了薄膜晶体管的可弯折程度。
发明内容
有鉴于此，本发明实施例提供了一种柔性薄膜晶体管及其制备方法，用于提升柔性显示屏的可弯折程度。
本发明的一个方面提供一种柔性薄膜晶体管，包括：基板；有源层，形成在基板上方；栅极，形成在有源层上方；以及有机绝缘层，形成在栅极上方。
在本发明的一个实施例中，该柔性薄膜晶体管还包括：无机绝缘层，形成在有机绝缘层上。
在本发明的一个实施例中，有机绝缘层的材料为有机胶或聚酰亚胺。
在本发明的一个实施例中，有机绝缘层还掺杂有无机材料。
在本发明的一个实施例中，无机绝缘层的厚度在45nm至55nm范围内。
在本发明的一个实施例中，无机绝缘层的厚度为50nm。
在本发明的一个实施例中，有机绝缘层的厚度在300nm至450nm范围内。
在本发明的一个实施例中，有机绝缘层的厚度为350nm。
在本发明的一个实施例中，该柔性薄膜晶体管还包括：缓冲层，形成在基板与有源层之间；栅极绝缘层，形成在有源层与栅极之间；以及电容绝缘层，形成在栅极与有机绝缘层之间。
本发明的另一个方面提供一种柔性薄膜晶体管的制备方法，包括：在基板上方形成有源层；在有源层上方形成栅极；以及在栅极上方形成有机绝缘层。
在本发明的一个实施例中，该柔性薄膜晶体管的制备方法还包括：在有机绝缘层上形成无机绝缘层。
在本发明的一个实施例中，所述在所述有机绝缘层上形成无机绝缘层，包括：通过化学气相沉积或成膜，在有机绝缘层上沉积一层薄薄的无机绝缘层，并对无机绝缘层进行曝光、显影、刻蚀，再通过物理气相沉积，将金属沉积到有机绝缘层上。
在本发明的一个实施例中，在基板上方形成有源层，包括：在基板上方形成至少一层缓冲层，并在至少一层缓冲层上设置所述有源层。
在本发明的一个实施例中，所述在所述栅极上方形成有机绝缘层，包括：
在栅极上形成电容绝缘层；
在电容绝缘层上形成电容金属；
在电容金属上形成有机绝缘层。
根据本发明实施例提供的技术方案，通过采用有机绝缘层替代现有技术的层间介电层，减小了层间介电层的应力，降低了层间介电层的整体厚度，进而提升了柔性显示屏的可弯折程度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。
附图简要说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。
图1是现有技术的薄膜晶体管的结构示意图。
图2是根据本发明一示例性实施例示出的一种柔性薄膜晶体管的结构示意图。
图3是根据本发明另一个示例性实施例示出的一种柔性薄膜晶体管的结构示意图。
图4是根据本发明一示例性实施例示出的一种柔性薄膜晶体管的制备方法的流程示意图。
图5是根据本发明另一个示例性实施例示出的一种柔性薄膜晶体管的制备方法的流程示意图。
实施本发明的方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、 完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是根据本发明一示例性实施例示出的一种柔性薄膜晶体管的结构示意图。如图2所示，该柔性薄膜晶体管包括：基板200；有源层202，形成在基板200上方；栅极204，形成在有源层202上方；以及有机绝缘层206，形成在栅极204上方。
在本发明实施例中，基板200通常为透明的玻璃基板，也可以是其他透明基板，例如透明的塑料基板，本发明对此不作限制。
有源层202的材料可以是多晶硅(p-Si)，也可以是非晶硅(a-Si)。本实施例优先选用多晶硅，因为多晶硅的电子迁移速率较快、稳定性较高，可以减小薄膜电路的面积、提升显示屏的分辨率。有源层202的厚度通常在20nm至50nm范围内，优选为45nm。
栅极204的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)、金(Au)、银(Ag)中的一种或多种的组合。栅极206的厚度通常在200nm至300nm范围内，优选为250nm。
有机绝缘层206的厚度可以在300nm至450nm范围内，优选为350nm。
根据本发明实施例提供的技术方案，通过采用有机绝缘层替代现有技术的层间介电层，减小了层间介电层的应力，降低了层间介电层的整体厚度，进而提升了柔性显示屏的可弯折程度。
在本发明的另一个实施例中，该柔性薄膜晶体管还包括：无机绝缘层(未示出)，形成在有机绝缘层206上。
具体地，无机绝缘层的材料可以是氧化硅(SiOx)、氮化硅(SiNx)中的一种或其组合。另外，无机绝缘层很薄，其厚度在45nm至55nm范围内，优选为50nm。在本发明实施例中，考虑到有机绝缘层的绝缘性远不及无机绝缘层的绝缘性，因此，通过在有机绝缘层206上布置一层薄薄的无机绝缘层，能够更有效地提高薄膜晶体管的绝缘性；此外，由于无机绝缘层的厚度仅为50nm，非常薄，因 此，不会对薄膜晶体管的整体厚度造成太大影响。进一步地，本发明实施例的有机绝缘层206和无机绝缘层的整体厚度在345nm至505nm范围内，优选为400nm，明显薄于现有技术的第一层间介电层106和第二层间介电层107(如图1所示)的整体厚度500nm，因此，节约了薄膜晶体管的制作成本。
在本发明的另一个实施例中，有机绝缘层206的材料为有机胶或聚酰亚胺。
具体地，有机绝缘层206的材料可以是具有高电阻率、高强度、高韧性、高绝缘性、耐磨耗、耐高温、防腐蚀的有机胶或聚酰亚胺(Polyimide，PI)。由于有机胶或聚酰亚胺具有高电阻率、高韧性和高绝缘性，因此，减小了层间介电层的应力，进而提升了柔性显示屏的可弯折程度。
在本发明的另一个实施例中，有机绝缘层206还掺杂有无机材料。
具体地，无机材料(例如氧化硅、氮化硅等)颗粒/小球可以掺杂在有机绝缘层206的有机胶或聚酰亚胺中，或者也可以布置在有机胶或聚酰亚胺上，本发明对此不作限制。本发明实施例中，通过在有机绝缘层206中掺杂无机材料，能够进一步提高有机绝缘层206的绝缘性，并因此可以省略布置在有机绝缘层206上的无机绝缘层，进而节约了薄膜晶体管的制作成本。
在本发明的另一个实施例中，该柔性薄膜晶体管还包括：缓冲层201，形成在基板200与有源层202之间；栅极绝缘层203，形成在有源层202与栅极204之间；以及电容绝缘层205，形成在栅极204与有机绝缘层206之间。
具体地，缓冲层201的材料可以是氧化硅、氮化硅中的一种或其组合。另外，缓冲层201的厚度通常在200nm至300nm范围内，优选为250nm。需要说明的是，缓冲层201的层数可以根据实际需要设置，例如两层、三层等，本发明对此不作限制。
栅极绝缘层203的材料可以是氧化硅、氮化硅中的一种或其组合，其厚度可以在100nm至150nm范围内，优选为120nm。
电容绝缘层205可以形成在栅极204与有机绝缘层206之间，其厚度可以在100nm至150nm范围内，优选为120nm。
进一步地，源极207和漏极208形成在缓冲层201上且分别与有源层202电 连接。源极207和漏极208的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)、金(Au)、银(Ag)中的一种或多种的组合。另外，栅极206的厚度通常在200nm至300nm范围内，优选为250nm。
上述所有可选技术方案，可以采用任意结合形成本发明的可选实施例，在此不再一一赘述。
图3是根据本发明另一个示例性实施例示出的一种柔性薄膜晶体管的结构示意图。如图3所示，该柔性薄膜晶体管包括：基板300；第一缓冲层301，形成在基板300上；第二缓冲层302，形成在第一缓冲层301上；有源层303，形成在第二缓冲层302上；栅极绝缘层304，形成在有源层303上；栅极305，形成在栅极绝缘304上；电容绝缘层306，形成在栅极305上；有机绝缘层307，形成在电容绝缘层306上；以及无机绝缘层308，形成有机绝缘层307上。
需要说明的是，图3所示的柔性薄膜晶体管的结构与图2所示的柔性薄膜晶体管的结构基本相同，因此，下文将仅针对不同之处进行说明。
在本发明实施例中，基板300上可以依次形成第一缓冲层301和第二缓冲层302，并且第一缓冲层301和第二缓冲层302的材料可以是氧化硅、氮化硅中的一种或其组合。具体地，第一缓冲层301的材料为氮化硅，其厚度通常在45nm至55nm范围内，优选为50nm。第二缓冲层302的材料为氧化硅，其厚度通常在200nm至300nm范围内，优选为250nm。需要说明的是，第一缓冲层301和第二缓冲层302的材料也可以是有机胶或聚酰亚胺，或者掺杂有无机材料的有机胶或聚酰亚胺，也就是说，为了提高薄膜晶体管的可弯折程度，也可以将第一缓冲层301和第二缓冲层302中的任一层或二层制备成有机绝缘层。
栅极绝缘层304的材料可以是氧化硅、氮化硅中的一种或其组合。需要说明的是，栅极绝缘层304的材料也可以是有机胶或聚酰亚胺，或者掺杂有无机材料的有机胶或聚酰亚胺，也就是说，为了提高薄膜晶体管的可弯折程度，也可以将栅极绝缘层304制备成有机绝缘层。
电容绝缘层306的材料可以是氧化硅、氮化硅中的一种或其组合。需要说明的是，电容绝缘层306的材料也可以是有机胶或聚酰亚胺，或者掺杂有无机材料 的有机胶或聚酰亚胺，也就是说，为了提高薄膜晶体管的可弯折程度，也可以将电容绝缘层306制备成有机绝缘层。
无机绝缘层308的材料可以是氧化硅、氮化硅中的一种或其组合。另外，无机绝缘层308很薄，其厚度在45nm至55nm范围内，优选为50nm。在本发明实施例中，考虑到有机绝缘层的绝缘性远不及无机绝缘层的绝缘性，因此，通过在有机绝缘层307上布置一层薄薄的无机绝缘层308，能够更有效地提高薄膜晶体管的绝缘性；此外，由于无机绝缘层308的厚度仅为50nm，非常薄，因此，不会对薄膜晶体管的整体厚度造成太大影响。进一步地，本发明实施例的有机绝缘层307和无机绝缘层308的整体厚度在345nm至505nm范围内，优选为400nm，明显薄于现有技术的第一层间介电层106和第二层间介电层107(如图1所示)的整体厚度500nm，因此，节约了薄膜晶体管的制作成本。
根据本发明实施例提供的技术方案，通过采用有机绝缘层加很薄的无机绝缘层替代现有技术的层间介电层，减小了层间介电层的整体应力，并提升了柔性显示屏的可弯折程度。
图4是根据本发明一示例性实施例示出的一种柔性薄膜晶体管的制备方法的流程示意图。如图4所示，该柔性薄膜晶体管的制备方法包括：
410：在基板上方形成有源层。
420：在有源层上方形成栅极。
430：在栅极上方形成有机绝缘层。
根据本发明实施例提供的技术方案，通过采用有机绝缘层替代现有技术的层间介电层，减小了层间介电层的应力，降低了层间介电层的整体厚度，进而提升了柔性显示屏的可弯折程度。
在本发明的另一个实施例中，该柔性薄膜晶体管的制备方法还包括：在有机绝缘层上形成无机绝缘层。
在本发明的另一个实施例中，该柔性薄膜晶体管的制备方法还包括：在基板与有源层之间形成缓冲层；在有源层与栅极之间形成栅极绝缘层；以及在栅极与有机绝缘层之间形成电容绝缘层。
图5是根据本发明另一个示例性实施例示出的一种柔性薄膜晶体管的制备方法的流程示意图。如图5所示，该柔性薄膜晶体管的制备方法包括：
510：在基板上形成第一缓冲层和第二缓冲层。
在本发明实施例中，通过化学气相沉积(Chemical Vapor Deposition，CVD)方法，在清洗洁净的玻璃基板或塑料基板上依次形成第一缓冲层和第二缓冲层。第一缓冲层和第二缓冲层可以是氧化硅层、氮化硅层、或者氧化硅层与氮化硅层的复合层。在该实施例中，第一缓冲层为氮化硅层，第二缓冲层为氧化硅层。
520：在第二缓冲层上形成有源层。
在本发明实施例中，通过化学气相沉积方法，在第二缓冲层上形成有源层，该有源层的材料为非晶硅。接续，通过准分子激光退火(Excimer Laser Anneal，ELA)工艺将非晶硅转化为多晶硅。
530：在有源层上形成栅极绝缘层。
在本发明实施例中，通过等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)方法，在有源层上形成栅极绝缘层，该栅极绝缘层覆盖第二缓冲层。
540：在栅极绝缘层上形成栅极。
在本发明实施例中，通过物理气相沉积(Physical Vapor Deposition，PVD)方法，在栅极绝缘层上形成正对有源层上方的栅极，即第一金属M1。进一步地，对有源层的两端进行硼离子注入形成源极和漏极。
550：在栅极上形成电容绝缘层。
在本发明实施例中，通过化学气相沉积或成膜，在栅极上形成电容绝缘层，该电容绝缘层覆盖栅极绝缘层。
560：在电容绝缘层上形成电容金属。
在本发明实施例中，通过物理气相沉积或成膜，在电容绝缘层上形成电容金属，即第二金属M2。
570：在电容金属上形成有机绝缘层。
在本发明实施例中，通过涂布有机胶或聚酰亚胺，在电容金属上形成有机绝 缘层，并对该有机绝缘层进行曝光、显影。
580：在有机绝缘层上形成无机绝缘层。
在本发明实施例中，通过化学气相沉积或成膜，在有机绝缘层上沉积一层薄薄的无机绝缘层，并对无机绝缘层进行曝光、显影、刻蚀。进一步地，通过物理气相沉积，将第三金属M3沉积到有机绝缘层上。
最后，对玻璃基板或塑料基板和薄膜晶体管进行分离。
需要说明的是，第一金属M1、第二金属M2和第三金属M3的材料可以是钼、钛、铝、铜、金、银中的一种或多种的组合。
根据本发明实施例提供的技术方案，通过采用有机绝缘层加很薄的无机绝缘层替代现有技术的层间介电层，减小了层间介电层的整体应力，并提升了柔性显示屏的可弯折程度。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换等，均应包含在本发明的保护范围之内。
工业实用性
本发明的柔性薄膜晶体管及其制备方法，通过采用有机绝缘层替代现有技术的层间介电层，减小了层间介电层的应力，降低了层间介电层的整体厚度，进而提升了柔性显示屏的可弯折程度。

Claims (14)

  1. 一种柔性薄膜晶体管，其中，包括：
    基板；
    有源层，形成在所述基板上方；
    栅极，形成在所述有源层上方；以及
    有机绝缘层，形成在所述栅极上方。
  2. 根据权利要求1所述的柔性薄膜晶体管，其中，还包括：
    无机绝缘层，形成在所述有机绝缘层上。
  3. 根据权利要求1或2所述的柔性薄膜晶体管，其中，所述有机绝缘层的材料为有机胶或聚酰亚胺。
  4. 根据权利要求3所述的柔性薄膜晶体管，其中，所述有机绝缘层还掺杂有无机材料。
  5. 根据权利要求2所述的柔性薄膜晶体管，其中，所述无机绝缘层的厚度在45nm至55nm范围内。
  6. 根据权利要求5所述的柔性薄膜晶体管，其中，所述无机绝缘层的厚度为50nm。
  7. 根据权利要求1所述的柔性薄膜晶体管，其中，所述有机绝缘层的厚度在300nm至450nm范围内。
  8. 根据权利要求7所述的柔性薄膜晶体管，其中，所述有机绝缘层的厚度为350nm。
  9. 根据权利要求1所述的柔性薄膜晶体管，其中，还包括：
    缓冲层，形成在所述基板与所述有源层之间；
    栅极绝缘层，形成在所述有源层与所述栅极之间；以及
    电容绝缘层，形成在所述栅极与所述有机绝缘层之间。
  10. 一种柔性薄膜晶体管的制备方法，其中，包括：
    在基板上方形成有源层；
    在所述有源层上方形成栅极；以及
    在所述栅极上方形成有机绝缘层。
  11. 根据权利要求10所述的柔性薄膜晶体管的制备方法，其中，还包括：
    在所述有机绝缘层上形成无机绝缘层。
  12. 根据权利要求11所述的柔性薄膜晶体管的制备方法，其中，所述在所述有机绝缘层上形成无机绝缘层，包括：通过化学气相沉积或成膜，在有机绝缘层上沉积一层薄薄的无机绝缘层，并对无机绝缘层进行曝光、显影、刻蚀，再通过物理气相沉积，将金属沉积到有机绝缘层上。
  13. 根据权利要求10所述的柔性薄膜晶体管的制备方法，其中，在基板上方形成有源层，包括：在基板上方形成至少一层缓冲层，并在至少一层缓冲层上设置所述有源层。
  14. 根据权利要求10所述的柔性薄膜晶体管的制备方法，其中，所述在所述栅极上方形成有机绝缘层，包括：
    在栅极上形成电容绝缘层；
    在电容绝缘层上形成电容金属；
    在电容金属上形成有机绝缘层。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109742088B (zh) * 2018-12-29 2021-03-16 武汉华星光电技术有限公司 一种tft阵列基板
CN110690256B (zh) * 2019-08-29 2023-02-03 福建华佳彩有限公司 一种柔性tft基板及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100462823C (zh) * 2002-12-31 2009-02-18 三星电子株式会社 薄膜晶体管及其电子器件和制造方法
US20140332767A1 (en) * 2013-05-09 2014-11-13 Samsung Display Co., Ltd. Thin film transistor and organic light emitting diode display including the same
US9219105B2 (en) * 2014-01-10 2015-12-22 Samsung Display Co., Ltd. Organic light emitting diode display
CN105449127A (zh) * 2016-01-04 2016-03-30 京东方科技集团股份有限公司 发光二极管显示基板及其制作方法、显示装置
US20160197130A1 (en) * 2015-01-05 2016-07-07 Samsung Display Co., Ltd. Display device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586791B1 (en) * 2000-07-19 2003-07-01 3M Innovative Properties Company Transistor insulator layer incorporating superfine ceramic particles
US6825496B2 (en) * 2001-01-17 2004-11-30 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
KR101130404B1 (ko) * 2005-02-16 2012-03-27 삼성전자주식회사 고차가지형 고분자에 분산된 고유전율 절연체를 포함하는유기 절연체 조성물 및 이를 이용한 유기박막 트랜지스터
US7651932B2 (en) * 2005-05-31 2010-01-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing antenna and method for manufacturing semiconductor device
KR100729054B1 (ko) * 2005-11-16 2007-06-14 삼성에스디아이 주식회사 박막 트랜지스터 및 그 제조 방법
KR101363835B1 (ko) * 2007-02-05 2014-02-17 엘지디스플레이 주식회사 표시장치 및 이의 제조 방법
KR101709422B1 (ko) * 2012-11-08 2017-02-22 아사히 가세이 이-매터리얼즈 가부시키가이샤 플렉서블 디바이스용 기판, 플렉서블 디바이스 및 그 제조 방법, 적층체 및 그 제조 방법, 그리고 수지 조성물
KR102022886B1 (ko) * 2012-12-28 2019-09-19 엘지디스플레이 주식회사 유기발광장치
US10199548B2 (en) * 2015-03-27 2019-02-05 Toray Industries, Inc. Photosensitive resin composition for thin film transistors, cured film, thin film transistor, liquid crystal display device or organic electroluminescent display device, method for producing cured film, method for manufacturing thin film transistor, and method for manufacturing liquid crystal display device or organic electroluminescent display device
CN105552084A (zh) * 2015-12-14 2016-05-04 昆山工研院新型平板显示技术中心有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN106783628B (zh) * 2017-02-27 2019-12-03 武汉华星光电技术有限公司 薄膜晶体管的制作方法、薄膜晶体管及显示器
CN106601133B (zh) * 2017-02-28 2020-04-14 京东方科技集团股份有限公司 一种柔性显示面板、其制作方法及显示装置
CN106935549B (zh) * 2017-03-20 2019-11-29 昆山工研院新型平板显示技术中心有限公司 薄膜晶体管阵列基板的制作方法及薄膜晶体管阵列基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100462823C (zh) * 2002-12-31 2009-02-18 三星电子株式会社 薄膜晶体管及其电子器件和制造方法
US20140332767A1 (en) * 2013-05-09 2014-11-13 Samsung Display Co., Ltd. Thin film transistor and organic light emitting diode display including the same
US9219105B2 (en) * 2014-01-10 2015-12-22 Samsung Display Co., Ltd. Organic light emitting diode display
US20160197130A1 (en) * 2015-01-05 2016-07-07 Samsung Display Co., Ltd. Display device
CN105449127A (zh) * 2016-01-04 2016-03-30 京东方科技集团股份有限公司 发光二极管显示基板及其制作方法、显示装置

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