WO2019028947A1 - 一种显示面板和显示装置 - Google Patents

一种显示面板和显示装置 Download PDF

Info

Publication number
WO2019028947A1
WO2019028947A1 PCT/CN2017/099602 CN2017099602W WO2019028947A1 WO 2019028947 A1 WO2019028947 A1 WO 2019028947A1 CN 2017099602 W CN2017099602 W CN 2017099602W WO 2019028947 A1 WO2019028947 A1 WO 2019028947A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
driving chip
connecting portion
out area
source driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/099602
Other languages
English (en)
French (fr)
Inventor
陈猷仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US15/869,654 priority Critical patent/US10620498B2/en
Publication of WO2019028947A1 publication Critical patent/WO2019028947A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133606—Direct backlight including a specially adapted diffusing, scattering or light controlling members
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the existing displays are generally controlled based on the active switch, and have many advantages such as thin body, power saving, no radiation, etc., and have been widely used, mainly including liquid crystal display, OLED (Organic Light-Emitting Diode) display, QLED (Quantum) Dot Light Emitting Diodes), such as displays and plasma displays, have both a flat display and a curved display.
  • OLED Organic Light-Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • displays and plasma displays have both a flat display and a curved display.
  • the liquid crystal display works by placing liquid crystal molecules in two parallel glass substrates and applying a driving voltage on the two glass substrates to control the liquid crystal. The direction of rotation of the molecules to refract the light from the backlight module to produce a picture.
  • the self-luminous display of the machine light-emitting diode is used for display, and has the advantages of self-illumination, wide viewing angle, almost infinite contrast, low power consumption, and extremely high reaction speed.
  • the QLED display structure is very similar to the OLED technology. The main difference is that the luminescent center of the QLED is composed of Quantum dots. Its structure is that two electrons (Electron) and holes (Hole) converge in the quantum dot layer to form photons (Exciton), and recombine by photons.
  • each line of Fan-out is not necessarily equal due to space, etc.
  • the maximum and minimum differences are too large, resulting in insufficient smooth display, especially in the mixed color screen, each driver chip.
  • the outermost fan-out wire has a large resistance value, and the RC delay is severe.
  • the charging rate of the latter pixel is greater than the charging rate of the previous pixel, and a color shift phenomenon occurs on both sides of the driving chip, which affects the display taste and reduces the user's visual experience.
  • a display panel including:
  • the substrate is provided with a display area, a fan-out area and a plurality of driving chips;
  • a plurality of fan-out wires are formed in the fan-out area, one end of the fan-out wire is connected to the signal line, and the other end of the fan-out wire is connected to the driving chip;
  • the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • the driving chip includes a first source driving chip and a second source driving chip.
  • the fan-out area includes a first fan-out area and a second fan-out area, the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip, and the second fan The output area includes a plurality of second fan-out wires connected to the second source driving chip;
  • the connecting portion includes a first connecting portion formed in the first fan-out area, a second connecting portion formed in the second fan-out area, the first source driving chip and the second source a driving chip is connected through the connecting line on the first connecting portion and the second connecting portion;
  • the first connecting portion is disposed on a side of the first fan-out area adjacent to the second fan-out area, and the plurality of the first fan-out wires are arranged corresponding to the set position of the first connecting portion. cloth;
  • the second connecting portion is disposed on a side of the second fan-out area adjacent to the first fan-out area, and the plurality of second fan-out wires are arranged corresponding to the set position of the second connecting portion cloth.
  • the second connecting portion is a way of setting the two connection parts between the two source driving chips in the fan-out area.
  • the first connecting portion is disposed on a side of the first fan-out area adjacent to the second fan-out area, and the second connecting portion is disposed at a side of the second fan-out area adjacent to the first fan-out area, such that the setting can effectively reduce the connection The layout of the line and the cost savings.
  • the driving chip includes a first source driving chip and a second source driving chip.
  • the fan-out area includes a first fan-out area and a second fan-out area, the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip, and the second fan The output area includes a plurality of second fan-out wires connected to the second source driving chip;
  • the connecting portion includes a first connecting portion formed in the first fan-out area, a second connecting portion formed in the second fan-out area, the first source driving chip and the second source a driving chip is connected through the connecting line on the first connecting portion and the second connecting portion;
  • the first connecting portion is disposed at an intermediate position of the first fan-out area, and the plurality of the first fan-out wires are arranged corresponding to the set position of the first connecting portion end;
  • the second connecting portion is disposed at an intermediate position of the second fan-out area, and the plurality of the second fan-out wires are arranged corresponding to the set position of the second connecting portion.
  • the first connecting portion is disposed at an intermediate position of the first fan-out area, and the second connecting portion is disposed at an intermediate position of the second fan-out area, so that the difference between the maximum and minimum impedance of the fan-out wire in the fan-out area can be as much as possible Get reduced while balancing overall.
  • the driving chip includes a source driving chip and a gate driving chip, and the source driving chip and the gate driving chip are connected by the connecting line on the connecting portion;
  • the fan-out wire is connected to the source driving chip
  • the connecting portion is disposed on a side of the fan-out area adjacent to the gate driving chip, and the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • the connecting portion is disposed on a side close to the gate driving chip in the fan-out area, so that the setting can effectively reduce the laying work of the connecting line and save cost.
  • the driving chip includes a source driving chip and a gate driving chip, and the source driving core a chip and the gate driving chip are connected by the connecting line on the connecting portion;
  • the fan-out wire is connected to the source driving chip
  • the connecting portion is disposed at an intermediate position of the fan-out area, and the plurality of fan-out wires are arranged corresponding to the set position of the first end.
  • the connecting portion is disposed at the middle of the fan-out area, so that the maximum and minimum difference of the impedance of the fan-out wire in the fan-out area can be reduced as much as possible while being balanced as a whole.
  • the driving chip includes a first source driving chip, a second source driving chip, a first gate driving chip, a second gate driving chip, the first source driving chip, and the second source
  • the driving chip is disposed adjacent to the same side of the display area as a first side, and the first gate driving chip and the second gate driving chip are respectively disposed on two sides of the first side;
  • the fan-out area includes a first fan-out area and a second fan-out area, the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip, and the second fan The output area includes a plurality of second fan-out wires connected to the second source driving chip;
  • the connecting portion includes a first connecting portion, a second connecting portion, and a third connecting portion and a fourth connecting portion formed in the second fan-out area, the first The source driving chip and the second source driving chip are connected by the connecting line on the first connecting portion and the third connecting portion, the first source driving chip and the first gate a driving chip is connected through the connecting line on the second connecting portion, and the second source driving chip and the second gate driving chip are connected by the connecting line on the fourth connecting portion;
  • the first connecting portion and the third connecting portion are disposed at an intermediate position of the first fan-out area, and the plurality of first fan-out wires are corresponding to the first connecting portion and the third connecting portion Arrangement of the set position;
  • the second connecting portion and the fourth connecting portion are disposed at an intermediate position of the second fan-out area, and the plurality of the second fan-out wires are corresponding to the second connecting portion and the fourth connecting portion Row of set positions cloth.
  • a specific case is provided in which the connection between the two source driving chips is disposed in the middle of the fan-out area and the connection between the source and the gate driving chip is disposed in the middle of the fan-out area.
  • the driving chip includes a source driving chip, a first gate driving chip, and a second gate driving chip, wherein the first gate driving chip and the second gate driving chip are respectively disposed at the source Both sides of the pole drive chip;
  • the fan-out wire is connected to the source driving chip
  • the connecting portion includes a first connecting portion and a second connecting portion formed in the fan-out area, and the source driving chip and the first gate driving chip pass the connection on the first connecting portion a line connection, wherein the source driving chip and the second gate driving chip are connected by the connecting line on the second connecting portion;
  • the first connecting portion and the second connecting portion are disposed at an intermediate position of the fan-out area, and the plurality of fan-out wires are disposed corresponding to the positions of the first connecting portion and the second connecting portion. Arrange.
  • the specific situation is that the source and the connection between the two gate drive chips are disposed in the middle of the fan-out area.
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the connection portion is provided with a conversion portion.
  • Another object of the present application is to provide a display device.
  • a display device includes a control component, and a display panel as described herein.
  • Another object of the present application is to provide a display panel.
  • the display panel includes:
  • the substrate is provided with a display area, a fan-out area and a plurality of driving chips;
  • a plurality of fan-out wires are formed in the fan-out area, one end of the fan-out wire is connected to the signal line, and the other end of the fan-out wire is connected to the driving chip;
  • the driving chip includes a first source driving chip and a second source driving chip
  • the fan-out area includes a first fan-out area and a second fan-out area
  • the first fan-out area includes the a plurality of first fan-out wires connected to the first source driving chip
  • the second fan-out region includes a plurality of second fan-out wires connected to the second source driving chip
  • the connecting portion includes a first connecting portion of the first fan-out area, a second connecting portion formed in the second fan-out area, the first source driving chip and the second source driving chip passing the first
  • the connecting portion and the connecting line on the second connecting portion are connected, and the first connecting portion is disposed on a side of the first fan-out area adjacent to the second fan-out area, and the plurality of the first a fan-out wire is arranged corresponding to the installation position of the first connecting portion, and the second connecting portion is disposed on a side of the second fan-out area adjacent to the first fan-out area, and the plurality of The second fan-out wire
  • the driving chip includes a first source driving chip, a second source driving chip, a first gate driving chip, a second gate driving chip, the first source driving chip, and the second source
  • the driving chip is disposed adjacent to the same side of the display area as a first side, and the first gate driving chip and the second gate driving chip are respectively disposed on two sides of the first side
  • the fan The exit area includes a first fan-out area and a second fan-out area
  • the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip
  • the second fan-out area includes a plurality of second fan-out wires connected to the second source driving chip
  • the connecting portion includes a first connecting portion, a second connecting portion formed in the first fan-out region, and formed on the first a third connection portion and a fourth connection portion of the two fan-out regions, wherein the first source driving chip and the second source driving chip pass through the first connection portion and the third connection portion a connection line connecting, the first source driving chip and the first gate
  • the driving chip includes a source driving chip, a first gate driving chip, and a second gate driving chip, and the first gate driving chip and the second gate driving chip are respectively disposed at the source
  • the fan-out wires are connected to the source driving chip on both sides of the pole driving chip
  • the connecting portion includes a first connecting portion and a second connecting portion formed in the fan-out area
  • the source driving chip and The first gate driving chip is connected by the connection line on the first connection portion
  • the source driving chip and the second gate driving chip pass the connection on the second connection portion a first connection portion and the second connection portion are disposed at an intermediate position of the fan-out area, and the plurality of fan-out wires are corresponding to the first connection portion and the second connection portion Set the layout of the location.
  • the connecting portion for communicating the driving chip is disposed in the fan-out area, the fan-out lines in the fan-out area are arranged correspondingly in a limited space, and the space layout is rationally optimized, and the fan-out wires are reduced.
  • FIG. 1 is a structural diagram showing a connection between a source driving chip connection portion of a display panel in a fan-out area according to an embodiment of the present application
  • FIG. 2 is a structural diagram of a connection between two source driving chips of a display panel in a fan-out area according to an embodiment of the present application
  • FIG. 3 is a structural diagram showing a connection between a source and a gate driving chip connection portion of a display panel in a fan-out area according to an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a connection between two source driving chips of a display panel according to an embodiment of the present application in a fan-out area And a structure diagram of the connection between the source and the gate driving chip in the fan-out area;
  • FIG. 5 is a structural diagram showing a source of a display panel and a connection portion between two gate driving chips in a fan-out area according to an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a display device according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected or coupled; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • Connected, or integrally connected may be mechanically connected or coupled; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the display panel includes: a substrate, the substrate is provided with a display area, a fan-out area, and a plurality of driving chips; and a plurality of signal lines are formed in the a display area; a plurality of pixel regions formed in the display area and coupled to the signal line; a plurality of fan-out wires formed in the fan-out area, and one end of the fan-out wire is connected to the signal line The other end of the fan-out wire is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line Wherein the plurality of fan-out wires are arranged corresponding to the set position of the connecting portion.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the display panel includes: a substrate, the substrate is provided with a display area, a fan-out area, and a plurality of driving chips; and a plurality of signal lines are formed on the display a plurality of pixel regions are formed in the display region and coupled to the signal line; a plurality of fan-out wires are formed in the fan-out region, and one end of the fan-out wire is connected to the signal line.
  • the other end of the fan-out wire is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line; Wherein, the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a first source driving chip and a second source driving chip.
  • the fan-out area includes a first fan-out area and a second fan-out area, the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip, and the second fan
  • the exit region includes a plurality of second fan-out wires connected to the second source driving chip;
  • the connecting portion includes a first connecting portion formed in the first fan-out region, and is formed in the second fan-out a second connection portion of the region, the first source driver chip and the second source driver chip are connected by the connection line on the first connection portion and the second connection portion;
  • a connecting portion is disposed on a side of the first fan-out area adjacent to the second fan-out area, and a plurality of the first fan-out wires are arranged corresponding to a set position of the first connecting portion;
  • the second connecting portion is disposed on a side of the second fan-out area adjacent to the first fan-out area, and the plurality of the second fan-out wires are arranged corresponding to the set position of the second
  • the first connecting portion is disposed on a side of the first fan-out area adjacent to the second fan-out area, and the second connecting portion is disposed at a side of the second fan-out area adjacent to the first fan-out area, such that the setting can effectively reduce the connection
  • the layout of the line and the cost savings As shown in FIG.
  • the two source driving chips 10 adopt a flip chip
  • the two gate driving chips 20 adopt a flip chip
  • the source driving chip 10 passes through a plurality of fan-out wires 31 in the corresponding fan-out area 30 and The display areas are connected, and the two source driving chips 10 are connected by a connecting line 40.
  • the connecting line 40 can adopt a WOA trace (wire on array trace, array substrate trace), and the connection portion 42 is disposed in the fan-out area 30.
  • the fan-out area corresponding to the opposite driving chip is disposed, and the connecting portion 42 is provided with a transfer 41.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • COF Chip On Flex, or Chip On Film
  • a soft add-on board that uses a soft add-on board as a packaged chip carrier to bond the chip to a flexible substrate circuit, or a single-chip unpackaged chip. It has the advantages of high density, small volume and free packaging.
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the display panel includes: a substrate, The substrate is provided with a display area, a fan-out area and a plurality of driving chips; a plurality of signal lines are formed in the display area; a plurality of pixel areas are formed in the display area and coupled to the signal lines; a fan-out wire is formed in the fan-out area, one end of the fan-out wire is connected to the signal line, and the other end of the fan-out wire is connected to the driving chip; a connecting portion is formed and the fan-out is formed a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line; wherein the plurality of fan-out wires are arranged corresponding to the set positions of the connecting portions.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a first source driving chip and a second source driving chip
  • the fan-out area includes a first fan-out area and a second fan-out area
  • the first fan-out area includes the a plurality of first fan-out wires connected to the first source driving chip
  • the second fan-out region includes a plurality of second fan-out wires connected to the second source driving chip
  • the connecting portion includes a first connecting portion of the first fan-out area, a second connecting portion formed in the second fan-out area, the first source driving chip and the second source driving chip passing the first The connecting portion and the connecting line on the second connecting portion are connected
  • the first connecting portion is disposed at an intermediate position of the first fan-out area, and the plurality of the first fan-out wires are corresponding to the first An arrangement of the position of the connecting end
  • the second connecting portion is disposed at an intermediate position of the second fan-out area, and the plurality of the second fan-out wires are disposed corresponding to the position of the second connecting portion Arrange.
  • the first connecting portion is disposed at an intermediate position of the first fan-out area
  • the second connecting portion is disposed at an intermediate position of the second fan-out area, so that the difference between the maximum and minimum impedance of the fan-out wire in the fan-out area can be as much as possible Get reduced while balancing overall.
  • the two source driving chips 10 adopt a flip chip
  • the two gate driving chips 20 adopt a flip chip
  • the source driving chip 10 passes through a plurality of fan-out wires 31 in the corresponding fan-out area 30.
  • the display areas are connected, and the two source driving chips 10 are connected by a connecting line 40.
  • the connecting line 40 can adopt a WOA trace (wire on array trace, array substrate trace), and the connection portion 42 is disposed in the fan-out area 30. Intermediate position setting, said connection A transfer portion 41 is provided on the joint portion 42.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • COF Chip On Flex, or Chip On Film
  • a soft add-on board that uses a soft add-on board as a packaged chip carrier to bond the chip to a flexible substrate circuit, or a single-chip unpackaged chip. It has the advantages of high density, small volume and free packaging.
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the display panel includes: a substrate provided with a display area, a fan-out area, and a plurality of driving chips; a plurality of signal lines formed on the display area; and a plurality of pixel areas Formed in the display area, coupled to the signal line; a plurality of fan-out wires are formed in the fan-out area, one end of the fan-out wire is connected to the signal line, and the fan-out wire is The other end is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line; wherein, the plurality of The fan-out wire is arranged to correspond to the set position of the connecting portion.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a source driving chip and a gate driving chip, and the source driving chip and the gate driving chip are connected by the connecting line on the connecting portion; the fan-out wire and the The source driving chip is connected; the connecting portion is disposed on a side of the fan-out area adjacent to the gate driving chip, and the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • the connecting portion is disposed on a side close to the gate driving chip in the fan-out area, so that the setting can effectively reduce the laying work of the connecting line and save cost.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • COF Chip On Flex, or Chip On Film
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the display panel includes: a substrate provided with a display area, a fan-out area, and a plurality of driving chips; and a plurality of signal lines formed on the display a plurality of pixel regions are formed in the display region and coupled to the signal line; a plurality of fan-out wires are formed in the fan-out region, and one end of the fan-out wire is connected to the signal line.
  • the other end of the fan-out wire is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line;
  • the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a source driving chip and a gate driving chip, and the source driving chip and the gate driving chip are connected by the connecting line on the connecting portion; the fan-out wire and the The source driving chip is connected; the connecting portion is disposed at an intermediate position of the fan-out area, and the plurality of fan-out wires are arranged corresponding to the set position of the first end.
  • the connecting portion is disposed at the middle of the fan-out area, so that the maximum and minimum difference of the impedance of the fan-out wire in the fan-out area can be reduced as much as possible while being balanced as a whole.
  • the two source driving chips 10 adopt a flip chip
  • the two gate driving chips 20 adopt a flip chip
  • the source driving chip 10 passes through a plurality of fan-out wires 31 in the corresponding fan-out area 30.
  • the display areas are connected, and the two source driving chips 10 are respectively connected to the corresponding gate driving chips 20 through the connecting lines 40.
  • the connecting lines 40 can adopt CF_com traces (color film substrate common electrode traces), and the connecting portion 42 is disposed on the fan.
  • An intermediate position in the exit area 30 is provided, and a transfer portion 41 is provided on the connecting portion 42.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • a chip-on-chip is a soft add-on board that uses a soft add-on board as a packaged chip carrier to bond the chip to a flexible substrate circuit, or a single-finger chip. It has the advantages of high density, small volume and free packaging.
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the display panel includes: a substrate, the substrate is provided with a display area, a fan-out area, and a plurality of driving chips; and a plurality of signal lines are formed on the display a plurality of pixel regions are formed in the display region and coupled to the signal line; a plurality of fan-out wires are formed in the fan-out region, and one end of the fan-out wire is connected to the signal line.
  • the other end of the fan-out wire is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line; Wherein, the plurality of fan-out wires are arranged corresponding to the installation position of the connecting portion.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a first source driving chip, a second source driving chip, a first gate driving chip, a second gate driving chip, the first source driving chip, and the second source
  • the driving chip is disposed adjacent to the same side of the display area as a first side, and the first gate driving chip and the second gate driving chip are respectively disposed on two sides of the first side
  • the fan The exit area includes a first fan-out area and a second fan-out area, the first fan-out area includes a plurality of first fan-out wires connected to the first source driving chip, and the second fan-out area includes a plurality of second fan-out wires connected to the second source driving chip
  • the connecting portion includes a first connecting portion, a second connecting portion formed in the first fan-out region, and formed on the first a third connection portion and a fourth connection portion of the two fan-out regions, wherein the first source driving chip and the second source driving chip pass through the first connection portion and the third connection portion a connection line connecting, the first source driving chip and the first gate driving
  • connection between the two source driving chips is disposed in the middle of the fan-out area and the connection between the source and the gate driving chip is disposed in the middle of the fan-out area.
  • the two source driving chips 10 adopt a flip chip
  • the two gate driving chips 20 adopt a flip chip
  • the source driving chip 10 passes through a plurality of fan-out wires 31 in the corresponding fan-out area 30.
  • the display areas are connected, and the two source driving chips 10 are respectively connected to the corresponding gate driving chips 20 through the connecting lines 40.
  • the connecting lines 40 can adopt CF_com traces (color film substrate common electrode traces), and two source driving chips. 10 is connected by a connection line 40.
  • connection line 40 can adopt a WOA trace (wire on array trace, array substrate trace), a connection between the source and gate drive chips 42 and a connection between the two source drive chips.
  • the portions 42 are collectively disposed at an intermediate position in the fan-out area 30, and a transfer portion 41 is provided on both of the connecting portions 42.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • COF Chip On Flex, or Chip On Film
  • a soft add-on board that uses a soft add-on board as a packaged chip carrier to bond the chip to a flexible substrate circuit, or a single-chip unpackaged chip. It has the advantages of high density, small volume and free packaging.
  • connection line includes an array substrate trace and a color film substrate common electrode trace, and the connection portion is provided with a conversion portion.
  • the display panel includes: a substrate provided with a display area, a fan-out area, and a plurality of driving chips; and a plurality of signal lines formed on the display a plurality of pixel regions are formed in the display region and coupled to the signal line; a plurality of fan-out wires are formed in the fan-out region, and one end of the fan-out wire is connected to the signal line.
  • the other end of the fan-out wire is connected to the driving chip; the connecting portion is formed in the fan-out area; a plurality of connecting lines are formed in the connecting portion, and the driving chips are connected by the connecting line; Among them, a plurality of said fans
  • the lead wires are arranged to correspond to the set positions of the connecting portions.
  • a connecting portion for communicating the driving chip is disposed in the fan-out area, so that fan-out lines in the fan-out area are arranged correspondingly in a limited space, reasonably optimizing the space layout, and reducing the resistance between the fan-out wires. Differences, improve or even eliminate color cast and improve display quality.
  • the driving chip includes a source driving chip, a first gate driving chip, and a second gate driving chip, wherein the first gate driving chip and the second gate driving chip are respectively disposed at the source Driving the two sides of the chip; the fan-out wire is connected to the source driving chip;
  • the connecting portion includes a first connecting portion and a second connecting portion formed in the fan-out area, and the source driving chip and the first gate driving chip pass the connection on the first connecting portion a line connection, the source driving chip and the second gate driving chip being connected by the connecting line on the second connecting portion; the first connecting portion and the second connecting portion are disposed in the In the middle position of the fan-out area, a plurality of the fan-out wires are arranged corresponding to the installation positions of the first connecting portion and the second connecting portion.
  • one source driving chip 10 adopts a flip chip
  • two gate driving chips 20 adopt a flip chip
  • the source driving chip 10 passes through a plurality of fan-out wires 31 and display in the corresponding fan-out area 30.
  • the source driving chip 10 is connected to the upper assembled printed circuit board (PCBA) 50 at the same time.
  • One source driving chip 10 and the two side gate driving chips 20 are respectively connected by a connecting line 40, and the connecting line 40 can be used.
  • CF_com trace color film substrate common electrode trace
  • the signal is transmitted to the plane through the fan-out wire 31
  • the CF_COM trace is the trace connecting the source driver chip 10 and the gate driver chip 20,
  • CF_com trace The function is to transmit the signal of CF_com from the side of the source driving chip 10 to the side of the gate driving chip 20, and the connecting portions 42 between the two sources and the gate driving chip are disposed in the middle position in the fan-out area 30, A transfer portion 41 is provided on each of the connecting portions 42.
  • the driving chip uses the flip chip.
  • COF Chip On Flex, or Chip On Film
  • COF Chip On Flex, or Chip On Film
  • a soft add-on board that uses a soft add-on board as a packaged chip carrier to bond the chip to a flexible substrate circuit, or a single-chip unpackaged chip. It has the advantages of high density, small volume and free packaging.
  • the connecting line includes an array substrate trace and a color film substrate common electrode trace, and the connection A conversion portion is provided on the joint.
  • the display panel includes a liquid crystal panel, an OLED (Organic Light-Emitting Diode) panel, a QLED (Quantum Dot Light Emitting Diodes) panel, a plasma panel, a flat panel, a curved panel, and the like.
  • OLED Organic Light-Emitting Diode
  • QLED Quadantum Dot Light Emitting Diodes
  • the present embodiment discloses a display device 100.
  • the display device 100 includes the control unit 200, and the display panel 300 of the present application.
  • the display panel is taken as an example for detailed description. It should be noted that the above description of the structure of the display panel is also applicable to the display of the embodiment of the present application.
  • the display device of the embodiment of the present application is a liquid crystal display
  • the liquid crystal display includes a backlight module, and the backlight module can be used as a light source for supplying sufficient light source with uniform brightness and distribution.
  • the backlight module of the embodiment can be For the front light type, it may also be a backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（300）和显示装置（100），显示面板（300）包括：基板，基板设置有显示区域、扇出区（30）和多个驱动芯片（10，20）；多条信号线，形成于显示区域；多个像素区，形成于显示区域，与信号线耦接；多条扇出导线（31），形成于扇出区（30），扇出导线（31）的一端与信号线连接，扇出导线（31）的另一端与驱动芯片（10，20）连接；连接部（42），形成于扇出区（30）内；多条连接线（40），形成于连接部（42）内，驱动芯片（10，20）之间通过连接线（40）连接；其中，多条扇出导线（31）作对应连接部（42）的设置位置的排布。

Description

一种显示面板和显示装置 【技术领域】
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
【背景技术】
现有的显示器一般都基于主动开关进行控制，具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，主要包括液晶显示器、OLED(Organic Light-Emitting Diode)显示器、QLED(Quantum Dot Light Emitting Diodes)显示器、等离子显示器等、从外观结构来看，既有平面型显示器、也有曲面型显示器。
对于液晶显示器，包括液晶面板及背光模组(Backlight Module)两大部分，液晶显示器的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
对于OLED显示器，采用机发光二极管自发光来进行显示，具有自发光、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点。
QLED显示器结构与OLED技术非常相似，主要区别在于QLED的发光中心由量子点(Quantum dots)物质构成。其结构是两侧电子(Electron)和空穴(Hole)在量子点层中汇聚后形成光子(Exciton)，并且通过光子的重组发光。
然而，Fan-out(扇出区)每条线的阻值因为空间等原因不一定阻值相等，有时最大和最小差异太大，导致画面显示不够流畅，尤其在混色画面下，每个驱动芯片最外侧的扇出导线阻值太大，RC delay严重，后一像素的充电率大于前一像素的充电率，在驱动芯片两侧会出现色偏现象，影响显示品味，降低用户的视觉体验。
【发明内容】
本申请的一个目的在于提供一种改善显示质量的显示面板。
为解决上述问题，本申请提供一种显示面板包括：
基板，所述基板设置有显示区域、扇出区和多个驱动芯片；
多条信号线，形成于所述显示区域；
多个像素区，形成于所述显示区域，与所述信号线耦接；
多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；
连接部，形成与所述扇出区内；
多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；
其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布；
所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。这里是两源极驱动芯片间两连接部在扇出区内的一种设置方式。在空间高度不够的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。第一连接部设置在第一扇出区内靠近第二扇出区的一侧，第二连接部设置在第二扇出区内靠近第一扇出区的一侧，这样设置可有效减少连接线的布设工作量、节省成本。
其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
所述第一连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部端的设置位置的排布；
所述第二连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。这里是两源极驱动芯片间两连接部在扇出区内的一种设置方式。在空间高度不够的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。第一连接部设置在第一扇出区的中间位置，第二连接部设置在第二扇出区的中间位置，这样设置扇出区内扇出导线的阻抗最大和最小的差异能尽可能的得到减小，同时整体平衡。
其中，所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
所述扇出导线与所述源极驱动芯片连接；
所述连接部设置在所述扇出区内靠近所述栅极驱动芯片的一侧，多条所述扇出导线作对应所述连接部的设置位置的排布。这里是源极、栅极驱动芯片间连接部在扇出区内的一种设置方式。在空间和驱动芯片数量一定的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。连接部设置在扇出区内靠近栅极驱动芯片的一侧，这样设置可有效减少连接线的布设工作量、节省成本。
其中，所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯 片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
所述扇出导线与所述源极驱动芯片连接；
所述连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一端的设置位置的排布。这里是源极、栅极驱动芯片间连接部在扇出区内的一种设置方式。在空间和驱动芯片数量一定的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。连接部设置在扇出区的中间位置，这样设置扇出区内扇出导线的阻抗最大和最小的差异能尽可能的得到减小，同时整体平衡。
其中，所述驱动芯片包括第一源极驱动芯片、第二源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一源极驱动芯片、所述第二源极驱动芯片相邻设置在所述显示区域的同一侧为第一边，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述第一边的两侧；
所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
所述连接部包括形成于所述第一扇出区的第一连接部、第二连接部，以及形成于所述第二扇出区的第三连接部、第四连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第三连接部上的所述连接线连接，所述第一源极驱动芯片和所述第一栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第二源极驱动芯片和所述第二栅极驱动芯片通过所述第四连接部上的所述连接线连接；
所述第一连接部和所述第三连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部、所述第三连接部的设置位置的排布；
所述第二连接部和所述第四连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部、所述第四连接部的设置位置的排 布。这里是两源极驱动芯片间连接部在扇出区中间设置以及源极、栅极驱动芯片间连接部在扇出区中间设置的具体情形。
其中，所述驱动芯片包括一个源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述源极驱动芯片的两侧；
所述扇出导线与所述源极驱动芯片连接；
所述连接部包括形成于所述扇出区的第一连接部、第二连接部，所述源极驱动芯片和所述第一栅极驱动芯片通过所述第一连接部上的所述连接线连接，所述源极驱动芯片和所述第二栅极驱动芯片通过所述第二连接部上的所述连接线连接；
所述第一连接部和所述第二连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一连接部、所述第二连接部的设置位置的排布。这里是源极分别与两栅极驱动芯片间连接部在扇出区中间设置的具体情形。
其中，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。这里是连接部的具体设置。
本申请的另一个目的在于提供一种显示装置。
一种显示装置，包括控制部件，以及本申请所述的显示面板。
本申请的另一个目的在于提供一种显示面板。
所述显示面板包括：
基板，所述基板设置有显示区域、扇出区和多个驱动芯片；
多条信号线，形成于所述显示区域；
多个像素区，形成于所述显示区域，与所述信号线耦接；
多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；
连接部，形成与所述扇出区内；
多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；
其中，多条所述扇出导线作对应所述连接部的设置位置的排布；
其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线，所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接，所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布，所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布；
或者，所述驱动芯片包括第一源极驱动芯片、第二源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一源极驱动芯片、所述第二源极驱动芯片相邻设置在所述显示区域的同一侧为第一边，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述第一边的两侧，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线，所述连接部包括形成于所述第一扇出区的第一连接部、第二连接部，以及形成于所述第二扇出区的第三连接部、第四连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第三连接部上的所述连接线连接，所述第一源极驱动芯片和所述第一栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第二源极驱动芯片和所述第二栅极驱动芯片通过所述第四连接部上的所述连接线连接，所述第一连接部和所述第三连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部、所述第三连接部的设置位置的排布，所述第二连接部和所述第四连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部、 所述第四连接部的设置位置的排布；
或者，所述驱动芯片包括一个源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述源极驱动芯片的两侧，述扇出导线与所述源极驱动芯片连接，所述连接部包括形成于所述扇出区的第一连接部、第二连接部，所述源极驱动芯片和所述第一栅极驱动芯片通过所述第一连接部上的所述连接线连接，所述源极驱动芯片和所述第二栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第一连接部和所述第二连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一连接部、所述第二连接部的设置位置的排布。
本申请由于用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一个实施例显示面板的源极驱动芯片间连接部在扇出区设置的结构示图；
图2是本申请一个实施例显示面板的两源极驱动芯片间连接部在扇出区设置的结构示图；
图3是本申请一个实施例显示面板的源极、栅极驱动芯片间连接部在扇出区设置的结构示图；
图4是本申请一个实施例显示面板的两源极驱动芯片间连接部在扇出区设 置以及源极、栅极驱动芯片间连接部在扇出区设置的结构示图；
图5是本申请一个实施例显示面板的源极、两栅极驱动芯片间连接部在扇出区设置的结构示图；
图6是本申请实施例显示装置的示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是耦接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项” 还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
在图中，结构相似的单元是以相同标号表示。
下面参考附图1至图6实施例进一步详细描述本申请的显示面板和显示装置。
作为本申请的一个实施例，如图1-6所示，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
作为本申请的又一个实施例，如图1所示，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布；所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。在空间高度不够的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。第一连接部设置在第一扇出区内靠近第二扇出区的一侧，第二连接部设置在第二扇出区内靠近第一扇出区的一侧，这样设置可有效减少连接线的布设工作量、节省成本。如图1所示，两个源极驱动芯片10采用覆晶薄膜，两个栅极驱动芯片20采用覆晶薄膜，源极驱动芯片10通过对应扇出区30内的多条扇出导线31与显示区域相连，两个源极驱动芯片10之间通过连接线40相连，连接线40可以采用WOA走线(wire on array走线，阵列基板走线)，连接部42设置在扇出区30内偏向相对的驱动芯片对应的扇出区设置，所述连接部42上设置有转换部(transfer)41。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
作为本申请的又一个实施例，如图2所示，所述显示面板包括：基板，所 述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；所述第一连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部端的设置位置的排布；所述第二连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。在空间高度不够的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。第一连接部设置在第一扇出区的中间位置，第二连接部设置在第二扇出区的中间位置，这样设置扇出区内扇出导线的阻抗最大和最小的差异能尽可能的得到减小，同时整体平衡。如图2所示，两个源极驱动芯片10采用覆晶薄膜，两个栅极驱动芯片20采用覆晶薄膜，源极驱动芯片10通过对应扇出区30内的多条扇出导线31与显示区域相连，两个源极驱动芯片10之间通过连接线40相连，连接线40可以采用WOA走线(wire on array走线，阵列基板走线)，连接部42设置在扇出区30内的中间位置设置，所述连 接部42上设置有转换部(transfer)41。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
作为本申请的又一个实施例，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；所述扇出导线与所述源极驱动芯片连接；所述连接部设置在所述扇出区内靠近所述栅极驱动芯片的一侧，多条所述扇出导线作对应所述连接部的设置位置的排布。在空间和驱动芯片数量一定的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。连接部设置在扇出区内靠近栅极驱动芯片的一侧，这样设置可有效减少连接线的布设工作量、节省成本。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自 由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
作为本申请的又一个实施例，如图3所示，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；所述扇出导线与所述源极驱动芯片连接；所述连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一端的设置位置的排布。在空间和驱动芯片数量一定的情况下拉出等阻抗，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。连接部设置在扇出区的中间位置，这样设置扇出区内扇出导线的阻抗最大和最小的差异能尽可能的得到减小，同时整体平衡。如图3所示，两个源极驱动芯片10采用覆晶薄膜，两个栅极驱动芯片20采用覆晶薄膜，源极驱动芯片10通过对应扇出区30内的多条扇出导线31与显示区域相连，两个源极驱动芯片10分别和对应的栅极驱动芯片20通过连接线40相连，连接线40可以采用CF_com走线(彩膜基板公共电极走线)，连接部42设置在扇出区30内的中间位置设置，所述连接部42上设置有转换部(transfer)41。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip  On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
作为本申请的又一个实施例，如图4所示，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括第一源极驱动芯片、第二源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一源极驱动芯片、所述第二源极驱动芯片相邻设置在所述显示区域的同一侧为第一边，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述第一边的两侧；所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；所述连接部包括形成于所述第一扇出区的第一连接部、第二连接部，以及形成于所述第二扇出区的第三连接部、第四连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第三连接部上的所述连接线连接，所述第一源极驱动芯片和所述第一栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第二源极驱动芯片和所述第二栅极驱动芯片通过 所述第四连接部上的所述连接线连接；所述第一连接部和所述第三连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部、所述第三连接部的设置位置的排布；所述第二连接部和所述第四连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部、所述第四连接部的设置位置的排布。这里是两源极驱动芯片间连接部在扇出区中间设置以及源极、栅极驱动芯片间连接部在扇出区中间设置的具体情形。如图4所示，两个源极驱动芯片10采用覆晶薄膜，两个栅极驱动芯片20采用覆晶薄膜，源极驱动芯片10通过对应扇出区30内的多条扇出导线31与显示区域相连，两个源极驱动芯片10分别和对应的栅极驱动芯片20通过连接线40相连，连接线40可以采用CF_com走线(彩膜基板公共电极走线)，两个源极驱动芯片10之间通过连接线40相连，连接线40可以采用WOA走线(wire on array走线，阵列基板走线)，源、栅极驱动芯片间的连接部42和两源极驱动芯片间的连接部42一并设置在扇出区30内的中间位置设置，两个连接部42上都设置有一个转换部(transfer)41。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
作为本申请的又一个实施例，如图5所示，所述显示面板包括：基板，所述基板设置有显示区域、扇出区和多个驱动芯片；多条信号线，形成于所述显示区域；多个像素区，形成于所述显示区域，与所述信号线耦接；多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；连接部，形成与所述扇出区内；多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；其中，多条所述扇 出导线作对应所述连接部的设置位置的排布。
用于沟通驱动芯片的连接部设置在所述扇出区内，使得扇出区内的扇出走线在有限的空间内作对应排布，合理优化空间布局，减小扇出导线间的阻值差异，改善甚至消除色偏，提高显示质量。
其中，所述驱动芯片包括一个源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述源极驱动芯片的两侧；所述扇出导线与所述源极驱动芯片连接；
所述连接部包括形成于所述扇出区的第一连接部、第二连接部，所述源极驱动芯片和所述第一栅极驱动芯片通过所述第一连接部上的所述连接线连接，所述源极驱动芯片和所述第二栅极驱动芯片通过所述第二连接部上的所述连接线连接；所述第一连接部和所述第二连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一连接部、所述第二连接部的设置位置的排布。如图5所示，一个源极驱动芯片10采用覆晶薄膜，两个栅极驱动芯片20采用覆晶薄膜，源极驱动芯片10通过对应扇出区30内的多条扇出导线31与显示区域相连，源极驱动芯片10同时与上方的装配印制电路板(PCBA)50连接，一个源极驱动芯片10与两侧的栅极驱动芯片20分别通过连接线40相连，连接线40可以采用CF_com走线(彩膜基板公共电极走线)，信号是通过扇出导线31传给面内的，CF_COM走线是连接源极驱动芯片10和栅极驱动芯片20的走线，CF_com走线的作用是把CF_com的信号从源极驱动芯片10侧传给栅极驱动芯片20侧，两组源、栅极驱动芯片间的连接部42一并设置在扇出区30内的中间位置设置，两个连接部42上都设置有一个转换部(transfer)41。
具体的，所述驱动芯片采用所述覆晶薄膜。COF(Chip On Flex，或者说Chip On Film，覆晶芯片)是运用软质附加电路板作封装芯片载体将芯片与软性基板电路接合，或单指未封装芯片的软质附加电路板。具有高密度、小体积，能自由封装的优点。
具体的，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连 接部上设置有一个转换部。
在上述实施例中，显示面板包括液晶面板、OLED(Organic Light-Emitting Diode)面板、QLED(Quantum Dot Light Emitting Diodes)面板、等离子面板、平面型面板、曲面型面板等。
参考图7，本实施方式公开一种显示装置100。该显示装置100包括控制部件200，以及本申请所述的显示面板300，以上以显示面板为例进行详细说明，需要说明的是，以上对显示面板结构的描述同样适用于本申请实施例的显示装置中。其中，当本申请实施例的显示装置为液晶显示器时，液晶显示器包括有背光模组，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种显示面板，包括：
    基板，所述基板设置有显示区域、扇出区和多个驱动芯片；
    多条信号线，形成于所述显示区域；
    多个像素区，形成于所述显示区域，与所述信号线耦接；
    多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；
    连接部，形成与所述扇出区内；
    多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；
    其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
  2. 如权利要求1所述的显示面板，其中所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
    所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布；
    所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。
  3. 如权利要求1所述的显示面板，其中所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第 一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
    所述第一连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部端的设置位置的排布；
    所述第二连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。
  4. 如权利要求1所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区内靠近所述栅极驱动芯片的一侧，多条所述扇出导线作对应所述连接部的设置位置的排布。
  5. 如权利要求2所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区内靠近所述栅极驱动芯片的一侧，多条所述扇出导线作对应所述连接部的设置位置的排布。
  6. 如权利要求3所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区内靠近所述栅极驱动芯片的一侧，多条所述 扇出导线作对应所述连接部的设置位置的排布。
  7. 如权利要求1所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一端的设置位置的排布。
  8. 如权利要求2所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一端的设置位置的排布。
  9. 如权利要求3所述的显示面板，其中所述驱动芯片包括源极驱动芯片和栅极驱动芯片，所述源极驱动芯片和所述栅极驱动芯片通过所述连接部上的所述连接线连接；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一端的设置位置的排布。
  10. 如权利要求1所述的显示面板，其中所述驱动芯片包括第一源极驱动芯片、第二源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一源极驱动芯片、所述第二源极驱动芯片相邻设置在所述显示区域的同一侧为第一边，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述第一边的两侧；
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源 极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、第二连接部，以及形成于所述第二扇出区的第三连接部、第四连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第三连接部上的所述连接线连接，所述第一源极驱动芯片和所述第一栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第二源极驱动芯片和所述第二栅极驱动芯片通过所述第四连接部上的所述连接线连接；
    所述第一连接部和所述第三连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部、所述第三连接部的设置位置的排布；
    所述第二连接部和所述第四连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部、所述第四连接部的设置位置的排布。
  11. 如权利要求1所述的显示面板，其中所述驱动芯片包括一个源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述源极驱动芯片的两侧；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部包括形成于所述扇出区的第一连接部、第二连接部，所述源极驱动芯片和所述第一栅极驱动芯片通过所述第一连接部上的所述连接线连接，所述源极驱动芯片和所述第二栅极驱动芯片通过所述第二连接部上的所述连接线连接；
    所述第一连接部和所述第二连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一连接部、所述第二连接部的设置位置的排布。
  12. 如权利要求1所述的显示面板，其中所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
  13. 一种显示面板，包括：
    基板，所述基板设置有显示区域、扇出区和多个驱动芯片；
    多条信号线，形成于所述显示区域；
    多个像素区，形成于所述显示区域，与所述信号线耦接；
    多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；
    连接部，形成与所述扇出区内；
    多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；
    其中，多条所述扇出导线作对应所述连接部的设置位置的排布；
    其中，所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线，所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接，所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布，所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布；
    其中，所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
  14. 一种显示装置，包括：
    控制部件，以及
    显示面板，所述显示面板包括：
    基板，所述基板设置有显示区域、扇出区和多个驱动芯片；
    多条信号线，形成于所述显示区域；
    多个像素区，形成于所述显示区域，与所述信号线耦接；
    多条扇出导线，形成于所述扇出区，所述扇出导线的一端与所述信号线连接，所述扇出导线的另一端与所述驱动芯片连接；
    连接部，形成与所述扇出区内；
    多条连接线，形成于连接部内，所述驱动芯片之间通过所述连接线连接；
    其中，多条所述扇出导线作对应所述连接部的设置位置的排布。
  15. 如权利要求14所述的显示装置，其中所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
    所述第一连接部设置在所述第一扇出区内靠近所述第二扇出区的一侧，多条所述第一扇出导线作对应所述第一连接部的设置位置的排布；
    所述第二连接部设置在所述第二扇出区内靠近所述第一扇出区的一侧，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。
  16. 如权利要求14所述的显示装置，其中所述驱动芯片包括第一源极驱动芯片和第二源极驱动芯片，
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、形成于所述第二扇出区的第二连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第二连接部上的所述连接线连接；
    所述第一连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导 线作对应所述第一连接部端的设置位置的排布；
    所述第二连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部的设置位置的排布。
  17. 如权利要求14所述的显示面板，其中所述驱动芯片包括第一源极驱动芯片、第二源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一源极驱动芯片、所述第二源极驱动芯片相邻设置在所述显示区域的同一侧为第一边，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述第一边的两侧；
    所述扇出区包括第一扇出区和第二扇出区，所述第一扇出区包括与所述第一源极驱动芯片连接的多条第一扇出导线，所述第二扇出区包括与所述第二源极驱动芯片连接的多条第二扇出导线；
    所述连接部包括形成于所述第一扇出区的第一连接部、第二连接部，以及形成于所述第二扇出区的第三连接部、第四连接部，所述第一源极驱动芯片和所述第二源极驱动芯片通过所述第一连接部、所述第三连接部上的所述连接线连接，所述第一源极驱动芯片和所述第一栅极驱动芯片通过所述第二连接部上的所述连接线连接，所述第二源极驱动芯片和所述第二栅极驱动芯片通过所述第四连接部上的所述连接线连接；
    所述第一连接部和所述第三连接部设置在所述第一扇出区的中间位置，多条所述第一扇出导线作对应所述第一连接部、所述第三连接部的设置位置的排布；
    所述第二连接部和所述第四连接部设置在所述第二扇出区的中间位置，多条所述第二扇出导线作对应所述第二连接部、所述第四连接部的设置位置的排布。
  18. 如权利要求14所述的显示面板，其中所述驱动芯片包括一个源极驱动芯片、第一栅极驱动芯片、第二栅极驱动芯片，所述第一栅极驱动芯片、所述第二栅极驱动芯片分别设置在所述源极驱动芯片的两侧；
    所述扇出导线与所述源极驱动芯片连接；
    所述连接部包括形成于所述扇出区的第一连接部、第二连接部，所述源极驱动芯片和所述第一栅极驱动芯片通过所述第一连接部上的所述连接线连接，所述源极驱动芯片和所述第二栅极驱动芯片通过所述第二连接部上的所述连接线连接；
    所述第一连接部和所述第二连接部设置在所述扇出区的中间位置，多条所述扇出导线作对应所述第一连接部、所述第二连接部的设置位置的排布。
  19. 如权利要求14所述的显示面板，其中所述连接线包括阵列基板走线和彩膜基板公共电极走线，所述连接部上设置有一个转换部。
PCT/CN2017/099602 2017-08-08 2017-08-30 一种显示面板和显示装置 Ceased WO2019028947A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/869,654 US10620498B2 (en) 2017-08-08 2018-01-12 Display panel and display device with connecting portion formed in fan-out region

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710669334.1A CN107393415B (zh) 2017-08-08 2017-08-08 一种显示面板和显示装置
CN201710669334.1 2017-08-08

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/869,654 Continuation US10620498B2 (en) 2017-08-08 2018-01-12 Display panel and display device with connecting portion formed in fan-out region

Publications (1)

Publication Number Publication Date
WO2019028947A1 true WO2019028947A1 (zh) 2019-02-14

Family

ID=60354468

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/099602 Ceased WO2019028947A1 (zh) 2017-08-08 2017-08-30 一种显示面板和显示装置

Country Status (3)

Country Link
US (1) US10620498B2 (zh)
CN (1) CN107393415B (zh)
WO (1) WO2019028947A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102489595B1 (ko) * 2017-12-15 2023-01-17 엘지디스플레이 주식회사 칩 온 필름 및 그를 포함하는 디스플레이 장치
CN107978291A (zh) * 2017-12-29 2018-05-01 深圳市华星光电技术有限公司 一种驱动信号的调整方法
CN109166515B (zh) * 2018-10-29 2019-09-17 惠科股份有限公司 显示装置及其调节方法
CN109557734A (zh) * 2018-10-31 2019-04-02 武汉华星光电技术有限公司 显示面板及显示模组
CN109377932B (zh) * 2018-12-26 2022-08-16 厦门天马微电子有限公司 显示面板及显示装置
CN110045554A (zh) * 2019-04-30 2019-07-23 深圳市华星光电技术有限公司 阵列基板及显示面板
CN111009183B (zh) * 2019-12-25 2021-11-23 Tcl华星光电技术有限公司 显示装置
CN111338136B (zh) * 2020-03-13 2023-03-28 深圳市华星光电半导体显示技术有限公司 一种阵列基板及显示装置
WO2022266830A1 (zh) * 2021-06-22 2022-12-29 京东方科技集团股份有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102236192A (zh) * 2010-04-27 2011-11-09 瀚宇彩晶股份有限公司 具有触控功能的液晶显示面板
CN103558703A (zh) * 2013-10-12 2014-02-05 深圳市华星光电技术有限公司 超窄边框液晶显示器及其驱动电路的cof封装结构
CN104977737A (zh) * 2014-04-09 2015-10-14 群创光电股份有限公司 扇出导线结构及其显示面板
US20160035307A1 (en) * 2014-07-30 2016-02-04 Samsung Display Co., Ltd. Display panel and display device having the same
CN106681067A (zh) * 2016-12-20 2017-05-17 深圳市华星光电技术有限公司 显示装置
CN106816142A (zh) * 2015-12-01 2017-06-09 瑞鼎科技股份有限公司 用于显示装置的具有扇出线路补偿设计的源极驱动器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098901B2 (en) * 2000-07-24 2006-08-29 Sharp Kabushiki Kaisha Display device and driver
KR100831235B1 (ko) * 2002-06-07 2008-05-22 삼성전자주식회사 박막 트랜지스터 기판
KR20070002278A (ko) * 2005-06-30 2007-01-05 삼성전자주식회사 표시 기판 및 이를 구비한 표시 장치
CN100552516C (zh) * 2006-03-23 2009-10-21 友达光电股份有限公司 具有均匀阻抗值的扇出区块的电子装置
KR20080017773A (ko) * 2006-08-22 2008-02-27 삼성전자주식회사 디스플레이장치 및 연성부재
CN101359106A (zh) * 2008-09-12 2009-02-04 友达光电股份有限公司 显示面板及其应用
TWI518428B (zh) * 2011-05-02 2016-01-21 元太科技工業股份有限公司 顯示裝置以及顯示陣列基板
CN105372858B (zh) * 2015-12-16 2018-09-04 深圳市华星光电技术有限公司 扇出线结构及包含其的阵列基板
JP2018136495A (ja) * 2017-02-23 2018-08-30 株式会社ジャパンディスプレイ 表示ドライバ及び表示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102236192A (zh) * 2010-04-27 2011-11-09 瀚宇彩晶股份有限公司 具有触控功能的液晶显示面板
CN103558703A (zh) * 2013-10-12 2014-02-05 深圳市华星光电技术有限公司 超窄边框液晶显示器及其驱动电路的cof封装结构
CN104977737A (zh) * 2014-04-09 2015-10-14 群创光电股份有限公司 扇出导线结构及其显示面板
US20160035307A1 (en) * 2014-07-30 2016-02-04 Samsung Display Co., Ltd. Display panel and display device having the same
CN106816142A (zh) * 2015-12-01 2017-06-09 瑞鼎科技股份有限公司 用于显示装置的具有扇出线路补偿设计的源极驱动器
CN106681067A (zh) * 2016-12-20 2017-05-17 深圳市华星光电技术有限公司 显示装置

Also Published As

Publication number Publication date
CN107393415A (zh) 2017-11-24
CN107393415B (zh) 2020-03-31
US20190049805A1 (en) 2019-02-14
US10620498B2 (en) 2020-04-14

Similar Documents

Publication Publication Date Title
WO2019028947A1 (zh) 一种显示面板和显示装置
KR102578845B1 (ko) 표시장치
WO2019028971A1 (zh) 显示面板和显示装置
CN110751922B (zh) 显示面板及显示装置
KR20250102115A (ko) 어레이 기판, 디스플레이 패널, 접합된 디스플레이 패널 및 디스플레이 구동 방법
WO2020228205A1 (zh) 显示面板及显示装置
WO2021012458A1 (zh) 无缝拼接屏
WO2021258489A1 (zh) 显示面板及显示装置
KR102917611B1 (ko) 디스플레이 모듈
CN109461744A (zh) 一种双面显示面板、制作方法以及显示装置
CN110061147A (zh) 显示面板及其制作方法、显示装置
TW200522769A (en) Organic electroluminescent display device and method of fabricating the same
CN206098394U (zh) 一种显示基板、显示面板及显示装置
CN111312090A (zh) 显示面板及其制作方法、显示装置
EP3807934B1 (en) Display panel and display apparatus including the same
KR20230153891A (ko) 투명 디스플레이 모듈 및 투명 디스플레이 장치
KR102276372B1 (ko) 초박막 플렉시블 투명 디스플레이 장치 및 그의 제조 방법
CN112669761B (zh) 一种显示面板及其制备方法、显示装置
KR20180121292A (ko) 발광 다이오드 디스플레이 장치
CN109671760A (zh) 一种有源矩阵有机发光二极管面板
KR102899916B1 (ko) 디스플레이 모듈 및 디스플레이 장치
WO2010150445A1 (ja) 表示装置
KR20190079487A (ko) 패널 내장형 게이트 드라이버를 포함한 표시장치
TW200306128A (en) Image display device
TWI590217B (zh) 有機發光顯示設備及其驅動方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17921148

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17921148

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205N DATED 31/03/2020)