WO2022266830A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022266830A1
WO2022266830A1 PCT/CN2021/101448 CN2021101448W WO2022266830A1 WO 2022266830 A1 WO2022266830 A1 WO 2022266830A1 CN 2021101448 W CN2021101448 W CN 2021101448W WO 2022266830 A1 WO2022266830 A1 WO 2022266830A1
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WO
WIPO (PCT)
Prior art keywords
fan
area
lead
sub
display panel
Prior art date
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PCT/CN2021/101448
Other languages
English (en)
French (fr)
Inventor
韩影
林奕呈
徐攀
王国英
张星
高展
朱明毅
Original Assignee
京东方科技集团股份有限公司
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Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/101448 priority Critical patent/WO2022266830A1/zh
Priority to CN202180001572.XA priority patent/CN115917638A/zh
Publication of WO2022266830A1 publication Critical patent/WO2022266830A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • organic light-emitting diode Organic Light-Emitting Diode, referred to as OLED
  • OLED Organic Light-Emitting Diode
  • the screen-to-body ratio of the OLED display device is increased, and a full-screen design of the display screen is realized.
  • the spliced display screen formed by splicing the full screen can reduce the width of the splicing seam and improve the integrity of the display screen of the spliced display screen.
  • a display panel in one aspect, includes a display area, a fan-out area located on one side of the display area, and a binding area located on a side of the fan-out area away from the display area.
  • the display panel includes a gate drive circuit arranged in the display area, a plurality of data lines, a plurality of data fan-out leads, a plurality of control signal lines and a plurality of first fan-out leads, wherein the plurality of data lines are connected from The display area extends to the fan-out area.
  • a plurality of data fan-out leads are arranged in the fan-out area, each data line is electrically connected to a data fan-out lead, and the plurality of data fan-out leads are collected into the first sub-bonding area.
  • a plurality of control signal lines are electrically connected to the gate drive circuit, the plurality of control signal lines are configured to transmit control signals to the gate drive circuit, and the plurality of control signal lines extend from the display area to the fan-out area.
  • a plurality of first fan-out leads are arranged in the fan-out area, each control signal line is electrically connected to a first fan-out lead, and the plurality of first fan-out leads are collected in the bonding area.
  • the first fan-out lead is electrically connected to one end of the control signal line extending to the fan-out area.
  • the display panel further includes a power supply voltage bus, which is disposed in the fan-out region and extends along the first direction.
  • the first fan-out lead is made of the same material as the power supply voltage bus and arranged on the same layer, and the first fan-out lead is wound from one of the two opposite sides of the power supply voltage bus along the first direction. row, and extend to the side of the power supply voltage bus away from the display area.
  • the display panel further includes a plurality of first connection lines disposed between the power supply voltage bus and the display area and extending along the first direction.
  • the control signal lines are electrically connected to corresponding first fan-out leads through first connection lines.
  • the display panel includes a first gate conductive layer and a source-drain conductive layer, and the plurality of first fan-out leads, the plurality of first connection lines and the power supply voltage bus are arranged on the The first gate conductive layer.
  • the source-drain conductive layer is arranged on the side of the first gate conductive layer away from the substrate of the display panel, and the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads are arranged on The source-drain conductive layer.
  • the display panel further includes a first insulating layer disposed between the first gate conductive layer and the source-drain conductive layer.
  • a first via hole is provided in the first insulating layer, and the first connection line is electrically connected to a corresponding control signal line through the first via hole.
  • the orthographic projections of the plurality of first fan-out leads on the substrate are staggered from the orthographic projections of the plurality of data fan-out leads on the substrate.
  • the display panel further includes a power supply voltage bus, which is disposed in the fan-out region and extends along the first direction. Wherein, at least part of the first fan-out lead is arranged in a different layer from the power supply voltage bus and the data fan-out lead.
  • the orthographic projection of the first fan-out lead on the substrate of the display panel partially overlaps the orthographic projection of the power supply voltage bus on the substrate, and overlaps with at least one data fan-out lead on the substrate. The orthographic projections on the bottom part overlap.
  • the first fan-out lead includes a first lead segment and a second lead segment electrically connected, and an end of the first lead segment away from the second lead segment is electrically connected to the control signal line , the end of the second lead segment away from the first lead segment extends to the binding area.
  • At least one first lead segment includes a first sub-lead segment and a second sub-lead segment electrically connected, the first sub-lead segment extends along the first direction, and the second sub-lead segment extending in the second direction.
  • the second direction is substantially perpendicular to the first direction.
  • the display panel includes a first gate conductive layer, a source-drain conductive layer and a first electrode layer, and the power supply voltage bus is disposed on the first gate conductive layer.
  • the source-drain conductive layer is disposed on the side of the first gate conductive layer away from the substrate, and the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads are disposed on the source drain conductive layer.
  • the first electrode layer is disposed on a side of the source-drain conductive layer away from the substrate. Wherein, the first lead segment is disposed on the first electrode layer, and the second lead segment is disposed on the source-drain conductive layer or the first gate conductive layer.
  • the orthographic projection of the first lead segment on the substrate partially overlaps the orthographic projection of the power supply voltage bus on the substrate, and overlaps with the orthographic projection of at least one data fan-out lead on the substrate.
  • the projections partially overlap.
  • the orthographic projection of the second lead segment on the substrate is staggered from the orthographic projection of the plurality of data fan-out leads on the substrate.
  • the display panel further includes a second insulating layer, the second insulating layer is disposed between the source-drain conductive layer and the first electrode layer, and the second insulating layer is disposed with a second vias and tertiary vias. Wherein, one end of the first lead segment away from the second lead segment is electrically connected to the corresponding control signal line through the second via hole.
  • the display panel further includes a first insulating layer disposed between the first gate conductive layer and the source-drain conductive layer, the first insulating layer is provided with a first via hole, and the first The via hole communicates with the third via hole, the first lead segment is close to one end of the second lead segment, and is electrically connected to the second lead segment through the third via hole and the first via hole. connect.
  • the display panel further includes a peripheral area surrounding the display area, and the peripheral area includes a first sub-peripheral area, a second sub-peripheral area, a third sub-peripheral area and a fourth sub-peripheral area.
  • the first sub-peripheral area and the second sub-peripheral area are respectively located on opposite sides of the display area along the first direction
  • the third sub-peripheral area and the fourth sub-peripheral area are respectively located on the display area regions along opposite sides of a second direction
  • the first direction is substantially perpendicular to the second direction
  • the fan-out region and the binding region are located in the fourth sub-peripheral region.
  • the control signal line includes a first routing segment and a second routing segment electrically connected, and a part of the first routing segments among the plurality of first routing segments runs from the third sub-peripheral area to along the first sub-peripheral area, extends to the fan-out zone. Another part of the first routing segment extends from the third sub-peripheral area along the second sub-peripheral area to the fan-out area. A plurality of second routing segments extend from the display area to the third sub-peripheral area.
  • One end of the first routing segment is electrically connected to one end of the second routing segment extending to the third sub-peripheral region, and the other end of the first routing segment is electrically connected to a corresponding first fan-out lead.
  • the plurality of first fan-out leads, the plurality of control signal lines and the plurality of data fan-out leads are made of the same material and arranged in the same layer.
  • the plurality of first fan-out leads are disposed on opposite sides of the plurality of data fan-out leads along the first direction.
  • the display panel further includes a power supply voltage bus, which is disposed in the fan-out region and extends along the first direction.
  • the first fan-out lead is arranged in a different layer from the power supply voltage bus, and the orthographic projection of the first fan-out lead on the substrate of the display panel is the same as that of the power supply voltage bus on the substrate.
  • the orthographic projections on are partially overlapping.
  • the display panel includes a first gate conductive layer and a source-drain conductive layer, and the power supply voltage bus is disposed on the first gate conductive layer.
  • the source-drain conductive layer is disposed on the side of the first gate conductive layer away from the substrate of the display panel, and the plurality of control signal lines, the plurality of data lines, the plurality of data fan-out leads and the plurality of The plurality of first fan-out leads are disposed on the source-drain conductive layer.
  • the display panel further includes a power supply voltage bus, which is disposed in the fan-out region and extends along the first direction.
  • the first routing segment of the control signal line and the plurality of first fan-out leads are made of the same material as the power supply voltage bus and arranged on the same layer, and the first fan-out leads are connected from the edge of the power supply voltage bus The first direction detours around one of the two opposite sides and extends to a side of the power supply voltage bus far away from the display area.
  • the display panel includes a first gate conductive layer and a source-drain conductive layer, and the first wiring segment, the plurality of first fan-out leads and the power supply voltage bus are arranged on the first gate conductive layer.
  • the source-drain conductive layer is arranged on the side of the first gate conductive layer away from the substrate of the display panel, and the second wiring segment of the control signal line, the plurality of data lines and the plurality of data fan-out Leads are arranged on the source-drain conductive layer.
  • the binding region includes a first sub-binding region, and two second sub-binding regions located on opposite sides of the first sub-binding region along the first direction, and the plurality of The data fan-out leads are collected into the first sub-binding area, the plurality of first fan-out leads are divided into two groups, and the two groups of first fan-out leads are respectively collected into two second sub-binding areas.
  • the display panel further includes a plurality of pins configured to bind the flexible printed circuit board.
  • the plurality of pins includes a plurality of first pins located in the first sub-binding area, and a plurality of second pins located in the second sub-binding area.
  • the data fan-out lead is electrically connected to at least one first pin, and the first fan-out lead is electrically connected to at least one second pin.
  • a display device in another aspect, includes: the display panel as described in any one of the above embodiments.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments of the present disclosure
  • FIG. 2 is a partially enlarged view at M of the display panel in FIG. 1;
  • Fig. 3 is a sectional view of the display panel in Fig. 2 along the section line A-A';
  • FIG. 4 is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 5 is a partially enlarged view at N of the display panel in FIG. 4;
  • FIG. 6 is a cross-sectional view of the display panel in FIG. 5 along the section line B-B';
  • FIG. 7 is another cross-sectional view of the display panel in FIG. 5 along the section line B-B';
  • FIG. 8 is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 9 is a partially enlarged view at O of the display panel in FIG. 8;
  • FIG. 10 is a cross-sectional view of the display panel in FIG. 9 along the section line C-C';
  • Fig. 11 is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 12 is a cross-sectional view of the display panel in FIG. 11 along the section line D-D';
  • FIG. 13 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expression “electrically connected” and its derivatives may be used.
  • the term “electrically connected” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the "same layer” in this article refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • heterolayer refers to the layer structure formed by using the corresponding film forming process to form the film layer for forming a specific pattern, and then using the corresponding mask plate to form the layer structure through the patterning process, for example, "two layer structure "Different layer arrangement” refers to the formation of two layer structures under corresponding process steps (film-forming process and patterning process).
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display panel adopts GOA (English full name: Gate Driver on Array, Chinese full name: array substrate line drive) driving method, that is, the gate drive circuit in the display panel is directly integrated on at least one side of the display area. surrounding area.
  • GOA English full name: Gate Driver on Array
  • the display panel further includes a plurality of signal lines disposed in the peripheral area, and the plurality of signal lines are electrically connected to the gate driving circuit for transmitting control signals to the gate driving circuit.
  • the arrangement of the gate driving circuit and multiple signal lines needs to occupy more area of the peripheral area, which makes the width of the peripheral area larger, which is not conducive to narrowing the frame of the display device using the display panel.
  • some embodiments of the present disclosure provide a display panel. As shown in FIG. A fan-out area (Fanout area) FA on the side of the area AA, and a binding area BA located on the side of the fan-out area FA away from the display area AA.
  • a plurality of sub-pixels (sub pixel) P are disposed in the display area AA of the display panel 100 .
  • the multiple sub-pixels P in the present disclosure are described as an example arranged in matrix form.
  • the sub-pixels P arranged in a row along the first direction X are called a row of sub-pixels
  • the sub-pixels P arranged in a row along the second direction Y are called a column of sub-pixels
  • a row of sub-pixels can be connected with a gate line (Gate Line , referred to as GL) GL connection
  • a column of sub-pixels can be connected to a data line (Data Line, referred to as DL) DL.
  • a pixel driving circuit T for controlling the sub-pixel P to display is disposed in the sub-pixel P.
  • the display panel 100 includes a gate drive circuit 20 disposed in the display area AA, that is, the gate drive circuit 20 is directly integrated in the display area AA of the display panel 100, and the gate drive circuit 20 is GIA (full name in English) : Gate driver Integrated in Active array) circuit.
  • GIA full name in English
  • the gate line GL is electrically connected to the gate driving circuit 20, and is configured to receive the gate scanning signal from the gate driving circuit 20, and transmit the gate scanning signal to the pixel driving circuit 10 in the display area AA, that is, the gate driving circuit 20 uses for driving the gate line GL.
  • a plurality of data lines DL extend from the display area AA to the fan-out area FA, and the data lines DL are configured to transmit data signals to the pixel driving circuit T located in the display area AA.
  • the display panel 100 further includes a plurality of data fan-out leads 30 disposed in the fan-out area FA, each data line DL is electrically connected to one data fan-out lead 30 , and the plurality of data fan-out leads 30 are collected in the bonding area BA.
  • the display panel 100 also includes a plurality of control signal lines 40 and a plurality of first fan-out leads 50, wherein the plurality of control signal lines 40 are electrically connected to the gate drive circuit 20 and configured to connect to the gate drive circuit 20.
  • the drive circuit 20 transmits control signals.
  • a plurality of control signal lines 40 extend from the display area AA to the fan-out area FA.
  • a plurality of first fan-out leads 50 are disposed in the fan-out area FA, and each control signal line 40 is electrically connected to one first fan-out lead.
  • a plurality of first fan-out leads 50 converge to the bonding area BA.
  • FIG. 1 is only schematic, and the display panel 100 is provided with gate driving circuits 20 on both sides of the display area AA along the first direction X, and each gate line GL is driven by the gate driving circuits 20 on both sides. That is, bilateral drive is taken as an example for description.
  • the display panel 100 may be provided with a gate driving circuit 20 on one side of the display area AA along the first direction X to drive each gate line GL from one side, that is, to drive each gate line GL from one side.
  • the gate drive circuit 20 is directly integrated in the display area AA by adopting the GIA driving method, which can save the area of the peripheral area of the display panel 100 occupied by the gate drive circuit 20 , so that the width of the peripheral region can be reduced, which is beneficial to the narrow frame of the display device to which the display panel 100 is applied.
  • the first fan-out lead 50 is electrically connected to one end of the control signal line 40 extending to the fan-out area FA. That is, the control signal line 40 extends from the display area AA to the fan-out area FA, and one end of the control signal line 40 close to the fan-out area FA is electrically connected to the first fan-out lead 50, and the first fan-out lead 50 and the control signal line 40 does not need to be arranged in other areas outside the display area AA and the fan-out area FA, so that the sum of the lengths of the control signal line 40 and the first fan-out lead 50 electrically connected to it is relatively small, and the signal line (first fan-out lead 50) can be improved.
  • the problem of disconnection of the signal line caused by the length of the lead wire 50 and the control signal line 40) is too long, and the yield rate of the signal line is improved.
  • FIG. 1 and FIG. 2 show a wiring method
  • the display panel 100 includes a power supply voltage bus 60 disposed in the fan-out area FA, and the power supply voltage bus 60 extends along the first direction X, and the power supply voltage bus 60 60 is configured to transmit a first supply voltage signal.
  • the first fan-out lead 50 is made of the same material as the power supply voltage bus 60 and is arranged on the same layer, the first fan-out lead 50 detours from one of the opposite sides of the power supply voltage bus 60 along the first direction X, and extends to The power supply voltage bus 60 is away from the side of the display area AA.
  • the power supply voltage bus 60 as a whole extends along the first direction X, and the power supply voltage bus 60 includes a main line segment extending along the first direction X, and a main line segment electrically connected to the main line extending to the first tie line.
  • the first fan-out lead 50 includes a first lead segment 51 extending along the second direction Y, and a second lead segment 52 extending along the first direction X.
  • the first fan-out lead 50 The first lead segment 51 of the first fan-out lead 50 is located on one side of the power supply voltage bus 60 on opposite sides along the first direction X, and the second lead segment 52 of the first fan-out lead 50 extends to the side of the power supply voltage bus 60 away from the display area AA .
  • the first fan-out lead 50 is insulated from the power supply voltage bus 60, and the first fan-out lead 50 does not need to be arranged in other areas outside the fan-out area FA. , making the length of the first fan-out lead 50 shorter can improve the problem of the disconnection of the first fan-out lead 50 due to the length of the first fan-out lead 50 being too long, and improve the yield of the first fan-out lead 50 .
  • the display panel 100 further includes a plurality of first connection lines 70, and the plurality of first connection lines 70 are arranged between the power supply voltage bus 60 and the display area AA, and along the The first direction X extends, and FIG. 1 shows a situation where the first connection line 70 is disposed in the fan-out area FA.
  • the control signal line 40 is electrically connected to the corresponding first fan-out lead 50 through the first connection line 70 , so as to realize the transmission of the control signal between the control signal line 40 and the corresponding first fan-out lead 50 .
  • FIG. 3 shows a cross-sectional view of the display panel 100 in FIG. 2 along the section line A-A', the display panel 100 includes a first gate conductive layer 102 and a source-drain conductive layer 103, and the source-drain conductive layer 103 is set On the side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100 .
  • a plurality of first fan-out leads 50, a plurality of first connection lines 70 and a power supply voltage bus 60 are arranged on the first gate conductive layer 101, that is, a plurality of first fan-out leads 50, a plurality of first connection lines 70 It is set on the same layer as the power supply voltage bus 60 .
  • a plurality of control signal lines 40, a plurality of data lines DL and a plurality of data fan-out leads 30 are arranged on the source-drain conductive layer 103, that is, a plurality of control signal lines 40, a plurality of data lines DL and a plurality of data fan-out leads 30 Same level settings.
  • first connection wires 70 are directly electrically connected to the corresponding first fan-out leads 50 .
  • first connection wires 70 are directly electrically connected to the corresponding first fan-out leads 50 .
  • multiple data lines DL and multiple data fan-out leads 30 are arranged on the same layer, and the data lines DL are directly electrically connected to corresponding data fan-out leads 30 .
  • the display panel 100 further includes a first insulating layer 104, the first insulating layer 104 is disposed between the first gate conductive layer 101 and the source-drain conductive layer 103, and the first insulating layer 104 is provided with a first via hole H1.
  • the first connection line 70 is electrically connected to the corresponding control signal line 40 through the first via hole H1 , so as to realize the transmission of the control signal between the control signal line 40 and the corresponding first connection line 70 .
  • the manufacturing process of the display panel 100 includes: sequentially preparing the first gate conductive layer 101 , the first insulating layer 104 and the source-drain conductive layer 103 on the substrate 101 .
  • a plurality of first connecting lines 70 are arranged on the first gate conductive layer 101, and a plurality of control signal lines 40 are arranged on the source-drain conductive layer 103, that is, a plurality of first connecting lines 70 are prepared first, and then prepared
  • a first insulating layer 104 covering multiple first connecting lines 70 is obtained, and a first via hole H1 exposing the first connecting lines 70 is opened on the first insulating layer 104, and finally a plurality of control signal lines 40 are prepared, so that each control signal line At least part of the signal line 40 is electrically connected to the first connection line 70 in the first via hole H1 , so as to realize the cross-layer electrical connection between the first connection line 70 and the corresponding control signal line 40 .
  • cross-layer refers to a cross-layer structure
  • the cross-layer electrical connection between the first connection line 70 and the corresponding control signal line 40 means that the first insulating layer 104 is disposed on the first gate conductive layer 101 and the source-drain conductive layer 103, and a plurality of first connecting lines 70 are arranged on the first gate conductive layer 101, and a plurality of control signal lines 40 are arranged on the source-drain conductive layer 103, and the first connecting lines 70 and corresponding The control signal line 40 is electrically connected across the first insulating layer 104 .
  • the orthographic projections of the plurality of first fan-out leads 50 on the substrate 101 are staggered from the orthographic projections of the plurality of data fan-out leads 30 on the substrate 101 to avoid Along the thickness direction Z of the substrate 101, the first fan-out lead 50 overlaps with the data fan-out lead 30, so as to avoid the generation of parasitic capacitance between the first fan-out lead 50 and the data fan-out lead 30, resulting in different signal lines. Interference occurs between transmitted signals.
  • FIG. 4 and FIG. 5 show another wiring method
  • the display panel 100 includes a power supply voltage bus 60 disposed in the fan-out area FA, and the power supply voltage bus 6 extends along the first direction X.
  • the first fan-out lead 50 is arranged in a different layer from the power supply voltage bus 60 and the data fan-out lead 30, that is, at least part of the first fan-out lead 50 is not part of the power supply voltage bus 60 and the data fan-out lead 30. same layer structure.
  • the orthographic projection of the first fan-out lead 50 on the substrate 101 of the display panel 100 overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101, and overlaps with the at least one data fan-out lead 30 on the substrate 101. The orthographic projections partially overlap.
  • the orthographic projection of the first fan-out lead 50 on the substrate 101 of the display panel 100 partially overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101, and overlaps with at least one data fan-out lead.
  • the orthographic projections of 30 on the substrate 101 partially overlap.
  • the first fan-out lead 50 partially overlaps the power supply voltage bus 60, and the first fan-out lead 50 partially overlaps with at least one data fan-out lead 30, so that the first fan-out lead 50 Without bypassing the power supply voltage bus 60 and the data fan-out leads 30, they can be collected in the binding area BA, which can further reduce the length of the first fan-out leads 50, and improve the problem caused by the length of the first fan-out leads 50 being too long. Therefore, the yield of the first fan-out lead 50 is improved.
  • the length of the first fan-out lead 50 is reduced, the area occupied by the first fan-out lead 50 will not increase, so the width of the frame corresponding to the fan-out area FA of the display device will not be increased.
  • the first fan-out lead 50 includes a first lead segment 51 and a second lead segment 52 electrically connected, and the end of the first lead segment 51 is away from the second lead segment 52 Electrically connected to the control signal line 40 , the end of the second lead segment 52 away from the first lead segment 51 extends to the binding area BA (second sub-binding area BA2 ).
  • the first lead segment 51 is used for electrical connection with the control signal line 40 to realize the first fan-out lead 50 and the electrical connection of the control signal line 40; the second lead segment 52 extends to the second sub-bonding area BA2, so as to realize the collection of a plurality of first fan-out leads 50 to the second sub-bonding area BA2.
  • At least one first lead segment 51 includes a first sub-lead segment 511 and a second sub-lead segment 512 electrically connected, the first sub-lead segment 511 extends along the first direction X, The second sub-lead segment 512 extends along a second direction Y, and the second direction Y is substantially perpendicular to the first direction X.
  • control signal line 40 of the bonding area BA2 is electrically connected to the first fan-out lead 50 , and the first fan-out lead 50 needs to cross over the data fan-out lead 30 and converge to the second sub-bonding area BA2 .
  • the first fan-out lead 50 electrically connected to the control signal line 40 away from the second sub-bonding area BA2, the first lead segment 51 of the first fan-out lead 50 is set to have the first sub-lead segment 511 and The second sub-lead segment 512, the first sub-lead segment 511 extends along the first direction X, and the first sub-lead segment 511 is electrically connected to the second lead segment 52 across the data fan-out lead 30 to realize the first lead segment 51 Electrical connection to the second lead segment 52 .
  • FIG. 6 shows a cross-sectional view of the display panel 100 along the section line B-B' in FIG.
  • the electrode layer 105, the source-drain conductive layer 103 is arranged on the side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100, the first electrode layer 105 is arranged on the side of the source-drain conductive layer 103 away from the substrate 101 of the display panel 100 side.
  • the power supply voltage bus 60 is disposed on the first gate conductive layer 101 .
  • a plurality of control signal lines 40, a plurality of data lines DL and a plurality of data fan-out leads 30 are arranged on the source-drain conductive layer 103, that is, a plurality of control signal lines 40, a plurality of data lines DL and a plurality of data fan-out leads 30 Same level settings.
  • the first lead segment 51 is disposed on the first electrode layer 105 .
  • the second lead segment 52 is disposed on the source-drain conductive layer 103 or the first gate conductive layer 102 .
  • the data lines DL and the multiple data fan-out leads 30 are arranged on the same layer, the data lines DL are directly electrically connected to the corresponding data fan-out leads 30 .
  • the orthographic projection of the first lead segment 51 on the substrate 101 partially overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101 , and overlaps with at least one data fan-out lead 30 on the substrate.
  • the orthographic projections on the base 101 partially overlap.
  • the first lead segment 51 partially overlaps the power supply voltage bus 60, and the first lead segment 51 partially overlaps with at least one data fan-out lead 30, so that the first lead segment 51 does not need to wrap around
  • the length of the first lead segment 51 can be reduced, thereby reducing the length of the first fan-out lead 50, and improving the problem caused by the length of the first fan-out lead 50 being too long.
  • the problem of open circuit is eliminated, thereby improving the yield rate of the first fan-out lead 50 .
  • the length of the first lead segment 51 is reduced, the length of the first fan-out lead 50 is reduced, and the area occupied by the first fan-out lead 50 in the fan-out area FA will not increase, and therefore, the size of the display device will not be increased.
  • the width of the border of the fan-out area FA corresponds to the width of the border of the fan-out area FA.
  • the orthographic projection of the second lead segment 52 on the substrate 101 is set staggered from the orthographic projection of the plurality of data fan-out leads 30 on the substrate 101 , which can avoid The direction Z overlaps between the second lead segment 52 and the data fan-out lead 30, thereby avoiding the generation of parasitic capacitance between the second lead segment 52 of the first fan-out lead 50 and the data fan-out lead 30, resulting in the transmission of different signal lines. interference between the signals.
  • the display panel 100 further includes a second insulating layer 106, the second insulating layer 106 is disposed between the source-drain conductive layer 103 and the first electrode layer 105, and the second insulating layer 106 A second via hole H2 and a third via hole H3 are provided.
  • the end of the first lead segment 51 away from the second lead segment 52 is electrically connected to the corresponding control signal line 40 through the second via hole H2.
  • a second via hole H2 exposing the control signal line 40 is opened on the second insulating layer 106, at least part of each first lead segment 51 is electrically connected to the control signal line 40 in the second via hole H2, In order to realize the cross-layer electrical connection between the first lead segment 51 and the corresponding control signal line 40 .
  • the first lead segment 51 is close to one end of the second lead segment 52, and is electrically connected to the second lead segment 52 through the third via hole H3. connect.
  • a third via hole H3 exposing the second lead segment 52 is opened on the second insulating layer 106, and at least part of each first lead segment 51 is electrically connected to the second lead segment 52 in the third via hole H3.
  • the display panel 100 further includes a first insulating layer 104, the first insulating layer 104 is disposed between the first gate conductive layer 102 and the source-drain conductive layer 103, and the first insulating layer 104 is provided with a second A via hole H1.
  • the vias in the first insulating layer 104 are collectively referred to as the first vias H1, and it can be seen from FIG. 3 and FIG. 7 that the first vias H1 in FIG. 3 and the first vias H1 in FIG. Different vias, that is, the position of the first via H1 in FIG. 3 in the first insulating layer 104 is different from the position of the first via H1 in FIG. 7 in the first insulating layer 104 .
  • the first lead segment 51 is close to one end of the second lead segment 52, and passes through the third via hole H3.
  • the via hole H3 and the first via hole H1 are electrically connected to the second lead segment 52 . It can be understood that the first via hole H1 and the third via hole H3 are connected and expose the second lead segment 52, and at least part of each first lead segment 51 is formed in the first via hole H1 and the third via hole H3.
  • the via hole is electrically connected to the second lead segment 52 to realize the cross-layer electrical connection between the first lead segment 51 and the corresponding second lead segment 52 .
  • FIG. 8 and FIG. 9 show yet another wiring method.
  • the display panel 100 further includes a peripheral area BB surrounding the display area AA.
  • the peripheral area BB includes a first sub-peripheral area BB1, a second sub-peripheral area BB2, the third sub-peripheral area BB3, and the fourth sub-peripheral area BB4.
  • the first sub-peripheral area BB1 and the second sub-peripheral area BB2 are respectively located on opposite sides of the display area AA along the first direction X
  • the third sub-peripheral area BB3 and the fourth sub-peripheral area BB4 are respectively located on the display area AA along the second direction.
  • the first direction X is substantially perpendicular to the second direction Y.
  • the fan-out area FA and the binding area BA mentioned above are located in the fourth peripheral area BB4, that is, the fan-out area FA and the binding area BA also belong to the peripheral area BB of the display panel 100, and belong to the fourth sub-area in the peripheral area BB. Peripheral area BB4.
  • the control signal line 40 includes a first wiring segment 41 and a second wiring segment 42 electrically connected, and a part of the first wiring segments 41 in the plurality of first wiring segments 41 are routed from the third sub-peripheral area BB3 extends to the fan-out area FA along the first sub-perimeter area BB1. Another part of the first routing segment 41 extends from the third sub-peripheral area BB3 along the second sub-peripheral area BB2 to the fan-out area FA.
  • a plurality of second routing segments 42 extend from the display area AA to the third sub-peripheral area BB3.
  • One end of the first routing segment 41 is electrically connected to one end of the second routing segment 42 extending to the third sub-peripheral area BB3 , and the other end of the first routing segment 41 is electrically connected to the corresponding first fan-out lead 50 .
  • control signal line 40 extends from the display area AA to the third sub-peripheral area BB3, and a part of the control signal line 40 extends from the third sub-peripheral area BB3 along the first sub-peripheral area BB1 to the sector.
  • another part of the control signal lines 40 extends from the third sub-peripheral area BB3 along the second sub-peripheral area BB2 to the fan-out area FA.
  • control signal line 40 is drawn from the side of the display area AA away from the fan-out area FA along the second direction Y to the third sub-peripheral area BB3, and extends along the first sub-peripheral area BB1 or the second sub-peripheral area BB2 to Fan-out area FA.
  • the length of the control signal line 40 can be made larger, and the resistance value of the control signal line 40 can be increased, which is conducive to reducing the difference in resistance value between different control signal lines 40, and is different from each control signal line. 40, so as to reduce the difference of IR-Drop (voltage drop) generated by the transmission of control signals by different control signal lines 40, so as to improve the phenomenon of horizontal stripes on the display screen of the display device.
  • IR-Drop voltage drop
  • control signal line 40 will not increase the width of the peripheral area BB of the display panel 100, and the area where the control signal line 40 is located in the peripheral area BB corresponds to the packaging frame of the display device. Therefore, the control signal line The setting of 40 will not increase the width of the packaging frame of the display device.
  • the multiple first fan-out leads 50, the multiple control signal lines 40, and the multiple data fan-out leads 30 are made of the same material and arranged on the same layer, and the multiple first fan-out leads The output leads 50 are disposed on opposite sides of the plurality of data fan-out leads 30 along the first direction X. As shown in FIG. 8 and FIG. 9, the multiple first fan-out leads 50, the multiple control signal lines 40, and the multiple data fan-out leads 30 are made of the same material and arranged on the same layer, and the multiple first fan-out leads The output leads 50 are disposed on opposite sides of the plurality of data fan-out leads 30 along the first direction X. As shown in FIG.
  • the insulation between the first fan-out lead 50 and the data fan-out lead 30 is arranged, and the first fan-out lead 50 and the data fan-out lead 30 are arranged along the first direction.
  • the arrangement of the Xs is compact, which can improve the utilization rate of the area of the fan-out area FA, thereby reducing the width of the fan-out area FA, which is beneficial to the narrow frame of the display device to which the display panel 100 is applied.
  • the display panel 100 further includes a power voltage bus 60 disposed in the fan-out area FA, and the power voltage bus 60 extends along the first direction X. As shown in FIG. 8 and FIG. 9 , the display panel 100 further includes a power voltage bus 60 disposed in the fan-out area FA, and the power voltage bus 60 extends along the first direction X. As shown in FIG. 8 and FIG. 9 , the display panel 100 further includes a power voltage bus 60 disposed in the fan-out area FA, and the power voltage bus 60 extends along the first direction X. As shown in FIG.
  • the first fan-out lead 50 and the power voltage bus 60 are arranged in different layers.
  • the orthographic projection of the first fan-out lead 50 on the substrate 101 of the display panel 100 partially overlaps with the orthographic projection of the power supply voltage bus 60 on the substrate 101, which can reduce the occupation of the fan-out area FA by the first fan-out lead 50. Therefore, it is beneficial to reduce the width of the fan-out area FA, which is beneficial to the narrow frame of the display device to which the display panel 100 is applied.
  • FIG. 10 shows a cross-sectional view of the display panel 100 in FIG. 9 along the section line C-C', the display panel 100 includes a first gate conductive layer 102 and a source-drain conductive layer 103, and the source-drain conductive layer 103 is set On the side of the first gate conductive layer 102 away from the substrate 101 of the display panel 100 .
  • the power supply voltage bus 60 is disposed on the first gate conductive layer 102 .
  • a plurality of control signal lines 40, a plurality of data lines DL, a plurality of data fan-out leads 30 and a plurality of first fan-out leads 50 are arranged on the source-drain conductive layer 103, that is, a plurality of control signal lines 40, a plurality of data lines DL, multiple data fan-out leads 30 and multiple first fan-out leads 50 are arranged on the same layer.
  • the data lines DL and the multiple data fan-out leads 30 are arranged on the same layer, the data lines DL are directly electrically connected to the corresponding data fan-out leads 30 .
  • the plurality of control signal lines 40 and the plurality of first fan-out leads 50 are arranged on the same layer, and the control signal lines 40 are directly electrically connected to the corresponding first fan-out leads 50 .
  • the first wiring segment 41 of the control signal line 10 and the plurality of first fan-out leads 50 are made of the same material as the power supply voltage bus 60 and arranged on the same layer.
  • the first fan-out leads 50 It detours from one of the opposite sides of the power voltage bus 60 along the first direction X, and extends to the side of the power voltage bus 60 away from the display area AA.
  • the insulation between the first fan-out lead 50 and the power supply voltage bus 60 is arranged, and the first fan-out lead 50 and the power supply voltage bus 60 are arranged along the first direction X.
  • the compact arrangement can improve the utilization rate of the area of the fan-out area FA, thereby reducing the width of the fan-out area FA, which is beneficial to the narrow frame of the display device to which the display panel 100 is applied.
  • the first wiring segment 41, the plurality of first fan-out leads 50 and the power supply voltage bus 60 are arranged on the first gate conductive layer 102, and the second of the control signal line 40
  • the routing segment 42 , multiple data lines DL and multiple data fan-out leads 30 are disposed on the source-drain conductive layer 103 .
  • the display panel 100 includes a first insulating layer 104 disposed between the first gate conductive layer 102 and the source-drain conductive layer 103, and the first insulating layer 104 is provided with a first pass The hole H1 , the first trace segment 41 is electrically connected to the corresponding second trace segment 42 through the first via hole H1 .
  • the via holes in the first insulating layer 104 are collectively referred to as the first via hole H1. It can be seen from FIG. 8 that the position where the first trace segment 41 is electrically connected to the corresponding second trace segment 42 is located in the third sub-peripheral area BB3, that is, the first insulating layer 104 is provided with a first via hole H1 at a position corresponding to the third sub-peripheral region BB3.
  • the binding area BA includes a first sub-binding area BA1 and at least one second sub-binding area BA2 arranged side by side along the first direction X.
  • a plurality of data fan-out wires 30 are collected into the first sub-bonding area BA1, and at least one of the plurality of first fan-out wires 50 is collected into the second sub-bonding area BA2.
  • the display panel 100 is provided with a gate driving circuit 20 along one side of the first direction X in the display area AA to drive each gate line GL from one side, that is, to drive each gate line GL from one side.
  • the binding area BA includes a first sub-binding area BA1 and a second sub-binding area BA2 arranged side by side along the first direction X, and a plurality of data fan-out leads 30 converge to the first sub-binding area BA1 , at least one of the plurality of first fan-out leads 50 converges to the second sub-bonding area BA2.
  • the first sub-binding area BA1 and the second sub-binding area BA2 are arranged side by side, and multiple data fan-out leads 30 are collected to the first sub-binding area BA1, and the multiple first fan-out At least one of the wires 50 is collected into the second sub-binding area BA2, and the area where the first fan-out wires 50 are collected is located on one side of the area where multiple data fan-out wires 30 are collected along the first direction X, so that the first fan-out
  • the arrangement of the leads 50 and the data fan-out leads 30 in the fan-out area FA is compact, which can improve the utilization rate of the area of the fan-out area FA, thereby reducing the width of the fan-out area FA, which is beneficial to the application of the display panel 100. Narrow bezels of display devices.
  • the display panel 100 is provided with gate driving circuits 20 on both sides of the display area AA along the first direction X, and each gate line GL is driven by the gate driving circuits 20 on both sides, that is, double-sided driving.
  • the binding area BA includes the first sub-binding area BA1, and two In the second sub-binding area BA2, a plurality of data fan-out leads 30 are collected into the first sub-binding area BA1, and a plurality of first fan-out leads 50 are divided into two groups, and the first fan-out leads 50 of the two groups are respectively collected into two sub-binding areas.
  • the two second sub-binding areas BA2 are respectively located on opposite sides of the first sub-binding area BA1 along the first direction X, and a plurality of data fan-out leads 30 converge to the first sub-binding area BA1.
  • Area BA1 a plurality of first fan-out leads 50 are divided into two groups, a group of first fan-out leads 50 are collected to one side of the second sub-binding area BA2, and another group of first fan-out leads 50 are collected to the other side
  • the second sub-binding area BA2 that is, the area where two groups of first fan-out wires 50 gather, are respectively located on opposite sides of the area where multiple data fan-out wires 30 gather along the first direction X, so that the first fan-out wires
  • the arrangement of 50 and data fan-out leads 30 in the fan-out area FA is compact, which can improve the utilization rate of the area of the fan-out area FA, thereby reducing the width of the fan-out area FA, which is beneficial to the application of the display panel 100. Narrow bezels of devices.
  • the display panel 100 further includes a power supply voltage line 80 disposed in the fan-out area FA.
  • the entire power supply voltage line 80 extends along the first direction X, and the power supply voltage
  • the line 80 includes a main line segment extending along the first direction X, and a branch line segment electrically connected to the main line segment and extending to the first binding area BA1 .
  • the supply voltage line 80 is configured to transmit a second supply voltage signal.
  • the display panel 100 further includes a plurality of pins 90 configured to be bound to a flexible printed circuit board.
  • the plurality of pins 90 includes a plurality of first pins 91 located in the first sub-binding area BA1, and a plurality of second pins 92 located in the second sub-binding area BA2.
  • each data fan-out lead 30 is electrically connected to at least one first pin 91
  • each first fan-out lead 50 is electrically connected to at least one second pin 92 .
  • each data fan-out lead 30 is electrically connected to a first pin 91 .
  • Each first fan-out lead 50 is electrically connected to a second pin 92 .
  • each data fan-out lead 30 is electrically connected to two first pins 91 .
  • Each first fan-out lead 50 is electrically connected to two second pins 92 .
  • the display device 200 includes the display panel 100 in any of the above embodiments.
  • the display panel 100 of the display device 200 adopts the GIA driving method, and the gate driving circuit 20 is directly integrated in the display area AA, which can save the peripheral area of the display panel 100 occupied by the gate driving circuit 20. area, so that the width of the peripheral area can be reduced, which is beneficial to the narrow frame of the display device 200 .
  • the arrangement of the first fan-out leads 50 and the data fan-out leads 30 in the display panel 100 in the fan-out area FA is compact, which can improve the utilization rate of the area of the fan-out area FA, thereby reducing the fan-out area FA.
  • the width of the display panel 100 is beneficial to the narrow frame of the display device to which the display panel 100 is applied.
  • the display device 200 may be an electroluminescent display device, and the electroluminescent display device may be an OLED display device.
  • the display device 200 described above may be any device that displays an image regardless of whether it is moving (for example, video) or fixed (for example, still image) and regardless of text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or Laptop Computers GPS Receiv

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Abstract

一种显示面板(100)，包括显示区(AA)，位于显示区(AA)一侧的扇出区(FA)，及位于扇出区(FA)远离显示区(AA)一侧的绑定区(BA)。显示面板(100)包括设置于显示区(100)的栅极驱动电路(20)、从显示区(AA)延伸至扇出区(FA)的多条数据线(DL)和多条控制信号线(40)，以及设置于扇出区(FA)的多条数据扇出引线(30)和多条第一扇出引线(50)。每条数据线(DL)与一条数据扇出引线(30)电连接，多条数据扇出引线(30)汇集至绑定区(BA)。多条控制信号线(40)与栅极驱动电路(20)电连接，多条控制信号线(40)被配置为向栅极驱动电路(20)传输控制信号。每条控制信号线(40)与一条第一扇出引线(50)电连接，多条第一扇出引线(50)汇集至绑定区(BA)。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的发展，有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置凭借其较高的屏占比，以及窄边框的特点，提升了人们观看的体验，受到越来越多的消费者青睐。
通过减小OLED显示装置的边框的宽度，提高OLED显示装置的屏占比，实现显示屏的全面屏设计。并且，采用全面屏拼接形成的拼接显示屏，可减小拼接缝的宽度，提高拼接显示屏的显示画面的整体性。
公开内容
一方面，提供一种显示面板。所述显示面板包括显示区，位于所述显示区一侧的扇出区，及位于所述扇出区远离所述显示区一侧的绑定区。
所述显示面板包括设置于所述显示区的栅极驱动电路、多条数据线、多条数据扇出引线、多条控制信号线和多条第一扇出引线，其中，多条数据线从所述显示区延伸至所述扇出区。多条数据扇出引线设置于所述扇出区，每条数据线与一条数据扇出引线电连接，所述多条数据扇出引线汇集至所述第一子绑定区。多条控制信号线与所述栅极驱动电路电连接，多条控制信号线被配置为向所述栅极驱动电路传输控制信号，所述多条控制信号线从所述显示区延伸至所述扇出区。多条第一扇出引线设置于所述扇出区，每条控制信号线与一条第一扇出引线电连接，所述多条第一扇出引线汇集至所述绑定区。
在一些实施例中，所述第一扇出引线与所述控制信号线的延伸至所述扇出区的一端电连接。
在一些实施例中，所述显示面板还包括电源电压总线，电源电压总线设置于所述扇出区，且沿所述第一方向延伸。其中，所述第一扇出引线与所述电源电压总线材料相同且同层设置，所述第一扇出引线从所述电源电压总线的沿所述第一方向相对两侧中的一侧绕行，并延伸至所述电源电压总线远离所述显示区的一侧。
在一些实施例中，所述显示面板还包括多条第一连接线，多条第一连接线设置于所述电源电压总线与所述显示区之间，且沿所述第一方向延伸。所述控制信号线通过第一连接线与相应的第一扇出引线电连接。
在一些实施例中，所述显示面板包括第一栅导电层和源漏导电层，所述 多条第一扇出引线、所述多条第一连接线和所述电源电压总线设置于所述第一栅导电层。源漏导电层设置于所述第一栅导电层远离所述显示面板的衬底的一侧，所述多条控制信号线、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层。
在一些实施例中，所述显示面板还包括第一绝缘层，第一绝缘层设置于所述第一栅导电层和所述源漏导电层之间。所述第一绝缘层中设有第一过孔，所述第一连接线通过所述第一过孔与相应的控制信号线电连接。
在一些实施例中，所述多条第一扇出引线在所述衬底上的正投影，与所述多条数据扇出引线在所述衬底上的正投影错开设置。
在一些实施例中，所述显示面板还包括电源电压总线，电源电压总线设置于所述扇出区，且沿所述第一方向延伸。其中，所述第一扇出引线的至少部分与所述电源电压总线及所述数据扇出引线异层设置。所述第一扇出引线在所述显示面板的衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠，且与至少一条数据扇出引线在所述衬底上的正投影部分重叠。
在一些实施例中，所述第一扇出引线包括电连接的第一引线段和第二引线段，所述第一引线段远离所述第二引线段的一端与所述控制信号线电连接，所述第二引线段远离所述第一引线段的一端延伸至所述绑定区。
在一些实施例中，至少一条第一引线段包括电连接的第一子引线段和第二子引线段，所述第一子引线段沿所述第一方向延伸，所述第二子引线段沿第二方向延伸。所述第二方向与所述第一方向大致垂直。
在一些实施例中，所述显示面板包括第一栅导电层、源漏导电层和第一电极层，所述电源电压总线设置于所述第一栅导电层。源漏导电层设置于所述第一栅导电层远离所述衬底的一侧，所述多条控制信号线、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层。第一电极层设置于所述源漏导电层远离所述衬底的一侧。其中，所述第一引线段设置于所述第一电极层，所述第二引线段设置于所述源漏导电层或所述第一栅导电层。
所述第一引线段在所述衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠，且与至少一条数据扇出引线在所述衬底上的正投影部分重叠。所述第二引线段在所述衬底上的正投影，与所述多条数据扇出引线在所述衬底上的正投影错开设置。
在一些实施例中，所述显示面板还包括第二绝缘层，第二绝缘层设置于所述源漏导电层与所述第一电极层之间，所述第二绝缘层中设置有第二过孔和第三过孔。其中，所述第一引线段远离所述第二引线段的一端，通过所述 第二过孔与相应的所述控制信号线电连接。
所述第一引线段靠近所述第二引线段的一端，通过所述第三过孔与所述第二引线段电连接。或者，所述显示面板还包括设置于所述第一栅导电层和所述源漏导电层之间的第一绝缘层，所述第一绝缘层中设有第一过孔，所述第一过孔与所述第三过孔相连通，所述第一引线段靠近所述第二引线段的一端，通过所述第三过孔和所述第一过孔与所述第二引线段电连接。
在一些实施例中，所述显示面板还包括围绕所述显示区的周边区，所述周边区包括第一子周边区、第二子周边区、第三子周边区和第四子周边区。所述第一子周边区和所述第二子周边区分别位于所述显示区沿第一方向的相对两侧，所述第三子周边区和所述第四子周边区分别位于所述显示区沿第二方向的相对两侧，所述第一方向与所述第二方向大致垂直，所述扇出区和所述绑定区位于所述第四子周边区。
所述控制信号线包括电连接的第一走线段和第二走线段，多条第一走线段中的一部分第一走线段从所述第三子周边区，沿所述第一子周边区，延伸至所述扇出区。另一部分第一走线段从所述第三子周边区，沿所述第二子周边区，延伸至所述扇出区。多条第二走线段从所述显示区延伸至所述第三子周边区。
所述第一走线段的一端与所述第二走线段的延伸至所述第三子周边区的一端电连接，所述第一走线段的另一端与相应的第一扇出引线电连接。
在一些实施例中，所述多条第一扇出引线、所述多条控制信号线和所述多条数据扇出引线材料相同且同层设置。所述多条第一扇出引线设置于所述多条数据扇出引线的沿所述第一方向的相对两侧。
在一些实施例中，所述显示面板还包括电源电压总线，电源电压总线设置于所述扇出区，且沿所述第一方向延伸。其中，所述第一扇出引线与所述电源电压总线异层设置，所述第一扇出引线在所述显示面板的衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠。
在一些实施例中，所述显示面板包括第一栅导电层和源漏导电层，所述电源电压总线设置于所述第一栅导电层。源漏导电层设置于所述第一栅导电层远离所述显示面板的衬底的一侧，所述多条控制信号线、所述多条数据线、所述多条数据扇出引线和所述多条第一扇出引线设置于所述源漏导电层。
在一些实施例中，所述显示面板还包括电源电压总线，电源电压总线设置于所述扇出区，且沿所述第一方向延伸。其中，所述控制信号线的第一走线段和所述多条第一扇出引线与所述电源电压总线材料相同且同层设置，所 述第一扇出引线从所述电源电压总线的沿所述第一方向相对两侧中的一侧绕行，并延伸至所述电源电压总线远离所述显示区的一侧。
在一些实施例中，所述显示面板包括第一栅导电层和源漏导电层，所述第一走线段、所述多条第一扇出引线和所述电源电压总线设置于所述第一栅导电层。源漏导电层设置于所述第一栅导电层远离所述显示面板的衬底的一侧，所述控制信号线的第二走线段、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层。
在一些实施例中，所述绑定区包括第一子绑定区，及位于所述第一子绑定区沿第一方向相对两侧的两个第二子绑定区，所述多条数据扇出引线汇集至所述第一子绑定区，所述多条第一扇出引线分为两组，两组第一扇出引线分别汇集至两个第二子绑定区。
在一些实施例中，所述显示面板还包括多个引脚，多个引脚被配置为绑定柔性印刷电路板。所述多个引脚包括位于所述第一子绑定区的多个第一引脚，及位于所述第二子绑定区的多个第二引脚。
其中，所述数据扇出引线与至少一个第一引脚电连接，所述第一扇出引线与至少一个第二引脚电连接。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开的一些实施例的显示面板的一种结构图；
图2为图1中的显示面板的M处的局部放大图；
图3为图2中的显示面板沿剖面线A-A＇的剖面图；
图4为根据本公开的一些实施例的显示面板的另一种结构图；
图5为图4中的显示面板的N处的局部放大图；
图6为图5中的显示面板沿剖面线B-B＇的一种剖面图；
图7为图5中的显示面板沿剖面线B-B＇的另一种剖面图；
图8为根据本公开的一些实施例的显示面板的又一种结构图；
图9为图8中的显示面板的O处的局部放大图；
图10为图9中的显示面板沿剖面线C-C＇的剖面图；
图11为根据本公开的一些实施例的显示面板的又一种结构图；
图12为图11中的显示面板沿剖面线D-D＇的剖面图；
图13为根据本公开的一些实施例的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限 性)所确定。
本文中“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。与之相反地，“异层”指的是分别采用相应的成膜工艺形成用于形成特定图形的膜层，然后利用相应的掩模板通过构图工艺形成的层结构，例如，“两个层结构异层设置”是指两个层结构分别在相应的工艺步骤(成膜工艺和构图工艺)下形成。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，显示面板采用GOA(英文全称：Gate Driver on Array，中文全称：阵列基板行驱动)的驱动方式，即，显示面板中的栅极驱动电路直接集成在位于显示区的至少一侧的周边区。
并且，显示面板还包括设置于周边区的多条信号线，多条信号线与栅极驱动电路电连接，用于向栅极驱动电路传输控制信号。但是，栅极驱动电路和多条信号线的设置需要占用较多的周边区的面积，使得周边区的宽度较大，不利于应用该显示面板的显示装置的窄边框化。
为解决上述问题，本公开的一些实施例提供了一种显示面板，如图1所示，显示面板100包括显示区(Active Area，简称AA区；也可称为有效显示区)AA，位于显示区AA一侧的扇出区(Fanout区)FA，以及位于扇出区FA远离显示区AA一侧的绑定区BA。
如图1所示，显示面板100的显示区AA内设置有多个子像素(sub pixel)P。为了方便说明，本公开的多个子像素P是以矩阵形式排列为例进行的说明。此时，沿第一方向X排列成一排的子像素P称为一行子像素，沿第二方向Y排列成一排的子像素P称为一列子像素，一行子像素可以与一条栅线(Gate Line，简称GL)GL连接，一列子像素可以与一条数据线(Data Line，简称 DL)DL连接。子像素P内设置有用于控制子像素P进行显示的像素驱动电路T。
如图1所示，显示面板100包括设置于显示区AA的栅极驱动电路20，即栅极驱动电路20直接集成在显示面板100的显示区AA中，栅极驱动电路20为GIA(英文全称：Gate driver Integrated in Active array)电路。
栅线GL与栅极驱动电路20电连接，被配置为接收来自栅极驱动电路20的栅扫描信号，将栅扫描信号传输至显示区AA中的像素驱动电路10，即栅极驱动电路20用于驱动栅线GL。
如图1所示，多条数据线DL从显示区AA延伸至扇出区FA，数据线DL被配置为向位于显示区AA的像素驱动电路T传输数据信号。显示面板100还包括设置于扇出区FA的多条数据扇出引线30，每条数据线DL与一条数据扇出引线30电连接，多条数据扇出引线30汇集至绑定区BA。
如图1所示，显示面板100还包括多条控制信号线40和多条第一扇出引线50，其中，多条控制信号线40与栅极驱动电路20电连接，被配置为向栅极驱动电路20传输控制信号。多条控制信号线40从显示区AA延伸至扇出区FA。
多条第一扇出引线50设置于扇出区FA，每条控制信号线40与一条第一扇出引线电连接。多条第一扇出引线50汇集至绑定区BA。
需要说明的是，图1仅是示意的，以显示面板100在显示区AA内沿第一方向X的两边分别设置栅极驱动电路20，通过两边的栅极驱动电路20驱动各栅线GL，即双边驱动为例进行说明。在另一些实施例中，显示面板100可以在显示区AA内沿第一方向X的一侧边设置栅极驱动电路20，从单边驱动各栅线GL，即单边驱动。
本公开以下实施例均是以双边驱动为例进行说明的。
本公开的上述实施例中的显示面板100，通过采用GIA的驱动方式，将栅极驱动电路20直接集成在显示区AA，可节省栅极驱动电路20所占用的显示面板100的周边区的面积，从而可减小周边区的宽度，有利于应用该显示面板100的显示装置的窄边框化。
下面结合附图，对显示面板100中的各信号线的具体布线方式进行描述。
在一些实施例中，如图1和图4所示，第一扇出引线50与控制信号线40的延伸至扇出区FA的一端电连接。即，控制信号线40从显示区AA延伸至扇出区FA，且控制信号线40的靠近扇出区FA的一端与第一扇出引线50电连接，第一扇出引线50和控制信号线40不需要设置于显示区AA和扇出区 FA外的其它区域，使得控制信号线40及与其电连接的第一扇出引线50的长度之和较小，可改善因信号线(第一扇出引线50和控制信号线40)的长度过长所导致的信号线断路的问题，提高信号线的良率。
在一些实施例中，图1和图2示出了一种布线方式，显示面板100包括设置于扇出区FA的电源电压总线60，且电源电压总线60沿第一方向X延伸，电源电压总线60被配置为传输第一电源电压信号。
其中，第一扇出引线50与电源电压总线60材料相同且同层设置，第一扇出引线50从电源电压总线60的沿第一方向X相对两侧中的一侧绕行，并延伸至电源电压总线60远离显示区AA的一侧。
需要说明的是，如图1所示，电源电压总线60的整体沿第一方向X延伸，电源电压总线60包括沿第一方向X延伸的主线段，以及与主线电连接的延伸至第一绑定区BA1的支线段。
示例性地，如图2所示，第一扇出引线50包括沿第二方向Y延伸的第一引线段51，以及沿第一方向X延伸的第二引线段52，第一扇出引线50的第一引线段51位于电源电压总线60的沿第一方向X相对两侧中的一侧，第一扇出引线50的第二引线段52延伸至电源电压总线60远离显示区AA的一侧。
通过采用上述第一扇出引线50的布线方式，使第一扇出引线50与电源电压总线60之间绝缘设置，并且，第一扇出引线50不需要设置于扇出区FA外的其它区域，使得第一扇出引线50的长度较小，可改善因第一扇出引线50的长度过长而导致其断路的问题，提高第一扇出引线50的良率。
在一些实施例中，如图1和图2所示，显示面板100还包括多条第一连接线70，多条第一连接线70设置于电源电压总线60与显示区AA之间，且沿第一方向X延伸，图1中示出了第一连接线70设置于扇出区FA的情形。控制信号线40通过第一连接线70与相应的第一扇出引线50电连接，以实现控制信号线40与相应的第一扇出引线50之间的控制信号的传输。
在一些实施例中，图3示出了图2中的显示面板100沿剖面线A-A＇的剖面图，显示面板100包括第一栅导电层102和源漏导电层103，源漏导电层103设置于第一栅导电层102远离显示面板100的衬底101的一侧。
其中，多条第一扇出引线50、多条第一连接线70和电源电压总线60设置于第一栅导电层101，即，多条第一扇出引线50、多条第一连接线70和电源电压总线60同层设置。多条控制信号线40、多条数据线DL和多条数据扇出引线30设置于源漏导电层103，即，多条控制信号线40、多条数据线DL和多条数据扇出引线30同层设置。
可以理解的是，由于多条第一扇出引线50与多条第一连接线70同层设置，因此第一连接线70与相应的第一扇出引线50之间直接电连接。同理，多条数据线DL和多条数据扇出引线30同层设置，数据线DL与相应的数据扇出引线30直接电连接。
在一些实施例中，如图3所示，显示面板100还包括第一绝缘层104，第一绝缘层104设置于第一栅导电层101和源漏导电层103之间，且第一绝缘层104中设有第一过孔H1。其中，第一连接线70通过第一过孔H1与相应的控制信号线40电连接，以实现控制信号线40与相应的第一连接线70之间的控制信号的传输。
需要说明的是，显示面板100的制备工艺包括：依次在衬底101上制备第一栅导电层101、第一绝缘层104和源漏导电层103。结合上文可知，多条第一连接线70设置于第一栅导电层101，多条控制信号线40设置于源漏导电层103，即，先制备得到多条第一连接线70，再制备得到覆盖多条第一连接线70的第一绝缘层104，第一绝缘层104上开设有暴露第一连接线70的第一过孔H1，最后制备多条控制信号线40，使每条控制信号线40的至少部分在第一过孔H1内与第一连接线70电连接，以实现第一连接线70与相应的控制信号线40的跨层电连接。
可以理解的是，“跨层”是指跨越层结构，例如，“第一连接线70与相应的控制信号线40的跨层电连接”是指，第一绝缘层104设置于第一栅导电层101和源漏导电层103之间，且多条第一连接线70设置于第一栅导电层101，多条控制信号线40设置于源漏导电层103，第一连接线70与相应的控制信号线40跨越第一绝缘层104电连接。
在一些实施例中，如图2所示，多条第一扇出引线50在衬底101上的正投影，与多条数据扇出引线30在衬底101上的正投影错开设置，可避免沿衬底101的厚度方向Z第一扇出引线50与数据扇出引线30之间重叠，从而避免第一扇出引线50与数据扇出引线30之间产生寄生电容，而导致不同信号线所传输的信号之间产生干扰。
在一些实施例中，图4和图5示出了另一种布线方式，显示面板100包括设置于扇出区FA的电源电压总线60，且电源电压总线6沿第一方向X延伸。
其中，第一扇出引线50的至少部分与电源电压总线60及数据扇出引线30异层设置，即，第一扇出引线50的至少部分与电源电压总线60及数据扇出引线30不属于同一层结构。第一扇出引线50在显示面板100的衬底101 上的正投影，与电源电压总线60在衬底101上的正投影部分重叠，且与至少一条数据扇出引线30在衬底101上的正投影部分重叠。
本公开的上述实施例，第一扇出引线50在显示面板100的衬底101上的正投影，与电源电压总线60在衬底101上的正投影部分重叠，且与至少一条数据扇出引线30在衬底101上的正投影部分重叠。即，沿衬底101的厚度方向Z，第一扇出引线50与电源电压总线60部分重叠，且第一扇出引线50与至少一条数据扇出引线30部分重叠，使得第一扇出引线50不需要绕过电源电压总线60及数据扇出引线30就可以汇集至绑定区BA，可进一步减小第一扇出引线50的长度，改善因第一扇出引线50的长度过长而导致其断路的问题，从而提高第一扇出引线50的良率。
并且，由于第一扇出引线50的长度减小，第一扇出引线50占用扇出区FA的面积不会增加，因此，不会增加显示装置的对应扇出区FA的边框的宽度。
在一些实施例中，如图4和图5所示，第一扇出引线50包括电连接的第一引线段51和第二引线段52，第一引线段51远离第二引线段52的一端与控制信号线40电连接，第二引线段52远离第一引线段51的一端延伸至绑定区BA(第二子绑定区BA2)。
可以理解的是，第一扇出引线50所包括的第一引线段51和第二引线段52中，第一引线段51用于与控制信号线40的电连接，以实现第一扇出引线50与控制信号线40的电连接；第二引线段52延伸至第二子绑定区BA2，以实现多条第一扇出引线50汇集至第二子绑定区BA2。
在一些实施例中，如图5所示，至少一条第一引线段51包括电连接的第一子引线段511和第二子引线段512，第一子引线段511沿第一方向X延伸，第二子引线段512沿第二方向Y延伸，第二方向Y与第一方向X大致垂直。
可以理解的是，结合图5，多条控制信号线40中，部分控制信号线40靠近第二子绑定区BA2，部分控制信号线40远离第二子绑定区BA2，与远离第二子绑定区BA2的控制信号线40电连接的第一扇出引线50，该第一扇出引线50需要跨过数据扇出引线30汇集至第二子绑定区BA2。因此，与远离第二子绑定区BA2的控制信号线40电连接的第一扇出引线50，将该第一扇出引线50的第一引线段51设置为具有第一子引线段511和第二子引线段512，第一子引线段511沿第一方向X延伸，且第一子引线段511跨过数据扇出引线30与第二引线段52电连接，以实现第一引线段51与第二引线段52的电连接。
在一些实施例中，图6示出了图5中的显示面板100沿剖面线B-B＇的剖面图，显示面板100包括依次层叠设置的第一栅导电层102、源漏导电层103和第一电极层105，源漏导电层103设置于第一栅导电层102远离显示面板100的衬底101的一侧，第一电极层105设置于源漏导电层103远离显示面板100的衬底101的一侧。
其中，电源电压总线60设置于第一栅导电层101。多条控制信号线40、多条数据线DL和多条数据扇出引线30设置于源漏导电层103，即，多条控制信号线40、多条数据线DL和多条数据扇出引线30同层设置。第一引线段51设置于第一电极层105。第二引线段52设置于源漏导电层103或第一栅导电层102。
可以理解的是，由于多条数据线DL和多条数据扇出引线30同层设置，因此，数据线DL与相应的数据扇出引线30直接电连接。
如图4和图5所示，第一引线段51在衬底101上的正投影，与电源电压总线60在衬底101上的正投影部分重叠，且与至少一条数据扇出引线30在衬底101上的正投影部分重叠。即，沿衬底101的厚度方向Z，第一引线段51与电源电压总线60部分重叠，且第一引线段51与至少一条数据扇出引线30部分重叠，使得第一引线段51不需要绕过电源电压总线60及数据扇出引线30，可减小第一引线段51的长度，从而减小第一扇出引线50的长度，改善因第一扇出引线50的长度过长而导致其断路的问题，从而提高第一扇出引线50的良率。
并且，由于第一引线段51的长度减小，使第一扇出引线50的长度减小，第一扇出引线50占用扇出区FA的面积不会增加，因此，不会增加显示装置的对应扇出区FA的边框的宽度。
如图4和图5所示，第二引线段52在衬底101上的正投影，与多条数据扇出引线30在衬底101上的正投影错开设置，可避免沿衬底101的厚度方向Z第二引线段52与数据扇出引线30之间重叠，从而避免第一扇出引线50的第二引线段52与数据扇出引线30之间产生寄生电容，而导致不同信号线所传输的信号之间产生干扰。
在一些实施例中，如图6所示，显示面板100还包括第二绝缘层106，第二绝缘层106设置于源漏导电层103与第一电极层105之间，第二绝缘层106中设置有第二过孔H2和第三过孔H3。
其中，第一引线段51远离第二引线段52的一端，通过第二过孔H2与相应的控制信号线40电连接。可以理解的是，第二绝缘层106上开设有暴露控 制信号线40的第二过孔H2，每条第一引线段51的至少部分在第二过孔H2内与控制信号线40电连接，以实现第一引线段51与相应的控制信号线40的跨层电连接。
如图6所示，在第二引线段52设置于源漏导电层103的情况下，第一引线段51靠近第二引线段52的一端，通过第三过孔H3与第二引线段52电连接。可以理解的是，第二绝缘层106上开设有暴露第二引线段52的第三过孔H3，每条第一引线段51的至少部分在第三过孔H3内与第二引线段52电连接，以实现第一引线段51与相应的第二引线段52的跨层电连接。
或者，如图7所示，显示面板100还包括第一绝缘层104，第一绝缘层104设置于第一栅导电层102和源漏导电层103之间，第一绝缘层104中设有第一过孔H1。
需要说明的是，第一绝缘层104中的过孔统称为第一过孔H1，结合图3和图7可知，图3中的第一过孔H1与图7中的第一过孔H1是不同的过孔，即图3中的第一过孔H1在第一绝缘层104中的位置，与图7中的第一过孔H1在第一绝缘层104中的位置不同。
在第二引线段52设置于第一栅导电层102，且第一过孔H1与第三过孔H3相连通的情况下，第一引线段51靠近第二引线段52的一端，通过第三过孔H3和第一过孔H1与第二引线段52电连接。可以理解的是，第一过孔H1和第三过孔H3相连通且暴露第二引线段52，每条第一引线段51的至少部分在第一过孔H1和第三过孔H3所形成的过孔内与第二引线段52电连接，以实现第一引线段51与相应的第二引线段52的跨层电连接。
在一些实施例中，图8和图9示出了又一种布线方式，显示面板100还包括围绕显示区AA的周边区BB，周边区BB包括第一子周边区BB1、第二子周边区BB2、第三子周边区BB3和第四子周边区BB4。第一子周边区BB1和第二子周边区BB2分别位于显示区AA沿第一方向X的相对两侧，第三子周边区BB3和第四子周边区BB4分别位于显示区AA沿第二方向Y的相对两侧，第一方向X与第二方向Y大致垂直。
前文所述的扇出区FA和绑定区BA位于第四子周边区BB4，即扇出区FA和绑定区BA也属于显示面板100的周边区BB，属于周边区BB中的第四子周边区BB4。
如图8和图9所示，控制信号线40包括电连接的第一走线段41和第二走线段42，多条第一走线段41中的一部分第一走线段41从第三子周边区BB3，沿第一子周边区BB1，延伸至扇出区FA。另一部分第一走线段41从 第三子周边区BB3，沿第二子周边区BB2，延伸至扇出区FA。多条第二走线段42从显示区AA延伸至第三子周边区BB3。
其中，第一走线段41的一端与第二走线段42的延伸至第三子周边区BB3的一端电连接，第一走线段41的另一端与相应的第一扇出引线50电连接。
本公开的上述实施例，使控制信号线40从显示区AA延伸至第三子周边区BB3，且一部分控制信号线40从第三子周边区BB3，沿第一子周边区BB1，延伸至扇出区FA，另一部分控制信号线40从第三子周边区BB3，沿第二子周边区BB2，延伸至扇出区FA。即，控制信号线40从显示区AA的沿第二方向Y远离扇出区FA的一侧引出至第三子周边区BB3，并沿第一子周边区BB1或第二子周边区BB2延伸至扇出区FA。
通过采用上述走线设计，可使得控制信号线40长度较大，可增加控制信号线40的电阻值，有利于减小不同控制信号线40之间的电阻值差值，与每条控制信号线40的电阻值的比值，从而减小不同控制信号线40传输控制信号所产生的IR-Drop(压降)的差异，以改善显示装置的显示画面产生横纹的现象。
并且，采用上述走线设计，控制信号线40的设置不会增加显示面板100的周边区BB的宽度，控制信号线40在周边区BB的设置区域对应显示装置的封装边框，因此，控制信号线40的设置不会增加显示装置的封装边框的宽度。
在一些实施例中，如图8和图9所示，多条第一扇出引线50、多条控制信号线40和多条数据扇出引线30材料相同且同层设置，多条第一扇出引线50设置于多条数据扇出引线30的沿第一方向X的相对两侧。
通过采用上述第一扇出引线50的布线方式，使第一扇出引线50与数据扇出引线30之间绝缘设置，并且，使得第一扇出引线50和数据扇出引线30沿第一方向X的排布紧凑，可提高对扇出区FA的面积的利用率，从而可减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
在一些实施例中，如图8和图9所示，显示面板100还包括设置于扇出区FA的电源电压总线60，且电源电压总线60沿第一方向X延伸。
其中，第一扇出引线50与电源电压总线60异层设置。第一扇出引线50在显示面板100的衬底101上的正投影，与电源电压总线60在衬底101上的正投影部分重叠，可减小第一扇出引线50占用扇出区FA的面积，从而有利于减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
在一些实施例中，图10示出了图9中的显示面板100沿剖面线C-C＇的 剖面图，显示面板100包括第一栅导电层102和源漏导电层103，源漏导电层103设置于第一栅导电层102远离显示面板100的衬底101的一侧。
其中，电源电压总线60设置于第一栅导电层102。多条控制信号线40、多条数据线DL、多条数据扇出引线30和多条第一扇出引线50设置于源漏导电层103，即，多条控制信号线40、多条数据线DL、多条数据扇出引线30和多条第一扇出引线50同层设置。
可以理解的是，由于多条数据线DL和多条数据扇出引线30同层设置，因此，数据线DL与相应的数据扇出引线30直接电连接。同理，多条控制信号线40和多条第一扇出引线50同层设置，控制信号线40与相应的第一扇出引线50直接电连接。
如图11所示，在另一些实施例中，控制信号线10的第一走线段41和多条第一扇出引线50与电源电压总线60材料相同且同层设置，第一扇出引线50从电源电压总线60的沿第一方向X相对两侧中的一侧绕行，并延伸至电源电压总线60远离显示区AA的一侧。
通过采用上述第一扇出引线50的布线方式，使第一扇出引线50与电源电压总线60之间绝缘设置，并且，使得第一扇出引线50和电源电压总线60沿第一方向X的排布紧凑，可提高对扇出区FA的面积的利用率，从而可减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
在一些实施例中，如图11和图12所示，第一走线段41、多条第一扇出引线50和电源电压总线60设置于第一栅导电层102，控制信号线40的第二走线段42、多条数据线DL和多条数据扇出引线30设置于源漏导电层103。
由于控制信号线40的第一走线段41设置于第一栅导电层102，第二走线段42设置于源漏导电层103，为实现第一走线段41与第二走线段42的电连接，在一些实施例中，如图12所示，显示面板100包括设置于第一栅导电层102和源漏导电层103之间的第一绝缘层104，第一绝缘层104中设有第一过孔H1，第一走线段41通过第一过孔H1与相应的第二走线段42电连接。
需要说明的是，第一绝缘层104中的过孔统称为第一过孔H1，结合图8可知，第一走线段41与相应的第二走线段42电连接的位置位于第三子周边区BB3，即第一绝缘层104在第三子周边区BB3的对应位置处开设有第一过孔H1。
在一些实施例中，如图1、图4和图8所示，绑定区BA包括沿第一方向X并列设置的第一子绑定区BA1和至少一个第二子绑定区BA2，多条数据扇出引线30汇集至第一子绑定区BA1，多条第一扇出引线50中的至少一条汇 集至第二子绑定区BA2。
示例性地，显示面板100在显示区AA内沿第一方向X的一侧边设置栅极驱动电路20，从单边驱动各栅线GL，即单边驱动。在此情况下，绑定区BA包括沿第一方向X并列设置的第一子绑定区BA1和第二子绑定区BA2，多条数据扇出引线30汇集至第一子绑定区BA1，多条第一扇出引线50中的至少一条汇集至第二子绑定区BA2。
本公开的上述实施例中，第一子绑定区BA1与第二子绑定区BA2并列设置，将多条数据扇出引线30汇集至第一子绑定区BA1，多条第一扇出引线50中的至少一条汇集至第二子绑定区BA2，第一扇出引线50汇集的区域位于多条数据扇出引线30汇集的区域沿第一方向X的一侧，使得第一扇出引线50和数据扇出引线30在扇出区FA的排布紧凑，可提高对扇出区FA的面积的利用率，从而可减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
在一些实施例中，显示面板100在显示区AA内沿第一方向X的两边分别设置栅极驱动电路20，通过两边的栅极驱动电路20驱动各栅线GL，即双边驱动。在此情况下，如图1、图4和图8所示，绑定区BA包括第一子绑定区BA1，及位于第一子绑定区BA1沿第一方向X相对两侧的两个第二子绑定区BA2，多条数据扇出引线30汇集至第一子绑定区BA1，多条第一扇出引线50分为两组，两组第一扇出引线50分别汇集至两个第二子绑定区BA2。
本公开的上述实施例中，两个第二子绑定区BA2分别位于第一子绑定区BA1沿第一方向X的相对两侧，多条数据扇出引线30汇集至第一子绑定区BA1，多条第一扇出引线50分为两组，一组第一扇出引线50汇集至一侧第二子绑定区BA2，另一组第一扇出引线50汇集至另一侧第二子绑定区BA2，即，两组第一扇出引线50汇集的区域，分别位于多条数据扇出引线30汇集的区域沿第一方向X的相对两侧，使得第一扇出引线50和数据扇出引线30在扇出区FA的排布紧凑，可提高对扇出区FA的面积的利用率，从而可减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
在一些实施例中，如图1、图4和图8所示，显示面板100还包括设置于扇出区FA的电源电压线80，电源电压线80的整体沿第一方向X延伸，电源电压线80包括沿第一方向X延伸的主线段，以及与主线段电连接的延伸至第一绑定区BA1的支线段。电源电压线80被配置为传输第二电源电压信号。
在一些实施例中，如图2、图5和图9所示，显示面板100还包括多个引脚90，多个引脚90被配置为绑定柔性印刷电路板。多个引脚90包括位于第 一子绑定区BA1的多个第一引脚91，及位于第二子绑定区BA2的多个第二引脚92。
其中，每条数据扇出引线30与至少一个第一引脚91电连接，每条第一扇出引线50与至少一个第二引脚92电连接。
示例性地，如图2、图5和图9所示，每条数据扇出引线30与一个第一引脚91电连接。每条第一扇出引线50与一个第二引脚92电连接。
示例性地，每条数据扇出引线30与两个第一引脚91电连接。每条第一扇出引线50与两个第二引脚92电连接。
本公开一些实施例还提供了一种显示装置，如图11所示，显示装置200包括上述任一实施例中的显示面板100。
本公开的上述实施例，显示装置200的显示面板100采用GIA的驱动方式，将栅极驱动电路20直接集成在显示区AA，可节省栅极驱动电路20所占用的显示面板100的周边区的面积，从而可减小周边区的宽度，有利于该显示装置200的窄边框化。
并且，显示面板100中的第一扇出引线50和数据扇出引线30在扇出区FA的排布紧凑，可提高对扇出区FA的面积的利用率，从而可减小扇出区FA的宽度，有利于应用该显示面板100的显示装置的窄边框化。
显示装置200可以为电致发光显示装置，该电致发光显示装置可以为OLED显示装置。
上述显示装置200可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示面板，包括显示区，位于所述显示区一侧的扇出区，及位于所述扇出区远离所述显示区一侧的绑定区；
    所述显示面板包括：
    多条数据线，从所述显示区延伸至所述扇出区；
    多条数据扇出引线，设置于所述扇出区；每条数据线与一条数据扇出引线电连接；所述多条数据扇出引线汇集至所述绑定区；
    栅极驱动电路，设置于所述显示区；
    多条控制信号线，与所述栅极驱动电路电连接，被配置为向所述栅极驱动电路传输控制信号；所述多条控制信号线从所述显示区延伸至所述扇出区；
    多条第一扇出引线，设置于所述扇出区；每条控制信号线与一条第一扇出引线电连接；所述多条第一扇出引线汇集至所述绑定区。
  2. 根据权利要求1所述的显示面板，其中，所述第一扇出引线与所述控制信号线的延伸至所述扇出区的一端电连接。
  3. 根据权利要求2所述的显示面板，还包括：
    电源电压总线，设置于所述扇出区，且沿所述第一方向延伸；
    其中，所述第一扇出引线与所述电源电压总线材料相同且同层设置，所述第一扇出引线从所述电源电压总线的沿所述第一方向相对两侧中的一侧绕行，并延伸至所述电源电压总线远离所述显示区的一侧。
  4. 根据权利要求3所述的显示面板，还包括：
    多条第一连接线，设置于所述电源电压总线与所述显示区之间，且沿所述第一方向延伸；所述控制信号线通过第一连接线与相应的第一扇出引线电连接。
  5. 根据权利要求4所述的显示面板，包括：
    第一栅导电层，所述多条第一扇出引线、所述多条第一连接线和所述电源电压总线设置于所述第一栅导电层；
    源漏导电层，设置于所述第一栅导电层远离所述显示面板的衬底的一侧，所述多条控制信号线、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层。
  6. 根据权利要求5所述的显示面板，还包括：
    第一绝缘层，设置于所述第一栅导电层和所述源漏导电层之间；所述第一绝缘层中设有第一过孔；
    其中，所述第一连接线通过所述第一过孔与相应的控制信号线电连接。
  7. 根据权利要求5或6所述的显示面板，其中，所述多条第一扇出引线 在所述衬底上的正投影，与所述多条数据扇出引线在所述衬底上的正投影错开设置。
  8. 根据权利要求2所述的显示面板，还包括：
    电源电压总线，设置于所述扇出区，且沿所述第一方向延伸；
    其中，所述第一扇出引线的至少部分与所述电源电压总线及所述数据扇出引线异层设置；
    所述第一扇出引线在所述显示面板的衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠，且与至少一条数据扇出引线在所述衬底上的正投影部分重叠。
  9. 根据权利要求8所述的显示面板，其中，所述第一扇出引线包括电连接的第一引线段和第二引线段；
    所述第一引线段远离所述第二引线段的一端与所述控制信号线电连接；
    所述第二引线段远离所述第一引线段的一端延伸至所述绑定区。
  10. 根据权利要求9所述的显示面板，其中，至少一条第一引线段包括电连接的第一子引线段和第二子引线段；
    所述第一子引线段沿所述第一方向延伸；
    所述第二子引线段沿第二方向延伸；所述第二方向与所述第一方向大致垂直。
  11. 根据权利要求9或10所述的显示面板，包括：
    第一栅导电层，所述电源电压总线设置于所述第一栅导电层；
    源漏导电层，设置于所述第一栅导电层远离所述衬底的一侧，所述多条控制信号线、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层；
    第一电极层，设置于所述源漏导电层远离所述衬底的一侧；
    其中，所述第一引线段设置于所述第一电极层，所述第二引线段设置于所述源漏导电层或所述第一栅导电层；
    所述第一引线段在所述衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠，且与至少一条数据扇出引线在所述衬底上的正投影部分重叠；
    所述第二引线段在所述衬底上的正投影，与所述多条数据扇出引线在所述衬底上的正投影错开设置。
  12. 根据权利要求11所述的显示面板，还包括：
    第二绝缘层，设置于所述源漏导电层与所述第一电极层之间；所述第二 绝缘层中设置有第二过孔和第三过孔；
    其中，所述第一引线段远离所述第二引线段的一端，通过所述第二过孔与相应的所述控制信号线电连接；
    所述第一引线段靠近所述第二引线段的一端，通过所述第三过孔与所述第二引线段电连接；或者，所述显示面板还包括设置于所述第一栅导电层和所述源漏导电层之间的第一绝缘层，所述第一绝缘层中设有第一过孔，所述第一过孔与所述第三过孔相连通，所述第一引线段靠近所述第二引线段的一端，通过所述第三过孔和所述第一过孔与所述第二引线段电连接。
  13. 根据权利要求1所述的显示面板，还包括围绕所述显示区的周边区，所述周边区包括第一子周边区、第二子周边区、第三子周边区和第四子周边区；所述第一子周边区和所述第二子周边区分别位于所述显示区沿第一方向的相对两侧，所述第三子周边区和所述第四子周边区分别位于所述显示区沿第二方向的相对两侧，所述第一方向与所述第二方向大致垂直；所述扇出区和所述绑定区位于所述第四子周边区；
    所述控制信号线包括电连接的第一走线段和第二走线段；
    多条第一走线段中的一部分第一走线段从所述第三子周边区，沿所述第一子周边区，延伸至所述扇出区；另一部分第一走线段从所述第三子周边区，沿所述第二子周边区，延伸至所述扇出区；
    多条第二走线段从所述显示区延伸至所述第三子周边区；
    所述第一走线段的一端与所述第二走线段的延伸至所述第三子周边区的一端电连接，所述第一走线段的另一端与相应的第一扇出引线电连接。
  14. 根据权利要求13所述的显示面板，其中，所述多条第一扇出引线、所述多条控制信号线和所述多条数据扇出引线材料相同且同层设置；
    所述多条第一扇出引线设置于所述多条数据扇出引线的沿所述第一方向的相对两侧。
  15. 根据权利要求14所述的显示面板，还包括：
    电源电压总线，设置于所述扇出区，且沿所述第一方向延伸；
    其中，所述第一扇出引线与所述电源电压总线异层设置；
    所述第一扇出引线在所述显示面板的衬底上的正投影，与所述电源电压总线在所述衬底上的正投影部分重叠。
  16. 根据权利要求15所述的显示面板，包括：
    第一栅导电层，所述电源电压总线设置于所述第一栅导电层；
    源漏导电层，设置于所述第一栅导电层远离所述显示面板的衬底的一侧， 所述多条控制信号线、所述多条数据线、所述多条数据扇出引线和所述多条第一扇出引线设置于所述源漏导电层。
  17. 根据权利要求13所述的显示面板，还包括：
    电源电压总线，设置于所述扇出区，且沿所述第一方向延伸；
    其中，所述控制信号线的第一走线段和所述多条第一扇出引线与所述电源电压总线材料相同且同层设置，所述第一扇出引线从所述电源电压总线的沿所述第一方向相对两侧中的一侧绕行，并延伸至所述电源电压总线远离所述显示区的一侧。
  18. 根据权利要求17所述的显示面板，包括：
    第一栅导电层，所述第一走线段、所述多条第一扇出引线和所述电源电压总线设置于所述第一栅导电层；
    源漏导电层，设置于所述第一栅导电层远离所述显示面板的衬底的一侧，所述控制信号线的第二走线段、所述多条数据线和所述多条数据扇出引线设置于所述源漏导电层。
  19. 根据权利要求1～18中任一项所述的显示面板，其中，所述绑定区包括第一子绑定区，及位于所述第一子绑定区沿第一方向相对两侧的两个第二子绑定区；
    所述多条数据扇出引线汇集至所述第一子绑定区；
    所述多条第一扇出引线分为两组，两组第一扇出引线分别汇集至两个第二子绑定区。
  20. 根据权利要求19所述的显示面板，还包括：
    多个引脚，被配置为绑定柔性印刷电路板；所述多个引脚包括位于所述第一子绑定区的多个第一引脚，及位于所述第二子绑定区的多个第二引脚；
    其中，所述数据扇出引线与至少一个第一引脚电连接；所述第一扇出引线与至少一个第二引脚电连接。
  21. 一种显示装置，包括如权利要求1～20中任一项所述的显示面板。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025690A1 (en) * 2008-07-29 2010-02-04 Samsung Electronics Co., Ltd. Thin film transistor substrate and method of manufacturing the same
CN107085333A (zh) * 2017-07-06 2017-08-22 上海天马微电子有限公司 一种阵列基板及显示面板
CN107331294A (zh) * 2017-06-30 2017-11-07 厦门天马微电子有限公司 显示面板及显示装置
CN107393415A (zh) * 2017-08-08 2017-11-24 惠科股份有限公司 一种显示面板和显示装置
CN108598142A (zh) * 2018-06-28 2018-09-28 上海天马微电子有限公司 柔性显示基板、柔性显示面板和柔性显示装置
CN110579917A (zh) * 2019-10-15 2019-12-17 上海中航光电子有限公司 显示模组及显示装置
CN210223509U (zh) * 2019-06-11 2020-03-31 重庆惠科金渝光电科技有限公司 一种显示面板和显示装置
CN111916488A (zh) * 2020-09-11 2020-11-10 京东方科技集团股份有限公司 一种显示基板、显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025690A1 (en) * 2008-07-29 2010-02-04 Samsung Electronics Co., Ltd. Thin film transistor substrate and method of manufacturing the same
CN107331294A (zh) * 2017-06-30 2017-11-07 厦门天马微电子有限公司 显示面板及显示装置
CN107085333A (zh) * 2017-07-06 2017-08-22 上海天马微电子有限公司 一种阵列基板及显示面板
CN107393415A (zh) * 2017-08-08 2017-11-24 惠科股份有限公司 一种显示面板和显示装置
CN108598142A (zh) * 2018-06-28 2018-09-28 上海天马微电子有限公司 柔性显示基板、柔性显示面板和柔性显示装置
CN210223509U (zh) * 2019-06-11 2020-03-31 重庆惠科金渝光电科技有限公司 一种显示面板和显示装置
CN110579917A (zh) * 2019-10-15 2019-12-17 上海中航光电子有限公司 显示模组及显示装置
CN111916488A (zh) * 2020-09-11 2020-11-10 京东方科技集团股份有限公司 一种显示基板、显示装置

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