WO2021244228A1 - 显示面板、显示装置及显示面板的制作方法 - Google Patents

显示面板、显示装置及显示面板的制作方法 Download PDF

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Publication number
WO2021244228A1
WO2021244228A1 PCT/CN2021/092722 CN2021092722W WO2021244228A1 WO 2021244228 A1 WO2021244228 A1 WO 2021244228A1 CN 2021092722 W CN2021092722 W CN 2021092722W WO 2021244228 A1 WO2021244228 A1 WO 2021244228A1
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WIPO (PCT)
Prior art keywords
sub
wiring
insulating layer
display panel
metal layer
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Application number
PCT/CN2021/092722
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English (en)
French (fr)
Inventor
王彬艳
黄炜赟
张跳梅
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/921,607 priority Critical patent/US20230165081A1/en
Publication of WO2021244228A1 publication Critical patent/WO2021244228A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display panel, a display device, and a manufacturing method of the display panel.
  • an embodiment of the present disclosure provides a display panel, including a base substrate, on which a first metal layer, a second metal layer, and a third metal layer are sequentially stacked on the base substrate;
  • the display panel also includes wiring;
  • the wiring includes a first wiring extending along a first direction, and the first wiring includes a first sub-wiring portion, a second sub-wiring portion, a first auxiliary portion, and a second auxiliary portion;
  • the wiring further includes a second wiring extending in a second direction, and the second wiring includes a third sub-wiring portion and a third auxiliary portion;
  • the first direction is different from the second direction
  • first sub-wiring portion and the second sub-wiring portion are located on the third metal layer, the first auxiliary portion is located on the first metal layer, and the second auxiliary portion is located on the A second metal layer, the third sub-wiring portion is located on the first metal layer, and the third auxiliary portion is located on the third metal layer;
  • the base substrate of the display panel further includes a digging area and a non-dugging area, and the non-dugging area includes a winding area;
  • the first auxiliary part, the second auxiliary part and the third auxiliary part include a winding structure arranged in the winding area.
  • the orthographic projections of the first auxiliary portion and the second auxiliary portion on the base substrate are alternately arranged.
  • first sub-wiring portion and the first auxiliary portion are electrically connected through a first via hole, and the second sub-wiring portion and the second auxiliary portion are electrically connected through a second Via electrical connection;
  • the third sub-wiring portion and the third auxiliary portion are electrically connected through a third via hole.
  • the second wiring further includes a fourth sub-wiring portion, and the fourth sub-wiring portion is located on the first metal layer.
  • the display panel further includes a fourth metal layer, and the fourth metal layer is disposed on a side of the third metal layer away from the base substrate.
  • the second wiring further includes a fourth auxiliary part located in the fourth metal layer; the fourth auxiliary part includes a fourth auxiliary part disposed in the winding area Winding structure.
  • orthographic projections of the third auxiliary portion and the fourth auxiliary portion on the base substrate are alternately arranged.
  • the method further includes: a first bridge portion located on the third metal layer, and the first bridge portion and the fourth sub-wiring portion are electrically connected through a fifth via.
  • the first bridge portion and the fourth auxiliary portion are electrically connected through a fourth via.
  • orthographic projections of the fourth via and the fifth via on the base substrate do not overlap.
  • the third sub-wiring portion, the fourth sub-wiring portion and the first auxiliary portion located on the first metal layer are insulated from each other;
  • the first sub-wiring portion, the second sub-wiring portion, the first bridge portion, and the third auxiliary portion located on the third metal layer are insulated from each other;
  • the first auxiliary part, the second auxiliary part, the third auxiliary part, and the fourth auxiliary part are insulated from each other.
  • the display panel further includes: a first insulating layer disposed between the first metal layer and the base substrate, and disposed between the first metal layer and the first insulating layer.
  • the second insulating layer between the two metal layers, the third insulating layer disposed between the second metal layer and the third metal layer, and the third insulating layer disposed on the side of the third metal layer away from the base substrate.
  • the fourth insulating layer is disposed on the fifth insulating layer on the side of the fourth insulating layer away from the base substrate.
  • the display panel further includes pixel units arranged in an array, and the pixel units include a driving circuit and a storage capacitor;
  • the driving circuit includes a thin film transistor, the thin film transistor includes an active layer disposed on the base substrate; a first gate insulating layer disposed on the side of the active layer away from the base substrate, so The first insulating layer includes the first gate insulating layer; a first gate disposed on a side of the first gate insulating layer away from the base substrate, and the first metal layer includes a first gate Provided on the interlayer insulating layer on the side of the first gate away from the base substrate, the third insulating layer includes the interlayer insulating layer; provided on the interlayer insulating layer away from the substrate The source and drain electrode layer on one side of the substrate, the third metal layer includes the source and drain electrode layer; a passivation layer disposed on the side of the source and drain electrode layer away from the base substrate; the fourth insulating layer Including the passivation layer; and a flat layer disposed on the side of the passivation layer away from the base substrate, and the fifth insulating layer includes the flat layer.
  • the first via is a via that penetrates at least the third insulating layer to electrically connect the first sub-wiring portion and the first auxiliary portion.
  • the second via is a via that penetrates at least the third insulating layer to electrically connect the second sub-wiring portion and the second auxiliary portion.
  • the third via is a via that penetrates at least the third insulating layer to electrically connect the third sub-wiring portion and the third auxiliary portion.
  • the fourth via is a via that penetrates at least the fourth insulating layer and the fifth insulating layer, so that the first bridge portion and the fourth auxiliary portion are electrically connected.
  • the fifth via is a via that penetrates at least the third insulating layer to electrically connect the fourth sub-wiring portion and the first bridge portion.
  • the first sub-wiring portion and the second sub-wiring portion are respectively electrically connected to the source or drain of the thin film transistor of different pixel units, and are configured to transmit data Signal.
  • the third sub-wiring portion is electrically connected to the first gate of the thin film transistor, and is configured to transmit a first gate signal.
  • the fourth sub-wiring part is configured to transmit a light-emitting control signal.
  • the first bridge portion electrically connected to the fourth sub-wiring portion configured to transmit the light-emitting control signal of the n+1th row and the fourth sub-wiring portion configured to transmit the light-emitting control signal of the nth row
  • the sub-wiring portions are electrically connected through the second bridge portion, where n is an integer greater than or equal to 1.
  • the second bridge portion is located in the third metal layer, the second bridge portion has a sixth via hole, and the sixth via hole is a via hole that penetrates at least the third insulating layer , Making the fourth sub-wiring part configured to transmit the light-emitting control signal of the nth row electrically connected to the second bridge part.
  • the fourth sub-wiring portion configured to transmit the light-emitting control signal of the nth row is electrically connected to the second bridge portion through the sixth via, and the and is configured to transmit the nth row of light-emitting control signals.
  • the first bridge portion and the second bridge portion that are electrically connected to the fourth sub-wiring portion of the +1 row light-emitting control signal are electrically connected to the fourth auxiliary portion through a fourth via hole, and the sixth via hole is electrically connected to the fourth auxiliary portion.
  • the orthographic projection of the fourth via on the base substrate does not overlap.
  • the projections of the fourth sub-wiring portion and the winding area on the base substrate do not overlap, and the fourth sub-wiring portion is configured to transmit light-emitting control signals in the same row.
  • the routing part is disconnected in the winding area.
  • the second wiring further includes a fifth sub-wiring part.
  • the fifth sub-wiring part is configured to transmit a reset signal.
  • the fifth sub-wiring portion configured to transmit the reset signal in the m+1th row and the third sub-wiring portion configured to transmit the first gate signal in the m-th row pass through the The three bridges are electrically connected, where m is an integer greater than or equal to 1.
  • the third bridge portion is located on the third metal layer, the third bridge portion has a seventh via hole and an eighth via hole, and the seventh via hole penetrates at least The via hole of the third insulating layer electrically connects the third sub-wiring portion configured to transmit the first gate signal of the m-th row to the third bridge portion; the eighth via hole penetrates at least the first gate signal The via hole of the three insulating layers electrically connects the fifth sub-wiring portion configured to transmit the reset signal of the m+1th row and the third bridge portion.
  • the third bridge portion is electrically connected to the third auxiliary portion through the seventh via hole or the eighth via hole.
  • the seventh via hole and the eighth via hole are multi-via parallel structures.
  • the storage capacitor includes a first electrode plate and a second electrode plate, wherein the first electrode plate is located on the first metal layer, and the second electrode plate is located on the second electrode plate.
  • a metal layer, a second gate insulating layer is arranged between the first electrode plate and the second electrode plate, and the second insulating layer includes the second gate insulating layer.
  • the shape of the digging area includes a circle, an ellipse, a triangle, a quadrilateral, or an irregular shape.
  • an embodiment of the present disclosure provides a display device, including the display panel provided in any of the foregoing embodiments.
  • a sensor is further included, and the sensor is disposed under the digging area.
  • the senor includes a camera, an infrared sensor, a fingerprint detection unit, and a pressure sensing unit.
  • embodiments of the present disclosure provide a method for manufacturing a display panel, including:
  • a base substrate is provided, and a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer, and a second insulating layer are sequentially fabricated on the base substrate.
  • the base substrate includes a digging area and a non-dugging area, a first trace extending in a first direction is made in the non-dugging area, and the first trace includes a first sub-wiring portion, a second The sub-wiring part, the first auxiliary part and the second auxiliary part; a second wiring extending in the second direction is made in the non-drilling area, and the second wiring includes a third sub-wiring part and a third sub-wiring part. Auxiliary part; the first direction is different from the second direction;
  • the third sub-wiring part and the first auxiliary part are made in the first metal layer
  • the second auxiliary part is made in the second metal layer
  • the third metal layer is made in the third metal layer.
  • the non-digging area includes a winding area, and at least a part of the first auxiliary part, the second auxiliary part and the third auxiliary part are made in the winding area.
  • the method further includes:
  • An active layer, a first gate insulating layer, a first gate, an interlayer insulating layer, a source and drain electrode layer, a passivation layer, and a flat layer are sequentially fabricated on the base substrate;
  • the first gate insulating layer Is a part of the first insulating layer, the first gate is a part of the first metal layer, the interlayer insulating layer is a part of the third insulating layer, and the source and drain electrode layers are the A part of the third metal layer, the passivation layer is a part of the fourth insulating layer, and the flat layer is a part of the fifth insulating layer;
  • the manufacturing method of the display panel further includes: making a first via hole penetrating at least the third insulating layer to electrically connect the first sub-wiring part and the first auxiliary part;
  • a third via hole penetrating at least the third insulating layer is made to electrically connect the third sub-wiring part and the third auxiliary part.
  • the method further includes:
  • Making a second trace extending in the second direction in the non-drilling area further includes: fabricating a fourth sub-wiring portion extending in the second direction;
  • n is an integer greater than or equal to 1.
  • the method further includes: making a second trace extending in the second direction in the non-drilling area, including fabricating a fifth sub-wiring portion extending in the second direction;
  • the third bridge portion is electrically connected to the third auxiliary portion through the seventh via hole or the eighth via hole;
  • n is an integer greater than or equal to 1.
  • Figure 1 is a schematic diagram of a display panel
  • FIG. 2 is a schematic diagram of a cross-sectional film layer of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a partially enlarged schematic top view of a winding area of a display panel provided by an embodiment of the disclosure
  • Fig. 4a is a partial enlarged schematic plan view of AA in Fig. 3;
  • Figure 4b is a schematic cross-sectional view at line EE' in Figure 4a;
  • Fig. 5a is a partial enlarged schematic plan view of BB in Fig. 3;
  • Fig. 5b is a schematic cross-sectional view at line FF' in Fig. 5a;
  • Fig. 6a is a partial enlarged schematic plan view of CC in Fig. 3;
  • Fig. 6b is a schematic cross-sectional view at line GG' in Fig. 6a;
  • Fig. 7a is a partial enlarged schematic plan view of DD in Fig. 3;
  • Figure 7b is a schematic cross-sectional view at line JJ' in Figure 7a;
  • Fig. 7c is a schematic cross-sectional view at line KK' in Fig. 7a;
  • FIG. 8 is a partially enlarged schematic top view of a winding area of another display panel provided by an embodiment of the disclosure.
  • 9a is a partially enlarged schematic top view of a fourth sub-wiring portion of another display panel provided by an embodiment of the disclosure, electrically connected to a fourth auxiliary portion through a first bridge portion, a second bridge portion, and a layer change;
  • Fig. 9b is a schematic cross-sectional view at line LL' in Fig. 9a;
  • FIG. 10 is a partially enlarged schematic top view of a third sub-wiring portion and a fifth sub-wiring portion of another display panel provided by an embodiment of the present disclosure that are electrically connected through a third bridge portion and changed layers;
  • FIG. 11 is a schematic diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a manufacturing method of a display panel provided by an embodiment of the disclosure.
  • an element or layer when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on the other element or layer. It is directly connected to the other element or layer, or an intermediate element or layer may be present.
  • an element or layer When an element or layer is referred to as being “disposed on” another element or layer "on one side", the element or layer can be directly on one side of the other element or layer, directly connected to the other element or Layers, or intermediate elements or intermediate layers may be present.
  • an element or layer when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • the hole-cutting screen is more and more used.
  • the display panel 1 is provided with a hole-cutting area HA and a winding area WA surrounding the hole-cutting area.
  • the wiring in the winding area WA is relatively dense, and there is no pixel unit, so the winding area WA cannot realize the display function, and a black border that cannot be displayed is formed around the hole-cutting area HA.
  • the display panel is also provided with a plurality of data lines DL extending in a first direction, a plurality of power supply lines VL, a plurality of gate lines GL extending in a second direction, a plurality of reset signal lines RL, and a plurality of light emitting control signal lines.
  • Traces such as EL (only one trace is shown in the figure)
  • the distance between multiple traces is very close, and it is easy to interfere with each other. If you want to ensure that there is enough distance between the traces , It will make the frame of the digging area HA larger, that is, the BD in the figure becomes larger, which is not conducive to increasing the screen-to-body ratio of the display screen.
  • the display panel includes a base substrate 100 on the base substrate.
  • a first metal layer 001, a second metal layer 002, and a third metal layer 003 are provided.
  • the second metal layer 002 is provided on the side of the first metal layer 001 away from the base substrate 100, and the third metal layer 003 is provided on the second metal layer.
  • the metal layer 002 is away from the side of the base substrate 100.
  • FIG. 3 is a partial enlarged top view of the winding area of the display panel provided by an embodiment of the present disclosure.
  • the display panel includes wiring, the wiring includes a first wiring extending in a first direction, and the first wiring includes a first sub-wiring portion 011, a first auxiliary portion 012, and a second sub-wiring portion Part 021, the second auxiliary part 022; the wiring also includes a second wiring extending in the second direction, the second wiring includes a third sub-wiring part 031, a third auxiliary part 032; the first direction is different from the second direction.
  • the first sub-wiring portion 011 and the second sub-wiring portion 021 are located on the third metal layer 003
  • the first auxiliary portion 012 is located on the first metal layer 001
  • the second auxiliary portion 022 is located on the second metal layer 002
  • the third The sub-wiring portion 031 is located on the first metal layer 001
  • the third auxiliary portion 032 is located on the third metal layer 003.
  • the first auxiliary part 012 includes a first winding structure 0121 arranged in the winding area WA, and also includes a first connecting structure 0122 located between the first winding structure 0121 and the first sub-wiring part 011, and the second auxiliary
  • the part 022 includes a second winding structure 0221 arranged in the winding area WA, and a second connecting structure 0222 located between the second winding structure 0221 and the second sub-wiring part 021.
  • the third auxiliary part 032 includes The third winding structure 0321 arranged in the winding area WA also includes a third connecting structure 0322 located between the third winding structure 0321 and the third sub-wiring portion 031.
  • the trace width shown in the figures of the present disclosure is only for a clearer indication and distinguishing different traces, and does not represent the actual trace width, nor does it constitute a limitation of the present disclosure.
  • the sizes and proportions of the digging area, the winding area, the display panel and the like in the figure are also merely illustrative, and do not constitute a limitation of the present disclosure.
  • the projections of the first auxiliary part and the second auxiliary part on the base substrate are alternately arranged. As shown in FIG. 3, the orthographic projections of the first auxiliary part 012 and the second auxiliary part 022 on the base substrate are alternately arranged.
  • the third sub-wiring part 031 located in the first metal layer is routed and transmitted in the winding area by being layered to the third auxiliary part 032 located in the third metal layer, and is located in the third metal layer.
  • the first sub-wiring portion 011 of the layer is changed to the first auxiliary portion 012 located in the first metal layer to be routed and transmitted in the winding area, and the second sub-wiring portion 021 located in the third metal layer is changed by being changed.
  • Layer to the second auxiliary part 022 located in the second metal layer is routed and transmitted in the winding area.
  • the first auxiliary part 012 and the second auxiliary part 022 The projections on the base substrate are arranged alternately, so that the adjacent winding structures in the winding area are distributed on different metal layers, which reduces the signal interference between adjacent wires and reduces the distance between adjacent wires. , Making it possible to reduce the border of the digging area without reducing the number of wires.
  • the third sub-wiring part 031 originally located in the first metal layer is changed to the third connection structure 0322 located in the third metal layer, and then connected to the third winding structure 0321.
  • Wire transmission in the winding area The first sub-wiring part 011 originally located in the third metal layer is changed to the first connection structure 0122 located in the first metal layer and then connected to the first winding structure 0121 in the winding area.
  • the second sub-wiring part 021 located in the third metal layer is changed to the second connection structure 0222 located in the second metal layer and then connected to the second winding structure 0221.
  • the winding structure 0121 and the second winding structure 0221 are arranged alternately on the projection of the base substrate.
  • the adjacent winding structures in the winding area are distributed on different metal layers, which reduces the signal interference between adjacent wirings. Reduce the distance between adjacent traces, so that the border of the digging area can be reduced without reducing the number of traces.
  • the first sub-wiring portion and the first auxiliary portion are electrically connected through a first via
  • the second sub-wiring portion and the second auxiliary portion are electrically connected through a second via
  • the third sub-wiring portion is electrically connected with the second via hole.
  • the wire part and the third auxiliary part are electrically connected through a third via hole.
  • FIG. 4a is a partial enlarged top view of AA
  • FIG. 4b is FIG. 4a.
  • the first sub-wiring portion 011 of the third metal layer 003 and the first connection structure 0122 of the first auxiliary portion 012 of the first metal layer 001 pass through
  • the first via H1 is electrically connected, so that the first sub-wiring part and the first auxiliary part are electrically connected.
  • the first via H1 can be a multi-via parallel structure, and this design can be better The metal of different layers is connected to each other. When one of the vias is defective, the other vias can still ensure the connection effect, but it is not limited to this. A single via can also achieve the purpose of electrical connection.
  • FIG. 5a is a partial enlarged top view of BB
  • FIG. 5b is FIG. 5a.
  • the cross-sectional view at the middle FF', combined with FIGS. 5a and 5b, the second sub-wiring portion 021 located in the third metal layer 003 and the first connection structure 0222 of the second auxiliary portion 022 located in the second metal layer 002 pass The second via hole H2 is electrically connected, so that the second sub-wiring portion and the second auxiliary portion are electrically connected.
  • FIG. 5a is a partial enlarged top view of BB
  • FIG. 5b is FIG. 5a.
  • the cross-sectional view at the middle FF', combined with FIGS. 5a and 5b, the second sub-wiring portion 021 located in the third metal layer 003 and the first connection structure 0222 of the second auxiliary portion 022 located in the second metal layer 002 pass The second via hole H2 is electrically connected, so that the second sub-wiring portion and the second auxiliary portion are electrically
  • the second via hole H2 can be a multi-via parallel structure, and this design can be better
  • the metal of different layers is connected to each other.
  • the other vias can still ensure the connection effect, but it is not limited to this.
  • a single via can also achieve the purpose of electrical connection.
  • FIG. 6a is a partial enlarged top view of CC
  • FIG. 6b is FIG. 6a
  • the cross-sectional view at the middle GG', combined with FIGS. 6a and 6b, the third sub-wiring portion 031 located in the first metal layer 001 and the third connecting structure 0322 located in the third auxiliary portion 032 of the third metal layer 003 pass The third via H3 is electrically connected, so that the third sub-wiring part and the third auxiliary part are electrically connected.
  • FIG. 6a is a partial enlarged top view of CC
  • FIG. 6b is FIG. 6a
  • the cross-sectional view at the middle GG', combined with FIGS. 6a and 6b, the third sub-wiring portion 031 located in the first metal layer 001 and the third connecting structure 0322 located in the third auxiliary portion 032 of the third metal layer 003 pass The third via H3 is electrically connected, so that the third sub-wiring part and the third auxiliary part are electrically connected.
  • the third via H3 can be a multi-via parallel structure, and this design can be better The metal of different layers is connected to each other. When one of the vias is defective, the other vias can still ensure the connection effect, but it is not limited to this. A single via can also achieve the purpose of electrical connection.
  • the second wiring may further include a fourth sub wiring portion 041, and the fourth sub wiring portion 041 is located on the first metal layer 001.
  • the display panel may further include a fourth metal layer 004, and the fourth metal layer 004 is disposed on a side of the third metal layer 003 away from the base substrate 100.
  • the second trace may further include a fourth auxiliary portion 042, and the fourth auxiliary portion 042 is located on the fourth metal layer 004.
  • the fourth auxiliary portion 042 includes a fourth winding structure 0421 disposed in the winding area WA, and also includes a fourth connecting structure 0422 located between the fourth winding structure 0421 and the fourth sub-wiring portion 041.
  • the orthographic projections of the third auxiliary part 032 and the fourth auxiliary part 042 on the base substrate are alternately arranged.
  • the third winding structure 0321 and the fourth winding structure are arranged alternately.
  • the orthographic projections of the structure 0421 on the base substrate are alternately arranged.
  • the display panel further includes a first bridge portion, the first bridge portion is located in the third metal layer, the first bridge portion is provided with a fifth via, and the fifth via makes the fourth sub-wiring portion It is electrically connected to the first bridge portion.
  • the first bridge portion and the fourth auxiliary portion are electrically connected through the fourth via hole.
  • FIG. 7a is A partial enlarged top view at DD in FIG. 3
  • FIG. 7b is a cross-sectional view at JJ' in FIG. 7a
  • FIG. 7c is a cross-sectional view at KK' in FIG. 7a.
  • the fourth sub-wiring portion 041 located on the first metal layer 001 is electrically connected to the first bridge portion BR1 located on the third metal layer 003 through the fifth via H5, and the first bridge portion BR1 passes through the
  • the four via holes H4 are electrically connected to the fourth connection structure 0422 located on the fourth metal layer 004, so that the fourth sub-wiring part and the fourth auxiliary part are electrically connected.
  • the fourth via H4 and the fifth via H5 can be a multi-via parallel structure. This design can better connect different layers of metal to each other. When one of the vias is defective, the other The via hole can still ensure the connection effect, but it is not limited to this. A single via hole can also achieve the purpose of electrical connection.
  • the orthographic projections of the fourth via H4 and the fifth via H5 on the base substrate do not overlap.
  • the third sub-wiring portion 031, the fourth sub-wiring portion 041, and the first auxiliary portion 012 are all located on the first metal layer 001, and one of the three The first sub-wiring portion 011, the second sub-wiring portion 021, the first bridge portion BR1, and the third auxiliary portion 032 are all located on the third metal layer 003, and the four are insulated from each other; the first auxiliary The part 012, the second auxiliary part 022, the third auxiliary part 032, and the fourth auxiliary part 042 are insulated from each other.
  • the first insulating layer 110 is further provided on the side of the first metal layer 001 facing the base substrate 100, and the side of the first metal layer 001 away from the base substrate is provided with
  • the second insulating layer 120 is provided with a second metal layer 002 on the side of the second insulating layer 120 away from the base substrate 100, and the third insulating layer 130 is provided on the side of the second metal layer 002 away from the base substrate 100, and the third insulating layer
  • the third metal layer 003 is provided on the side of 130 away from the base substrate 100, the fourth insulating layer 140 is provided on the side of the third metal layer 003 away from the base substrate 100, and the fourth insulating layer 140 is provided on the side away from the base substrate 100
  • the fifth insulating layer 150 is provided on the side of the first metal layer 001 facing the base substrate 100, and the side of the first metal layer 001 away from the base substrate is provided with
  • the second insulating layer 120 is provided with a second metal layer 002 on the side
  • the display panel further includes pixel units P arranged in an array.
  • the pixel units P include a driving circuit and a storage capacitor 300; the driving circuit includes a thin film transistor TFT, and a thin film transistor TFT.
  • the first gate 0011 of the first gate 0011 is disposed on the interlayer insulating layer 1301 on the side of the first gate 0011 away from the base substrate, and the source and drain electrode layer 0031 disposed on the side of the interlayer insulating layer 1301 away from the base substrate.
  • the drain electrode layer 0031 is far from the passivation layer 1401 of the base substrate and the flat layer 1501 is disposed on the side of the passivation layer 1401 far away from the base substrate;
  • the first insulating layer 110 includes a first gate insulating layer 111, a first metal
  • the layer 001 includes a first gate 0011;
  • the third insulating layer 130 includes an interlayer insulating layer 1301;
  • the third metal layer 003 includes a source and drain electrode layer 0031;
  • the fourth insulating layer 140 includes a passivation layer 1401; and
  • the fifth insulating layer 150 includes Flat layer 1501.
  • the first via H1 is a through hole that penetrates at least the third insulating layer 130.
  • the second via hole H2 is a through hole that penetrates at least the third insulating layer 130 to make the second sub-wiring portion 021 and the second auxiliary portion 022 (second connection structure 0222) are electrically connected
  • the third via H3 is a through hole that penetrates at least the third insulating layer 130, so that the third sub-wiring portion 031 and the third auxiliary portion 032 (the first The three connection structure 0322) is electrically connected;
  • the fourth via hole H4 is a through hole that penetrates at least the fourth insulating layer 140 and the fifth insulating layer 150, so that the first bridge portion BR1 and the fourth auxiliary portion 042 (fourth connection structure 0422
  • the first sub-wiring portion 011 and the second sub-wiring portion 021 are respectively connected to the source or drain of the thin film transistors of different pixel units P1 and P2. Connected, configured to transmit data signals, the third sub-wiring portion 031 is electrically connected to the first gate 0011 of the thin film transistor, and configured to transmit the first gate signal, and the fourth sub-wiring portion is configured to transmit light emission control Signal.
  • the projections of the fourth sub-wiring portion and the winding area on the base substrate do not overlap, and the fourth sub-wiring portion configured to transmit the light-emitting control signal of the same row is in the winding area. disconnect.
  • the fourth sub-wiring part 041 configured to transmit the light-emitting control signal and the projection of the winding area WA on the base substrate do not overlap, and are configured to transmit the light-emitting control signal of the same row.
  • the fourth sub-wiring part is disconnected in the winding area.
  • the EM GOA Gate on array
  • the EM GOA on both sides of the display panel jointly provides the luminescence control signal EM to the display panel, so the fourth The disconnection of the sub-wiring part in the winding area will not affect the pixel unit in this row to receive the emission control signal EM.
  • Such a design can reduce the wiring inside the winding area WA, and can reduce the border BD of the digging area.
  • the first bridge portion BR1 is electrically connected to the fourth sub-wiring portion 041(n+1) configured to transmit the light-emitting control signal in the n+1th row. It is electrically connected to the fourth sub-wiring portion 041(n) configured to transmit the light-emitting control signal in the nth row through the second bridge portion BR2, where n is an integer greater than or equal to 1.
  • the second bridge portion BR2 is located on the third metal layer 003, the second bridge portion BR2 has a sixth via hole H6, the sixth via hole H6 is a via hole that penetrates at least the third insulating layer 130, FIG. 9b is LL' in FIG. 9a As shown in Fig.
  • the fourth sub-wiring part 041(n) configured to transmit the light-emitting control signal of the nth row is electrically connected to the second bridge part BR2 through the sixth via H6.
  • the sixth via H6 can be a multi-via parallel structure. This design can better connect different layers of metal to each other. When one of the vias is defective, the other vias can still ensure the connection effect , But not limited to this, a single via can also achieve the purpose of electrical connection.
  • the fourth sub-wiring portion 041(n) configured to transmit the light-emitting control signal in the nth row is electrically connected to the second bridge portion BR2 through the sixth via H6, and is configured to transmit the n+th
  • the first bridging portion BR1 and the second bridging portion BR2 electrically connected to the fourth sub-wiring portion 041 (n+1) of the light-emitting control signal in one row pass through the fourth via H4 and the fourth auxiliary portion 042 (fourth connection structure 0422) Electrically connected, the orthographic projections of the sixth via H6 and the fourth via H4 on the base substrate do not overlap.
  • This design enables the light-emitting control signals of two adjacent rows to be combined and transmitted in the winding area, thereby reducing the number of wires in the winding area and reducing the border BD of the hole-cutting area.
  • the second wiring further includes a fifth sub-wiring portion 051, the fifth sub-wiring portion 051 is configured to transmit the reset signal Rst, and is configured to transmit the mth sub-wiring portion.
  • the fifth sub-wiring portion 051 of the +1 row reset signal Rst and the third sub-wiring portion 031 configured to transmit the first gate signal of the m-th row are electrically connected by the third bridge portion BR3, where m is greater than or equal to An integer of 1.
  • the third bridge portion BR3 is located on the third metal layer 003, and the third bridge portion has a seventh via H7 and an eighth via H8.
  • the seventh via H7 is a via that penetrates at least the third insulating layer and is configured to
  • the third sub-wiring portion 031 that transmits the first gate signal of the mth row is electrically connected to the third bridge portion BR3;
  • the eighth via H8 is a via hole that penetrates at least the third insulating layer and is configured to transmit the m+th
  • the fifth sub-wiring portion 051 of one row of reset signals is electrically connected to the third bridge portion BR3.
  • the third bridge portion BR3 is electrically connected to the third auxiliary portion 032 (third connection structure 0322) through the seventh via H7 or the eighth via H8, and only the third bridge portion BR3 and the third connection structure 0322 are shown in the figure.
  • the seventh via H7 can also realize the electrical connection between the third bridge portion BR3 and the third connection structure 0322.
  • This design allows the traces configured to transmit the first gate signal of the mth row and the traces configured to transmit the reset signal of the m+1th row to be combined and transmitted in the winding area, thereby reducing the wiring area The number of traces in, can reduce the border BD of the digging area.
  • the seventh via H7 and the eighth via H8 can be a multi-via parallel structure. This design can better connect different layers of metal to each other. When one via is defective, other vias can still ensure the connection effect, but it is not limited to this, and a single via can also achieve the purpose of electrical connection.
  • the storage capacitor 300 includes a first electrode plate 301 and a second electrode plate 302, wherein the first electrode plate 301 is located on the first metal layer 001, and the second electrode plate 302 is located on the second electrode plate 301.
  • the shape of the digging area includes a circle, an ellipse, a triangle, a quadrilateral, or an irregular shape, but it is not limited thereto.
  • the shape of the digging area can be designed according to the shape, appearance or other conditions of the product, which is not limited in the present disclosure.
  • the shape of the winding area may be determined according to the shape of the digging area, or may be different from the shape of the digging area, which is not limited in the present disclosure.
  • the digging area and the winding area have the same shape and both are circular or elliptical. Such a shape is beneficial to the routing and winding.
  • the power supply line VL may include a high-level power supply line VDD.
  • the power signal given by the driver IC so in the winding area WA, the power line VL can be disconnected without affecting the transmission of the power signal.
  • This design reduces the number of wires in the winding area, which is beneficial to reduce The border BD of the digging area.
  • the embodiments provided by the present disclosure change the layers of the first wiring and the second wiring in the winding area to different metal layers, so that the adjacent wiring in the winding area is distributed on different metal layers.
  • the signal interference between the traces can be reduced, and the traces can be arranged more densely, so that the border of the digging area can be reduced without reducing the traces.
  • the embodiment provided by the present disclosure proposes to combine and transmit the fifth sub-wiring portion that transmits the reset signal of m+1 rows and the third sub-wiring portion that transmits the first gate signal of m rows in the winding area.
  • the number of wires in the winding area can be reduced, which is conducive to reducing the frame of the digging area.
  • the embodiment provided by the present disclosure also proposes that the fourth sub-wire that transmits the light-emitting control signal is disconnected in the winding area, which can further reduce the number of wires in the winding area and obtain a smaller frame of the digging area.
  • the embodiments provided in the present disclosure are beneficial for realizing a full-screen display.
  • the embodiments of the present disclosure all take the display panel including one digging area as an example, but it is not limited to this.
  • the number of digging areas on the display panel can be one, two or more, and the wiring around different digging areas is uniform.
  • the design of the present disclosure can be adopted.
  • an embodiment of the present disclosure also provides a display device, as shown in FIG. 11, which includes the display panel provided by any of the foregoing embodiments, and a sensor, the sensor being disposed under the digging area.
  • the sensor includes a camera, an infrared sensor, a fingerprint detection unit, and a pressure sensing unit.
  • the display device includes a display panel 1 and a sensor 2.
  • the sensor 2 is arranged under the hole-cutting area HA, so that the sensor can better receive signals from outside the display panel.
  • the sensor may include a camera, an infrared sensor, a fingerprint detection unit, and a pressure sensing unit, but it is not limited to this. Taking the sensor as the camera as an example, setting it under the digging area can prevent the camera from being interfered by the pixel unit of the display area, and can take clearer pictures.
  • the display device provided by the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the present disclosure.
  • embodiments of the present disclosure also provide a method for manufacturing a display panel, as shown in FIG. 12, which specifically includes:
  • a base substrate is provided, and the first insulating layer, the first metal layer, the second insulating layer, the second metal layer, the third insulating layer, the third metal layer, the fourth insulating layer, and the fifth insulating layer are sequentially fabricated on the base substrate Floor;
  • the base substrate of the display panel includes a digging area and a non-dugging area.
  • a first trace extending in the first direction is made in the non-dugging area.
  • the first trace includes a first sub-wiring part and a second sub-wiring. Part, the first auxiliary part and the second auxiliary part; make a second trace extending in the second direction in the non-digging area, the second trace includes the third sub-wiring part and the third auxiliary part; the first direction is different In the second direction
  • the third sub-wiring portion and the first auxiliary portion are made on the first metal layer
  • the second auxiliary portion is made on the second metal layer
  • the first sub-wiring portion and the second sub-wiring portion are made on the third metal layer.
  • the non-digging area includes a winding area, and at least a part of the first auxiliary part, the second auxiliary part and the third auxiliary part are made in the winding area.
  • the manufacturing method of the display panel provided in the embodiment of the present disclosure further includes: manufacturing a thin film transistor on the base substrate, which specifically includes:
  • An active layer, a first gate insulating layer, a first gate, an interlayer insulating layer, a source and drain electrode layer, a passivation layer, and a flat layer are sequentially fabricated on the base substrate;
  • the first gate insulating layer is the first insulating layer
  • the first gate is a part of the first metal layer
  • the interlayer insulating layer is a part of the third insulating layer
  • the source and drain electrode layer is a part of the third metal layer
  • the passivation layer is a part of the fourth insulating layer
  • the flat layer is a part of the fifth insulating layer;
  • the manufacturing method of the display panel further includes: manufacturing a first via hole penetrating at least the third insulating layer to electrically connect the first sub-wiring part and the first auxiliary part;
  • a third via hole penetrating at least the third insulating layer is made to electrically connect the third sub-wiring part and the third auxiliary part.
  • the manufacturing method of the display panel provided in the embodiment of the present disclosure further includes: fabricating a fourth metal layer on the side of the third metal layer away from the base substrate, and fabricating a fourth auxiliary part on the fourth metal layer;
  • Making a second wiring extending in the second direction in the non-digging area further includes: making a fourth sub wiring portion extending in the second direction;
  • n is an integer greater than or equal to 1.
  • making the second wiring extending in the second direction in the non-drilling area further includes: making a fifth sub-wiring portion extending in the second direction;
  • the third bridge portion is electrically connected to the third auxiliary portion through the seventh via hole or the eighth via hole;
  • n is an integer greater than or equal to 1.

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Abstract

一种显示面板（1）、显示装置及显示面板（1）的制作方法，显示面板（1）包括：衬底基板（100），衬底基板（100）上设置第一金属层（001）、第二金属层（002）、第三金属层（003）；显示面板（1）还包括走线；走线包括沿第一方向延伸的第一走线、沿第二方向延伸的第二走线，第一走线包括第一子走线部（011）、第二子走线部（021）、第一辅助部（012）和第二辅助部（022）；第二走线包括第三子走线部（031）和第三辅助部（032）；第一方向不同于第二方向；第一子走线部（011）和第二子走线部（021）位于第三金属层（003），第一辅助部（012）位于第一金属层（001），第二辅助部（022）位于第二金属层（002），第三子走线部（031）位于第一金属层（001），第三辅助部（032）位于第三金属层（003）；衬底基板（100）还包括挖孔区（HA）和非挖孔区；非挖孔区包括绕线区（WA）；第一辅助部（012）、第二辅助部（022）和第三辅助部（032）包括设置于绕线区（WA）内的绕线结构。

Description

显示面板、显示装置及显示面板的制作方法
相关申请的交叉引用
本公开要求在2020年06月02日提交中国专利局、申请号为202010490145.X、申请名称为“一种显示面板、显示装置及显示面板的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤指一种显示面板、显示装置及显示面板的制作方法。
背景技术
随着手机等显示电子产品的发展，显示屏的屏占比的提升成为一种产品趋势，为了实现全面屏显示，可以在显示屏上设置挖孔区，而围绕挖孔区的走线结构则需进行绕线。
发明内容
第一方面，本公开实施例提供了一种显示面板，包括衬底基板，在所述衬底基板上依次层叠设置的第一金属层、第二金属层和第三金属层；
所述显示面板还包括走线；
所述走线包括沿第一方向延伸的第一走线，所述第一走线包括第一子走线部、第二子走线部、第一辅助部和第二辅助部；
所述走线还包括沿第二方向延伸的第二走线，所述第二走线包括第三子走线部和第三辅助部；
所述第一方向不同于所述第二方向；
其中，所述第一子走线部和所述第二子走线部位于所述第三金属层，所述第一辅助部位于所述第一金属层，所述第二辅助部位于所述第二金属层， 所述第三子走线部位于所述第一金属层，所述第三辅助部位于所述第三金属层；
所述显示面板的所述衬底基板还包括挖孔区和非挖孔区，所述非挖孔区包括绕线区；
所述第一辅助部、第二辅助部和第三辅助部包括设置于所述绕线区内的绕线结构。
在一种可能的实施方式中，所述第一辅助部和所述第二辅助部在所述衬底基板上的正投影交替排列。
在一种可能的实施方式中，所述第一子走线部与所述第一辅助部通过第一过孔电连接，所述第二子走线部与所述第二辅助部通过第二过孔电连接；
所述第三子走线部与所述第三辅助部通过第三过孔电连接。
在一种可能的实施方式中，所述第二走线还包括第四子走线部，所述第四子走线部位于所述第一金属层。
在一种可能的实施方式中，所述显示面板还包括第四金属层，所述第四金属层设置于所述第三金属层远离衬底基板的一侧。
在一种可能的实施方式中，所述第二走线还包括第四辅助部，所述第四辅助部位于所述第四金属层；第四辅助部包括设置于所述绕线区内的绕线结构。
在一种可能的实施方式中，所述第三辅助部和所述第四辅助部在所述衬底基板上的正投影交替排列。
在一种可能的实施方式中，还包括：位于所述第三金属层的第一桥接部，所述第一桥接部与所述第四子走线部通过第五过孔电连接。
在一种可能的实施方式中，所述第一桥接部与所述第四辅助部通过第四过孔电连接。
在一种可能的实施方式中，所述第四过孔和所述第五过孔在所述衬底基板上的正投影不交叠。
在一种可能的实施方式中，位于所述第一金属层的所述第三子走线部、 所述第四子走线部和所述第一辅助部三者之间相互绝缘；
位于所述第三金属层的所述第一子走线部、所述第二子走线部、所述第一桥接部、所述第三辅助部四者之间相互绝缘；
所述第一辅助部、所述第二辅助部、所述第三辅助部、所述第四辅助部之间相互绝缘。
在一种可能的实施方式中，所述显示面板还包括：设置于所述第一金属层与所述衬底基板之间的第一绝缘层，设置于所述第一金属层与所述第二金属层之间的第二绝缘层，设置于所述第二金属层和所述第三金属层之间的第三绝缘层，设置于所述第三金属层远离所述衬底基板一侧的第四绝缘层，设置于所述第四绝缘层远离衬底基板一侧的第五绝缘层。
在一种可能的实施方式中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括驱动电路和存储电容；
所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括设置于所述衬底基板上的有源层；设置于所述有源层远离所述衬底基板一侧的第一栅极绝缘层，所述第一绝缘层包括所述第一栅极绝缘层；设置于所述第一栅极绝缘层远离所述衬底基板一侧的第一栅极，所述第一金属层包括第一栅极；设置于所述第一栅极远离所述衬底基板一侧的层间绝缘层，所述第三绝缘层包括所述层间绝缘层；设置于所述层间绝缘层远离所述衬底基板一侧的源漏电极层，所述第三金属层包括所述源漏电极层；设置于所述源漏电极层远离所述衬底基板一侧的钝化层；所述第四绝缘层包括所述钝化层；以及设置于所述钝化层远离所述衬底基板一侧的平坦层，所述第五绝缘层包括所述平坦层。
在一种可能的实施方式中，所述第一过孔为至少贯穿第三绝缘层的通孔，使所述第一子走线部和所述第一辅助部电连接。
在一种可能的实施方式中，所述第二过孔为至少贯穿第三绝缘层的通孔，使所述第二子走线部和所述第二辅助部电连接。
在一种可能的实施方式中，所述第三过孔为至少贯穿第三绝缘层的通孔，使所述第三子走线部和所述第三辅助部电连接。
在一种可能的实施方式中，所述第四过孔为至少贯穿第四绝缘层和第五绝缘层的通孔，使所述第一桥接部和所述第四辅助部电连接。
在一种可能的实施方式中，所述第五过孔为至少贯穿第三绝缘层的通孔，使所述第四子走线部和所述第一桥接部电连接。
在一种可能的实施方式中，所述第一子走线部和所述第二子走线部分别与不同像素单元的所述薄膜晶体管的源极或漏极电连接，被配置为传递数据信号。
在一种可能的实施方式中，所述第三子走线部和所述薄膜晶体管的所述第一栅极电连接，被配置为传递第一栅极信号。
所述第四子走线部被配置为传递发光控制信号。
在一种可能的实施方式中，与被配置为传递第n+1行发光控制信号的第四子走线部电连接的第一桥接部和被配置为传递第n行发光控制信号的第四子走线部之间通过第二桥接部电连接，其中n为大于等于1的整数。
在一种可能的实施方式中，所述第二桥接部位于第三金属层，所述第二桥接部处具有第六过孔，所述第六过孔为至少贯穿第三绝缘层的过孔，使所述被配置为传递第n行发光控制信号的第四子走线部与第二桥接部电连接。
在一种可能的实施方式中，所述被配置为传递第n行发光控制信号的第四子走线部通过第六过孔与第二桥接部电连接，所述与被配置为传递第n+1行发光控制信号的第四子走线部电连接的第一桥接部和所述第二桥接部共同通过第四过孔与第四辅助部电连接，所述第六过孔和所述第四过孔在所述衬底基板上的正投影不交叠。
在一种可能的实施方式中，所述第四子走线部与所述绕线区在衬底基板上的投影不交叠，被配置为传递同一行的发光控制信号的所述第四子走线部在所述绕线区断开。
在一种可能的实施方式中，所述第二走线还包括第五子走线部。
在一种可能的实施方式中，所述第五子走线部被配置为传递重置信号。
在一种可能的实施方式中，被配置为传递第m+1行重置信号的第五子走 线部和被配置为传递第m行第一栅极信号的第三子走线部通过第三桥接部电连接，其中m为大于等于1的整数。
在一种可能的实施方式中，所述第三桥接部位于所述第三金属层，所述第三桥接部处具有第七过孔和第八过孔，所述第七过孔为至少贯穿第三绝缘层的过孔，使所述被配置为传递第m行第一栅极信号的第三子走线部与所述第三桥接部电连接；所述第八过孔为至少贯穿第三绝缘层的过孔，使所述被配置为传递第m+1行重置信号的第五子走线部与所述第三桥接部电连接。
在一种可能的实施方式中，所述第三桥接部通过所述第七过孔或所述第八过孔与所述第三辅助部电连接。
在一种可能的实施方式中，至少部分所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔、第六过孔、第七过孔、第八过孔为多过孔并联结构。
在一种可能的实施方式中，所述存储电容包括第一电极板和第二电极板，其中所述第一电极板位于所述第一金属层，所述第二电极板位于所述第二金属层，所述第一电极板和所述第二电极板之间设置第二栅极绝缘层，所述第二绝缘层包括所述第二栅极绝缘层。
在一种可能的实施方式中，所述挖孔区的形状包括圆形、椭圆形、三角形、四边形或不规则形状。
第二方面，本公开实施例提供了一种显示装置，包括上述任一实施例提供的所述显示面板。
在一种可能的实施方式中，还包括感测器，所述感测器设置于所述挖孔区下方。
在一种可能的实施方式中，所述感测器包括摄像头、红外感测器、指纹检测单元、压力感测单元。
第三方面，本公开实施例提供了一种显示面板的制作方法，包括：
提供衬底基板，在所述衬底基板上依次制作第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第五绝 缘层；
所述衬底基板包括挖孔区和非挖孔区，在所述非挖孔区制作沿第一方向延伸的第一走线，所述第一走线包括第一子走线部、第二子走线部、第一辅助部和第二辅助部；在所述非挖孔区制作沿第二方向延伸的第二走线，所述第二走线包括第三子走线部和第三辅助部；所述第一方向不同于所述第二方向；
其中，在所述第一金属层制作所述第三子走线部和所述第一辅助部，在所述第二金属层制作所述第二辅助部，在所述第三金属层制作所述第一子走线部、所述第二子走线部和所述第三辅助部；
所述非挖孔区包括绕线区，至少部分所述第一辅助部、第二辅助部和第三辅助部制作在所述绕线区中。
在一种可能的实施方式中，所述方法还包括：
在所述衬底基板上依次制作有源层、第一栅极绝缘层、第一栅极、层间绝缘层、源漏电极层、钝化层、平坦层；所述第一栅极绝缘层为所述第一绝缘层的一部分，所述第一栅极为所述第一金属层的一部分，所述层间绝缘层为所述第三绝缘层的一部分，所述源漏电极层为所述第三金属层的一部分，所述钝化层为所述第四绝缘层的一部分，所述平坦层为所述第五绝缘层的一部分；
所述的显示面板的制作方法还包括：制作至少贯穿所述第三绝缘层的第一过孔，使所述第一子走线部和所述第一辅助部电连接；
制作至少贯穿所述第三绝缘层的第二过孔，使所述第二子走线部和所述第二辅助部电连接；
制作至少贯穿所述第三绝缘层的第三过孔，使所述第三子走线部和所述第三辅助部电连接。
在一种可能的实施方式中，所述方法还包括：
在所述第三金属层远离所述衬底基板的一侧制作第四金属层，在所述第四金属层制作第四辅助部；
在所述非挖孔区制作沿第二方向延伸的第二走线还包括：制作沿第二方向延伸的第四子走线部；
在第三金属层制作第一桥接部和第二桥接部；
制作至少贯穿第三绝缘层的第六过孔，使第n行的第四子走线部与第二桥接部电连接；
制作至少贯穿第三绝缘层的第五过孔，使第n+1行的第四子走线部与所述第一桥接部电连接；
制作至少贯穿第四绝缘层和第五绝缘层的第四过孔，使所述第一桥接部、第二桥接部与所述第四辅助部电连接；
其中n为大于等于1的整数。
在一种可能的实施方式中，所述方法还包括：在所述非挖孔区制作沿第二方向延伸的第二走线，包括，制作沿第二方向延伸的第五子走线部；
在第三金属层制作第三桥接部；
制作至少贯穿第三绝缘层的第七过孔，使第m行的第三子走线部与第三桥接部电连接；
制作至少贯穿第三绝缘层的第八过孔，使第m+1行的第五子走线部与第三桥接部电连接；
第三桥接部通过第七过孔或第八过孔与第三辅助部电连接；
其中m为大于等于1的整数。
附图说明
图1为显示面板示意图；
图2为本公开实施例提供的显示面板的一种截面膜层示意图；
图3为本公开实施例提供的显示面板的绕线区的局部放大俯视示意图；
图4a为图3中AA处的局部放大俯视示意图；
图4b为图4a中EE’线处的截面示意图；
图5a为图3中BB处的局部放大俯视示意图；
图5b为图5a中FF’线处的截面示意图；
图6a为图3中CC处的局部放大俯视示意图；
图6b为图6a中GG’线处的截面示意图；
图7a为图3中DD处的局部放大俯视示意图；
图7b为图7a中JJ’线处的截面示意图；
图7c为图7a中KK’线处的截面示意图；
图8为本公开实施例提供的另一种显示面板的绕线区的局部放大俯视示意图；
图9a为本公开实施例提供的另一种显示面板的第四子走线部通过第一桥接部、第二桥接部与第四辅助部电连接并换层的局部放大俯视示意图；
图9b为图9a中LL’线处的截面示意图；
图10为本公开实施例提供的另一种显示面板的第三子走线部、第五子走线部通过第三桥接部电连接并换层的局部放大俯视示意图；
图11为本公开实施例提供的显示装置的示意图；
图12为本公开实施例提供的显示面板制作方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现所述词前面的元件或者物件涵盖出现在所述词后面列举的元件或者物件及其等同， 而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅被配置为表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。当元件或层被称作“设置于”另一元件或层“的一侧”时，该元件或层可以直接在所述另一元件或层的一侧，直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
为了追求显示屏的屏占比的提高，挖孔屏被越来越多的应用，如图1所示，在显示面板1上设置有挖孔区HA，以及围绕挖孔区的绕线区WA，绕线区WA内走线比较密集，不设置像素单元，故绕线区WA不能实现显示功能，会围绕挖孔区HA形成一个无法显示的黑边。显示面板上还设置有沿第一方向延伸的多条数据线DL、多条电源线VL和沿第二方向延伸的多条栅线GL、多条重置信号线RL和多条发光控制信号线EL等走线(图中各走线仅示出一条)，在绕线区WA，多条走线之间的距离很近，容易互相产生干扰，如果想要保证走线之间有足够的距离，则会使挖孔区HA的边框变大，即图中的BD变大，这不利于提升显示屏的屏占比。
图2为本公开一个实施例中显示面板的截面膜层图，为了改善此问题，本公开实施例提供了一种显示面板，如图2所示，包括衬底基板100，在衬底基板上设置有第一金属层001、第二金属层002和第三金属层003，第二金属层002设置于第一金属层001远离衬底基板100的一侧，第三金属层003设置于第二金属层002远离衬底基板100的一侧。
图3为本公开一个实施例所提供的显示面板的绕线区的局部放大俯视图。 如图3所示，显示面板包括走线，走线包括沿第一方向延伸的第一走线，第一走线包括第一子走线部011、第一辅助部012和第二子走线部021、第二辅助部022；走线还包括沿第二方向延伸的第二走线，第二走线包括第三子走线部031、第三辅助部032；第一方向不同于第二方向。
其中，第一子走线部011和第二子走线部021位于第三金属层003，第一辅助部012位于第一金属层001，第二辅助部022位于第二金属层002，第三子走线部031位于第一金属层001，第三辅助部032位于第三金属层003。
第一辅助部012包括设置于绕线区WA内的第一绕线结构0121，也包括位于第一绕线结构0121和第一子走线部011之间的第一连接结构0122，第二辅助部022包括设置于绕线区WA内的第二绕线结构0221，也包括位于第二绕线结构0221和第二子走线部021之间的第二连接结构0222，第三辅助部032包括设置于绕线区WA内的第三绕线结构0321，也包括位于第三绕线结构0321和第三子走线部031之间的第三连接结构0322。
本公开图中所示的走线宽度仅为更清楚的示意和区分出不同的走线，并不代表实际的走线宽度，也不构成对本公开的限定。图中的挖孔区、绕线区、显示面板等各区域的大小和比例也仅为示意，不构成对本公开的限定。
第一辅助部和第二辅助部在衬底基板上的投影交替排列，如图3所示，第一辅助部012和第二辅助部022在衬底基板上的正投影交替排列。
在本公开的实施例中，位于第一金属层的第三子走线部031通过被换层到位于第三金属层的第三辅助部032在绕线区内绕线传输，位于第三金属层的第一子走线部011通过被换层到位于第一金属层的第一辅助部012在绕线区内绕线传输，位于第三金属层的第二子走线部021通过被换层到位于第二金属层的第二辅助部022在绕线区内绕线传输，在从挖孔区HA指向绕线区WA外边界的方向上，第一辅助部012和第二辅助部022在衬底基板的投影交替排列，这样使得绕线区内相邻的绕线结构分布在不同的金属层，减弱了相邻走线之间信号的干扰，可以缩小相邻走线之间的距离，使得可以在走线数量不减少的前提下，缩小挖孔区的边框。
示例的，原本位于第一金属层的第三子走线部031被换层到位于第三金属层的第三连接结构0322后再连接到第三绕线结构0321在绕线区内绕线传输，原本位于第三金属层的第一子走线部011被换层到位于第一金属层的第一连接结构0122后再连接到第一绕线结构0121在绕线区内绕线传输，原本位于第三金属层的第二子走线部021被换层到位于第二金属层的第二连接结构0222后再连接到第二绕线结构0221在绕线区内绕线传输，且第一绕线结构0121和第二绕线结构0221在衬底基板的投影交替排列，绕线区内相邻的绕线结构分布在不同的金属层，减弱了相邻走线之间信号的干扰，可以缩小相邻走线之间的距离，使得可以在不减少走线数量的前提下缩小挖孔区的边框。
在本公开的实施例中，第一子走线部与第一辅助部通过第一过孔电连接，第二子走线部与第二辅助部通过第二过孔电连接，第三子走线部与第三辅助部通过第三过孔电连接。
示例的，如图3中的虚线框AA处，第一子走线部011与第一辅助部012通过第一过孔电连接，图4a即为AA处的局部放大俯视图，图4b为图4a中EE’处的截面图，结合图4a和图4b，位于第三金属层003的第一子走线部011与位于第一金属层的001的第一辅助部012的第一连接结构0122通过第一过孔H1电连接，从而使得第一子走线部和第一辅助部实现电连接，如图4a所示，第一过孔H1可以是多过孔并联结构，这样的设计可以更好的使不同层的金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。
示例的，如图3中的虚线框BB处，第二子走线部021与第二辅助部022通过第二过孔电连接，图5a即为BB处的局部放大俯视图，图5b为图5a中FF’处的截面图，结合图5a和图5b，位于第三金属层003的第二子走线部021与位于第二金属层的002的第二辅助部022的第一连接结构0222通过第二过孔H2电连接，从而使得第二子走线部和第二辅助部实现电连接，如图5a所示，第二过孔H2可以是多过孔并联结构，这样的设计可以更好的使不同层的 金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。
示例的，如图3中的虚线框CC处，第三子走线部031与第三辅助部032通过第三过孔电连接，图6a即为CC处的局部放大俯视图，图6b为图6a中GG’处的截面图，结合图6a和图6b，位于第一金属层001的第三子走线部031与位于第三金属层的003的第三辅助部032的第三连接结构0322通过第三过孔H3电连接，从而使得第三子走线部和第三辅助部实现电连接，如图6a所示，第三过孔H3可以是多过孔并联结构，这样的设计可以更好的使不同层的金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。
在本公开的实施例中，如图3所示，第二走线还可以包括第四子走线部041，第四子走线部041位于第一金属层001。
在本公开的实施例中，如图2所示，显示面板还可以包括第四金属层004，第四金属层004设置于第三金属层003远离衬底基板100的一侧。
在本公开的实施例中，如图3所示，第二走线还可以包括第四辅助部042，第四辅助部042位于第四金属层004。第四辅助部042包括设置于绕线区WA内的第四绕线结构0421，也包括位于第四绕线结构0421和第四子走线部041之间的第四连接结构0422。
在本公开的实施例中，如图3所示，第三辅助部032和第四辅助部042在衬底基板上的正投影交替排列，具体地，第三绕线结构0321和第四绕线结构0421在衬底基板上的正投影交替排列。
在本公开的实施例中，显示面板还包括第一桥接部，第一桥接部位于第三金属层，第一桥接部处设置有第五过孔，第五过孔使第四子走线部与第一桥接部电连接。第一桥接部与第四辅助部通过第四过孔电连接。
示例的，如图3中的虚线框DD处，第四子走线部041与第四辅助部042通过第一桥接部电连接(第一桥接部在图3中未示出)，图7a为图3中DD处的局部放大俯视图，图7b为图7a中JJ’处的截面图，图7c为图7a中KK’处 的截面图。结合图7a～图7c，位于第一金属层001的第四子走线部041通过第五过孔H5电连接至位于第三金属层003的第一桥接部BR1，第一桥接部BR1通过第四过孔H4电连接至位于第四金属层004的第四连接结构0422，从而使得第四子走线部和第四辅助部实现电连接。如图7a所示，第四过孔H4、第五过孔H5可以是多过孔并联结构，这样的设计可以更好的使不同层的金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。示例的，如图7a所示，第四过孔H4和第五过孔H5在衬底基板上的正投影不交叠。
在本公开的实施例中，如图3、图7a所示，第三子走线部031、第四子走线部041和第一辅助部012均位于第一金属层001，且三者之间相互绝缘；第一子走线部011、第二子走线部021、第一桥接部BR1、第三辅助部032均位于第三金属层003，且四者之间相互绝缘；第一辅助部012、第二辅助部022、第三辅助部032、第四辅助部042之间相互绝缘。
在本公开的实施例中，如图2所示，第一金属层001朝向衬底基板100的一侧还设置有第一绝缘层110，第一金属层001远离衬底基板的一侧设置有第二绝缘层120，第二绝缘层120远离衬底基板100的一侧设置第二金属层002，第二金属层002远离衬底基板100的一侧设置第三绝缘层130，第三绝缘层130远离衬底基板100的一侧设置第三金属层003，第三金属层003远离衬底基板100的一侧设置第四绝缘层140，第四绝缘层140远离衬底基板100的一侧设置第五绝缘层150。
在本公开的实施例中，如图1、图2所示，显示面板还包括阵列排布的像素单元P，像素单元P包括驱动电路和存储电容300；驱动电路包括薄膜晶体管TFT，薄膜晶体管TFT包括设置于衬底基板上的有源层200、设置于有源层200远离衬底基板100一侧的第一栅极绝缘层111、设置于第一栅极绝缘层111远离衬底基板一侧的第一栅极0011、设置于第一栅极0011远离衬底基板一侧的层间绝缘层1301、设置于层间绝缘层1301远离衬底基板一侧的源漏电极层0031、设置于源漏电极层0031远离衬底基板一侧的钝化层1401以及设 置于钝化层1401远离衬底基板一侧的平坦层1501；第一绝缘层110包括第一栅极绝缘层111，第一金属层001包括第一栅极0011；第三绝缘层130包括层间绝缘层1301；第三金属层003包括源漏电极层0031；第四绝缘层140包括钝化层1401；第五绝缘层150包括平坦层1501。
在本公开的实施例中，如图4a-图4b、图5a-图5b、图6a-图6b、图7a-图7c所示，第一过孔H1为至少贯穿第三绝缘层130的通孔，使第一子走线部011和第一辅助部012(第一连接结构0122)电连接；第二过孔H2为至少贯穿第三绝缘层130的通孔，使第二子走线部021和第二辅助部022(第二连接结构0222)电连接；第三过孔H3为至少贯穿第三绝缘层130的通孔，使第三子走线部031和第三辅助部032(第三连接结构0322)电连接；第四过孔H4为至少贯穿第四绝缘层140和第五绝缘层150的通孔，使第一桥接部BR1和第四辅助部042(第四连接结构0422)电连接；第五过孔H5为至少贯穿第三绝缘层130的通孔，使第四子走线部041和第一桥接部BR1电连接。
在本公开的实施例中，如图2、图3所示，第一子走线部011和第二子走线部021分别与不同像素单元P1、P2的薄膜晶体管的源极或漏极电连接，被配置为传递数据信号，第三子走线部031和薄膜晶体管的第一栅极0011电连接，被配置为传递第一栅极信号，第四子走线部被配置为传递发光控制信号。
在本公开的实施例中，第四子走线部与绕线区在衬底基板上的投影不交叠，被配置为传递同一行的发光控制信号的第四子走线部在绕线区断开。
示例的，如图8所示，被配置为传递发光控制信号的第四子走线部041与绕线区WA在衬底基板上的投影不交叠，被配置为传递同一行的发光控制信号的第四子走线部在绕线区断开。这是因为被配置为给出发光控制信号EM的EM GOA(Gate on array)可以制作在显示面板的两侧，由显示面板两侧的EM GOA共同向显示面板提供发光控制信号EM，所以第四子走线部在绕线区断开不会影响这一行的像素单元接收发光控制信号EM。这样的设计可以使绕线区WA内部的走线减少，可以缩小挖孔区的边框BD。
在本公开的另一实施例中，如图9a所示，与被配置为传递第n+1行发光 控制信号的第四子走线部041(n+1)电连接的第一桥接部BR1和被配置为传递第n行发光控制信号的第四子走线部041(n)之间通过第二桥接部BR2电连接，其中n为大于等于1的整数。第二桥接部BR2位于第三金属层003，第二桥接部BR2处具有第六过孔H6，第六过孔H6为至少贯穿第三绝缘层130的过孔，图9b为图9a中LL’处的截面图，如图9b所示，被配置为传递第n行发光控制信号的第四子走线部041(n)与第二桥接部BR2通过第六过孔H6电连接。如图所示，第六过孔H6可以是多过孔并联结构，这样的设计可以更好的使不同层的金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。
如图9a所示，被配置为传递第n行发光控制信号的第四子走线部041(n)通过第六过孔H6与第二桥接部BR2电连接，与被配置为传递第n+1行发光控制信号的第四子走线部041(n+1)电连接的第一桥接部BR1和第二桥接部BR2共同通过第四过孔H4与第四辅助部042(第四连接结构0422)电连接，第六过孔H6和第四过孔H4在衬底基板上的正投影不交叠。这样的设计使得相邻两行的发光控制信号在绕线区可以合并传输，从而减少了在绕线区中的走线数量，可以缩小挖孔区的边框BD。
在本公开的实施例中，如图10所示，第二走线还包括第五子走线部051，第五子走线部051被配置为传递重置信号Rst，被配置为传递第m+1行重置信号Rst的第五子走线部051和被配置为传递第m行第一栅极信号的第三子走线部031通过第三桥接部BR3电连接，其中m为大于等于1的整数。第三桥接部BR3位于第三金属层003，第三桥接部处具有第七过孔H7和第八过孔H8，第七过孔H7为至少贯穿第三绝缘层的过孔，使被配置为传递第m行第一栅极信号的第三子走线部031与第三桥接部BR3电连接；第八过孔H8为至少贯穿第三绝缘层的过孔，使被配置为传递第m+1行重置信号的第五子走线部051与第三桥接部BR3电连接。第三桥接部BR3通过第七过孔H7或第八过孔H8与第三辅助部032(第三连接结构0322)电连接，图中仅示出了第三桥接部BR3和第三连接结构0322通过第八过孔H8电连接的情况，但不以 此为限，第七过孔H7也可以实现第三桥接部BR3和第三连接结构0322的电连接。这样的设计使得被配置为传递第m行第一栅极信号的走线和被配置为传递第m+1行重置信号的走线在绕线区可以合并传输，从而减少了在绕线区中的走线数量，可以缩小挖孔区的边框BD。
在本公开的实施例中，如图10所示，第七过孔H7、第八过孔H8可以是多过孔并联结构，这样的设计可以更好的使不同层的金属互相连接，当其中一个过孔出现不良时，其他过孔仍能保证连接效果，但并不以此为限，单过孔也可以达到电连接的目的。
在本公开的实施例中，如图2所示，存储电容300包括第一电极板301和第二电极板302，其中第一电极板301位于第一金属层001，第二电极板302位于第二金属层002，第一电极板001和第二电极板002之间设置第二栅极绝缘层1201，第二绝缘层120包括第二栅极绝缘层1201。
在本公开的实施例中，挖孔区的形状包括圆形、椭圆形、三角形、四边形或不规则形状，但不以此为限。具体的，挖孔区的形状可以根据产品的形状、外观或其他条件进行设计，本公开对此不做限定。绕线区的形状可以依据挖孔区的形状而定，也可以与挖孔区形状不同，本公开对此不做限定。优选的，挖孔区与绕线区形状相同且都为圆形或椭圆形，这样的形状有利于走线绕线。
在本公开的实施例中，如图1所示，电源线VL可以包括高电平电源线VDD，电源线VL与设置于显示面板两侧的驱动IC(图中未示出)连接，并传输驱动IC给出的电源信号，故在绕线区WA，电源线VL可以断开，而不影响电源信号的传输，这样的设计使得绕线区内的走线数量可以减少一部分，有利于减小挖孔区的边框BD。
本公开所提供的实施例通过将第一走线和第二走线在绕线区的部分换层到不同的金属层中，使绕线区中相邻的走线分布在不同的金属层，可以减少走线之间的信号干扰，走线可以排布的更密集，使得在不减少走线的前提下，减小挖孔区的边框。此外，本公开所提供的实施例提出将传递m+1行的重置 信号的第五子走线和传递m行的第一栅极信号的第三子走线部在绕线区合并传输，可以减少绕线区的走线数量，有利于减小挖孔区的边框。另外，本公开所提供的实施例还提出将传递发光控制信号的第四子走线在绕线区断线，可以进一步减少绕线区的走线数量，可以得到更小的挖孔区边框。本公开所提供的实施例有利于实现全面屏显示。
本公开的实施例均以显示面板包括一个挖孔区为例，但不以此为限，显示面板上挖孔区的数量可以一个、两个或更多，围绕不同挖孔区的走线均可以采用本公开的设计。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图11所示，包括上述任一实施例提供的显示面板，以及感测器，感测器设置于挖孔区下方。感测器包括摄像头、红外感测器、指纹检测单元、压力感测单元。
示例的，如图11所示，显示装置包括显示面板1以及感测器2，感测器2设置于挖孔区HA下方，使感测器可以更好的接收来自显示面板外部的信号而不受到显示面板本身的影响，例如感测器可以包括摄像头、红外感测器、指纹检测单元、压力感测单元，但不以此为限。以感测器为摄像头为例，设置于挖孔区下方可以使摄像头不受显示区像素单元的干扰，可以拍摄出更加清晰的照片。
本公开实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一发明构思，本公开实施例还提供了一种显示面板的制作方法，如图12所示，具体包括：
提供衬底基板，在衬底基板上依次制作第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第五绝缘层；
显示面板的衬底基板包括挖孔区和非挖孔区，在非挖孔区制作沿第一方向延伸的第一走线，第一走线包括第一子走线部、第二子走线部、第一辅助 部和第二辅助部；在非挖孔区制作沿第二方向延伸的第二走线，第二走线包括第三子走线部和第三辅助部；第一方向不同于第二方向；
其中，在第一金属层制作第三子走线部和第一辅助部，在第二金属层制作第二辅助部，在第三金属层制作第一子走线部、第二子走线部和第三辅助部；
非挖孔区包括绕线区，至少部分第一辅助部、第二辅助部和第三辅助部制作在绕线区中。
在本公开实施例提供的显示面板的制作方法还包括：在衬底基板上制作薄膜晶体管，具体包括：
在衬底基板上依次制作有源层、第一栅极绝缘层、第一栅极、层间绝缘层、源漏电极层、钝化层、平坦层；第一栅极绝缘层为第一绝缘层的一部分，第一栅极为第一金属层的一部分，层间绝缘层为第三绝缘层的一部分，源漏电极层为第三金属层的一部分，钝化层为第四绝缘层的一部分，平坦层为第五绝缘层的一部分；
显示面板的制作方法还包括：制作至少贯穿第三绝缘层的第一过孔，使第一子走线部和第一辅助部电连接；
制作至少贯穿第三绝缘层的第二过孔，使第二子走线部和第二辅助部电连接；
制作至少贯穿第三绝缘层的第三过孔，使第三子走线部和第三辅助部电连接。
在本公开实施例提供的显示面板的制作方法还包括：在第三金属层远离衬底基板的一侧制作第四金属层，在第四金属层制作第四辅助部；
在非挖孔区制作沿第二方向延伸的第二走线还包括；制作沿第二方向延伸的第四子走线部；
在第三金属层制作第一桥接部和第二桥接部；
制作至少贯穿第三绝缘层的第六过孔，使第n行的第四子走线部与第二桥接部电连接；
制作至少贯穿第三绝缘层的第五过孔，使第n+1行的第四子走线部与第一桥接部电连接；
制作至少贯穿第四绝缘层和第五绝缘层的第四过孔，使第一桥接部、第二桥接部与第四辅助部电连接；
其中n为大于等于1的整数。
在本公开实施例提供的显示面板的制作方法中，在非挖孔区制作沿第二方向延伸的第二走线还包括：制作沿第二方向延伸的第五子走线部；
在第三金属层制作第三桥接部；
制作至少贯穿第三绝缘层的第七过孔，使第m行的第三子走线部与第三桥接部电连接；
制作至少贯穿第三绝缘层的第八过孔，使第m+1行的第五子走线部与第三桥接部电连接；
第三桥接部通过第七过孔或第八过孔与第三辅助部电连接；
其中m为大于等于1的整数。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (40)

  1. 一种显示面板，其中，包括衬底基板，在所述衬底基板上依次层叠设置的第一金属层、第二金属层和第三金属层；
    所述显示面板还包括走线；
    所述走线包括沿第一方向延伸的第一走线，所述第一走线包括第一子走线部、第二子走线部、第一辅助部和第二辅助部；
    所述走线还包括沿第二方向延伸的第二走线，所述第二走线包括第三子走线部和第三辅助部；
    所述第一方向不同于所述第二方向；
    其中，所述第一子走线部和所述第二子走线部位于所述第三金属层，所述第一辅助部位于所述第一金属层，所述第二辅助部位于所述第二金属层，所述第三子走线部位于所述第一金属层，所述第三辅助部位于所述第三金属层；
    所述衬底基板包括挖孔区和非挖孔区，所述非挖孔区包括绕线区；
    所述第一辅助部、第二辅助部和第三辅助部包括设置于所述绕线区内的绕线结构。
  2. 如权利要求1所述的显示面板，其中，所述第一辅助部和所述第二辅助部在所述衬底基板上的正投影交替排列。
  3. 如权利要求2所述的显示面板，其中，所述第一子走线部与所述第一辅助部通过第一过孔电连接，所述第二子走线部与所述第二辅助部通过第二过孔电连接；
    所述第三子走线部与所述第三辅助部通过第三过孔电连接。
  4. 如权利要求3所述的显示面板，其中，所述第二走线还包括第四子走线部，所述第四子走线部位于所述第一金属层。
  5. 如权利要求4所述的显示面板，其中，还包括第四金属层，所述第四金属层设置于所述第三金属层远离衬底基板的一侧。
  6. 如权利要求5所述的显示面板，其中，所述第二走线还包括第四辅助部，所述第四辅助部位于所述第四金属层；第四辅助部包括设置于所述绕线区内的绕线结构。
  7. 如权利要求6所述的显示面板，其中，所述第三辅助部和所述第四辅助部在所述衬底基板上的正投影交替排列。
  8. 如权利要求7所述的显示面板，其中，还包括：位于所述第三金属层的第一桥接部，所述第一桥接部与所述第四子走线部通过第五过孔电连接。
  9. 如权利要求8所述的显示面板，其中，所述第一桥接部与所述第四辅助部通过第四过孔电连接。
  10. 如权利要求9所述的显示面板，其中，所述第四过孔和所述第五过孔在所述衬底基板上的正投影不交叠。
  11. 如权利要求10所述的显示面板，其中，位于所述第一金属层的所述第三子走线部、所述第四子走线部和所述第一辅助部三者之间相互绝缘；
    位于所述第三金属层的所述第一子走线部、所述第二子走线部、所述第一桥接部、所述第三辅助部四者之间相互绝缘；
    所述第一辅助部、所述第二辅助部、所述第三辅助部、所述第四辅助部之间相互绝缘。
  12. 如权利要求9-11任一项所述的显示面板，其中，所述显示面板还包括：设置于所述第一金属层与所述衬底基板之间的第一绝缘层，设置于所述第一金属层与所述第二金属层之间的第二绝缘层，设置于所述第二金属层和所述第三金属层之间的第三绝缘层，设置于所述第三金属层远离所述衬底基板一侧的第四绝缘层，设置于所述第四绝缘层远离衬底基板一侧的第五绝缘层。
  13. 如权利要求12所述的显示面板，其中，所述显示面板还包括阵列排布的像素单元，所述像素单元包括驱动电路和存储电容；
    所述驱动电路包括薄膜晶体管，所述薄膜晶体管包括设置于所述衬底基板上的有源层；设置于所述有源层远离所述衬底基板一侧的第一栅极绝缘层， 所述第一绝缘层包括所述第一栅极绝缘层；设置于所述第一栅极绝缘层远离所述衬底基板一侧的第一栅极，所述第一金属层包括第一栅极；设置于所述第一栅极远离所述衬底基板一侧的层间绝缘层，所述第三绝缘层包括所述层间绝缘层；设置于所述层间绝缘层远离所述衬底基板一侧的源漏电极层，所述第三金属层包括所述源漏电极层；设置于所述源漏电极层远离所述衬底基板一侧的钝化层；所述第四绝缘层包括所述钝化层；以及设置于所述钝化层远离所述衬底基板一侧的平坦层，所述第五绝缘层包括所述平坦层。
  14. 如权利要求13所述的显示面板，其中，所述第一过孔为至少贯穿第三绝缘层的通孔，使所述第一子走线部和所述第一辅助部电连接。
  15. 如权利要求13所述的显示面板，其中，所述第二过孔为至少贯穿第三绝缘层的通孔，使所述第二子走线部和所述第二辅助部电连接。
  16. 如权利要求13所述的显示面板，其中，所述第三过孔为至少贯穿第三绝缘层的通孔，使所述第三子走线部和所述第三辅助部电连接。
  17. 如权利要求13所述的显示面板，其中，所述第四过孔为至少贯穿第四绝缘层和第五绝缘层的通孔，使所述第一桥接部和所述第四辅助部电连接。
  18. 如权利要求13所述的显示面板，其中，所述第五过孔为至少贯穿第三绝缘层的通孔，使所述第四子走线部和所述第一桥接部电连接。
  19. 如权利要求13所述的显示面板，其中，所述第一子走线部和所述第二子走线部分别与不同像素单元的所述薄膜晶体管的源极或漏极电连接，被配置为传递数据信号。
  20. 如权利要求19所述的显示面板，其中，所述第三子走线部和所述薄膜晶体管的所述第一栅极电连接，被配置为传递第一栅极信号。
  21. 如权利要求20所述的显示面板，其中，所述第四子走线部被配置为传递发光控制信号。
  22. 如权利要求21所述的显示面板，其中，与被配置为传递第n+1行发光控制信号的第四子走线部电连接的第一桥接部和被配置为传递第n行发光控制信号的第四子走线部之间通过第二桥接部电连接，其中n为大于等于1 的整数。
  23. 如权利要求22所述的显示面板，其中，所述第二桥接部位于第三金属层，所述第二桥接部处具有第六过孔，所述第六过孔为至少贯穿第三绝缘层的过孔，使所述被配置为传递第n行发光控制信号的第四子走线部与所述第二桥接部电连接。
  24. 如权利要求23所述的显示面板，其中，所述被配置为传递第n行发光控制信号的第四子走线部通过所述第六过孔与所述第二桥接部电连接，所述与被配置为传递第n+1行发光控制信号的第四子走线部电连接的第一桥接部和所述第二桥接部共同通过所述第四过孔与所述第四辅助部电连接，所述第六过孔和所述第四过孔在所述衬底基板上的正投影不交叠。
  25. 如权利要求21所述的显示面板，其中，所述第四子走线部与所述绕线区在所述衬底基板上的正投影不交叠，被配置为传递同一行的发光控制信号的所述第四子走线部在所述绕线区断开。
  26. 如权利要求18所述的显示面板，其中，所述第二走线还包括第五子走线部。
  27. 如权利要求26所述的显示面板，其中，所述第五子走线部被配置为传递重置信号。
  28. 如权利要求27所述的显示面板，其中，被配置为传递第m+1行重置信号的第五子走线部和被配置为传递第m行第一栅极信号的第三子走线部通过所述第三桥接部电连接，其中m为大于或等于1的整数。
  29. 如权利要求28所述的显示面板，其中，所述第三桥接部位于所述第三金属层，所述第三桥接部处具有第七过孔和第八过孔，所述第七过孔为至少贯穿所述第三绝缘层的过孔，使所述被配置为传递第m行第一栅极信号的第三子走线部与所述第三桥接部电连接；所述第八过孔为至少贯穿第三绝缘层的过孔，使所述被配置为传递第m+1行重置信号的第五子走线部与所述第三桥接部电连接。
  30. 如权利要求29所述的显示面板，其中，所述第三桥接部通过所述第 七过孔或所述第八过孔与所述第三辅助部电连接。
  31. 如权利要求30所述的显示面板，其中，至少部分所述第一过孔、所述第二过孔、所述第三过孔、所述第四过孔、所述第五过孔、第六过孔、第七过孔、第八过孔为多过孔并联结构。
  32. 如权利要求13所述的显示面板，其中，所述存储电容包括第一电极板和第二电极板，所述第一电极板位于所述第一金属层，所述第二电极板位于所述第二金属层，所述第一电极板和所述第二电极板之间设置第二栅极绝缘层，所述第二绝缘层包括所述第二栅极绝缘层。
  33. 如权利要求1-11、13-32任一项所述的显示面板，其中，所述挖孔区的形状包括圆形、椭圆形、三角形、四边形或不规则形状。
  34. 一种显示装置，其中，包括如权利要求1-33任一项所述的显示面板。
  35. 如权利要求34所述的显示装置，其中，还包括：感测器，所述感测器设置于所述挖孔区下方。
  36. 如权利要求35所述的显示装置，其中，所述感测器包括摄像头、红外感测器、指纹检测单元、压力感测单元。
  37. 一种显示面板的制作方法，其中，包括：
    提供衬底基板，在所述衬底基板上依次制作第一绝缘层、第一金属层、第二绝缘层、第二金属层、第三绝缘层、第三金属层、第四绝缘层、第五绝缘层；
    所述衬底基板包括挖孔区和非挖孔区，在所述非挖孔区制作沿第一方向延伸的第一走线，所述第一走线包括第一子走线部、第二子走线部、第一辅助部和第二辅助部；在所述非挖孔区制作沿第二方向延伸的第二走线，所述第二走线包括第三子走线部和第三辅助部；所述第一方向不同于所述第二方向；
    其中，在所述第一金属层制作所述第三子走线部和所述第一辅助部，在所述第二金属层制作所述第二辅助部，在所述第三金属层制作所述第一子走线部、所述第二子走线部和所述第三辅助部；
    所述非挖孔区包括绕线区，至少部分所述第一辅助部、第二辅助部和第三辅助部制作在所述绕线区中。
  38. 如权利要求37所述的显示面板的制作方法，其中，还包括：
    在所述衬底基板上依次制作有源层、第一栅极绝缘层、第一栅极、层间绝缘层、源漏电极层、钝化层、平坦层；所述第一栅极绝缘层为所述第一绝缘层的一部分，所述第一栅极为所述第一金属层的一部分，所述层间绝缘层为所述第三绝缘层的一部分，所述源漏电极层为所述第三金属层的一部分，所述钝化层为所述第四绝缘层的一部分，所述平坦层为所述第五绝缘层的一部分；
    所述的显示面板的制作方法还包括：制作至少贯穿所述第三绝缘层的第一过孔，使所述第一子走线部和所述第一辅助部电连接；
    制作至少贯穿所述第三绝缘层的第二过孔，使所述第二子走线部和所述第二辅助部电连接；
    制作至少贯穿所述第三绝缘层的第三过孔，使所述第三子走线部和所述第三辅助部电连接。
  39. 如权利要求38所述的显示面板的制作方法，其中，还包括：
    在所述第三金属层远离所述衬底基板的一侧制作第四金属层，在所述第四金属层制作第四辅助部；
    在所述非挖孔区制作沿第二方向延伸的第二走线还包括：制作沿第二方向延伸的第四子走线部；
    在所述第三金属层制作第一桥接部和第二桥接部；
    制作至少贯穿所述第三绝缘层的第六过孔，使第n行的第四子走线部与所述第二桥接部电连接；
    制作至少贯穿所述第三绝缘层的第五过孔，使第n+1行的第四子走线部与所述第一桥接部电连接；
    制作至少贯穿所述第四绝缘层和所述第五绝缘层的第四过孔，使所述第一桥接部、所述第二桥接部与所述第四辅助部电连接；
    其中n为大于等于1的整数。
  40. 如权利要求38所述的显示面板的制作方法，其中，在所述非挖孔区制作沿第二方向延伸的第二走线还包括：制作沿第二方向延伸的第五子走线部；
    在所述第三金属层制作第三桥接部；
    制作至少贯穿所述第三绝缘层的第七过孔，使第m行的第三子走线部与所述第三桥接部电连接；
    制作至少贯穿所述第三绝缘层的第八过孔，使第m+1行的第五子走线部与所述第三桥接部电连接；
    所述第三桥接部通过所述第七过孔或所述第八过孔与所述第三辅助部电连接；
    其中m为大于等于1的整数。
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