WO2019028934A1 - Transistor à couches minces de polysilicium basse température et son procédé de préparation - Google Patents

Transistor à couches minces de polysilicium basse température et son procédé de préparation Download PDF

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WO2019028934A1
WO2019028934A1 PCT/CN2017/098337 CN2017098337W WO2019028934A1 WO 2019028934 A1 WO2019028934 A1 WO 2019028934A1 CN 2017098337 W CN2017098337 W CN 2017098337W WO 2019028934 A1 WO2019028934 A1 WO 2019028934A1
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layer
polysilicon
active layer
polysilicon active
thin film
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PCT/CN2017/098337
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English (en)
Chinese (zh)
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肖东辉
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武汉华星光电技术有限公司
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Priority to US15/575,107 priority Critical patent/US10516058B2/en
Publication of WO2019028934A1 publication Critical patent/WO2019028934A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to a manufacturing process of a semiconductor device, and more particularly to a low temperature polysilicon thin film transistor and a method of fabricating the same.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
  • LTPS thin film transistors have many advantages. For example, LTPS thin film transistors have high electron mobility, which not only can effectively reduce the area of thin film transistors, increase the aperture ratio, but also improve the display brightness while reducing the overall power consumption. For example, a higher electron mobility can integrate part of the driving circuit on the substrate, reduce the driving integrated circuit IC, greatly improve the reliability of the display panel, and greatly reduce the manufacturing cost. Therefore, LTPS thin film transistors have gradually become a research hotspot in the field of display technology.
  • the structure of the existing LTPS thin film transistor mainly comprises a base substrate and a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode which are sequentially disposed on the base substrate, and the source electrode and the drain electrode pass through the via hole Electrically connected to the polysilicon active layer.
  • the gate insulating layer covering the active layer of the polysilicon is formed by a deposition process, the defect density of the gate insulating layer is large, and carriers in the active layer of the polysilicon are easily diffused into the gate insulating layer, forming a comparison Large leakage current increases the instability of the electrical properties of LTPS thin film transistors. Therefore, the prior art has yet to be improved and developed.
  • the present invention provides a low temperature polysilicon thin film transistor and a method of fabricating the same, which can reduce the defect density of the interface between the active layer of the polysilicon and the gate insulating layer, and reduce the leakage of the thin film transistor.
  • the current makes the thin film transistor have good and stable electrical properties.
  • a method for preparing a low-temperature polysilicon thin film transistor comprising: sequentially forming a polysilicon active layer and a gate insulating layer covering the polysilicon active layer on a substrate; applying an ion implantation process, wherein the polysilicon has Nitrogen ions are implanted into the surface of the source layer facing the gate insulating layer to form an ion implantation layer; the ion implantation layer is recrystallized by a high temperature annealing process, and the polysilicon active layer and the gate insulating layer are A silicon nitride spacer layer is formed between them.
  • the preparation method comprises the steps of:
  • the preparation method comprises the steps of:
  • the step S1 specifically includes: S11, sequentially depositing a buffer layer and an amorphous silicon film layer on the substrate substrate; S12, applying an excimer laser annealing process to form the amorphous silicon film layer to form a polysilicon film Floor.
  • the buffer layer comprises a silicon nitride layer and a silicon oxide layer sequentially formed on the substrate substrate.
  • the method further comprises the steps of: S0, preparing a patterned light-shielding unit on the substrate substrate, wherein the light-shielding unit is for preparing a patterned polysilicon active layer formed in a subsequent process.
  • the polysilicon active layer is doped by an ion implantation process, so that the polysilicon active layer is sequentially formed from the middle to the both ends. a dummy region, a lightly doped region, and a heavily doped region; wherein the source electrode is electrically connected to a heavily doped region of one end of the polysilicon active layer, and the drain electrode is electrically connected to the polysilicon A heavily doped region at the other end of the source layer.
  • the gate insulating layer is a silicon oxide layer or a silicon nitride layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the present invention also provides a low temperature crystalline silicon thin film transistor comprising a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode sequentially disposed on a base substrate, wherein the polysilicon active layer and The connection interface between the gate insulating layers is formed with a silicon nitride spacer layer, and the silicon nitride spacer layer and the polysilicon active layer are integrally connected to each other.
  • the silicon nitride spacer layer is passed through an ion implanter on the surface of the polysilicon active layer Formed by a high temperature annealing process, the gate insulating layer is formed on the polysilicon active layer by a deposition process, and a defect density of the silicon nitride spacer layer is smaller than a defect density of the gate insulating layer.
  • the low-temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer by an ion implantation process and a high temperature annealing process, the nitrogen
  • the silicon spacer layer can reduce the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduce the leakage current of the thin film transistor, increase the breakdown voltage, and make the thin film transistor have good and stable electrical properties.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to Embodiment 1 of the present invention.
  • Figure 2 is an enlarged schematic view of a portion A in Figure 1;
  • 3a-3k are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to Embodiment 2 of the present invention.
  • 4a to 4f are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to a third embodiment of the present invention.
  • the present embodiment provides a low-temperature crystalline silicon thin film transistor.
  • the low-temperature crystalline silicon thin film transistor includes a polysilicon active layer 2, a gate insulating layer 3, and a gate electrode which are sequentially disposed on a base substrate 1. 4.
  • Source electrode 5a and drain electrode 5b are sequentially disposed on a base substrate 1.
  • a connection interface between the polysilicon active layer 2 and the gate insulating layer 3 is formed with a silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 and the polysilicon active layer 2 are integrated with each other. The structure of the connection.
  • the base substrate 1 is first provided with a buffer layer 7 including a silicon nitride layer 71 and silicon oxide sequentially formed on the substrate substrate.
  • the polysilicon active layer 2 is prepared to be formed on the buffer layer 7.
  • the silicon nitride spacer layer 6 is formed on the surface of the polysilicon active layer 2 by an ion implantation process and a high temperature annealing process.
  • the gate insulating layer 3 is formed on the buffer layer 7 by a deposition process and covers the polysilicon active layer 2 and the silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 is formed in the On the connection interface of the polysilicon active layer 2 and the gate insulating layer 3.
  • the gate electrode 4 is formed on the gate insulating layer 3 and directly above the polysilicon active layer 2, and the gate electrode 4 is covered with an interlayer dielectric layer 8.
  • the source electrode 5a and the drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first via 81 provided in the interlayer dielectric layer 8 and the gate insulating layer 3. Electrically connected to one end of the polysilicon active layer 2, the drain electrode 5b is electrically connected to the second via 82 disposed in the interlayer dielectric layer 8 and the gate insulating layer 3 The other end of the polysilicon active layer 2 is described.
  • a patterned light shielding unit 9 is disposed between the substrate substrate 1 and the buffer layer 7 , and the light shielding unit 9 is directly opposite to the patterned polysilicon active layer 2 . .
  • the polysilicon active layer 2 is further subjected to a sub-region doping process, and the polysilicon active layer 2 is sequentially formed with an undoped region 21 from the middle to the both ends, and lightly doped.
  • the source electrode 5a penetrates the silicon nitride spacer 6 to be electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 2b penetrates the silicon nitride spacer layer 6 is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2.
  • the low temperature polysilicon thin film transistor provided in the above embodiment is prepared to form a silicon nitride spacer layer at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is formed by an ion implantation process and a high temperature annealing process.
  • the polysilicon active layer On the surface of the polysilicon active layer, the polysilicon active layer is integrally connected to each other, and the defect density is much smaller than the defect density of the gate insulating layer.
  • the silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties.
  • This embodiment provides a method for preparing a low temperature polysilicon thin film transistor.
  • the preparation method includes the steps of:
  • a substrate 1 is provided on which a pattern is formed on the substrate substrate 1 Shading unit 9.
  • the base substrate 1 may be an optional glass substrate, and a patterned shading unit 9 is prepared by a deposition process and a photolithography process in sequence.
  • a polysilicon thin film layer 2a is formed on the base substrate 1. This step specifically includes:
  • step S1 specifically includes:
  • a buffer layer 7 and an amorphous silicon film layer 2b are sequentially deposited on the substrate substrate 1 by using a semiconductor deposition process, and the buffer layer 7 is sequentially formed on the substrate substrate 1.
  • the silicon nitride layer 71 and the silicon oxide layer 72 cover the light shielding unit 9.
  • S12 is processed by an excimer laser annealing (ELA) process to crystallize the amorphous silicon thin film layer 2b to form a polysilicon thin film layer 2a.
  • ELA excimer laser annealing
  • the amorphous silicon thin film layer 2b is also subjected to a heating dehydrogenation treatment before the ELA process of step S12 is performed, thereby making the finally prepared polycrystalline silicon thin film layer 2a have better electrical properties.
  • the temperature of the heating dehydrogenation treatment may be selected to be 350 to 450 °C.
  • the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by using a photolithography process, and the ion implantation layer 6a is left on the surface of the polysilicon active layer 2.
  • the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
  • the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends.
  • the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
  • a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1.
  • the gate insulating layer 3 is formed on the buffer layer 7 and covers the polysilicon active layer 2 and the ion implantation layer 6a, and the gate insulating layer 3 may be silicon oxide (SiO x ).
  • a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. Specifically, first, a patterned gate electrode 4 is formed by a deposition process and a photolithography process, the gate electrode 4 is located directly above the polysilicon active layer 2, and the material of the gate electrode 4 is selected from It is not limited to one or more of Cr, Mo, Al, and Cu, and may be one or more layers stacked.
  • the interlayer dielectric layer 8 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN x
  • the layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween.
  • Most of the nitrogen in the implanted silicon is embedded in the lattice loss region formed by the implantation, and at the high temperature annealing, the damaged region begins to recrystallize and grow to form a continuous solid solution Si-N band, in the polysilicon active layer 2 and the gate.
  • the interface of the pole insulating layer 3 is deposited to form a silicon nitride spacer layer and to generate a silicon surface oxidation inhibiting effect.
  • the implantation of nitrogen ions can effectively suppress the TED (Transient Enhanced Diffusion) problem in the heat treatment, control the channel length of the polysilicon active layer 2, and improve the leakage problem of the p-n junction.
  • TED Transient Enhanced Diffusion
  • TED is formed by the supersaturated self-gap silicon atoms combined with the doping atoms of the substitution sites to form a gap state, which is then moved in a high temperature heat treatment.
  • the nitrogen ions are more likely to combine with the self-gap atoms to form a movable atom than the dopant atoms, thereby suppressing TED, that is, suppressing diffusion of the dopant atoms to the gate insulating layer 3.
  • a first via 81 and a second via 82 are etched into the interlayer dielectric layer 8 and the gate insulating layer 3 by using a photolithography process, the first pass
  • the hole 81 and the second via 82 penetrate the silicon nitride spacer layer 6 until the polysilicon active layer 2 is exposed.
  • the first via 81 and the second via 82 are respectively connected to the heavily doped region 23 at both ends of the polysilicon active layer 2.
  • the source electrode 5a being connected to the polysilicon active through the first via 81 Layer 2
  • the drain electrode 5b is connected to the polysilicon active layer 2 through the second via 82.
  • the patterned source electrode 5a and the drain electrode 5b are prepared by a deposition process and a photolithography process, and the source electrode 5a is electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 5b is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2.
  • the material of the source electrode 5a and the drain electrode 5b is selected from, but not limited to, Cr, Mo, Al, Cu. One or more of them may be stacked in one or more layers.
  • a photolithography process (patterning process) is employed in a plurality of steps.
  • Each of the photolithography processes includes masking, exposure, development, etching, and stripping processes, respectively, wherein the etching process includes dry etching and wet etching.
  • Lithography is already a relatively mature process technology in the field. The details are not described here.
  • This embodiment provides a method for preparing a low-temperature polysilicon thin film transistor. Compared with the preparation method provided in Embodiment 2, the preparation method of the present embodiment differs in the order of partial steps.
  • a polysilicon thin film layer 2a is formed on the base substrate 1, as shown in Fig. 3c. After the preparation of the polycrystalline silicon thin film layer 2a, the following steps are different from those in the second embodiment.
  • the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by a photolithography process.
  • the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
  • the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends.
  • the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
  • a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1.
  • the gate insulating layer 3 is formed on the buffer layer 7 to cover the polysilicon active layer 2, the gate insulating layer 3 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN The x ) layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. This step is carried out with reference to step S5 in the second embodiment.
  • the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween.
  • This step is carried out with reference to step S6 in the second embodiment.
  • a patterned source electrode 5a and a drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first pass.
  • Hole 81 is connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 5b is connected to the heavily doped region of the other end of the polysilicon active layer 2 through the second via 5b 23.
  • the finally prepared low temperature polysilicon thin film transistor is shown in Figure 3k.
  • the low temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is passed through
  • the ion implantation process and the high temperature annealing process are formed on the surface of the polysilicon active layer, and are integrally connected to the polysilicon active layer, and the defect density is much smaller than the defect density of the gate insulating layer.
  • the silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties. Further improvements in the quality of the final product (such as LCD or OLED).

Abstract

L'invention concerne un procédé de préparation d'un transistor à couches minces de polysilicium basse température comprenant les étapes consistant à : former séquentiellement une couche active de polysilicium (2) et une couche d'isolation de grille (3) recouvrant la couche active de polysilicium (2) sur un substrat de base (1) ; utiliser un procédé d'implantation ionique pour implanter des ions azote sur la surface de la couche active de polysilicium (2) tournée vers la couche d'isolation de grille (3), de manière à former une couche d'implantation ionique (6a) ; et utiliser un processus de recuit à haute température pour recristalliser la couche d'implantation ionique (6a), de manière à former une couche d'espacement de nitrure de silicium (6) entre la couche active de polysilicium (2) et la couche d'isolation de grille (3). Un transistor à couches minces de silicium cristallin basse température, comprenant une couche active de polysilicium (2), une couche d'isolation de grille (3), une électrode de grille (4), une électrode de source (5a) et une électrode de drain (5b) qui sont disposées successivement sur un substrat de base (1), une couche d'espacement de nitrure de silicium (6) étant formée sur une interface de jonction entre la couche active de polysilicium (2) et la couche d'isolation de grille (3), la couche d'espacement de nitrure de silicium (6) et la couche active de polysilicium (2) étant d'une structure interconnectée intégrée.
PCT/CN2017/098337 2017-08-07 2017-08-21 Transistor à couches minces de polysilicium basse température et son procédé de préparation WO2019028934A1 (fr)

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CN110504164B (zh) * 2019-08-27 2022-04-15 京东方科技集团股份有限公司 薄膜晶体管及其制造方法和显示装置
CN111370524B (zh) * 2020-03-18 2021-07-23 武汉华星光电技术有限公司 感光传感器及其制备方法、阵列基板、显示面板

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